2018-11-08 13:31:28 +01:00
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/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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2017-09-21 13:13:01 +02:00
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#include "sysc/SiFive/spi.h"
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2018-11-08 13:31:28 +01:00
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#include "cci_configuration"
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2021-08-26 17:27:33 +02:00
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#include "tlm/scc/signal_initiator_mixin.h"
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#include "tlm/scc/signal_target_mixin.h"
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2018-11-08 13:31:28 +01:00
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#include "scc/tlm_target.h"
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2017-10-04 14:30:25 +02:00
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#include "scc/utilities.h"
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2017-09-21 13:13:01 +02:00
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#include "sysc/SiFive/gen/spi_regs.h"
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2018-11-08 13:31:28 +01:00
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#include "sysc/tlm_extensions.h"
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2018-07-23 22:15:38 +02:00
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#include <util/ities.h>
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2017-09-21 13:13:01 +02:00
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namespace sysc {
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2018-11-08 13:31:28 +01:00
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namespace spi_impl {
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using namespace sc_core;
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class beh : public sysc::spi, public scc::tlm_target<> {
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public:
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SC_HAS_PROCESS(beh); // NOLINT
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cci::cci_param<bool> bit_true_transfer;
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2017-09-21 13:13:01 +02:00
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2018-11-08 13:31:28 +01:00
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beh(sc_core::sc_module_name nm);
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~beh() override;
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protected:
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2021-08-26 17:27:33 +02:00
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tlm::scc::tlm_signal_bool_opt_out _sck_o;
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tlm::scc::tlm_signal_bool_opt_out _mosi_o;
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tlm::scc::tlm_signal_bool_opt_in _miso_i;
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sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> _scs_o;
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2018-11-08 13:31:28 +01:00
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void clock_cb();
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void reset_cb();
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void transmit_data();
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2021-08-26 17:27:33 +02:00
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void receive_data(tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay);
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2018-11-08 13:31:28 +01:00
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void update_irq();
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sc_core::sc_event update_irq_evt;
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sc_core::sc_time clk;
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std::unique_ptr<spi_regs> regs;
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sc_core::sc_fifo<uint8_t> rx_fifo, tx_fifo;
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};
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beh::beh(sc_core::sc_module_name nm)
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: sysc::spi(nm)
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2017-09-26 17:10:10 +02:00
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, tlm_target<>(clk)
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2018-11-08 13:31:28 +01:00
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, NAMED(_sck_o)
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, NAMED(_mosi_o)
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, NAMED(_miso_i)
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, NAMED(_scs_o, 4)
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2018-07-23 22:15:38 +02:00
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, NAMED(bit_true_transfer, false)
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2018-11-08 13:31:28 +01:00
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, NAMEDD(regs, spi_regs)
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, rx_fifo(8)
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, tx_fifo(8) {
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spi::socket(scc::tlm_target<>::socket);
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_sck_o(sck_o);
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_mosi_o(mosi_o);
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miso_i(_miso_i);
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_scs_o(scs_o);
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2017-09-21 13:13:01 +02:00
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regs->registerResources(*this);
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SC_METHOD(clock_cb);
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2017-09-22 11:23:23 +02:00
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sensitive << clk_i;
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2017-09-21 13:13:01 +02:00
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SC_METHOD(reset_cb);
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2017-09-22 11:23:23 +02:00
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sensitive << rst_i;
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2017-10-04 10:31:11 +02:00
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dont_initialize();
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2018-07-23 22:15:38 +02:00
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SC_THREAD(transmit_data);
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2018-11-08 13:31:28 +01:00
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_miso_i.register_nb_transport(
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2021-08-26 17:27:33 +02:00
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[this](tlm::scc::tlm_signal_gp<bool> &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum {
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2018-11-08 13:31:28 +01:00
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this->receive_data(gp, delay);
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return tlm::TLM_COMPLETED;
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});
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regs->txdata.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data, sc_core::sc_time d) -> bool {
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2018-07-23 22:15:38 +02:00
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if (!this->regs->in_reset()) {
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reg.put(data);
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tx_fifo.nb_write(static_cast<uint8_t>(regs->r_txdata.data));
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}
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return true;
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});
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2018-11-08 13:31:28 +01:00
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regs->rxdata.set_read_cb([this](const scc::sc_register<uint32_t> ®, uint32_t &data, sc_core::sc_time d) -> bool {
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2018-07-23 22:15:38 +02:00
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if (!this->regs->in_reset()) {
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uint8_t val;
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2018-11-08 13:31:28 +01:00
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if (rx_fifo.nb_read(val)) {
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regs->r_rxdata.empty = 0;
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regs->r_rxdata.data = val;
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if (regs->r_rxmark.rxmark <= rx_fifo.num_available()) {
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regs->r_ip.rxwm = 1;
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2018-07-23 22:15:38 +02:00
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update_irq();
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}
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} else
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2018-11-08 13:31:28 +01:00
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regs->r_rxdata.empty = 1;
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data = reg.get() & reg.rdmask;
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2018-07-23 22:15:38 +02:00
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}
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return true;
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});
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2018-11-08 13:31:28 +01:00
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regs->csmode.set_write_cb(
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2019-04-11 07:40:02 +02:00
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[this](const scc::sc_register<uint32_t> ®, const uint32_t &data, sc_core::sc_time d) -> bool {
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2018-11-08 13:31:28 +01:00
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if (regs->r_csmode.mode == 2 && regs->r_csmode.mode != bit_sub<0, 2>(data) && regs->r_csid < 4) {
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tlm::tlm_phase phase(tlm::BEGIN_REQ);
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sc_core::sc_time delay(SC_ZERO_TIME);
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2021-08-26 17:27:33 +02:00
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tlm::scc::tlm_signal_gp<> gp;
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2018-11-08 13:31:28 +01:00
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gp.set_command(tlm::TLM_WRITE_COMMAND);
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gp.set_value(true);
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_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
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}
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reg.put(data);
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return true;
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});
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2019-04-11 07:40:02 +02:00
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regs->csid.set_write_cb([this](const scc::sc_register<uint32_t> ®, const uint32_t &data, sc_core::sc_time d) -> bool {
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2018-11-08 13:31:28 +01:00
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if (regs->r_csmode.mode == 2 && regs->csid != data && regs->r_csid < 4) {
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2018-07-23 22:15:38 +02:00
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tlm::tlm_phase phase(tlm::BEGIN_REQ);
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sc_core::sc_time delay(SC_ZERO_TIME);
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2021-08-26 17:27:33 +02:00
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tlm::scc::tlm_signal_gp<> gp;
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2018-07-23 22:15:38 +02:00
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gp.set_command(tlm::TLM_WRITE_COMMAND);
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gp.set_value(true);
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2018-11-08 13:31:28 +01:00
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_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
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2018-07-23 22:15:38 +02:00
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}
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reg.put(data);
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return true;
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});
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2019-04-11 07:40:02 +02:00
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regs->csdef.set_write_cb([this](const scc::sc_register<uint32_t> ®, const uint32_t &data, sc_core::sc_time d) -> bool {
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2018-11-08 13:31:28 +01:00
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auto diff = regs->csdef ^ data;
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if (regs->r_csmode.mode == 2 && diff != 0 && (regs->r_csid < 4) && (diff & (1 << regs->r_csid)) != 0) {
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2018-07-23 22:15:38 +02:00
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tlm::tlm_phase phase(tlm::BEGIN_REQ);
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sc_core::sc_time delay(SC_ZERO_TIME);
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2021-08-26 17:27:33 +02:00
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tlm::scc::tlm_signal_gp<> gp;
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2018-07-23 22:15:38 +02:00
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gp.set_command(tlm::TLM_WRITE_COMMAND);
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gp.set_value(true);
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2018-11-08 13:31:28 +01:00
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_scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay);
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2018-07-23 22:15:38 +02:00
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}
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reg.put(data);
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return true;
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});
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2018-11-08 13:31:28 +01:00
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regs->ie.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data, sc_core::sc_time d) -> bool {
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2018-07-23 22:15:38 +02:00
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reg.put(data);
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2018-11-08 13:31:28 +01:00
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update_irq_evt.notify();
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2018-07-23 22:15:38 +02:00
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return true;
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});
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2018-11-08 13:31:28 +01:00
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regs->ip.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data, sc_core::sc_time d) -> bool {
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reg.put(data);
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update_irq_evt.notify();
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return true;
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2018-07-23 22:15:38 +02:00
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});
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2018-11-08 13:31:28 +01:00
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SC_METHOD(update_irq);
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sensitive << update_irq_evt << rx_fifo.data_written_event() << rx_fifo.data_read_event()
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<< tx_fifo.data_written_event() << tx_fifo.data_read_event();
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2017-09-21 13:13:01 +02:00
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}
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2018-11-08 13:31:28 +01:00
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beh::~beh() = default;
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2017-09-21 13:13:01 +02:00
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2018-11-08 13:31:28 +01:00
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void beh::clock_cb() { this->clk = clk_i.read(); }
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2017-09-21 13:13:01 +02:00
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2018-11-08 13:31:28 +01:00
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void beh::reset_cb() {
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2017-09-22 11:23:23 +02:00
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if (rst_i.read())
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2017-09-21 13:13:01 +02:00
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regs->reset_start();
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else
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regs->reset_stop();
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}
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2018-11-08 13:31:28 +01:00
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void beh::transmit_data() {
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2018-07-23 22:15:38 +02:00
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uint8_t txdata;
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tlm::tlm_phase phase(tlm::BEGIN_REQ);
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sc_core::sc_time delay(SC_ZERO_TIME);
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sc_core::sc_time bit_duration(SC_ZERO_TIME);
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2018-11-08 13:31:28 +01:00
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sc_core::sc_time start_time;
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2018-07-23 22:15:38 +02:00
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2021-08-26 17:27:33 +02:00
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auto set_bit = [&](bool val, tlm::scc::tlm_signal_bool_opt_out &socket,
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2018-11-08 13:31:28 +01:00
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bool data_valid = false) -> std::pair<bool, uint32_t> {
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if (socket.get_interface() == nullptr) return std::pair<bool, uint32_t>{false, 0};
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2021-08-26 17:27:33 +02:00
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auto *gp = tlm::scc::tlm_signal_gp<>::create();
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2018-11-08 13:31:28 +01:00
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auto *ext = new sysc::tlm_signal_spi_extension();
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ext->tx.data_bits = 8;
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ext->start_time = start_time;
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ext->tx.m2s_data = txdata;
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ext->tx.m2s_data_valid = data_valid;
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ext->tx.s2m_data_valid = false;
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gp->set_extension(ext);
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gp->set_command(tlm::TLM_WRITE_COMMAND);
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gp->set_value(val);
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2018-07-23 22:15:38 +02:00
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tlm::tlm_phase phase(tlm::BEGIN_REQ);
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2018-11-08 13:31:28 +01:00
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gp->acquire();
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phase = tlm::BEGIN_REQ;
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delay = SC_ZERO_TIME;
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socket->nb_transport_fw(*gp, phase, delay);
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std::pair<bool, uint32_t> ret{ext->tx.s2m_data_valid != 0, ext->tx.s2m_data};
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gp->release();
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return ret;
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2018-07-23 22:15:38 +02:00
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};
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2018-11-08 13:31:28 +01:00
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wait(delay); // intentionally 0ns;
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while (true) {
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2018-07-23 22:15:38 +02:00
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wait(tx_fifo.data_written_event());
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2018-11-08 13:31:28 +01:00
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if (regs->r_csmode.mode != 3 && regs->r_csid < 4) // not in OFF mode
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set_bit(false, _scs_o[regs->r_csid]);
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set_bit(regs->r_sckmode.pol, _sck_o);
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while (tx_fifo.nb_read(txdata)) {
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regs->r_txdata.full = tx_fifo.num_free() == 0;
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regs->r_ip.txwm = regs->r_txmark.txmark <= (7 - tx_fifo.num_free()) ? 1 : 0;
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update_irq_evt.notify();
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bit_duration = 2 * (regs->r_sckdiv.div + 1) * clk;
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start_time = sc_core::sc_time_stamp();
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set_bit(txdata & 0x80, _mosi_o); // 8 data bits, MSB first
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auto s2m = set_bit(1 - regs->r_sckmode.pol, _sck_o, true);
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wait(bit_duration / 2);
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set_bit(regs->r_sckmode.pol, _sck_o, true);
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wait(bit_duration / 2);
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if (bit_true_transfer.get_value()) {
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for (size_t i = 0, mask = 0x40; i < 7; ++i, mask >= 1) {
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set_bit(txdata & mask, _mosi_o); // 8 data bits, MSB first
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set_bit(1 - regs->r_sckmode.pol, _sck_o);
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wait(bit_duration / 2);
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set_bit(regs->r_sckmode.pol, _sck_o);
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wait(bit_duration / 2);
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2018-07-23 22:15:38 +02:00
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}
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} else
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2018-11-08 13:31:28 +01:00
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wait(7 * bit_duration);
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if (s2m.first) rx_fifo.nb_write(s2m.second & 0xff);
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update_irq_evt.notify();
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2018-07-23 22:15:38 +02:00
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}
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2018-11-08 13:31:28 +01:00
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if (regs->r_csmode.mode == 0 && regs->r_csid < 4) // in AUTO mode
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set_bit(false, _scs_o[regs->r_csid]);
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2018-07-23 22:15:38 +02:00
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}
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}
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2021-08-26 17:27:33 +02:00
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void beh::receive_data(tlm::scc::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {}
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2018-11-08 13:31:28 +01:00
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void beh::update_irq() {
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regs->r_ip.rxwm = regs->r_rxmark.rxmark < rx_fifo.num_available();
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regs->r_ip.txwm = regs->r_txmark.txmark <= tx_fifo.num_available();
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regs->r_txdata.full = tx_fifo.num_free() == 0;
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irq_o.write((regs->r_ie.rxwm > 0 && regs->r_ip.rxwm > 0) || (regs->r_ie.txwm > 0 && regs->r_ip.txwm > 0));
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2018-07-23 22:15:38 +02:00
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}
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2018-11-08 13:31:28 +01:00
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} /* namespace spi:impl */
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2018-07-23 22:15:38 +02:00
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2018-11-08 13:31:28 +01:00
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template <> std::unique_ptr<spi> spi::create<sysc::spi_impl::beh>(sc_core::sc_module_name nm) {
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auto *res = new sysc::spi_impl::beh(nm);
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return std::unique_ptr<spi>(res);
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2018-07-23 22:15:38 +02:00
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}
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2017-09-21 13:13:01 +02:00
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} /* namespace sysc */
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