2018-11-08 13:31:28 +01:00
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/*******************************************************************************
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* Copyright (C) 2017, 2018 MINRES Technologies GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*******************************************************************************/
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2017-10-04 10:31:11 +02:00
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#include "sysc/SiFive/prci.h"
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2017-10-04 14:30:25 +02:00
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#include "scc/utilities.h"
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2017-10-04 10:31:11 +02:00
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#include "sysc/SiFive/gen/prci_regs.h"
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namespace sysc {
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2018-11-08 13:31:28 +01:00
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using namespace sc_core;
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prci::prci(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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2018-07-13 20:04:07 +02:00
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, tlm_target<>(hfclk)
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, NAMED(rst_i)
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, NAMED(hfclk_o)
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, NAMEDD(regs, prci_regs) {
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regs->registerResources(*this);
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SC_METHOD(reset_cb);
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sensitive << rst_i;
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dont_initialize();
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SC_METHOD(hfxosc_cb);
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sensitive << hfxosc_i;
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SC_METHOD(hfrosc_en_cb);
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sensitive << hfrosc_en_evt;
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dont_initialize();
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2018-11-08 13:31:28 +01:00
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regs->hfxosccfg.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data, sc_core::sc_time d) -> bool {
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reg.put(data);
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if (this->regs->r_hfxosccfg.hfxoscen == 1) { // check rosc_en
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this->hfxosc_en_evt.notify(1, sc_core::SC_US);
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} else {
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this->hfxosc_en_evt.notify(SC_ZERO_TIME);
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}
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return true;
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});
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regs->hfrosccfg.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data, sc_core::sc_time d) -> bool {
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reg.put(data);
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if (this->regs->r_hfrosccfg.hfroscen == 1) { // check rosc_en
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this->hfrosc_en_evt.notify(1, sc_core::SC_US);
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} else {
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this->hfrosc_en_evt.notify(SC_ZERO_TIME);
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}
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return true;
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});
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regs->pllcfg.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data, sc_core::sc_time d) -> bool {
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reg.put(data);
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auto &pllcfg = this->regs->r_pllcfg;
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if (pllcfg.pllbypass == 0 && pllcfg.pllq != 0) { // set pll_lock if pll is selected
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pllcfg.plllock = 1;
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}
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update_hfclk();
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return true;
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});
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regs->plloutdiv.set_write_cb([this](scc::sc_register<uint32_t> ®, uint32_t data, sc_core::sc_time d) -> bool {
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reg.put(data);
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update_hfclk();
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return true;
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});
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hfxosc_clk = 62.5_ns;
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}
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2018-11-08 13:31:28 +01:00
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prci::~prci() = default;
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void prci::reset_cb() {
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if (rst_i.read())
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regs->reset_start();
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else {
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regs->reset_stop();
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this->hfxosc_en_evt.notify(1, sc_core::SC_US);
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}
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}
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void prci::hfxosc_cb() {
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this->regs->r_hfxosccfg.hfxoscrdy = 0;
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this->hfxosc_en_evt.notify(1, sc_core::SC_US);
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}
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void prci::hfxosc_en_cb() {
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update_hfclk();
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2018-11-08 13:31:28 +01:00
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if (regs->r_hfxosccfg.hfxoscen == 1) // set rosc_rdy
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regs->r_hfxosccfg.hfxoscrdy = 1;
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else
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regs->r_hfxosccfg.hfxoscrdy = 0;
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}
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void prci::hfrosc_en_cb() {
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update_hfclk();
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auto &hfrosccfg = regs->r_hfrosccfg;
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if (regs->r_hfrosccfg.hfroscen == 1) { // set rosc_rdy
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regs->r_hfrosccfg.hfroscrdy = 1;
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} else {
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regs->r_hfrosccfg.hfroscrdy = 0;
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}
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}
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void prci::update_hfclk() {
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auto &hfrosccfg = regs->r_hfrosccfg;
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auto &pllcfg = regs->r_pllcfg;
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auto &plldiv = regs->r_plloutdiv;
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uint32_t trim = hfrosccfg.hfrosctrim;
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uint32_t div = hfrosccfg.hfroscdiv;
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hfrosc_clk = sc_core::sc_time(((div + 1) * 1.0) / (70000000 + 12000.0 * trim), sc_core::SC_SEC);
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auto pll_ref = pllcfg.pllrefsel == 1 ? hfxosc_clk : hfrosc_clk;
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auto r = pllcfg.pllr + 1;
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auto f = 2 * (pllcfg.pllf + 1);
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auto q = 1 << pllcfg.pllq;
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auto pll_out = pllcfg.pllbypass == 1 || pllcfg.plllock == 0 ? pll_ref : ((pll_ref * r) / f) * q;
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auto pll_res = plldiv & 0x100 ? pll_out : 2 * pll_out * ((plldiv & 0x3f) + 1);
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hfclk = pllcfg.pllsel ? pll_res : hfrosc_clk;
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hfclk_o.write(hfclk);
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}
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} /* namespace sysc */
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