start implementing FW to control SPN HW

feature/fpga-alloc-free
Stanislaw Kaushanski 2 years ago
parent 62da6407d8
commit 7d5de86015
  1. 3
      .gitignore
  2. 28
      raven_spn/.project
  3. 29
      raven_spn/Makefile
  4. 163
      raven_spn/bsp/drivers/clic/clic_driver.c
  5. 44
      raven_spn/bsp/drivers/clic/clic_driver.h
  6. 252
      raven_spn/bsp/drivers/fe300prci/fe300prci_driver.c
  7. 79
      raven_spn/bsp/drivers/fe300prci/fe300prci_driver.h
  8. 122
      raven_spn/bsp/drivers/plic/plic_driver.c
  9. 52
      raven_spn/bsp/drivers/plic/plic_driver.h
  10. 66
      raven_spn/bsp/env/common.mk
  11. 161
      raven_spn/bsp/env/coreip-e2-arty/flash.lds
  12. 98
      raven_spn/bsp/env/coreip-e2-arty/init.c
  13. 31
      raven_spn/bsp/env/coreip-e2-arty/openocd.cfg
  14. 98
      raven_spn/bsp/env/coreip-e2-arty/platform.h
  15. 3
      raven_spn/bsp/env/coreip-e2-arty/settings.mk
  16. 157
      raven_spn/bsp/env/coreip-e2-arty/tim-split.lds
  17. 161
      raven_spn/bsp/env/coreip-e2-arty/tim.lds
  18. 102
      raven_spn/bsp/env/coreplexip-arty.h
  19. 157
      raven_spn/bsp/env/coreplexip-e31-arty/dhrystone.lds
  20. 161
      raven_spn/bsp/env/coreplexip-e31-arty/flash.lds
  21. 122
      raven_spn/bsp/env/coreplexip-e31-arty/init.c
  22. 31
      raven_spn/bsp/env/coreplexip-e31-arty/openocd.cfg
  23. 100
      raven_spn/bsp/env/coreplexip-e31-arty/platform.h
  24. 161
      raven_spn/bsp/env/coreplexip-e31-arty/scratchpad.lds
  25. 3
      raven_spn/bsp/env/coreplexip-e31-arty/settings.mk
  26. 157
      raven_spn/bsp/env/coreplexip-e51-arty/dhrystone.lds
  27. 161
      raven_spn/bsp/env/coreplexip-e51-arty/flash.lds
  28. 122
      raven_spn/bsp/env/coreplexip-e51-arty/init.c
  29. 31
      raven_spn/bsp/env/coreplexip-e51-arty/openocd.cfg
  30. 100
      raven_spn/bsp/env/coreplexip-e51-arty/platform.h
  31. 161
      raven_spn/bsp/env/coreplexip-e51-arty/scratchpad.lds
  32. 3
      raven_spn/bsp/env/coreplexip-e51-arty/settings.mk
  33. 1313
      raven_spn/bsp/env/encoding.h
  34. 98
      raven_spn/bsp/env/entry.S
  35. 161
      raven_spn/bsp/env/freedom-e300-arty/flash.lds
  36. 87
      raven_spn/bsp/env/freedom-e300-arty/init.c
  37. 30
      raven_spn/bsp/env/freedom-e300-arty/openocd.cfg
  38. 124
      raven_spn/bsp/env/freedom-e300-arty/platform.h
  39. 3
      raven_spn/bsp/env/freedom-e300-arty/settings.mk
  40. 157
      raven_spn/bsp/env/freedom-e300-hifive1/dhrystone.lds
  41. 161
      raven_spn/bsp/env/freedom-e300-hifive1/flash.lds
  42. 238
      raven_spn/bsp/env/freedom-e300-hifive1/init.c
  43. 34
      raven_spn/bsp/env/freedom-e300-hifive1/openocd.cfg
  44. 133
      raven_spn/bsp/env/freedom-e300-hifive1/platform.h
  45. 3
      raven_spn/bsp/env/freedom-e300-hifive1/settings.mk
  46. 81
      raven_spn/bsp/env/hifive1.h
  47. 111
      raven_spn/bsp/env/start.S
  48. 288
      raven_spn/bsp/env/ventry.S
  49. 36
      raven_spn/bsp/include/sifive/bits.h
  50. 18
      raven_spn/bsp/include/sifive/const.h
  51. 88
      raven_spn/bsp/include/sifive/devices/aon.h
  52. 30
      raven_spn/bsp/include/sifive/devices/clic.h
  53. 14
      raven_spn/bsp/include/sifive/devices/clint.h
  54. 24
      raven_spn/bsp/include/sifive/devices/gpio.h
  55. 23
      raven_spn/bsp/include/sifive/devices/otp.h
  56. 31
      raven_spn/bsp/include/sifive/devices/plic.h
  57. 56
      raven_spn/bsp/include/sifive/devices/prci.h
  58. 37
      raven_spn/bsp/include/sifive/devices/pwm.h
  59. 80
      raven_spn/bsp/include/sifive/devices/spi.h
  60. 27
      raven_spn/bsp/include/sifive/devices/uart.h
  61. 17
      raven_spn/bsp/include/sifive/sections.h
  62. 65
      raven_spn/bsp/include/sifive/smp.h
  63. 56
      raven_spn/bsp/libwrap/libwrap.mk
  64. 19
      raven_spn/bsp/libwrap/misc/write_hex.c
  65. 17
      raven_spn/bsp/libwrap/stdlib/malloc.c
  66. 17
      raven_spn/bsp/libwrap/sys/_exit.c
  67. 11
      raven_spn/bsp/libwrap/sys/close.c
  68. 11
      raven_spn/bsp/libwrap/sys/execve.c
  69. 9
      raven_spn/bsp/libwrap/sys/fork.c
  70. 18
      raven_spn/bsp/libwrap/sys/fstat.c
  71. 8
      raven_spn/bsp/libwrap/sys/getpid.c
  72. 13
      raven_spn/bsp/libwrap/sys/isatty.c
  73. 11
      raven_spn/bsp/libwrap/sys/kill.c
  74. 11
      raven_spn/bsp/libwrap/sys/link.c
  75. 16
      raven_spn/bsp/libwrap/sys/lseek.c
  76. 11
      raven_spn/bsp/libwrap/sys/open.c
  77. 11
      raven_spn/bsp/libwrap/sys/openat.c
  78. 28
      raven_spn/bsp/libwrap/sys/puts.c
  79. 32
      raven_spn/bsp/libwrap/sys/read.c
  80. 18
      raven_spn/bsp/libwrap/sys/sbrk.c
  81. 12
      raven_spn/bsp/libwrap/sys/stat.c
  82. 10
      raven_spn/bsp/libwrap/sys/stub.h
  83. 12
      raven_spn/bsp/libwrap/sys/times.c
  84. 11
      raven_spn/bsp/libwrap/sys/unlink.c
  85. 9
      raven_spn/bsp/libwrap/sys/wait.c
  86. 7
      raven_spn/bsp/libwrap/sys/weak_under_alias.h
  87. 31
      raven_spn/bsp/libwrap/sys/write.c
  88. BIN
      raven_spn/raven_spn
  89. 22
      raven_spn/src/bsp.h
  90. 123
      raven_spn/src/delay.c
  91. 25
      raven_spn/src/delay.h
  92. 89
      raven_spn/src/io/gpio.h
  93. 122
      raven_spn/src/io/pwm.h
  94. 200
      raven_spn/src/io/spi.h
  95. 83
      raven_spn/src/io/uart.h
  96. 105
      raven_spn/src/raven_spn.cpp
  97. 6
      raven_spn/src/raven_spn.h
  98. 78
      raven_spn/src/spn_regs.h
  99. 179
      raven_spn/src/util/bit_field.h
  100. 271
      raven_spn/src/wrap_printf.c
  101. Some files were not shown because too many files have changed in this diff Show More

3
.gitignore vendored

@ -99,9 +99,6 @@ local.properties
.loadpath
.recommenders
# Eclipse Core
.project
# External tool builders
.externalToolBuilders/

@ -0,0 +1,28 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>raven_spn</name>
<comment></comment>
<projects>
<project>bsp</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

@ -0,0 +1,29 @@
TARGET = raven_spn
C_SRCS = $(wildcard src/*.c) $(BSP_BASE)/drivers/fe300prci/fe300prci_driver.c $(BSP_BASE)/drivers/plic/plic_driver.c
CXX_SRCS = $(wildcard src/*.cpp)
HEADERS = $(wildcard src/*.h)
CFLAGS = -g -fno-builtin-printf -DUSE_PLIC -I./src
CXXFLAGS = -fno-use-cxa-atexit
LDFLAGS = -Wl,--wrap=printf
LDFLAGS += -g -lstdc++ -fno-use-cxa-atexit -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=medany
BOARD=freedom-e300-hifive1
LINK_TARGET=flash
RISCV_ARCH=rv32imac
RISCV_ABI=ilp32
TOOL_DIR=/home/stas/Downloads/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin
#TOOL_DIR?=/opt/riscv/FreedomStudio/20180122/SiFive/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin
BSP_BASE = ./bsp
include $(BSP_BASE)/env/common.mk
.PHONY: all
all: $(TARGET).dump
$(TARGET).dump: $(TARGET)
$(TOOL_DIR)/$(TRIPLET)-objdump -d -S -C $< > $@

@ -0,0 +1,163 @@
// See LICENSE for license details.
#include "sifive/devices/clic.h"
#include "clic/clic_driver.h"
#include "platform.h"
#include "encoding.h"
#include <string.h>
void volatile_memzero(uint8_t * base, unsigned int size) {
volatile uint8_t * ptr;
for (ptr = base; ptr < (base + size); ptr++){
*ptr = 0;
}
}
// Note that there are no assertions or bounds checking on these
// parameter values.
void clic_init (
clic_instance_t * this_clic,
uintptr_t hart_addr,
interrupt_function_ptr_t* vect_table,
interrupt_function_ptr_t default_handler,
uint32_t num_irq,
uint32_t num_config_bits
)
{
this_clic->hart_addr= hart_addr;
this_clic->vect_table= vect_table;
this_clic->num_config_bits= num_config_bits;
//initialize vector table
for(int i=0;i++;i<num_irq) {
this_clic->vect_table[i] = default_handler;
}
//set base vectors
write_csr(mtvt, vect_table);
//clear all interrupt enables and pending
volatile_memzero((uint8_t*)(this_clic->hart_addr+CLIC_INTIE), num_irq);
volatile_memzero((uint8_t*)(this_clic->hart_addr+CLIC_INTIP), num_irq);
//clear nlbits and nvbits; all interrupts trap to level 15
*(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG)=0;
}
void clic_install_handler (clic_instance_t * this_clic, uint32_t source, interrupt_function_ptr_t handler) {
this_clic->vect_table[source] = handler;
}
void clic_enable_interrupt (clic_instance_t * this_clic, uint32_t source) {
*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIE+source) = 1;
}
void clic_disable_interrupt (clic_instance_t * this_clic, uint32_t source){
*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIE+source) = 0;
}
void clic_set_pending(clic_instance_t * this_clic, uint32_t source){
*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIP+source) = 1;
}
void clic_clear_pending(clic_instance_t * this_clic, uint32_t source){
*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIP+source) = 0;
}
void clic_set_intcfg (clic_instance_t * this_clic, uint32_t source, uint32_t intcfg){
*(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTCFG+source) = intcfg;
}
uint8_t clic_get_intcfg (clic_instance_t * this_clic, uint32_t source){
return *(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTCFG+source);
}
void clic_set_cliccfg (clic_instance_t * this_clic, uint32_t cfg){
*(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG) = cfg;
}
uint8_t clic_get_cliccfg (clic_instance_t * this_clic){
return *(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG);
}
//sets an interrupt level based encoding of nmbits, nlbits
uint8_t clic_set_int_level( clic_instance_t * this_clic, uint32_t source, uint8_t level) {
//extract nlbits
uint8_t nlbits = clic_get_cliccfg(this_clic);
nlbits = (nlbits >>1) & 0x7;
//shift level right to mask off unused bits
level = level>>((this_clic->num_config_bits)-nlbits); //plus this_clic->nmbits which is always 0 for now.
//shift level into correct bit position
level = level << (8-this_clic->num_config_bits) + (this_clic->num_config_bits - nlbits);
//write to clicintcfg
uint8_t current_intcfg = clic_get_intcfg(this_clic, source);
clic_set_intcfg(this_clic, source, (current_intcfg | level));
return level;
}
//gets an interrupt level based encoding of nmbits, nlbits
uint8_t clic_get_int_level( clic_instance_t * this_clic, uint32_t source) {
uint8_t level;
level = clic_get_intcfg(this_clic, source);
//extract nlbits
uint8_t nlbits = clic_get_cliccfg(this_clic);
nlbits = (nlbits >>1) & 0x7;
//shift level
level = level >> (8-(this_clic->num_config_bits));
//shift level right to mask off priority bits
level = level>>(this_clic->num_config_bits-nlbits); //this_clic->nmbits which is always 0 for now.
return level;
}
//sets an interrupt priority based encoding of nmbits, nlbits
uint8_t clic_set_int_priority( clic_instance_t * this_clic, uint32_t source, uint8_t priority) {
//priority bits = num_config_bits - nlbits
//extract nlbits
uint8_t nlbits = clic_get_cliccfg(this_clic);
nlbits = (nlbits >>1) & 0x7;
uint8_t priority_bits = this_clic->num_config_bits-nlbits;
if(priority_bits = 0) {
//no bits to set
return 0;
}
//mask off unused bits
priority = priority >> (8-priority_bits);
//shift into the correct bit position
priority = priority << (8-(this_clic->num_config_bits));
//write to clicintcfg
uint8_t current_intcfg = clic_get_intcfg(this_clic, source);
clic_set_intcfg(this_clic, source, (current_intcfg | priority));
return current_intcfg;
}
//gets an interrupt priority based encoding of nmbits, nlbits
uint8_t clic_get_int_priority( clic_instance_t * this_clic, uint32_t source) {
uint8_t priority;
priority = clic_get_intcfg(this_clic, source);
//extract nlbits
uint8_t nlbits = clic_get_cliccfg(this_clic);
nlbits = (nlbits >>1) & 0x7;
//shift left to mask off level bits
priority = priority << nlbits;
//shift priority
priority = priority >> (8-((this_clic->num_config_bits)+nlbits));
return priority;
}

@ -0,0 +1,44 @@
// See LICENSE file for licence details
#ifndef PLIC_DRIVER_H
#define PLIC_DRIVER_H
__BEGIN_DECLS
#include "platform.h"
typedef void (*interrupt_function_ptr_t) (void);
typedef struct __clic_instance_t
{
uintptr_t hart_addr;
interrupt_function_ptr_t* vect_table;
uint32_t num_config_bits;
uint32_t num_sources;
} clic_instance_t;
// Note that there are no assertions or bounds checking on these
// parameter values.
void clic_init (clic_instance_t * this_clic, uintptr_t hart_addr, interrupt_function_ptr_t* vect_table, interrupt_function_ptr_t default_handler, uint32_t num_irq,uint32_t num_config_bits);
void clic_install_handler (clic_instance_t * this_clic, uint32_t source, interrupt_function_ptr_t handler);
void clic_enable_interrupt (clic_instance_t * this_clic, uint32_t source);
void clic_disable_interrupt (clic_instance_t * this_clic, uint32_t source);
void clic_set_pending(clic_instance_t * this_clic, uint32_t source);
void clic_clear_pending(clic_instance_t * this_clic, uint32_t source);
void clic_set_intcfg (clic_instance_t * this_clic, uint32_t source, uint32_t intcfg);
uint8_t clic_get_intcfg (clic_instance_t * this_clic, uint32_t source);
void clic_set_cliccfg (clic_instance_t * this_clic, uint32_t cfg);
uint8_t clic_get_cliccfg (clic_instance_t * this_clic);
//sets an interrupt level based encoding of nmbits, nlbits
uint8_t clic_set_int_level( clic_instance_t * this_clic, uint32_t source, uint8_t level);
//get an interrupt level based encoding of nmbits, nlbits
uint8_t clic_get_int_level( clic_instance_t * this_clic, uint32_t source);
//sets an interrupt priority based encoding of nmbits, nlbits
uint8_t clic_set_int_priority( clic_instance_t * this_clic, uint32_t source, uint8_t priority);
//sets an interrupt priority based encoding of nmbits, nlbits
uint8_t clic_get_int_priority( clic_instance_t * this_clic, uint32_t source);
__END_DECLS
#endif

@ -0,0 +1,252 @@
// See LICENSE file for license details
#include "platform.h"
#ifdef PRCI_CTRL_ADDR
#include "fe300prci/fe300prci_driver.h"
#include <unistd.h>
#define rdmcycle(x) { \
uint32_t lo, hi, hi2; \
__asm__ __volatile__ ("1:\n\t" \
"csrr %0, mcycleh\n\t" \
"csrr %1, mcycle\n\t" \
"csrr %2, mcycleh\n\t" \
"bne %0, %2, 1b\n\t" \
: "=r" (hi), "=r" (lo), "=r" (hi2)) ; \
*(x) = lo | ((uint64_t) hi << 32); \
}
uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq)
{
uint32_t start_mtime = CLINT_REG(CLINT_MTIME);
uint32_t end_mtime = start_mtime + mtime_ticks + 1;
// Make sure we won't get rollover.
while (end_mtime < start_mtime){
start_mtime = CLINT_REG(CLINT_MTIME);
end_mtime = start_mtime + mtime_ticks + 1;
}
// Don't start measuring until mtime edge.
uint32_t tmp = start_mtime;
do {
start_mtime = CLINT_REG(CLINT_MTIME);
} while (start_mtime == tmp);
uint64_t start_mcycle;
rdmcycle(&start_mcycle);
while (CLINT_REG(CLINT_MTIME) < end_mtime) ;
uint64_t end_mcycle;
rdmcycle(&end_mcycle);
uint32_t difference = (uint32_t) (end_mcycle - start_mcycle);
uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks;
return (uint32_t) freq & 0xFFFFFFFF;
}
void PRCI_use_hfrosc(int div, int trim)
{
// Make sure the HFROSC is running at its default setting
// It is OK to change this even if we are running off of it.
PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0);
PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
}
void PRCI_use_pll(int refsel, int bypass,
int r, int f, int q, int finaldiv,
int hfroscdiv, int hfrosctrim)
{
// Ensure that we aren't running off the PLL before we mess with it.
if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
// Make sure the HFROSC is running at its default setting
PRCI_use_hfrosc(4, 16);
}
// Set PLL Source to be HFXOSC if desired.
uint32_t config_value = 0;
config_value |= PLL_REFSEL(refsel);
if (bypass) {
// Bypass
config_value |= PLL_BYPASS(1);
PRCI_REG(PRCI_PLLCFG) = config_value;
// If we don't have an HFXTAL, this doesn't really matter.
// Set our Final output divide to divide-by-1:
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
} else {
// To overclock, use the hfrosc
if (hfrosctrim >= 0 && hfroscdiv >= 0) {
PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
}
// Set DIV Settings for PLL
// (Legal values of f_REF are 6-48MHz)
// Set DIVR to divide-by-2 to get 8MHz frequency
// (legal values of f_R are 6-12 MHz)
config_value |= PLL_BYPASS(1);
config_value |= PLL_R(r);
// Set DIVF to get 512Mhz frequncy
// There is an implied multiply-by-2, 16Mhz.
// So need to write 32-1
// (legal values of f_F are 384-768 MHz)
config_value |= PLL_F(f);
// Set DIVQ to divide-by-2 to get 256 MHz frequency
// (legal values of f_Q are 50-400Mhz)
config_value |= PLL_Q(q);
// Set our Final output divide to divide-by-1:
if (finaldiv == 1){
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
} else {
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1));
}
PRCI_REG(PRCI_PLLCFG) = config_value;
// Un-Bypass the PLL.
PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
// Wait for PLL Lock
// Note that the Lock signal can be glitchy.
// Need to wait 100 us
// RTC is running at 32kHz.
// So wait 4 ticks of RTC.
uint32_t now = CLINT_REG(CLINT_MTIME);
while (CLINT_REG(CLINT_MTIME) - now < 4) ;
// Now it is safe to check for PLL Lock
while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0);
}
// Switch over to PLL Clock source
PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
// If we're running off HFXOSC, turn off the HFROSC to
// save power.
if (refsel) {
PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1);
}
}
void PRCI_use_default_clocks()
{
// Turn off the LFROSC
AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
// Use HFROSC
PRCI_use_hfrosc(4, 16);
}
void PRCI_use_hfxosc(uint32_t finaldiv)
{
PRCI_use_pll(1, // Use HFXTAL
1, // Bypass = 1
0, // PLL settings don't matter
0, // PLL settings don't matter
0, // PLL settings don't matter
finaldiv,
-1,
-1);
}
// This is a generic function, which
// doesn't span the entire range of HFROSC settings.
// It only adjusts the trim, which can span a hundred MHz or so.
// This function does not check the legality of the PLL settings
// at all, and it is quite possible to configure invalid PLL settings
// this way.
// It returns the actual measured CPU frequency.
uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target )
{
uint32_t hfrosctrim = 0;
uint32_t hfroscdiv = 4;
uint32_t prev_trim = 0;
// In this function we use PLL settings which
// will give us a 32x multiplier from the output
// of the HFROSC source to the output of the
// PLL. We first measure our HFROSC to get the
// right trim, then finally use it as the PLL source.
// We should really check here that the f_cpu
// requested is something in the limit of the PLL. For
// now that is up to the user.
// This will undershoot for frequencies not divisible by 16.
uint32_t desired_hfrosc_freq = (f_cpu/ 16);
PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
// Ignore the first run (for icache reasons)
uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
uint32_t prev_freq = cpu_freq;
while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){
prev_trim = hfrosctrim;
prev_freq = cpu_freq;
hfrosctrim ++;
PRCI_use_hfrosc(hfroscdiv, hfrosctrim);
cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ);
}
// We couldn't go low enough
if (prev_freq > desired_hfrosc_freq){
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
return cpu_freq;
}
// We couldn't go high enough
if (cpu_freq < desired_hfrosc_freq){
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
return cpu_freq;
}
// Check for over/undershoot
switch(target) {
case(PRCI_FREQ_CLOSEST):
if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) {
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
} else {
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
}
break;
case(PRCI_FREQ_UNDERSHOOT):
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim);
break;
default:
PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim);
}
cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ);
return cpu_freq;
}
#endif

@ -0,0 +1,79 @@
// See LICENSE file for license details
#ifndef _FE300PRCI_DRIVER_H_
#define _FE300PRCI_DRIVER_H_
__BEGIN_DECLS
#include <unistd.h>
typedef enum prci_freq_target {
PRCI_FREQ_OVERSHOOT,
PRCI_FREQ_CLOSEST,
PRCI_FREQ_UNDERSHOOT
} PRCI_freq_target;
/* Measure and return the approximate frequency of the
* CPU, as given by measuring the mcycle counter against
* the mtime ticks.
*/
uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq);
/* Safely switch over to the HFROSC using the given div
* and trim settings.
*/
void PRCI_use_hfrosc(int div, int trim);
/* Safely switch over to the 16MHz HFXOSC,
* applying the finaldiv clock divider (1 is the lowest
* legal value).
*/
void PRCI_use_hfxosc(uint32_t finaldiv);
/* Safely switch over to the PLL using the given
* settings.
*
* Note that not all combinations of the inputs are actually
* legal, and this function does not check for their
* legality ("safely" means that this function won't turn off
* or glitch the clock the CPU is actually running off, but
* doesn't protect against you making it too fast or slow.)
*/
void PRCI_use_pll(int refsel, int bypass,
int r, int f, int q, int finaldiv,
int hfroscdiv, int hfrosctrim);
/* Use the default clocks configured at reset.
* This is ~16Mhz HFROSC and turns off the LFROSC
* (on the current FE310 Dev Platforms, an external LFROSC is
* used as it is more power efficient).
*/
void PRCI_use_default_clocks();
/* This routine will adjust the HFROSC trim
* while using HFROSC as the clock source,
* measure the resulting frequency, then
* use it as the PLL clock source,
* in an attempt to get over, under, or close to the
* requested frequency. It returns the actual measured
* frequency.
*
* Note that the requested frequency must be within the
* range supported by the PLL so not all values are
* achievable with this function, and not all
* are guaranteed to actually work. The PLL
* is rated higher than the hardware.
*
* There is no check on the desired f_cpu frequency, it
* is up to the user to specify something reasonable.
*/
uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target);
__END_DECLS
#endif

@ -0,0 +1,122 @@
// See LICENSE for license details.
#include "sifive/devices/plic.h"
#include "plic/plic_driver.h"
#include "platform.h"
#include "encoding.h"
#include <string.h>
// Note that there are no assertions or bounds checking on these
// parameter values.
void volatile_memzero(uint8_t * base, unsigned int size)
{
volatile uint8_t * ptr;
for (ptr = base; ptr < (base + size); ptr++){
*ptr = 0;
}
}
void PLIC_init (
plic_instance_t * this_plic,
uintptr_t base_addr,
uint32_t num_sources,
uint32_t num_priorities,
uint32_t target_hartid
)
{
this_plic->base_addr = base_addr;
this_plic->num_sources = num_sources;
this_plic->num_priorities = num_priorities;
this_plic->target_hartid = target_hartid;
// Disable all interrupts (don't assume that these registers are reset).
volatile_memzero((uint8_t*) (this_plic->base_addr +
PLIC_ENABLE_OFFSET +
(this_plic->target_hartid << PLIC_ENABLE_SHIFT_PER_TARGET)),
(num_sources + 8) / 8);
// Set all priorities to 0 (equal priority -- don't assume that these are reset).
volatile_memzero ((uint8_t *)(this_plic->base_addr +
PLIC_PRIORITY_OFFSET),
(num_sources + 1) << PLIC_PRIORITY_SHIFT_PER_SOURCE);
// Set the threshold to 0.
volatile plic_threshold* threshold = (plic_threshold*)
(this_plic->base_addr +
PLIC_THRESHOLD_OFFSET +
(this_plic->target_hartid << PLIC_THRESHOLD_SHIFT_PER_TARGET));
*threshold = 0;
}
void PLIC_set_threshold (plic_instance_t * this_plic,
plic_threshold threshold){
volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr +
PLIC_THRESHOLD_OFFSET +
(this_plic->target_hartid << PLIC_THRESHOLD_SHIFT_PER_TARGET));
*threshold_ptr = threshold;
}
void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){
volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr +
PLIC_ENABLE_OFFSET +
(this_plic->target_hartid << PLIC_ENABLE_SHIFT_PER_TARGET) +
(source >> 3));
uint8_t current = *current_ptr;
current = current | ( 1 << (source & 0x7));
*current_ptr = current;
}
void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){
volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr +
PLIC_ENABLE_OFFSET +
(this_plic->target_hartid << PLIC_ENABLE_SHIFT_PER_TARGET) +
(source >> 3));
uint8_t current = *current_ptr;
current = current & ~(( 1 << (source & 0x7)));
*current_ptr = current;
}
void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority){
if (this_plic->num_priorities > 0) {
volatile plic_priority * priority_ptr = (volatile plic_priority *)
(this_plic->base_addr +
PLIC_PRIORITY_OFFSET +
(source << PLIC_PRIORITY_SHIFT_PER_SOURCE));
*priority_ptr = priority;
}
}
plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){
volatile plic_source * claim_addr = (volatile plic_source * )
(this_plic->base_addr +
PLIC_CLAIM_OFFSET +
(this_plic->target_hartid << PLIC_CLAIM_SHIFT_PER_TARGET));
return *claim_addr;
}
void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){
volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr +
PLIC_CLAIM_OFFSET +
(this_plic->target_hartid << PLIC_CLAIM_SHIFT_PER_TARGET));
*claim_addr = source;
}

@ -0,0 +1,52 @@
// See LICENSE file for licence details
#ifndef PLIC_DRIVER_H
#define PLIC_DRIVER_H
__BEGIN_DECLS
#include "platform.h"
typedef struct __plic_instance_t
{
uintptr_t base_addr;
uint32_t num_sources;
uint32_t num_priorities;
uint32_t target_hartid;
} plic_instance_t;
typedef uint32_t plic_source;
typedef uint32_t plic_priority;
typedef uint32_t plic_threshold;
void PLIC_init (
plic_instance_t * this_plic,
uintptr_t base_addr,
uint32_t num_sources,
uint32_t num_priorities,
uint32_t target_hartid
);
void PLIC_set_threshold (plic_instance_t * this_plic,
plic_threshold threshold);
void PLIC_enable_interrupt (plic_instance_t * this_plic,
plic_source source);
void PLIC_disable_interrupt (plic_instance_t * this_plic,
plic_source source);
void PLIC_set_priority (plic_instance_t * this_plic,
plic_source source,
plic_priority priority);
plic_source PLIC_claim_interrupt(plic_instance_t * this_plic);
void PLIC_complete_interrupt(plic_instance_t * this_plic,
plic_source source);
__END_DECLS
#endif

@ -0,0 +1,66 @@
# See LICENSE for license details.
ifndef _SIFIVE_MK_COMMON
_SIFIVE_MK_COMMON := # defined
.PHONY: all
all: $(TARGET)
include $(BSP_BASE)/libwrap/libwrap.mk
ENV_DIR = $(BSP_BASE)/env
PLATFORM_DIR = $(ENV_DIR)/$(BOARD)
ASM_SRCS += $(ENV_DIR)/start.S
ASM_SRCS += $(ENV_DIR)/entry.S
C_SRCS += $(PLATFORM_DIR)/init.c
LINKER_SCRIPT := $(PLATFORM_DIR)/$(LINK_TARGET).lds
INCLUDES += -I$(BSP_BASE)/include
INCLUDES += -I$(BSP_BASE)/drivers/
INCLUDES += -I$(ENV_DIR)
INCLUDES += -I$(PLATFORM_DIR)
TOOL_DIR ?= $(BSP_BASE)/../toolchain/bin
LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles
LDFLAGS += -L$(ENV_DIR) --specs=nano.specs
ASM_OBJS := $(ASM_SRCS:.S=.o)
C_OBJS := $(C_SRCS:.c=.o)
CXX_OBJS := $(CXX_SRCS:.cpp=.o)
LINK_OBJS += $(ASM_OBJS) $(C_OBJS) $(CXX_OBJS)
LINK_DEPS += $(LINKER_SCRIPT)
CLEAN_OBJS += $(TARGET) $(LINK_OBJS)
CFLAGS += -march=$(RISCV_ARCH)
CFLAGS += -mabi=$(RISCV_ABI)
CFLAGS += -mcmodel=medany
TRIPLET?=riscv64-unknown-elf
CXX=$(TOOL_DIR)/$(TRIPLET)-c++
CC=$(TOOL_DIR)/$(TRIPLET)-gcc
LD=$(TOOL_DIR)/$(TRIPLET)-gcc
AR=$(TOOL_DIR)/$(TRIPLET)-ar
$(TARGET): $(LINK_OBJS) $(LINK_DEPS)
$(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP) -o $@
$(ASM_OBJS): %.o: %.S $(HEADERS)
$(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
$(C_OBJS): %.o: %.c $(HEADERS)
$(CC) $(CFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $<
$(CXX_OBJS): %.o: %.cpp $(HEADERS)
$(CXX) $(CFLAGS) $(CXXFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $<
.PHONY: clean
clean:
rm -f $(CLEAN_OBJS) $(LIBWRAP)
endif # _SIFIVE_MK_COMMON

@ -0,0 +1,161 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
}
PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init :
{
KEEP (*(SORT_NONE(.init)))
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >flash AT>flash :flash
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
} >flash AT>flash :flash
. = ALIGN(4);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >flash AT>flash :flash
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >flash AT>flash :flash
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >flash AT>flash :flash
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >flash AT>flash :flash
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >flash AT>flash :flash
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash :flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram :ram
. = ALIGN(8);
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
}

@ -0,0 +1,98 @@
//See LICENSE for license details.
#include <stdint.h>
#include <stdio.h>
#include <unistd.h>
#include "platform.h"
#include "encoding.h"
#define CPU_FREQ 32000000
#define XSTR(x) #x
#define STR(x) XSTR(x)
extern int main(int argc, char** argv);
unsigned long get_cpu_freq()
{
return CPU_FREQ;
}
unsigned long get_timer_freq()
{
return get_cpu_freq();
}
uint64_t get_timer_value()
{
#if __riscv_xlen == 32
while (1) {
uint32_t hi = read_csr(mcycleh);
uint32_t lo = read_csr(mcycle);
if (hi == read_csr(mcycleh))
return ((uint64_t)hi << 32) | lo;
}
#else
return read_csr(mcycle);
#endif
}
static void uart_init(size_t baud_rate)
{
UART0_REG(UART_REG_DIV) = (get_cpu_freq() ) / baud_rate - 1;
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
}
typedef void (*interrupt_function_ptr_t) (void);
interrupt_function_ptr_t localISR[CLIC_NUM_INTERRUPTS] __attribute__((aligned(64)));
void trap_entry(void) __attribute__((interrupt, aligned(64)));
void trap_entry(void)
{
unsigned long mcause = read_csr(mcause);
unsigned long mepc = read_csr(mepc);
if (mcause & MCAUSE_INT) {
localISR[mcause & MCAUSE_CAUSE] ();
} else {
while(1);
}
}
#ifdef CLIC_DIRECT
#else
void default_handler(void)__attribute__((interrupt));;
#endif
void default_handler(void)
{
puts("default handler\n");
while(1);
}
void _init()
{
#ifndef NO_INIT
uart_init(115200);
puts("core freq at " STR(CPU_FREQ) " Hz\n");
//initialize vector table
int i=0;
while(i<CLIC_NUM_INTERRUPTS) {
localISR[i++] = default_handler;
}
write_csr(mtvt, localISR);
#ifdef CLIC_DIRECT
write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC));
#else
write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC_VECT));
#endif
#endif
}
void _fini()
{
}

@ -0,0 +1,31 @@
# JTAG adapter setup
adapter_khz 10000
interface ftdi
ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
ftdi_vid_pid 0x15ba 0x002a
ftdi_layout_init 0x0808 0x0a1b
ftdi_layout_signal nSRST -oe 0x0200
#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
ftdi_layout_signal LED -data 0x0800
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
# Un-comment these two flash lines if you have a SPI flash and want to write
# it.
flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
init
if {[ info exists pulse_srst]} {
ftdi_set_signal nSRST 0
ftdi_set_signal nSRST z
}
halt
#flash protect 0 64 last off
echo "Ready for Remote Connections"

@ -0,0 +1,98 @@
// See LICENSE for license details.
#ifndef _SIFIVE_PLATFORM_H
#define _SIFIVE_PLATFORM_H
// Some things missing from the official encoding.h
#if __riscv_xlen == 32
#define MCAUSE_INT 0x80000000UL
#define MCAUSE_CAUSE 0x000003FFUL
#else
#define MCAUSE_INT 0x8000000000000000UL
#define MCAUSE_CAUSE 0x00000000000003FFUL
#endif
#define MTVEC_DIRECT 0X00
#define MTVEC_VECTORED 0x01
#define MTVEC_CLIC 0x02
#define MTVEC_CLIC_VECT 0X03
#include "sifive/const.h"
#include "sifive/devices/gpio.h"
#include "sifive/devices/clint.h"
#include "sifive/devices/clic.h"
#include "sifive/devices/pwm.h"
#include "sifive/devices/spi.h"
#include "sifive/devices/uart.h"
/****************************************************************************
* Platform definitions
*****************************************************************************/
// Memory map
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
#define CLIC_HART0_ADDR _AC(0x02800000,UL)
#define GPIO_CTRL_ADDR _AC(0x20002000,UL)
#define PWM0_CTRL_ADDR _AC(0x20005000,UL)
#define RAM_MEM_ADDR _AC(0x80000000,UL)
#define RAM_MEM_SIZE _AC(0x10000,UL)
#define SPI0_CTRL_ADDR _AC(0x20004000,UL)
#define SPI0_MEM_ADDR _AC(0x40000000,UL)
#define SPI0_MEM_SIZE _AC(0x20000000,UL)
#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL)
#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL)
//#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
#define UART0_CTRL_ADDR _AC(0x20000000,UL)
// IOF masks
// Interrupt numbers
#define RESERVED_INT_BASE 0
#define UART0_INT_BASE 1
#define EXTERNAL_INT_BASE 2
#define SPI0_INT_BASE 6
#define GPIO_INT_BASE 7
#define PWM0_INT_BASE 23
// Helper functions
#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
#define CLIC0_REG(offset) _REG32(CLIC_HART0_ADDR, offset)
#define CLIC0_REG8(offset) (*(volatile uint8_t *)((CLIC_HART0_ADDR) + (offset)))
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
#define CLIC0_REG64(offset) _REG64(CLIC_HART0_ADDR, offset)
#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset)
#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset)
#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset)
// Misc
#define NUM_GPIO 16
#define CLIC_NUM_INTERRUPTS 28 + 16
#ifdef E20
#define CLIC_CONFIG_BITS 2
#else
#define CLIC_CONFIG_BITS 4
#endif
#define HAS_BOARD_BUTTONS
#include "coreplexip-arty.h"
unsigned long get_cpu_freq(void);
unsigned long get_timer_freq(void);
uint64_t get_timer_value(void);
#endif /* _SIFIVE_PLATFORM_H */

@ -0,0 +1,3 @@
# Describes the CPU on this board to the rest of the SDK.
RISCV_ARCH := rv32imac
RISCV_ABI := ilp32

@ -0,0 +1,157 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
flash (rxai!w) : ORIGIN = 0x80008000, LENGTH = 32K
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32K
}
PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
.init :
{
KEEP (*(SORT_NONE(.init)))
} >flash AT>flash :flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >flash AT>flash :flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >flash AT>flash :flash
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
. = ALIGN(4);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >flash AT>flash :flash
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >flash AT>flash :flash
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >flash AT>flash :flash
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >flash AT>flash :flash
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >flash AT>flash :flash
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash :flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>flash :ram_init
.data :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>flash :ram_init
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram :ram
. = ALIGN(8);
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
}

@ -0,0 +1,161 @@
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
}
PHDRS
{
ram PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
.init :
{
KEEP (*(SORT_NONE(.init)))
} >ram AT>ram :ram
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >ram AT>ram :ram