mirror of https://github.com/Minres/RDL-Editor.git
107 lines
4.2 KiB
Plaintext
107 lines
4.2 KiB
Plaintext
package com.minres.rdl.generator
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import com.minres.rdl.rdl.ComponentDefinition
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import com.minres.rdl.rdl.ComponentDefinitionType
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import static extension com.minres.rdl.RdlUtil.*
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class ModuleGenerator extends RdlBaseGenerator {
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val ComponentDefinition componentDefinition
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new(ComponentDefinition definition) {
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componentDefinition=definition
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}
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override boolean getOverwrite(){
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false
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}
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override generateHeader(String namespace){
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if(componentDefinition.type!=ComponentDefinitionType.REGFILE) return ''
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val addrMaps = componentDefinition.eResource.resourceSet.allContents
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.filter[ it instanceof ComponentDefinition]
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.map[it as ComponentDefinition]
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.filter[it.type == ComponentDefinitionType.ADDRMAP]
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.filter[def | def.instantiations.filter[it.componentRef==componentDefinition].size>0]
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if(addrMaps.size==0) return ''
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'''
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#ifndef _«namespace.toUpperCase»_«componentDefinition.effectiveName.toUpperCase»_H_
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#define _«namespace.toUpperCase»_«componentDefinition.effectiveName.toUpperCase»_H_
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#include <scc/tlm_target.h>
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namespace «namespace» {
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namespace gen {
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class «componentDefinition.effectiveName»_regs;
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}
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class «componentDefinition.effectiveName» : public sc_core::sc_module, public scc::tlm_target<> {
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public:
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sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
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sc_core::sc_in<bool> rst_i{"rst_i"};
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«componentDefinition.effectiveName»(sc_core::sc_module_name nm);
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virtual ~«componentDefinition.effectiveName»() override;
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protected:
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void clock_cb();
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void reset_cb();
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sc_core::sc_time clk;
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std::unique_ptr<gen::«componentDefinition.effectiveName»_regs> regs;
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};
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} /* namespace «namespace» */
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#endif /* _«namespace.toUpperCase»_«componentDefinition.effectiveName.toUpperCase»_H_ */
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'''
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}
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override generateSource(String namespace) {
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if(componentDefinition.type!=ComponentDefinitionType.REGFILE) return ''
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val addrMaps = componentDefinition.eResource.resourceSet.allContents
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.filter[ it instanceof ComponentDefinition]
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.map[it as ComponentDefinition]
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.filter[it.type == ComponentDefinitionType.ADDRMAP]
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.filter[def | def.instantiations.filter[it.componentRef==componentDefinition].size>0]
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if(addrMaps.size==0) return ''
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'''
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/*
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* Copyright (c) 2019 -2022 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "«componentDefinition.effectiveName».h"
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#include "gen/«componentDefinition.effectiveName».h"
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#include <scc/utilities.h>
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namespace «namespace» {
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SC_HAS_PROCESS(«componentDefinition.effectiveName»);// NOLINT
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«componentDefinition.effectiveName»::«componentDefinition.effectiveName»(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, scc::tlm_target<>(clk)
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, NAMEDD(regs, gen::«componentDefinition.effectiveName»_regs) {
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regs->registerResources(*this);
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SC_METHOD(clock_cb);
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sensitive << clk_i;
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SC_METHOD(reset_cb);
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sensitive << rst_i;
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}
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«componentDefinition.effectiveName»::~«componentDefinition.effectiveName»() {} // NOLINT
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void «componentDefinition.effectiveName»::clock_cb() { this->clk = clk_i.read(); }
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void «componentDefinition.effectiveName»::reset_cb() {
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if (rst_i.read()) {
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regs->reset_start();
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} else {
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regs->reset_stop();
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}
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}
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} /* namespace «namespace» */
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'''
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}
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} |