diff --git a/.gitignore b/.gitignore
index cf64e51..25f64fe 100644
--- a/.gitignore
+++ b/.gitignore
@@ -3,3 +3,6 @@ com.minres.rdl.parent/*/target
*.xtextbin
*.xtendbin
*._trace
+/.envrc
+/*.py
+/*.txt
diff --git a/com.minres.rdl.parent/com.minres.rdl.ide/src-gen/com/minres/rdl/ide/AbstractRDLIdeModule.java b/com.minres.rdl.parent/com.minres.rdl.ide/src-gen/com/minres/rdl/ide/AbstractRDLIdeModule.java
index 04e644e..5dfee80 100644
--- a/com.minres.rdl.parent/com.minres.rdl.ide/src-gen/com/minres/rdl/ide/AbstractRDLIdeModule.java
+++ b/com.minres.rdl.parent/com.minres.rdl.ide/src-gen/com/minres/rdl/ide/AbstractRDLIdeModule.java
@@ -16,8 +16,6 @@ import org.eclipse.xtext.ide.editor.contentassist.antlr.AntlrProposalConflictHel
import org.eclipse.xtext.ide.editor.contentassist.antlr.IContentAssistParser;
import org.eclipse.xtext.ide.editor.contentassist.antlr.internal.Lexer;
import org.eclipse.xtext.ide.refactoring.IRenameStrategy2;
-import org.eclipse.xtext.ide.server.rename.IRenameService;
-import org.eclipse.xtext.ide.server.rename.RenameService;
/**
* Manual modifications go to {@link RDLIdeModule}.
@@ -47,11 +45,6 @@ public abstract class AbstractRDLIdeModule extends DefaultIdeModule {
return FQNPrefixMatcher.class;
}
- // contributed by org.eclipse.xtext.xtext.generator.ui.refactoring.RefactorElementNameFragment2
- public Class extends IRenameService> bindIRenameService() {
- return RenameService.class;
- }
-
// contributed by org.eclipse.xtext.xtext.generator.ui.refactoring.RefactorElementNameFragment2
public Class extends IRenameStrategy2> bindIRenameStrategy2() {
return IRenameStrategy2.DefaultImpl.class;
diff --git a/com.minres.rdl.parent/com.minres.rdl.ide/xtend-gen/com/minres/rdl/ide/RDLIdeModule.java b/com.minres.rdl.parent/com.minres.rdl.ide/xtend-gen/com/minres/rdl/ide/RDLIdeModule.java
index d5f95b6..3af4dcc 100644
--- a/com.minres.rdl.parent/com.minres.rdl.ide/xtend-gen/com/minres/rdl/ide/RDLIdeModule.java
+++ b/com.minres.rdl.parent/com.minres.rdl.ide/xtend-gen/com/minres/rdl/ide/RDLIdeModule.java
@@ -3,8 +3,6 @@
*/
package com.minres.rdl.ide;
-import com.minres.rdl.ide.AbstractRDLIdeModule;
-
/**
* Use this class to register ide components.
*/
diff --git a/com.minres.rdl.parent/com.minres.rdl.ide/xtend-gen/com/minres/rdl/ide/RDLIdeSetup.java b/com.minres.rdl.parent/com.minres.rdl.ide/xtend-gen/com/minres/rdl/ide/RDLIdeSetup.java
index 8cbc604..1b08293 100644
--- a/com.minres.rdl.parent/com.minres.rdl.ide/xtend-gen/com/minres/rdl/ide/RDLIdeSetup.java
+++ b/com.minres.rdl.parent/com.minres.rdl.ide/xtend-gen/com/minres/rdl/ide/RDLIdeSetup.java
@@ -7,7 +7,6 @@ import com.google.inject.Guice;
import com.google.inject.Injector;
import com.minres.rdl.RDLRuntimeModule;
import com.minres.rdl.RDLStandaloneSetup;
-import com.minres.rdl.ide.RDLIdeModule;
import org.eclipse.xtext.util.Modules2;
/**
diff --git a/com.minres.rdl.parent/com.minres.rdl.target/com.minres.rdl.target.target b/com.minres.rdl.parent/com.minres.rdl.target/com.minres.rdl.target.target
index fbd1431..d222fbc 100644
--- a/com.minres.rdl.parent/com.minres.rdl.target/com.minres.rdl.target.target
+++ b/com.minres.rdl.parent/com.minres.rdl.target/com.minres.rdl.target.target
@@ -1,25 +1,37 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/com.minres.rdl.parent/com.minres.rdl.tests/xtend-gen/com/minres/rdl/tests/RDLParsingTest.java b/com.minres.rdl.parent/com.minres.rdl.tests/xtend-gen/com/minres/rdl/tests/RDLParsingTest.java
index 052fc47..d5cf24d 100644
--- a/com.minres.rdl.parent/com.minres.rdl.tests/xtend-gen/com/minres/rdl/tests/RDLParsingTest.java
+++ b/com.minres.rdl.parent/com.minres.rdl.tests/xtend-gen/com/minres/rdl/tests/RDLParsingTest.java
@@ -5,7 +5,6 @@ package com.minres.rdl.tests;
import com.google.inject.Inject;
import com.minres.rdl.rdl.Root;
-import com.minres.rdl.tests.RDLInjectorProvider;
import org.eclipse.emf.common.util.EList;
import org.eclipse.emf.ecore.resource.Resource;
import org.eclipse.xtend2.lib.StringConcatenation;
diff --git a/com.minres.rdl.parent/com.minres.rdl.ui/src/com/minres/rdl/ui/labeling/RDLLabelProvider.xtend b/com.minres.rdl.parent/com.minres.rdl.ui/src/com/minres/rdl/ui/labeling/RDLLabelProvider.xtend
index 882f376..5f16be2 100644
--- a/com.minres.rdl.parent/com.minres.rdl.ui/src/com/minres/rdl/ui/labeling/RDLLabelProvider.xtend
+++ b/com.minres.rdl.parent/com.minres.rdl.ui/src/com/minres/rdl/ui/labeling/RDLLabelProvider.xtend
@@ -43,7 +43,10 @@ class RDLLabelProvider extends DefaultEObjectLabelProvider {
val pa = e.propertyAssignments.findFirst[PropertyAssignment pa |
pa instanceof ExplicitPropertyAssignment && (pa as ExplicitPropertyAssignment).name==PropertyEnum.NAME
]
- e.type.literal+' '+ text((pa as ExplicitPropertyAssignment).rhs)
+ if(pa!== null)
+ e.type.literal+' '+ text((pa as ExplicitPropertyAssignment).rhs)
+ else
+ e.type.literal
}
}
diff --git a/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/RDLUiModule.java b/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/RDLUiModule.java
index 699aff6..537aaf8 100644
--- a/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/RDLUiModule.java
+++ b/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/RDLUiModule.java
@@ -3,9 +3,6 @@
*/
package com.minres.rdl.ui;
-import com.minres.rdl.ui.AbstractRDLUiModule;
-import com.minres.rdl.ui.RDLEObjectDocumentationProvider;
-import com.minres.rdl.ui.RDLEObjectHoverProvider;
import com.minres.structural.ui.hyperlink.MyHyperlinkHelper;
import com.minres.structural.ui.hyperlink.MyXtextHyperlink;
import org.eclipse.ui.plugin.AbstractUIPlugin;
diff --git a/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/contentassist/RDLProposalProvider.java b/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/contentassist/RDLProposalProvider.java
index 561b4e8..39107b1 100644
--- a/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/contentassist/RDLProposalProvider.java
+++ b/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/contentassist/RDLProposalProvider.java
@@ -3,8 +3,6 @@
*/
package com.minres.rdl.ui.contentassist;
-import com.minres.rdl.ui.contentassist.AbstractRDLProposalProvider;
-
/**
* See https://www.eclipse.org/Xtext/documentation/304_ide_concepts.html#content-assist
* on how to customize the content assistant.
diff --git a/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/labeling/RDLLabelProvider.java b/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/labeling/RDLLabelProvider.java
index 09d07d8..0e8bb5c 100644
--- a/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/labeling/RDLLabelProvider.java
+++ b/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/labeling/RDLLabelProvider.java
@@ -58,10 +58,16 @@ public class RDLLabelProvider extends DefaultEObjectLabelProvider {
return Boolean.valueOf(((pa instanceof ExplicitPropertyAssignment) && Objects.equal(((ExplicitPropertyAssignment) pa).getName(), PropertyEnum.NAME)));
};
final PropertyAssignment pa = IterableExtensions.findFirst(e.getPropertyAssignments(), _function);
- String _literal_1 = e.getType().getLiteral();
- String _plus_1 = (_literal_1 + " ");
- Object _text = this.text(((ExplicitPropertyAssignment) pa).getRhs());
- _xblockexpression = (_plus_1 + _text);
+ String _xifexpression_1 = null;
+ if ((pa != null)) {
+ String _literal_1 = e.getType().getLiteral();
+ String _plus_1 = (_literal_1 + " ");
+ Object _text = this.text(((ExplicitPropertyAssignment) pa).getRhs());
+ _xifexpression_1 = (_plus_1 + _text);
+ } else {
+ _xifexpression_1 = e.getType().getLiteral();
+ }
+ _xblockexpression = _xifexpression_1;
}
_xifexpression = _xblockexpression;
}
diff --git a/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/wizard/RDLProjectTemplateProvider.java b/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/wizard/RDLProjectTemplateProvider.java
index e7d1025..178bd47 100644
--- a/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/wizard/RDLProjectTemplateProvider.java
+++ b/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/rdl/ui/wizard/RDLProjectTemplateProvider.java
@@ -3,7 +3,6 @@
*/
package com.minres.rdl.ui.wizard;
-import com.minres.rdl.ui.wizard.RdlProject;
import org.eclipse.xtext.ui.wizard.template.AbstractProjectTemplate;
import org.eclipse.xtext.ui.wizard.template.IProjectTemplateProvider;
diff --git a/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/structural/ui/hyperlink/MyHyperlinkHelper.java b/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/structural/ui/hyperlink/MyHyperlinkHelper.java
index 545637e..ec3c325 100644
--- a/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/structural/ui/hyperlink/MyHyperlinkHelper.java
+++ b/com.minres.rdl.parent/com.minres.rdl.ui/xtend-gen/com/minres/structural/ui/hyperlink/MyHyperlinkHelper.java
@@ -1,7 +1,6 @@
package com.minres.structural.ui.hyperlink;
import com.google.inject.Inject;
-import com.minres.structural.ui.hyperlink.MyXtextHyperlink;
import org.eclipse.emf.common.util.URI;
import org.eclipse.emf.ecore.EObject;
import org.eclipse.emf.ecore.resource.Resource;
diff --git a/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLServlet.java b/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLServlet.java
index a0ff00d..c53616a 100644
--- a/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLServlet.java
+++ b/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLServlet.java
@@ -4,7 +4,6 @@
package com.minres.rdl.web;
import com.google.inject.Injector;
-import com.minres.rdl.web.RDLWebSetup;
import javax.servlet.annotation.WebServlet;
import org.eclipse.xtext.util.DisposableRegistry;
import org.eclipse.xtext.web.servlet.XtextServlet;
diff --git a/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLWebModule.java b/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLWebModule.java
index cf4d468..4911369 100644
--- a/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLWebModule.java
+++ b/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLWebModule.java
@@ -3,8 +3,6 @@
*/
package com.minres.rdl.web;
-import com.minres.rdl.web.AbstractRDLWebModule;
-
/**
* Use this class to register additional components to be used within the web application.
*/
diff --git a/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLWebSetup.java b/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLWebSetup.java
index 463acdd..ded8df7 100644
--- a/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLWebSetup.java
+++ b/com.minres.rdl.parent/com.minres.rdl.web/xtend-gen/com/minres/rdl/web/RDLWebSetup.java
@@ -8,7 +8,6 @@ import com.google.inject.Injector;
import com.minres.rdl.RDLRuntimeModule;
import com.minres.rdl.RDLStandaloneSetup;
import com.minres.rdl.ide.RDLIdeModule;
-import com.minres.rdl.web.RDLWebModule;
import org.eclipse.xtext.util.Modules2;
/**
diff --git a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/GenerateRDL.mwe2 b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/GenerateRDL.mwe2
index a0fe5b9..ae8bcff 100644
--- a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/GenerateRDL.mwe2
+++ b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/GenerateRDL.mwe2
@@ -30,6 +30,7 @@ Workflow {
encoding = "UTF-8"
lineDelimiter = "\n"
fileHeader = "/*\n * generated by Xtext \${version}\n */"
+ preferXtendStubs = false
}
}
language = StandardLanguage {
@@ -53,8 +54,10 @@ Workflow {
}
validator = {
- // composedCheck = "org.eclipse.xtext.validation.NamesAreUniqueValidator"
composedCheck = "org.eclipse.xtext.validation.ImportUriValidator"
+ // composedCheck = "org.eclipse.xtext.validation.NamesAreUniqueValidator"
+ // Generates checks for @Deprecated grammar annotations, an IssueProvider and a corresponding PropertyPage
+ generateDeprecationValidation = true
}
generator = {
@@ -64,6 +67,9 @@ Workflow {
projectWizard = {
generate = true
}
+ junitSupport = {
+ junitVersion = "5"
+ }
}
}
}
diff --git a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/RdlUtil.xtend b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/RdlUtil.xtend
index 16ac2e2..ea49869 100644
--- a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/RdlUtil.xtend
+++ b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/RdlUtil.xtend
@@ -11,6 +11,7 @@ import com.minres.rdl.rdl.PropertyAssignmentRhs
import com.minres.rdl.rdl.RValue
import com.minres.rdl.rdl.RValueConstant
import com.minres.rdl.rdl.InstancePropertyRef
+import com.minres.rdl.rdl.Range
class RdlUtil {
@@ -153,5 +154,44 @@ class RdlUtil {
componentSize = subInstantiation.byteSize(componentSize)
return componentSize
}
-
+
+ static def ComponentDefinition getComponentDefinition(Instantiation instantiation) {
+ if(instantiation.component!==null) instantiation.component else instantiation.componentRef
+ }
+
+ static def long absSize(Range range){
+ if(range.size!==null)
+ return (range.size as IntegerWithRadix).value
+ else
+ return Math.abs((range.left as IntegerWithRadix).value - (range.right as IntegerWithRadix).value)+1
+ }
+
+ static def boolean isFilledByField(Instantiation instantiation){
+ val fieldCount = instantiation.componentDefinition.instanceCountOfType(ComponentDefinitionType.FIELD)
+ if(fieldCount==1) {
+ val instSize=instantiation.size
+ val field = instantiation.component.instantiationsOfType(ComponentDefinitionType.FIELD).get(0)
+ val inst = field.componentInstances.get(0)
+ val range = inst.range
+ if(range===null)
+ return instSize==field.size
+ if(range.size !== null)
+ return instSize==(range.size as IntegerWithRadix).value
+ else {
+ val left=(range.left as IntegerWithRadix).value
+ val right=(range.right as IntegerWithRadix).value
+ val size = if(left>right) left-right+1 else right-left+1
+ return instSize==size
+ }
+ }
+ return false
+ }
+
+ static def int instanceCountOfType(ComponentDefinition definition, ComponentDefinitionType type){
+ val insts = definition.instantiationsOfType(type)
+ if(insts.size>0) {
+ insts.map[it.componentInstances.size].reduce[p1, p2| p1+p2]
+ } else
+ 0
+ }
}
\ No newline at end of file
diff --git a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/AddrmapGenerator.xtend b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/AddrmapGenerator.xtend
index ac7ecc0..24a279c 100644
--- a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/AddrmapGenerator.xtend
+++ b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/AddrmapGenerator.xtend
@@ -13,14 +13,18 @@ class AddrmapGenerator extends RdlBaseGenerator {
componentDefinition=definition
}
- override generateHeader() {'''
+ override boolean getOverwrite(){
+ true
+ }
+
+ override generateHeader(String namespace) {'''
#ifndef _«componentDefinition.effectiveName.toUpperCase»_MAP_H_
#define _«componentDefinition.effectiveName.toUpperCase»_MAP_H_
// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
- const std::array, «componentDefinition.instanceCount(ComponentDefinitionType.REGFILE)»> «componentDefinition.effectiveName»_map = {{
+ const std::array, «componentDefinition.instanceCount(ComponentDefinitionType.REGFILE)»> «componentDefinition.effectiveName»_map = {{
«FOR instantiation : componentDefinition.instantiationsOfType(ComponentDefinitionType.REGFILE)»
«FOR instance : instantiation.componentInstances»
- {&i_«instance.name», «instance.addressValue», 0x«Long.toHexString(instantiation.byteSize)»},
+ {i_«instance.name».socket, «instance.addressValue», 0x«Long.toHexString(instantiation.byteSize)»},
«ENDFOR»
«ENDFOR»
}};
@@ -29,7 +33,7 @@ class AddrmapGenerator extends RdlBaseGenerator {
'''
}
- override generateSource() {
+ override generateSource(String namespace) {
''
}
diff --git a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/FwAddrmapGenerator.xtend b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/FwAddrmapGenerator.xtend
index cfa3d37..0287e49 100644
--- a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/FwAddrmapGenerator.xtend
+++ b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/FwAddrmapGenerator.xtend
@@ -16,9 +16,13 @@ class FwAddrmapGenerator extends RdlBaseGenerator {
val nameMap = newLinkedHashSet()
- override generateHeader() {'''
+ override boolean getOverwrite(){
+ true
+ }
+
+ override generateHeader(String namespace) {'''
////////////////////////////////////////////////////////////////////////////////
- // Copyright (C) 2020, MINRES Technologies GmbH
+ // Copyright (C) 2020-2022, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -57,10 +61,10 @@ class FwAddrmapGenerator extends RdlBaseGenerator {
«FOR instantiation : componentDefinition.instantiationsOfType(ComponentDefinitionType.REGFILE)»
«IF instantiation.component !== null && !nameMap.contains(instantiation.component.name)»
- #include "«instantiation.component.name».h"«nameMap.add(instantiation.component.name)»
+ #include "«instantiation.component.name».h"«nameMap.add(instantiation.component.name)?"":""»
«ENDIF»
«IF instantiation.componentRef !== null && !nameMap.contains(instantiation.componentRef.name)»
- #include "«instantiation.componentRef.name».h"«nameMap.add(instantiation.componentRef.name)»
+ #include "«instantiation.componentRef.name».h"«nameMap.add(instantiation.componentRef.name)?"":""»
«ENDIF»
«ENDFOR»
@@ -80,7 +84,7 @@ class FwAddrmapGenerator extends RdlBaseGenerator {
'''
}
- override generateSource() {
+ override generateSource(String namespace) {
''
}
}
\ No newline at end of file
diff --git a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/FwRegfileGenerator.xtend b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/FwRegfileGenerator.xtend
index 8cdcba3..10bdbff 100644
--- a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/FwRegfileGenerator.xtend
+++ b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/FwRegfileGenerator.xtend
@@ -6,7 +6,6 @@ import com.minres.rdl.rdl.ComponentDefinitionType
import com.minres.rdl.rdl.ComponentInstance
import com.minres.rdl.rdl.Instantiation
import java.util.Date
-import com.minres.rdl.rdl.Range
import static extension com.minres.rdl.RdlUtil.*
@@ -18,9 +17,13 @@ class FwRegfileGenerator extends RdlBaseGenerator{
componentDefinition=definition
}
- override String generateHeader()'''
+ override boolean getOverwrite(){
+ true
+ }
+
+ override String generateHeader(String namespace)'''
////////////////////////////////////////////////////////////////////////////////
- // Copyright (C) 2020, MINRES Technologies GmbH
+ // Copyright (C) 2020-2022, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -117,40 +120,8 @@ class FwRegfileGenerator extends RdlBaseGenerator{
#endif // _«componentDefinition.name.toUpperCase»_H_
'''
-
- def long absSize(Range range){
- if(range.size!==null)
- return (range.size as IntegerWithRadix).value
- else
- return Math.abs((range.left as IntegerWithRadix).value - (range.right as IntegerWithRadix).value)+1
- }
-
- def boolean isFilledByField(Instantiation instantiation){
- val fieldCount = instantiation.component.instanceCountOfType(ComponentDefinitionType.FIELD)
- if(fieldCount==1) {
- val instSize=instantiation.size
- val field = instantiation.component.instantiationsOfType(ComponentDefinitionType.FIELD).get(0)
- val inst = field.componentInstances.get(0)
- val range = inst.range
- if(range===null)
- return instSize==field.size
- if(range.size !== null)
- return instSize==(range.size as IntegerWithRadix).value
- else {
- val left=(range.left as IntegerWithRadix).value
- val right=(range.right as IntegerWithRadix).value
- val size = if(left>right) left-right+1 else right-left+1
- return instSize==size
- }
- }
- return false
- }
-
- def int instanceCountOfType(ComponentDefinition definition, ComponentDefinitionType type){
- definition.instantiationsOfType(type).map[it.componentInstances.size].reduce[p1, p2|p1+p1]
- }
-
- override generateSource() {
+
+ override generateSource(String namespace) {
''
}
diff --git a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/Main.xtend b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/Main.xtend
index cef6f52..5cd2c8b 100644
--- a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/Main.xtend
+++ b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/Main.xtend
@@ -23,7 +23,7 @@ import org.eclipse.xtext.generator.IFileSystemAccess
class Main {
- val USAGE_STR = "RDL2code [-h] [-v] [-I ] ";
+ val USAGE_STR = "RDL2code [-h] [-v] [-f] [-n ] [-I ] ";
def static main(String[] args) {
if (args.empty) {
@@ -60,6 +60,8 @@ class Main {
val opt = new Options(args, 0, Integer.MAX_VALUE);
opt.getSet().addOption("h", Multiplicity.ZERO_OR_ONE);
opt.getSet().addOption("v", Multiplicity.ZERO_OR_ONE);
+ opt.getSet().addOption("f", Multiplicity.ZERO_OR_ONE);
+ opt.getSet().addOption("n", Separator.BLANK, Multiplicity.ZERO_OR_ONE);
opt.getSet().addOption("o", Separator.BLANK, Multiplicity.ZERO_OR_ONE);
opt.getSet().addOption("I", Separator.BLANK, Multiplicity.ZERO_OR_ONE);
if (!opt.check(false, false)) { // Print usage hints
@@ -106,7 +108,10 @@ class Main {
throw new ParseException("error validating " + resource.URI, issues.size)
}
- val context = new GeneratorContext => [cancelIndicator = CancelIndicator.NullImpl]
+ val context = new RdlGeneratorContext => [cancelIndicator = CancelIndicator.NullImpl]
+ context.forceOverwrite= opt.getSet().isSet('f')
+ if(opt.getSet().isSet('n'))
+ context.namespace=opt.getSet().getOption('n').getResultValue(0)
generator.generate(resource, fileAccess, context)
if(verbose) println('Code generation for ' + string + ' finished')
diff --git a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/ModuleGenerator.xtend b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/ModuleGenerator.xtend
new file mode 100644
index 0000000..6981494
--- /dev/null
+++ b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/ModuleGenerator.xtend
@@ -0,0 +1,107 @@
+package com.minres.rdl.generator
+
+import com.minres.rdl.rdl.ComponentDefinition
+import com.minres.rdl.rdl.ComponentDefinitionType
+
+import static extension com.minres.rdl.RdlUtil.*
+
+class ModuleGenerator extends RdlBaseGenerator {
+
+ val ComponentDefinition componentDefinition
+
+ new(ComponentDefinition definition) {
+ componentDefinition=definition
+ }
+
+ override boolean getOverwrite(){
+ false
+ }
+
+ override generateHeader(String namespace){
+ if(componentDefinition.type!=ComponentDefinitionType.REGFILE) return ''
+ val addrMaps = componentDefinition.eResource.resourceSet.allContents
+ .filter[ it instanceof ComponentDefinition]
+ .map[it as ComponentDefinition]
+ .filter[it.type == ComponentDefinitionType.ADDRMAP]
+ .filter[def | def.instantiations.filter[it.componentRef==componentDefinition].size>0]
+ if(addrMaps.size==0) return ''
+ '''
+ #ifndef _«namespace.toUpperCase»_«componentDefinition.effectiveName.toUpperCase»_H_
+ #define _«namespace.toUpperCase»_«componentDefinition.effectiveName.toUpperCase»_H_
+ #include
+
+ namespace «namespace» {
+ namespace gen {
+ class «componentDefinition.effectiveName»_regs;
+ }
+
+ class «componentDefinition.effectiveName» : public sc_core::sc_module, public scc::tlm_target<> {
+ public:
+ sc_core::sc_in clk_i{"clk_i"};
+ sc_core::sc_in rst_i{"rst_i"};
+ «componentDefinition.effectiveName»(sc_core::sc_module_name nm);
+ virtual ~«componentDefinition.effectiveName»() override;
+
+ protected:
+ void clock_cb();
+ void reset_cb();
+ sc_core::sc_time clk;
+ std::unique_ptr regs;
+ };
+
+ } /* namespace «namespace» */
+
+ #endif /* _«namespace.toUpperCase»_«componentDefinition.effectiveName.toUpperCase»_H_ */
+ '''
+ }
+
+ override generateSource(String namespace) {
+ if(componentDefinition.type!=ComponentDefinitionType.REGFILE) return ''
+ val addrMaps = componentDefinition.eResource.resourceSet.allContents
+ .filter[ it instanceof ComponentDefinition]
+ .map[it as ComponentDefinition]
+ .filter[it.type == ComponentDefinitionType.ADDRMAP]
+ .filter[def | def.instantiations.filter[it.componentRef==componentDefinition].size>0]
+ if(addrMaps.size==0) return ''
+ '''
+ /*
+ * Copyright (c) 2019 -2022 MINRES Technologies GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ #include "«componentDefinition.effectiveName».h"
+ #include "gen/«componentDefinition.effectiveName».h"
+
+ #include
+
+ namespace «namespace» {
+ SC_HAS_PROCESS(«componentDefinition.effectiveName»);// NOLINT
+
+ «componentDefinition.effectiveName»::«componentDefinition.effectiveName»(sc_core::sc_module_name nm)
+ : sc_core::sc_module(nm)
+ , scc::tlm_target<>(clk)
+ , NAMEDD(regs, gen::«componentDefinition.effectiveName»_regs) {
+ regs->registerResources(*this);
+ SC_METHOD(clock_cb);
+ sensitive << clk_i;
+ SC_METHOD(reset_cb);
+ sensitive << rst_i;
+ }
+
+ «componentDefinition.effectiveName»::~«componentDefinition.effectiveName»() {} // NOLINT
+
+ void «componentDefinition.effectiveName»::clock_cb() { this->clk = clk_i.read(); }
+
+ void «componentDefinition.effectiveName»::reset_cb() {
+ if (rst_i.read()) {
+ regs->reset_start();
+ } else {
+ regs->reset_stop();
+ }
+ }
+
+ } /* namespace «namespace» */
+ '''
+ }
+}
\ No newline at end of file
diff --git a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RDLGenerator.xtend b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RDLGenerator.xtend
index 6ada4fe..9894b9f 100644
--- a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RDLGenerator.xtend
+++ b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RDLGenerator.xtend
@@ -18,25 +18,35 @@ import java.util.Map
* See https://www.eclipse.org/Xtext/documentation/303_runtime_concepts.html#code-generation
*/
class RDLGenerator extends AbstractGenerator {
-
override void doGenerate(Resource resource, IFileSystemAccess2 fsa, IGeneratorContext context) {
+ val force = if(context instanceof RdlGeneratorContext) context.forceOverwrite else false
+ val namespace = if(context instanceof RdlGeneratorContext) context.namespace else "sysc"
resource.resourceSet.allContents.filter[ it instanceof ComponentDefinition].map[it as ComponentDefinition].forEach[
val genMap = it.fileGenerator
if(genMap!==null) genMap.forEach[p1, gen |
- val header = gen.generateHeader
- if(header!==null && header.length>0)
- fsa.generateFile(p1+'/'+it.effectiveName+'.h', fsa.outputConfig('incl-out'), header)
- val source = gen.generateSource
- if(source!==null && source.length>0)
- fsa.generateFile(p1+'/'+it.effectiveName+'.cpp', fsa.outputConfig('src-out'), source)
+ val header = gen.generateHeader(namespace)
+ val inclFileName = p1+'/'+it.effectiveName+'.h'
+ val inclCfg = fsa.outputConfig('incl-out')
+ if((force || !fsa.isFile(inclFileName, inclCfg) || gen.overwrite) && header!==null && header.length>0)
+ fsa.generateFile(inclFileName, inclCfg, header)
+ val source = gen.generateSource(namespace)
+ val srcFileName = p1+'/'+it.effectiveName+'.cpp'
+ val srcCfg = fsa.outputConfig('src-out')
+ if((force || !fsa.isFile(srcFileName, srcCfg) || gen.overwrite) && source!==null && source.length>0)
+ fsa.generateFile(srcFileName, srcCfg, source)
]
]
}
-
+
def Map fileGenerator(ComponentDefinition definition){
switch(definition.type){
- case ComponentDefinitionType.REGFILE: #{'vp' -> new RegfileGenerator(definition), 'fw' -> new FwRegfileGenerator(definition)}
- case ComponentDefinitionType.ADDRMAP: #{'vp' -> new AddrmapGenerator(definition), 'fw' -> new FwAddrmapGenerator(definition)}
+ case ComponentDefinitionType.REGFILE: #{
+ 'gen' -> new RegfileGenerator(definition),
+ 'fw' -> new FwRegfileGenerator(definition),
+ '.' -> new ModuleGenerator(definition)}
+ case ComponentDefinitionType.ADDRMAP: #{
+ 'gen' -> new AddrmapGenerator(definition),
+ 'fw' -> new FwAddrmapGenerator(definition)}
default: null
}
}
diff --git a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RdlBaseGenerator.xtend b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RdlBaseGenerator.xtend
index 5343dd9..e0cb61b 100644
--- a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RdlBaseGenerator.xtend
+++ b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RdlBaseGenerator.xtend
@@ -2,8 +2,10 @@ package com.minres.rdl.generator
abstract class RdlBaseGenerator {
- def String generateHeader()
+ def String generateHeader(String namespace)
- def String generateSource()
+ def String generateSource(String namespace)
+
+ def boolean getOverwrite()
}
\ No newline at end of file
diff --git a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RdlGeneratorContext.xtend b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RdlGeneratorContext.xtend
new file mode 100644
index 0000000..495d8ac
--- /dev/null
+++ b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RdlGeneratorContext.xtend
@@ -0,0 +1,8 @@
+package com.minres.rdl.generator
+
+import org.eclipse.xtext.generator.GeneratorContext
+
+class RdlGeneratorContext extends GeneratorContext {
+ public boolean forceOverwrite = false
+ public String namespace ="scc"
+}
\ No newline at end of file
diff --git a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RegfileGenerator.xtend b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RegfileGenerator.xtend
index a74635f..9d3d0af 100644
--- a/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RegfileGenerator.xtend
+++ b/com.minres.rdl.parent/com.minres.rdl/src/com/minres/rdl/generator/RegfileGenerator.xtend
@@ -6,7 +6,6 @@ import com.minres.rdl.rdl.ComponentDefinitionType
import com.minres.rdl.rdl.ComponentInstance
import com.minres.rdl.rdl.Instantiation
import java.util.Date
-import com.minres.rdl.rdl.Range
import static extension com.minres.rdl.RdlUtil.*
@@ -18,9 +17,13 @@ class RegfileGenerator extends RdlBaseGenerator{
componentDefinition=definition
}
- override String generateHeader()'''
+ override boolean getOverwrite(){
+ true
+ }
+
+ override String generateHeader(String namespace)'''
////////////////////////////////////////////////////////////////////////////////
- // Copyright (C) 2017, MINRES Technologies GmbH
+ // Copyright (C) 2017-2022, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -50,26 +53,34 @@ class RegfileGenerator extends RdlBaseGenerator{
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: «new Date»
- // * «componentDefinition.name».h Author:
+ // * «componentDefinition.effectiveName».h Author:
//
////////////////////////////////////////////////////////////////////////////////
- #ifndef _«componentDefinition.name.toUpperCase»_H_
- #define _«componentDefinition.name.toUpperCase»_H_
+ #ifndef _«namespace.toUpperCase»_GEN_«componentDefinition.effectiveName.toUpperCase»_H_
+ #define _«namespace.toUpperCase»_GEN_«componentDefinition.effectiveName.toUpperCase»_H_
- #include
+ #include
#include
- #include
- #include
+ #include
+ #include
+ «FOR instantiation : componentDefinition.instantiations»
+ «IF instantiation.componentDefinition.type == ComponentDefinitionType.REGFILE»
+ #include "«instantiation.componentDefinition.effectiveName».h"
+ «ENDIF»
+ «ENDFOR»
- namespace sysc {
+ namespace «namespace» {
+ namespace gen {
- class «componentDefinition.name» :
+ class «componentDefinition.effectiveName»_regs :
public sc_core::sc_module,
- public sysc::resetable
+ public scc::resetable
{
public:
+ //////////////////////////////////////////////////////////////////////////////
// storage declarations
+ //////////////////////////////////////////////////////////////////////////////
«FOR cdef : componentDefinition.componentDefinitions»
«IF cdef.type == ComponentDefinitionType.REG»
BEGIN_BF_DECL(«cdef.effectiveName»+'_t'», uint«cdef»_t);
@@ -78,10 +89,11 @@ class RegfileGenerator extends RdlBaseGenerator{
«ENDIF»
«ENDFOR»
«FOR instantiation : componentDefinition.instantiations»
- «IF instantiation.componentRef !==null && instantiation.componentRef.type == ComponentDefinitionType.REG»
- «instantiation.componentRef.effectiveName»+'_t' «instantiation.componentInstances.map[it.name].join(', ')»;
- «ENDIF»
- «IF instantiation.component !== null && instantiation.component.type == ComponentDefinitionType.REG»
+ «IF instantiation.componentDefinition.type == ComponentDefinitionType.REGFILE»
+ «FOR instance : instantiation.componentInstances»
+ «instantiation.componentDefinition.effectiveName»_regs i_«instance.name»{"«instance.name»"};
+ «ENDFOR»
+ «ELSEIF instantiation.componentDefinition.type == ComponentDefinitionType.REG»
«IF instantiation.isFilledByField»
«IF instantiation.componentInstances.filter[it.range===null].size>0»
uint«instantiation.size»_t «instantiation.componentInstances.filter[it.range===null].map['r_'+it.name].join(', ')»;
@@ -89,8 +101,14 @@ class RegfileGenerator extends RdlBaseGenerator{
«FOR componentInstance : instantiation.componentInstances.filter[it.range!==null]»
std::array r_«componentInstance.name»;
«ENDFOR»
- «ENDIF»
- «IF !instantiation.isFilledByField»
+ «ELSEIF instantiation.componentDefinition.instantiations.size==0»
+ «IF instantiation.componentInstances.filter[it.range===null].size>0»
+ uint«instantiation.size»_t «instantiation.componentInstances.filter[it.range===null].map['r_'+it.name].join(', ')»;
+ «ENDIF»
+ «FOR componentInstance : instantiation.componentInstances.filter[it.range!==null]»
+ std::array r_«componentInstance.name»;
+ «ENDFOR»
+ «ELSE»
BEGIN_BF_DECL(«instantiation.component.effectiveName»_t, uint«instantiation.size»_t);
«instantiation.definingComponent.genFieldDeclarations»
END_BF_DECL() «instantiation.componentInstances.filter[it.range===null].map['r_'+it.name].join(', ')»;
@@ -98,96 +116,79 @@ class RegfileGenerator extends RdlBaseGenerator{
std::array<«instantiation.component.effectiveName»_t, «componentInstance.range.absSize»> r_«componentInstance.name»;
«ENDFOR»
«ENDIF»
-
«ENDIF»
«ENDFOR»
+ //////////////////////////////////////////////////////////////////////////////
// register declarations
+ //////////////////////////////////////////////////////////////////////////////
«FOR instantiation : componentDefinition.instantiations»
«FOR instance : instantiation.componentInstances»
- «IF instance.range===null»
- «IF instantiation.isFilledByField»
- sysc::sc_register «instance.name»;
- «ENDIF»
- «IF !instantiation.isFilledByField»
- sysc::sc_register<«instantiation.component.effectiveName»_t> «instance.name»;
- «ENDIF»
- «ENDIF»
- «IF instance.range!==null»
- «IF instantiation.isFilledByField»
- sysc::sc_register_indexed «instance.name»;
- «ENDIF»
- «IF !instantiation.isFilledByField»
- sysc::sc_register_indexed<«instantiation.component.effectiveName»_t, «instance.range.absSize»> «instance.name»;
+ «IF instantiation.componentDefinition.type == ComponentDefinitionType.REGFILE»
+ // scc::sc_register_file<«instantiation.componentDefinition.effectiveName»_regs> «instance.name»;
+ «ELSEIF instantiation.componentDefinition.type == ComponentDefinitionType.REG»
+ «IF instance.range===null»
+ «IF instantiation.componentDefinition.instantiations.size==0»
+ scc::sc_register «instance.name»;
+ «ELSEIF instantiation.isFilledByField»
+ scc::sc_register «instance.name»;
+ «ELSE»
+ scc::sc_register<«instantiation.componentDefinition.effectiveName»_t> «instance.name»;
+ «ENDIF»
+ «ELSE»
+ «IF instantiation.componentDefinition.instantiations.size==0»
+ scc::sc_register_indexed «instance.name»;
+ «ELSEIF instantiation.isFilledByField»
+ scc::sc_register_indexed «instance.name»;
+ «ELSE»
+ scc::sc_register_indexed<«instantiation.component.effectiveName»_t, «instance.range.absSize»> «instance.name»;
+ «ENDIF»
«ENDIF»
«ENDIF»
«ENDFOR»
«ENDFOR»
- «componentDefinition.name»(sc_core::sc_module_name nm);
+ «componentDefinition.effectiveName»_regs(sc_core::sc_module_name nm);
template
- void registerResources(sysc::tlm_target& target);
+ void registerResources(scc::tlm_target& target, uint64_t offset=0);
};
- }
+ } // namespace gen
+ } // namespace «namespace»
//////////////////////////////////////////////////////////////////////////////
// member functions
//////////////////////////////////////////////////////////////////////////////
- inline sysc::«componentDefinition.name»::«componentDefinition.name»(sc_core::sc_module_name nm)
+ inline «namespace»::gen::«componentDefinition.effectiveName»_regs::«componentDefinition.effectiveName»_regs(sc_core::sc_module_name nm)
: sc_core::sc_module(nm)
«FOR instantiation : componentDefinition.instantiations»
«FOR instance : instantiation.componentInstances»
- , NAMED(«instance.name», r_«instance.name», 0, *this)
+ «IF instantiation.componentDefinition.type == ComponentDefinitionType.REGFILE»
+ // , NAMED(«instance.name», i_«instance.name», 0, *this)
+ «ELSEIF instantiation.componentDefinition.type == ComponentDefinitionType.REG»
+ , NAMED(«instance.name», r_«instance.name», 0, *this)
+ «ENDIF»
«ENDFOR»
«ENDFOR»
{
}
template
- inline void sysc::«componentDefinition.name»::registerResources(sysc::tlm_target& target) {
+ inline void «namespace»::gen::«componentDefinition.effectiveName»_regs::registerResources(scc::tlm_target& target, uint64_t offset) {
«FOR instantiation : componentDefinition.instantiations»
«FOR instance : instantiation.componentInstances»
- target.addResource(«instance.name», «instance.addressValue»UL);
+ «IF instantiation.componentDefinition.type == ComponentDefinitionType.REGFILE»
+ i_«instance.name».registerResources(target, «instance.addressValue»UL+offset);
+ «ELSEIF instantiation.componentDefinition.type == ComponentDefinitionType.REG»
+ target.addResource(«instance.name», «instance.addressValue»UL);
+ «ENDIF»
«ENDFOR»
«ENDFOR»
}
- #endif // _«componentDefinition.name.toUpperCase»_H_
+ #endif // _«namespace.toUpperCase»_GEN_«componentDefinition.effectiveName.toUpperCase»_H_
'''
- def long absSize(Range range){
- if(range.size!==null)
- return (range.size as IntegerWithRadix).value
- else
- return Math.abs((range.left as IntegerWithRadix).value - (range.right as IntegerWithRadix).value)+1
- }
-
- def boolean isFilledByField(Instantiation instantiation){
- val fieldCount = instantiation.component.instanceCountOfType(ComponentDefinitionType.FIELD)
- if(fieldCount==1) {
- val instSize=instantiation.size
- val field = instantiation.component.instantiationsOfType(ComponentDefinitionType.FIELD).get(0)
- val inst = field.componentInstances.get(0)
- val range = inst.range
- if(range===null)
- return instSize==field.size
- if(range.size !== null)
- return instSize==(range.size as IntegerWithRadix).value
- else {
- val left=(range.left as IntegerWithRadix).value
- val right=(range.right as IntegerWithRadix).value
- val size = if(left>right) left-right+1 else right-left+1
- return instSize==size
- }
- }
- return false
- }
-
- def int instanceCountOfType(ComponentDefinition definition, ComponentDefinitionType type){
- definition.instantiationsOfType(type).map[it.componentInstances.size].reduce[p1, p2|p1+p1]
- }
-
- override generateSource() {
+ override generateSource(String namespace) {
''
}
diff --git a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RDLRuntimeModule.java b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RDLRuntimeModule.java
index 65a219c..634ba0c 100644
--- a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RDLRuntimeModule.java
+++ b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RDLRuntimeModule.java
@@ -5,7 +5,6 @@ package com.minres.rdl;
import com.google.inject.Binder;
import com.google.inject.name.Names;
-import com.minres.rdl.AbstractRDLRuntimeModule;
import com.minres.rdl.converter.RdlTerminalConverters;
import org.eclipse.xtext.conversion.IValueConverterService;
import org.eclipse.xtext.scoping.IGlobalScopeProvider;
diff --git a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RDLStandaloneSetup.java b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RDLStandaloneSetup.java
index d440897..029f96a 100644
--- a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RDLStandaloneSetup.java
+++ b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RDLStandaloneSetup.java
@@ -3,8 +3,6 @@
*/
package com.minres.rdl;
-import com.minres.rdl.RDLStandaloneSetupGenerated;
-
/**
* Initialization support for running Xtext languages without Equinox extension registry.
*/
diff --git a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RdlUtil.java b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RdlUtil.java
index ec144d6..114c34c 100644
--- a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RdlUtil.java
+++ b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/RdlUtil.java
@@ -1,7 +1,6 @@
package com.minres.rdl;
import com.google.common.base.Objects;
-import com.minres.rdl.IntegerWithRadix;
import com.minres.rdl.rdl.ComponentDefinition;
import com.minres.rdl.rdl.ComponentDefinitionType;
import com.minres.rdl.rdl.ComponentInstance;
@@ -14,7 +13,9 @@ import com.minres.rdl.rdl.PropertyAssignmentRhs;
import com.minres.rdl.rdl.PropertyEnum;
import com.minres.rdl.rdl.RValue;
import com.minres.rdl.rdl.RValueConstant;
+import com.minres.rdl.rdl.Range;
import org.eclipse.emf.common.util.EList;
+import org.eclipse.xtext.xbase.lib.Conversions;
import org.eclipse.xtext.xbase.lib.Functions.Function1;
import org.eclipse.xtext.xbase.lib.Functions.Function2;
import org.eclipse.xtext.xbase.lib.IterableExtensions;
@@ -260,4 +261,87 @@ public class RdlUtil {
}
return componentSize;
}
+
+ public static ComponentDefinition getComponentDefinition(final Instantiation instantiation) {
+ ComponentDefinition _xifexpression = null;
+ ComponentDefinition _component = instantiation.getComponent();
+ boolean _tripleNotEquals = (_component != null);
+ if (_tripleNotEquals) {
+ _xifexpression = instantiation.getComponent();
+ } else {
+ _xifexpression = instantiation.getComponentRef();
+ }
+ return _xifexpression;
+ }
+
+ public static long absSize(final Range range) {
+ Object _size = range.getSize();
+ boolean _tripleNotEquals = (_size != null);
+ if (_tripleNotEquals) {
+ Object _size_1 = range.getSize();
+ return ((IntegerWithRadix) _size_1).value;
+ } else {
+ Object _left = range.getLeft();
+ Object _right = range.getRight();
+ long _abs = Math.abs((((IntegerWithRadix) _left).value - ((IntegerWithRadix) _right).value));
+ return (_abs + 1);
+ }
+ }
+
+ public static boolean isFilledByField(final Instantiation instantiation) {
+ final int fieldCount = RdlUtil.instanceCountOfType(RdlUtil.getComponentDefinition(instantiation), ComponentDefinitionType.FIELD);
+ if ((fieldCount == 1)) {
+ final long instSize = RdlUtil.getSize(instantiation);
+ final Instantiation field = ((Instantiation[])Conversions.unwrapArray(RdlUtil.instantiationsOfType(instantiation.getComponent(), ComponentDefinitionType.FIELD), Instantiation.class))[0];
+ final ComponentInstance inst = field.getComponentInstances().get(0);
+ final Range range = inst.getRange();
+ if ((range == null)) {
+ long _size = RdlUtil.getSize(field);
+ return (instSize == _size);
+ }
+ Object _size_1 = range.getSize();
+ boolean _tripleNotEquals = (_size_1 != null);
+ if (_tripleNotEquals) {
+ Object _size_2 = range.getSize();
+ return (instSize == ((IntegerWithRadix) _size_2).value);
+ } else {
+ Object _left = range.getLeft();
+ final long left = ((IntegerWithRadix) _left).value;
+ Object _right = range.getRight();
+ final long right = ((IntegerWithRadix) _right).value;
+ long _xifexpression = (long) 0;
+ if ((left > right)) {
+ _xifexpression = ((left - right) + 1);
+ } else {
+ _xifexpression = ((right - left) + 1);
+ }
+ final long size = _xifexpression;
+ return (instSize == size);
+ }
+ }
+ return false;
+ }
+
+ public static int instanceCountOfType(final ComponentDefinition definition, final ComponentDefinitionType type) {
+ Integer _xblockexpression = null;
+ {
+ final Iterable insts = RdlUtil.instantiationsOfType(definition, type);
+ Integer _xifexpression = null;
+ int _size = IterableExtensions.size(insts);
+ boolean _greaterThan = (_size > 0);
+ if (_greaterThan) {
+ final Function1 _function = (Instantiation it) -> {
+ return Integer.valueOf(it.getComponentInstances().size());
+ };
+ final Function2 _function_1 = (Integer p1, Integer p2) -> {
+ return Integer.valueOf(((p1).intValue() + (p2).intValue()));
+ };
+ _xifexpression = IterableExtensions.reduce(IterableExtensions.map(insts, _function), _function_1);
+ } else {
+ _xifexpression = Integer.valueOf(0);
+ }
+ _xblockexpression = _xifexpression;
+ }
+ return (_xblockexpression).intValue();
+ }
}
diff --git a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/converter/RdlTerminalConverters.java b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/converter/RdlTerminalConverters.java
index 5c438ef..92ce426 100644
--- a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/converter/RdlTerminalConverters.java
+++ b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/converter/RdlTerminalConverters.java
@@ -2,9 +2,6 @@ package com.minres.rdl.converter;
import com.google.inject.Inject;
import com.minres.rdl.IntegerWithRadix;
-import com.minres.rdl.converter.IDValueConverter;
-import com.minres.rdl.converter.NUMValueConverter;
-import com.minres.rdl.converter.STRValueConverter;
import org.eclipse.xtext.common.services.DefaultTerminalConverters;
import org.eclipse.xtext.conversion.IValueConverter;
import org.eclipse.xtext.conversion.ValueConverter;
diff --git a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/generator/AddrmapGenerator.java b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/generator/AddrmapGenerator.java
index 3b0f1ef..ca0cd07 100644
--- a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/generator/AddrmapGenerator.java
+++ b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/generator/AddrmapGenerator.java
@@ -2,7 +2,6 @@ package com.minres.rdl.generator;
import com.minres.rdl.IntegerWithRadix;
import com.minres.rdl.RdlUtil;
-import com.minres.rdl.generator.RdlBaseGenerator;
import com.minres.rdl.rdl.ComponentDefinition;
import com.minres.rdl.rdl.ComponentDefinitionType;
import com.minres.rdl.rdl.ComponentInstance;
@@ -19,7 +18,12 @@ public class AddrmapGenerator extends RdlBaseGenerator {
}
@Override
- public String generateHeader() {
+ public boolean getOverwrite() {
+ return true;
+ }
+
+ @Override
+ public String generateHeader(final String namespace) {
StringConcatenation _builder = new StringConcatenation();
_builder.append("#ifndef _");
String _upperCase = RdlUtil.effectiveName(this.componentDefinition).toUpperCase();
@@ -33,7 +37,7 @@ public class AddrmapGenerator extends RdlBaseGenerator {
_builder.newLineIfNotEmpty();
_builder.append("// need double braces, see https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191");
_builder.newLine();
- _builder.append("const std::array, ");
+ _builder.append("const std::array, ");
int _instanceCount = RdlUtil.instanceCount(this.componentDefinition, ComponentDefinitionType.REGFILE);
_builder.append(_instanceCount);
_builder.append("> ");
@@ -48,10 +52,10 @@ public class AddrmapGenerator extends RdlBaseGenerator {
EList _componentInstances = instantiation.getComponentInstances();
for(final ComponentInstance instance : _componentInstances) {
_builder.append(" ");
- _builder.append("{&i_");
+ _builder.append("{i_");
String _name = instance.getName();
_builder.append(_name, " ");
- _builder.append(", ");
+ _builder.append(".socket, ");
IntegerWithRadix _addressValue = RdlUtil.addressValue(instance);
_builder.append(_addressValue, " ");
_builder.append(", 0x");
@@ -75,7 +79,7 @@ public class AddrmapGenerator extends RdlBaseGenerator {
}
@Override
- public String generateSource() {
+ public String generateSource(final String namespace) {
return "";
}
}
diff --git a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/generator/FwAddrmapGenerator.java b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/generator/FwAddrmapGenerator.java
index 117ad64..ad17b6d 100644
--- a/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/generator/FwAddrmapGenerator.java
+++ b/com.minres.rdl.parent/com.minres.rdl/xtend-gen/com/minres/rdl/generator/FwAddrmapGenerator.java
@@ -2,7 +2,6 @@ package com.minres.rdl.generator;
import com.minres.rdl.IntegerWithRadix;
import com.minres.rdl.RdlUtil;
-import com.minres.rdl.generator.RdlBaseGenerator;
import com.minres.rdl.rdl.ComponentDefinition;
import com.minres.rdl.rdl.ComponentDefinitionType;
import com.minres.rdl.rdl.ComponentInstance;
@@ -24,11 +23,16 @@ public class FwAddrmapGenerator extends RdlBaseGenerator {
private final LinkedHashSet