# VexRiscv
- operation: RdCustReg
  earliest: 1
  latency: 0
  latest: 3
- operation: WrCustReg.addr
  earliest: 1
  latency: 0
  latest: 1
- operation: WrCustReg.data
  earliest: 1
  latency: 1
  costly: 2
- operation: RdRS1
  earliest: 2
  latency: 0
  latest: 3
  costly: 4
- operation: RdRS2
  earliest: 2
  latency: 0
  latest: 3
  costly: 4
- operation: WrRD
  earliest: 2
  latency: 1
  costly: 3
- operation: RdPC
  earliest: 1
  latency: 0
  costly: 4
- operation: WrPC
  earliest: 0
  latency: 0
  costly: 1
- operation: RdMem
  earliest: 2
  latency: 1
  costly: 3
- operation: WrMem
  earliest: 2
  latency: 1
  costly: 3
- operation: RdIValid
  earliest: 1
  latency: 0
  latest: 3
  costly: 4
- operation: RdInstr
  earliest: 1
  latency: 0
  latest: 3
  costly: 4
- operation: RdStall
  earliest: 1
  latency: 0
  latest: 3
  costly: 4
- operation: WrStall
  earliest: 1
  latency: 0
  latest: 3
  costly: 4
- operation: RdFlush
  earliest: 1
  latency: 0
  latest: 3
  costly: 4
- operation: WrFlush
  earliest: 1
  latency: 0
  latest: 3
  costly: 4