From f9649d4c5d63a07b3dffa4aa96197c19dced7ce0 Mon Sep 17 00:00:00 2001 From: Johannes Wirth Date: Fri, 10 Oct 2025 13:56:49 +0200 Subject: [PATCH] add reprod examples for issues --- reprod/10_const_array.core_desc | 32 +++++++++++++++++ reprod/11_function_multiple_return.core_desc | 36 +++++++++++++++++++ reprod/12_function_no_return.core_desc | 23 ++++++++++++ reprod/13_external_loop_variable.core_desc | 23 ++++++++++++ reprod/14_memory_access_width.core_desc | 21 +++++++++++ reprod/15_memory_access_funct.core_desc | 21 +++++++++++ reprod/16_custom_register_read.core_desc | 20 +++++++++++ reprod/17_read_custom_reg_in_loop.core_desc | 25 +++++++++++++ ...custom_register_written_per_ISAX.core_desc | 26 ++++++++++++++ ...untime_access_to_impl_parameters.core_desc | 21 +++++++++++ reprod/2_unsigned_subtract.core_desc | 20 +++++++++++ reprod/3_any_type_in_if.core_desc | 22 ++++++++++++ .../4_assign_bitliteral_to_signed.core_desc | 19 ++++++++++ reprod/5_dynamic_loop.core_desc | 23 ++++++++++++ reprod/6_precalc_fixed.core_desc | 24 +++++++++++++ reprod/7_reg_read_in_loop.core_desc | 26 ++++++++++++++ reprod/8_bit_access_loop_variable.core_desc | 28 +++++++++++++++ reprod/9_nested_lvalues.core_desc | 21 +++++++++++ 18 files changed, 431 insertions(+) create mode 100644 reprod/10_const_array.core_desc create mode 100644 reprod/11_function_multiple_return.core_desc create mode 100644 reprod/12_function_no_return.core_desc create mode 100644 reprod/13_external_loop_variable.core_desc create mode 100644 reprod/14_memory_access_width.core_desc create mode 100644 reprod/15_memory_access_funct.core_desc create mode 100644 reprod/16_custom_register_read.core_desc create mode 100644 reprod/17_read_custom_reg_in_loop.core_desc create mode 100644 reprod/18_custom_register_written_per_ISAX.core_desc create mode 100644 reprod/1_runtime_access_to_impl_parameters.core_desc create mode 100644 reprod/2_unsigned_subtract.core_desc create mode 100644 reprod/3_any_type_in_if.core_desc create mode 100644 reprod/4_assign_bitliteral_to_signed.core_desc create mode 100644 reprod/5_dynamic_loop.core_desc create mode 100644 reprod/6_precalc_fixed.core_desc create mode 100644 reprod/7_reg_read_in_loop.core_desc create mode 100644 reprod/8_bit_access_loop_variable.core_desc create mode 100644 reprod/9_nested_lvalues.core_desc diff --git a/reprod/10_const_array.core_desc b/reprod/10_const_array.core_desc new file mode 100644 index 0000000..5279a16 --- /dev/null +++ b/reprod/10_const_array.core_desc @@ -0,0 +1,32 @@ +// An ISA parameter may not be declared as an array +// Need to use "const register" instead + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + + const unsigned<8> AES_ENC_SBOX[256] = + {0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, + 0x47, 0xF0, 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, + 0x71, 0xD8, 0x31, 0x15, 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75, 0x09, 0x83, + 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84, 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, + 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF, 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, + 0x9F, 0xA8, 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2, 0xCD, 0x0C, 0x13, 0xEC, + 0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73, 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, + 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB, 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79, + 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08, 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, + 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A, 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, 0x61, 0x35, 0x57, 0xB9, + 0x86, 0xC1, 0x1D, 0x9E, 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF, 0x8C, 0xA1, + 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16}; + } + instructions { + + LUI { + encoding: imm[31:12] :: rd[4:0] :: 7'b0110111; + assembly: "{name(rd)}, {imm:#05x}"; + behavior: if (rd != 0) X[rd] = (unsigned) ((signed) imm); + } + } +} \ No newline at end of file diff --git a/reprod/11_function_multiple_return.core_desc b/reprod/11_function_multiple_return.core_desc new file mode 100644 index 0000000..f075aef --- /dev/null +++ b/reprod/11_function_multiple_return.core_desc @@ -0,0 +1,36 @@ +// Multiple returns / returns in ifs are not allowed in functions + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + } + functions { + // ROT_0 = { 19, 61, 1, 10, 7 } + unsigned<64> rot_0(unsigned<5> imm){ + if(imm == 0) + return 19; + else if(imm==1) + return 61; + else if(imm==2) + return 1; + else if(imm==3) + return 10; + else if(imm==4) + return 7; + return 0; + } + } + instructions { + + ASCON_SIGMA_LO [[enable=XLEN==32]] { + encoding: 2'b00 :: imm[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b0101011; + behavior: { + unsigned<64> r = rot_0(imm); + X[rd] = (unsigned)r[31:0]; + } + + } + } +} \ No newline at end of file diff --git a/reprod/12_function_no_return.core_desc b/reprod/12_function_no_return.core_desc new file mode 100644 index 0000000..526f616 --- /dev/null +++ b/reprod/12_function_no_return.core_desc @@ -0,0 +1,23 @@ +// Functions with no return are not supported + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + } + functions { + void XORLane(unsigned int x, unsigned int y, unsigned<32> value) { + X[x + 5 * y] = X[x + 5 * y] ^ value; + } + } + instructions { + TEST { + encoding: 12'b011000000000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + XORLane(5,2,1); + } + } + } +} \ No newline at end of file diff --git a/reprod/13_external_loop_variable.core_desc b/reprod/13_external_loop_variable.core_desc new file mode 100644 index 0000000..8ca457f --- /dev/null +++ b/reprod/13_external_loop_variable.core_desc @@ -0,0 +1,23 @@ +// A loop variable defined beforehand does not work + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + } + instructions { + TEST { + encoding: 12'b011000000000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + unsigned int count = 0; + unsigned int i = 0; + for(i=0; i<=32; i++){ + count = 1; + } + X[rd] = count; + } + } + } +} \ No newline at end of file diff --git a/reprod/14_memory_access_width.core_desc b/reprod/14_memory_access_width.core_desc new file mode 100644 index 0000000..96a3fd3 --- /dev/null +++ b/reprod/14_memory_access_width.core_desc @@ -0,0 +1,21 @@ +// Memory access width can only be 8,16,32 + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + register unsigned<64> K[32]; + extern unsigned<8> MEM[1 << XLEN] [[is_main_mem]]; + } + instructions { + LK64 { + encoding: imm[11:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: "{name(rd)}, {imm}({name(rs1)})"; + behavior: { + unsigned load_address = (unsigned)(X[rs1] + (signed<12>)imm); + K[rd]= MEM[load_address+7:load_address]; + } + } + } +} \ No newline at end of file diff --git a/reprod/15_memory_access_funct.core_desc b/reprod/15_memory_access_funct.core_desc new file mode 100644 index 0000000..50c0fd8 --- /dev/null +++ b/reprod/15_memory_access_funct.core_desc @@ -0,0 +1,21 @@ +// Memory access width must match funct3 field + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + register unsigned<64> K[32]; + extern unsigned<8> MEM[1 << XLEN] [[is_main_mem]]; + } + instructions { + LK64 { + encoding: imm[11:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: "{name(rd)}, {imm}({name(rs1)})"; + behavior: { + unsigned load_address = (unsigned)(X[rs1] + (signed<12>)imm); + K[rd]= MEM[load_address+3:load_address]; + } + } + } +} \ No newline at end of file diff --git a/reprod/16_custom_register_read.core_desc b/reprod/16_custom_register_read.core_desc new file mode 100644 index 0000000..28bb7df --- /dev/null +++ b/reprod/16_custom_register_read.core_desc @@ -0,0 +1,20 @@ +// Custom registers can be read only once (also for custom register fields) + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + register unsigned<8> LFSR; + } + instructions { + TEST { + encoding: 12'b011000000000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + unsigned<8> a = LFSR; + unsigned<8> b = LFSR; + } + } + } +} \ No newline at end of file diff --git a/reprod/17_read_custom_reg_in_loop.core_desc b/reprod/17_read_custom_reg_in_loop.core_desc new file mode 100644 index 0000000..b7f0a14 --- /dev/null +++ b/reprod/17_read_custom_reg_in_loop.core_desc @@ -0,0 +1,25 @@ +// Custom registers (and register fields) cannot be accessed in loops + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + register unsigned<8> LFSR; + register unsigned<64> K[32]; + } + instructions { + TEST { + encoding: 12'b011000000000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + for(int i=0; i<=32-1; i++) { + LFSR = 1; + K[0] = 1; + ; + } + X[rd] = 1; + } + } + } +} \ No newline at end of file diff --git a/reprod/18_custom_register_written_per_ISAX.core_desc b/reprod/18_custom_register_written_per_ISAX.core_desc new file mode 100644 index 0000000..5c1122e --- /dev/null +++ b/reprod/18_custom_register_written_per_ISAX.core_desc @@ -0,0 +1,26 @@ +// Non const registers must be written at least once per ISAX! (unsure why this is not an issue for 17??) + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + register unsigned<8> LFSR; + register unsigned<64> K[32]; + } + instructions { + KECCAK_RHO_PI { + encoding: 7'b0000000 :: 5'b00000 :: 5'b00000 :: 3'b001 :: 5'b00000 :: 7'b0001011; + assembly: "keccak.rhopi"; + behavior: { + unsigned<64> current; + unsigned int x, y; + + // Start at coordinates (1, 0) + x = 1; + y = 0; + current = K[x + 5 * y]; + } + } + } +} \ No newline at end of file diff --git a/reprod/1_runtime_access_to_impl_parameters.core_desc b/reprod/1_runtime_access_to_impl_parameters.core_desc new file mode 100644 index 0000000..06955a8 --- /dev/null +++ b/reprod/1_runtime_access_to_impl_parameters.core_desc @@ -0,0 +1,21 @@ +// Parameters in "architectural_state" cannot be used as value in the ISAX implementation + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + // added for workaround + const register unsigned<32> XLEN_R = XLEN; + register unsigned X[32] [[is_main_reg]]; + } + instructions { + ROL [[enable=XLEN==32]] { + encoding: 7'b0110000 :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0110011; + assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}"; + behavior: { + unsigned shamt = X[rs2][4:0]; + X[rd] = (X[rs1] << shamt) |( X[rs1] >> (XLEN - shamt)); + //X[rd] = (X[rs1] << shamt) |( X[rs1] >> (XLEN_R - shamt)); + } + } + } +} \ No newline at end of file diff --git a/reprod/2_unsigned_subtract.core_desc b/reprod/2_unsigned_subtract.core_desc new file mode 100644 index 0000000..62fadb7 --- /dev/null +++ b/reprod/2_unsigned_subtract.core_desc @@ -0,0 +1,20 @@ +// When substracting from an unsigned value, the result cannot auto-cast to the same unsigned type (e.g. "value of UI<32> - 1" gives a SI<33>, cannot be cast to UI<32>) + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + } + instructions { + TEST { + encoding: 12'b011000000000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + unsigned int test = XLEN_R - 1; + //unsigned int test = (unsigned int)(XLEN_R - 1); + X[rd] = test; + } + } + } +} \ No newline at end of file diff --git a/reprod/3_any_type_in_if.core_desc b/reprod/3_any_type_in_if.core_desc new file mode 100644 index 0000000..60d8ea6 --- /dev/null +++ b/reprod/3_any_type_in_if.core_desc @@ -0,0 +1,22 @@ +// Types wider than 1 bit cannot be directly used as if condition (0 => false, other => true) + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + } + instructions { + TEST { + encoding: 12'b011000000000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + unsigned int test = 1; + if (test) { + //if (test != 0) { + X[rd] = 2; + } + } + } + } +} \ No newline at end of file diff --git a/reprod/4_assign_bitliteral_to_signed.core_desc b/reprod/4_assign_bitliteral_to_signed.core_desc new file mode 100644 index 0000000..d2af17c --- /dev/null +++ b/reprod/4_assign_bitliteral_to_signed.core_desc @@ -0,0 +1,19 @@ +// A bit literal cannot be directly assigned to a signed of same width + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + } + instructions { + TEST { + encoding: 12'b011000000000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + signed<2> test2 = 2'b11; + X[rd] = 2; + } + } + } +} \ No newline at end of file diff --git a/reprod/5_dynamic_loop.core_desc b/reprod/5_dynamic_loop.core_desc new file mode 100644 index 0000000..5772582 --- /dev/null +++ b/reprod/5_dynamic_loop.core_desc @@ -0,0 +1,23 @@ +// A loop which can NOT be dynamically unrolled breaks longnail +// the increment of the loop variable errors as "out of region" + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + } + instructions { + TEST { + encoding: 12'b011000000000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + unsigned int count = XLEN_R; + for(unsigned int i=0; i<=rs1; i++){ + count = 1; + } + X[rd] = count; + } + } + } +} \ No newline at end of file diff --git a/reprod/6_precalc_fixed.core_desc b/reprod/6_precalc_fixed.core_desc new file mode 100644 index 0000000..10221b9 --- /dev/null +++ b/reprod/6_precalc_fixed.core_desc @@ -0,0 +1,24 @@ +// The compiler does not seem to precalculate fixed expressions +// This can be seen e.g. as it breaks loop unrolling (see also dynamic_loop) + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + } + instructions { + TEST { + encoding: 12'b011000000000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + unsigned int count = XLEN_R; + for(int i=0; i<=32-1; i++){ + //for(int i=0; i<=31; i++){ + count = 1; + } + X[rd] = count; + } + } + } +} \ No newline at end of file diff --git a/reprod/7_reg_read_in_loop.core_desc b/reprod/7_reg_read_in_loop.core_desc new file mode 100644 index 0000000..112a102 --- /dev/null +++ b/reprod/7_reg_read_in_loop.core_desc @@ -0,0 +1,26 @@ +// Register reads (e.g. X) are not allowed in loops + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + } + instructions { + TEST { + encoding: 12'b011000000000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + unsigned int bitcount = 0; + unsigned int r1 = X[rs1]; + for(unsigned int i = 0; i<32; i++){ + if(X[rs1] == 1'b1) { + //if(r1[rs1] == 1'b1) { + bitcount = 1; + } + } + X[rd] = bitcount; + } + } + } +} \ No newline at end of file diff --git a/reprod/8_bit_access_loop_variable.core_desc b/reprod/8_bit_access_loop_variable.core_desc new file mode 100644 index 0000000..3936c1e --- /dev/null +++ b/reprod/8_bit_access_loop_variable.core_desc @@ -0,0 +1,28 @@ +// The loop variable cannot be used as bit index in conditions +// Same issue when using an equivalent expression using shift + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + } + instructions { + TEST { + encoding: 12'b011000000000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + unsigned int bitcount = 0; + unsigned int r1 = 1; + for(unsigned int i = 0; i<32; i++){ + if(r1[i]) { + //if(((r1 >> i) & 1) == 1) { // also broken + //if(r1[rs1]) { + bitcount = 1; + } + } + X[rd] = bitcount; + } + } + } +} \ No newline at end of file diff --git a/reprod/9_nested_lvalues.core_desc b/reprod/9_nested_lvalues.core_desc new file mode 100644 index 0000000..a4b7006 --- /dev/null +++ b/reprod/9_nested_lvalues.core_desc @@ -0,0 +1,21 @@ +// Nexted Lvalues not implemented (seems to be in Treenail) + +InstructionSet Zbb { + architectural_state { + unsigned int XLEN=32; + const register unsigned<32> XLEN_R = 32; + register unsigned X[32] [[is_main_reg]]; + } + instructions { + ZIP [[enable=XLEN==32]] { + encoding: 12'b000010001111 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0010011; + assembly: "{name(rd)}, {name(rs1)}"; + behavior: { + for(unsigned int i = 0; i<=XLEN/2-1; i++){ + X[rd][2*i] = X[rs1][i]; + X[rd][2*i+1] = X[rs1][i+XLEN/2]; + } + } + } + } +} \ No newline at end of file