#ifndef _TESTBENCH_H_ #define _TESTBENCH_H_ #include #include #include #include #include #include #include #include #include #include using namespace sc_core; using namespace sc_dt; using namespace std; using namespace cxs; const char* sc_gen_unique_name(const char*, bool preserve_first); template struct testbench : public sc_core::sc_module { using transaction_type = cxs_packet_types::tlm_payload_type; using phase_type = cxs_packet_types::tlm_phase_type; sc_core::sc_clock clk{"clk", 1_ns}; sc_core::sc_signal rst{"rst"}; tlm::nw::initiator_mixin, cxs_packet_types> isck{"isck"}; cxs_transmitter tx{"tx"}; cxs_channel cxs_chan{"cxs_chan"}; cxs_receiver rx{"rx"}; tlm::nw::target_mixin, cxs_packet_types> tsck{"tsck"}; testbench() : testbench(sc_core::sc_gen_unique_name("testbench", false)) {} testbench(sc_core::sc_module_name const& nm) : sc_module(nm) { isck.register_nb_transport_bw( [this](transaction_type& trans, phase_type& phase, sc_core::sc_time& t) { return this->nb_transport_fw(trans, phase, t); }); tsck.register_nb_transport_fw( [this](transaction_type& trans, phase_type& phase, sc_core::sc_time& t) { return this->nb_transport_fw(trans, phase, t); }); isck(tx.tsck); tx.clk_i(clk); tx.isck(cxs_chan.tsck); cxs_chan.isck(rx.tsck); rx.clk_i(clk); rx.rst_i(rst); rx.isck(tsck); cxs_chan.channel_delay.set_value(100_ns); rx.max_credit.set_value(15); } tlm::tlm_sync_enum nb_transport_fw(transaction_type& trans, phase_type& phase, sc_core::sc_time& t) { if(phase == tlm::nw::REQUEST) { SCCINFO(SCMOD) << "Received non-blocking transaction with phase " << phase.get_name(); recv.push_back(&trans); phase = tlm::nw::CONFIRM; return tlm::TLM_UPDATED; } throw std::runtime_error("illegal request in forward path"); } tlm::tlm_sync_enum nb_transport_bw(transaction_type& trans, phase_type& phase, sc_core::sc_time& t) { if(phase == tlm::nw::CONFIRM) { confirmation_evt.notify(sc_core::SC_ZERO_TIME); return tlm::TLM_ACCEPTED; } throw std::runtime_error("illegal response in backward path"); } sc_core::sc_event confirmation_evt; scc::fifo_w_cb recv; }; #endif // _TESTBENCH_H_