#define SC_INCLUDE_DYNAMIC_PROCESSES #include "testbench.h" #include #include #undef CHECK #include #include using namespace sc_core; factory::add tb; bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b){ auto ret = true; ret &= a.get_command() == b.get_command(); ret &= a.get_address() == b.get_address(); ret &= a.get_data_length() == b.get_data_length(); for(auto i=0u; i tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned len, unsigned width, unsigned id_offs) { static uint8_t id{0}; auto trans = tlm::scc::tlm_mm<>::get().allocate(len); trans->set_address(start_address); tlm::scc::setId(*trans, id); auto ext = trans->get_extension(); trans->set_data_length(len); trans->set_streaming_width(len); ext->set_size(scc::ilog2(width)); sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0); auto length = (len * 8 - 1) / 32; if(width==(bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8)) length++; ext->set_length(length); // ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED); ext->set_burst(axi::burst_e::INCR); ext->set_id(id); id = (id + 1) % 8; return trans; } inline void randomize(tlm::tlm_generic_payload& gp) { static uint8_t req_cnt{0}; auto addr = gp.get_address(); uint8_t const* src = reinterpret_cast(&addr); for(size_t i = 0; i < gp.get_data_length(); ++i) { *(gp.get_data_ptr() + i) = i % 2 ? i : req_cnt; } req_cnt++; } template void run_scenario(STATE& state){ auto& dut = factory::get(); dut.tgt_pe.set_operation_cb([&state](axi::axi_protocol_types::tlm_payload_type& trans) -> unsigned { auto id = axi::get_axi_id(trans); if(trans.is_read()) { for(size_t i = 0; i < trans.get_data_length(); ++i) { *(trans.get_data_ptr() + i) = i % 2 ? i : (state.resp_cnt+128); } state.read_tx[id].second.emplace_back(&trans); } if(trans.is_write()) state.write_tx[id].second.emplace_back(&trans); SCCDEBUG(__FUNCTION__)<<"RX: "<(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0); randomize(*trans); trans->set_command(tlm::TLM_READ_COMMAND); SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans; dut.intor_pe.transport(*trans, false); auto id = axi::get_axi_id(*trans); state.read_tx[id].first.emplace_back(trans); if(trans->get_response_status() != tlm::TLM_OK_RESPONSE) SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string(); } { // 2 tlm::scc::tlm_gp_shared_ptr trans = prepare_trans(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0); trans->set_command(tlm::TLM_WRITE_COMMAND); randomize(*trans); SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans; dut.intor_pe.transport(*trans, false); auto id = axi::get_axi_id(*trans); state.write_tx[id].first.emplace_back(trans); if(trans->get_response_status() != tlm::TLM_OK_RESPONSE) SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string(); } StartAddr += state.BurstSizeBytes; } }); auto run2 = sc_spawn([&dut, &state](){ wait(0_ns); unsigned int StartAddr{0x1000}; for(int i = 0; i < state.NumberOfIterations; ++i) { SCCDEBUG(__FUNCTION__) << "run1 executing transactions in iteration " << i; { // 1 tlm::scc::tlm_gp_shared_ptr trans = prepare_trans(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0x8); randomize(*trans); trans->set_command(tlm::TLM_READ_COMMAND); SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans; dut.intor_pe.transport(*trans, false); auto id = axi::get_axi_id(*trans); state.read_tx[id].first.emplace_back(trans); if(trans->get_response_status() != tlm::TLM_OK_RESPONSE) SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string(); } { // 2 tlm::scc::tlm_gp_shared_ptr trans = prepare_trans(StartAddr, state.BurstLengthByte, state.BurstSizeBytes, 0x8); trans->set_command(tlm::TLM_WRITE_COMMAND); randomize(*trans); SCCDEBUG(__FUNCTION__)<<"TX: "<<*trans; dut.intor_pe.transport(*trans, false); auto id = axi::get_axi_id(*trans); state.write_tx[id].first.emplace_back(trans); if(trans->get_response_status() != tlm::TLM_OK_RESPONSE) SCCERR(__FUNCTION__) << "Invalid response status" << trans->get_response_string(); } StartAddr += state.BurstSizeBytes; } }); sc_start(120 * dut.clk.period()); REQUIRE(run1.terminated()); REQUIRE(run2.terminated()); } TEST_CASE("pin level narrow burst", "[AXI][pin-level]") { struct { unsigned int ResetCycles{4}; unsigned int BurstLengthByte{16}; unsigned int BurstSizeBytes{4}; unsigned int NumberOfIterations{8}; std::unordered_map, std::vector>> read_tx; std::unordered_map, std::vector>> write_tx; unsigned resp_cnt{0}; } state; run_scenario(state); REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0); REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0); REQUIRE(state.resp_cnt==4*state.NumberOfIterations); for(auto& e: state.write_tx) { auto const& send_tx = e.second.first; auto const& recv_tx = e.second.second; REQUIRE(send_tx.size() == recv_tx.size()); for(auto i = 0; i