diff --git a/tests/memory_subsys/memory_test.cpp b/tests/memory_subsys/memory_test.cpp
index 81eec6e..92f8f0d 100644
--- a/tests/memory_subsys/memory_test.cpp
+++ b/tests/memory_subsys/memory_test.cpp
@@ -6,8 +6,6 @@
 #include <array>
 #include <catch2/catch_all.hpp>
 #include <cstdint>
-#include <deque>
-#include <unordered_map>
 
 using namespace sc_core;
 namespace scc {
@@ -69,4 +67,33 @@ TEST_CASE("dmi_access", "[memory][tlm-level]") {
     sc_start(dut.clk.read());
 }
 
+TEST_CASE("page_boundary_check", "[memory][tlm-level]") {
+    auto& dut = factory::get<testbench>();
+    constexpr uint64_t kPageSize = decltype(dut.mem3)::page_size;
+
+    std::array<uint8_t, 2> write_data{{0xAAu, 0xBBu}};
+    tlm::tlm_generic_payload write;
+    sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
+    write.set_command(tlm::TLM_WRITE_COMMAND);
+    write.set_address(kPageSize - 1); // straddles page boundary
+    write.set_data_length(write_data.size());
+    write.set_streaming_width(write_data.size());
+    write.set_data_ptr(write_data.data());
+    dut.mem3.handle_operation(write, delay);
+
+    std::array<uint8_t, 4> read_buf{{0xEEu, 0x00u, 0x00u, 0xEEu}};
+    tlm::tlm_generic_payload read;
+    read.set_command(tlm::TLM_READ_COMMAND);
+    read.set_address(kPageSize - 1);
+    read.set_data_length(write_data.size());
+    read.set_streaming_width(write_data.size());
+    read.set_data_ptr(read_buf.data() + 1); // leave guard bytes at both ends
+    dut.mem3.handle_operation(read, delay);
+
+    REQUIRE(read_buf[0] == 0xEEu); // leading guard untouched
+    REQUIRE(read_buf[1] == 0xAAu); // first byte read correctly
+    REQUIRE(read_buf[2] == 0xBBu); // second byte read correctly
+    REQUIRE(read_buf[3] == 0xEEu); // trailing guard must remain
+}
+
 } // namespace scc