From 972eb6b001a9d062cf82bd08d5f3d10f0e4a824c Mon Sep 17 00:00:00 2001 From: Hongyu Liu Date: Thu, 7 Sep 2023 17:43:30 +0200 Subject: [PATCH 1/5] updates README --- .cproject | 1 - README.md | 54 +++++++++++------------------------------------------- 2 files changed, 11 insertions(+), 44 deletions(-) diff --git a/.cproject b/.cproject index d6bd789..a71d80d 100644 --- a/.cproject +++ b/.cproject @@ -10,7 +10,6 @@ - diff --git a/README.md b/README.md index b13e549..c7d55fc 100644 --- a/README.md +++ b/README.md @@ -1,50 +1,18 @@ # SystemC-Components-Test Examples and tests for the SystemC-Components -#Prerequisites: +## Prerequisites: In Console: - -Check for needed modules in ~/.bashrc - they should be available directly in the linux installation or in the Modulefile top level file in the Project. If not, install it and add it to $PATH with: - - export PATH="needed-path:$PATH" - - -Edit bashrc and add: - - ./opt/shared/modules/4.4.1/init/bash - module use /opt/shared/modules/modulefiles - - at end of file. - - -Load the Modules from the top level file in the Project: - - module load ./Modulefile - - -Install conan with: - - pip install conan - - -and run this comands to run conan with the C++11 library: - - conan profile new default --detect --force - conan profile update settings.compiler.libcxx=libstdc++11 default - - -Add conan to $PATH - -#Build: - -Create folder "build" in SystemC-Components-Test project folder. - -Build the project with: - - cmake .. - - -compile - - make -j4 #4 means number of cores where it is compiled. - - -#Run: - -from build folder run: - - ./bin/"binary-name" #binary name: zb. "sim_performance" + git clone --recursive -b develop https://git.minres.com/SystemC/SystemC-Components-Test.git + cd SystemC-Components-Test/ + module load ./Modulefile + python3 -mvenv .venv + . .venv/bin/activate + pip3 install conan==1.59.0 + cmake -S . -B build + cmake --build build -j30 + + \ No newline at end of file From 3f97fcc28c76175bb528193751d1a7d1c3a7b2ef Mon Sep 17 00:00:00 2001 From: Hongyu Liu Date: Tue, 26 Sep 2023 22:13:36 +0200 Subject: [PATCH 2/5] update submodule scc --- scc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scc b/scc index e510457..3d5f733 160000 --- a/scc +++ b/scc @@ -1 +1 @@ -Subproject commit e510457db91b95cc085cbd30cfadde4b06aa5c9d +Subproject commit 3d5f733ed40ffdbd8f9f788a5a5075fe0797498c From 50bd12b4ecd1c4a3eb24b2d6f633afb3bd26e09e Mon Sep 17 00:00:00 2001 From: Hongyu Liu Date: Fri, 29 Sep 2023 12:31:00 +0200 Subject: [PATCH 3/5] add ace_pin_level testcase and update scc --- scc | 2 +- tests/CMakeLists.txt | 1 + tests/ace_pin_level/CMakeLists.txt | 9 + tests/ace_pin_level/ace_narrow_burst_test.cpp | 242 ++++++++++++++++++ tests/ace_pin_level/testbench.h | 83 ++++++ 5 files changed, 336 insertions(+), 1 deletion(-) create mode 100644 tests/ace_pin_level/CMakeLists.txt create mode 100644 tests/ace_pin_level/ace_narrow_burst_test.cpp create mode 100644 tests/ace_pin_level/testbench.h diff --git a/scc b/scc index 3d5f733..a21316a 160000 --- a/scc +++ b/scc @@ -1 +1 @@ -Subproject commit 3d5f733ed40ffdbd8f9f788a5a5075fe0797498c +Subproject commit a21316a97fff4953a3c08d32f6b97cf6d11d441e diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 173dc7f..f50c669 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -1,6 +1,7 @@ add_subdirectory(io-redirector) add_subdirectory(ordered_semaphore) add_subdirectory(axi4_pin_level) +add_subdirectory(ace_pin_level) add_subdirectory(configuration) if(FULL_TEST_SUITE) add_subdirectory(sim_performance) diff --git a/tests/ace_pin_level/CMakeLists.txt b/tests/ace_pin_level/CMakeLists.txt new file mode 100644 index 0000000..78d5cf1 --- /dev/null +++ b/tests/ace_pin_level/CMakeLists.txt @@ -0,0 +1,9 @@ +project (ace_pin_level) + +add_executable(${PROJECT_NAME} + ace_narrow_burst_test.cpp + ${test_util_SOURCE_DIR}/sc_main.cpp +) +target_link_libraries (${PROJECT_NAME} PUBLIC test_util) + +catch_discover_tests(${PROJECT_NAME}) diff --git a/tests/ace_pin_level/ace_narrow_burst_test.cpp b/tests/ace_pin_level/ace_narrow_burst_test.cpp new file mode 100644 index 0000000..5800a76 --- /dev/null +++ b/tests/ace_pin_level/ace_narrow_burst_test.cpp @@ -0,0 +1,242 @@ + +#include "testbench.h" +#include +#include +#undef CHECK +#include +#include + +using namespace sc_core; + +factory::add tb; + +bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b){ + auto ret = true; + ret &= a.get_command() == b.get_command(); + ret &= a.get_address() == b.get_address(); + ret &= a.get_data_length() == b.get_data_length(); + for(auto i=0u; i +tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) { + auto trans = tlm::scc::tlm_mm<>::get().allocate(len); + trans->set_address(start_address); + tlm::scc::setId(*trans, id); + auto ext = trans->get_extension(); + trans->set_data_length(len); + trans->set_streaming_width(len); + ext->set_size(scc::ilog2(width)); + sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0); + auto length = (len * 8 - 1) / (8*width); + if(width==(bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8)) + length++; + ext->set_length(length); + // ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED); + ext->set_burst(axi::burst_e::INCR); + ext->set_id(id); + return trans; +} + +template +tlm::tlm_generic_payload* prepare_trans_ace(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) { + auto trans = tlm::scc::tlm_mm<>::get().allocate(len); + trans->set_address(start_address); + tlm::scc::setId(*trans, id); + auto ext = trans->get_extension(); + trans->set_data_length(len); + trans->set_streaming_width(len); + ext->set_size(scc::ilog2(width)); + sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0); + auto length = (len * 8 - 1) / (8*width); + if(width==(bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8)) + length++; + ext->set_length(length); + // ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED); + ext->set_burst(axi::burst_e::INCR); + ext->set_id(id); + ext->set_snoop(axi::snoop_e::READ_SHARED); // set it so that is_data_less return true??? + return trans; +} + +inline void randomize(tlm::tlm_generic_payload& gp) { + static uint8_t req_cnt{0}; + auto addr = gp.get_address(); + uint8_t const* src = reinterpret_cast(&addr); + for(size_t i = 0; i < gp.get_data_length(); ++i) { + *(gp.get_data_ptr() + i) = i % 2 ? i : req_cnt; + } + req_cnt++; +} + +template +unsigned run_scenario(STATE& state){ + auto& dut = factory::get(); + + dut.axi_tgt_pe.set_operation_cb([&state](axi::axi_protocol_types::tlm_payload_type& trans) -> unsigned { + auto id = axi::get_axi_id(trans); + if(trans.is_read()) { + for(size_t i = 0; i < trans.get_data_length(); ++i) { + *(trans.get_data_ptr() + i) = i % 2 ? 123 : (state.resp_cnt+128); + } + state.read_tx[id].second.emplace_back(&trans); + } + if(trans.is_write()) + state.write_tx[id].second.emplace_back(&trans); + SCCDEBUG(__FUNCTION__)<<"RX: "<(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1); + tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1); + trans->set_command(tlm::TLM_READ_COMMAND); + SCCDEBUG(__FUNCTION__) << "run1, iteration " << i <<" TX: "<<*trans; + dut.intor_pe.transport(*trans, false); + state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans); + StartAddr += state.BurstSizeBytes; + } + }); +/* + auto run2 = sc_spawn([&dut, &state](){ + unsigned int StartAddr{0x2000}; + for(int i = 0; i < state.NumberOfIterations; ++i) { + tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 2); + trans->set_command(tlm::TLM_WRITE_COMMAND); + randomize(*trans); + SCCDEBUG(__FUNCTION__) << "run2, iteration " << i <<" TX: "<<*trans; + dut.intor_pe.transport(*trans, false); + state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans); + StartAddr += state.BurstSizeBytes; + } + }); + auto run3 = sc_spawn([&dut, &state](){ + unsigned int StartAddr{0x1000}; + for(int i = 0; i < state.NumberOfIterations; ++i) { + tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 3); + trans->set_command(tlm::TLM_READ_COMMAND); + SCCDEBUG(__FUNCTION__) << "run3, iteration " << i <<" TX: "<<*trans; + dut.intor_pe.transport(*trans, false); + state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans); + StartAddr += state.BurstSizeBytes; + } + }); + auto run4 = sc_spawn([&dut, &state](){ + unsigned int StartAddr{0x3000}; + for(int i = 0; i < state.NumberOfIterations; ++i) { + tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 4); + trans->set_command(tlm::TLM_WRITE_COMMAND); + randomize(*trans); + SCCDEBUG(__FUNCTION__) << "run4, iteration " << i <<" TX: "<<*trans; + dut.intor_pe.transport(*trans, false); + state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans); + StartAddr += state.BurstSizeBytes; + } + }); +*/ + unsigned cycles{0}; + // while(cycles<1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())){ + while(cycles<1000 && !(run1.terminated())){ + sc_start(10 * dut.clk.period()); + cycles+=10; + } + return cycles; +} + +TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") { + struct { + unsigned int ResetCycles{4}; + // unsigned int BurstLengthByte{16}; + unsigned int BurstLengthByte{32}; + unsigned int BurstSizeBytes{8}; +// unsigned int NumberOfIterations{8}; + unsigned int NumberOfIterations{1}; + std::unordered_map, std::vector>> read_tx; + std::unordered_map, std::vector>> write_tx; + unsigned resp_cnt{0}; + } state; + + auto cycles = run_scenario(state); + + REQUIRE(cycles<1000); + REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0); + REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0); + + REQUIRE(state.resp_cnt==4*state.NumberOfIterations); + for(auto& e: state.write_tx) { + auto const& send_tx = e.second.first; + auto const& recv_tx = e.second.second; + REQUIRE(send_tx.size() == recv_tx.size()); + for(auto i = 0; iget_response_status() == tlm::TLM_OK_RESPONSE); + CHECK(*send_tx[i] == *recv_tx[i]); + } + + } + for(auto& e: state.read_tx) { + auto const& send_tx = e.second.first; + auto const& recv_tx = e.second.second; + REQUIRE(send_tx.size() == recv_tx.size()); + for(auto i = 0; iget_response_status() == tlm::TLM_OK_RESPONSE); + CHECK(*send_tx[i] == *recv_tx[i]); + } + } +} + +TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { + struct { + unsigned int ResetCycles{4}; + unsigned int BurstLengthByte{32}; + // unsigned int BurstLengthByte{16}; + unsigned int BurstSizeBytes{4}; + // unsigned int NumberOfIterations{8}; + unsigned int NumberOfIterations{1}; + std::unordered_map, std::vector>> read_tx; + std::unordered_map, std::vector>> write_tx; + unsigned resp_cnt{0}; + } state; + + auto cycles = run_scenario(state); + + REQUIRE(cycles<1000); + REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0); + REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0); + + REQUIRE(state.resp_cnt==4*state.NumberOfIterations); + for(auto& e: state.write_tx) { + auto const& send_tx = e.second.first; + auto const& recv_tx = e.second.second; + REQUIRE(send_tx.size() == recv_tx.size()); + for(auto i = 0; i +#include +#include +#include +#include +#include +#include + +using namespace sc_core; +using namespace axi; +using namespace axi::pe; + +class testbench : public sc_core::sc_module { +public: + using bus_cfg = axi::ace_cfg; + + sc_core::sc_time clk_period{10, sc_core::SC_NS}; + sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true}; + sc_core::sc_signal rst{"rst"}; + // initiator side + axi::ace_initiator_socket intor{"ace_intor"}; + + axi::pin::ace_initiator intor_bfm{"ace_intor_bfm"}; + // signal accurate bus + axi::aw_ch_ace aw; + axi::wdata_ch_ace wdata; + axi::b_ch_ace b; + axi::ar_ch_ace ar; + axi::rresp_ch_ace rresp; + + axi::pin::ace_target tgt_bfm{"ace_tgt_bfm"}; + // target side + axi::ace_target_socket tgt_ace{"tgt_ace"}; + axi::axi_target_socket tgt_axi{"tgt_axi"}; + // engines + axi::pe::ace_initiator intor_pe; + axi::pe::simple_target axi_tgt_pe; + axi::pe::simple_ace_target ace_tgt_pe; + +public: + SC_HAS_PROCESS(testbench); + testbench(): testbench("testbench") {} + testbench(sc_core::sc_module_name nm) + : sc_core::sc_module(nm) + , intor_pe("ace_intor_pe", intor) + , ace_tgt_pe("ace_tgt_pe", tgt_ace) + , axi_tgt_pe("axi_tgt_pe", tgt_axi) { + intor_pe.clk_i(clk); + intor_bfm.clk_i(clk); + tgt_bfm.clk_i(clk); + axi_tgt_pe.clk_i(clk); + ace_tgt_pe.clk_i(clk); + // pe socket to recorder + intor(intor_bfm.tsckt); + + // bfm to signals + intor_bfm.bind_aw(aw); + intor_bfm.bind_w(wdata); + intor_bfm.bind_b(b); + intor_bfm.bind_ar(ar); + intor_bfm.bind_r(rresp); + // signals to bfm + tgt_bfm.bind_aw(aw); + tgt_bfm.bind_w(wdata); + tgt_bfm.bind_b(b); + tgt_bfm.bind_ar(ar); + tgt_bfm.bind_r(rresp); + // bfm to recorder + tgt_bfm.isckt(tgt_ace); + + ace_tgt_pe.isckt_axi(tgt_axi); + + } + + + void run1() { + } +}; + +#endif // _TESTBENCH_H_ From e30a569cfa1f63f18831eabd894f52509c932373 Mon Sep 17 00:00:00 2001 From: Hongyu Liu Date: Wed, 4 Oct 2023 22:17:38 +0200 Subject: [PATCH 4/5] updates ace_pin_level testcase with snoop and updates scc --- scc | 2 +- tests/ace_pin_level/ace_narrow_burst_test.cpp | 110 ++++++++++++++---- tests/ace_pin_level/testbench.h | 28 ++++- 3 files changed, 112 insertions(+), 28 deletions(-) diff --git a/scc b/scc index a21316a..b205dce 160000 --- a/scc +++ b/scc @@ -1 +1 @@ -Subproject commit a21316a97fff4953a3c08d32f6b97cf6d11d441e +Subproject commit b205dce627b36cc865c9da372a2e84e927a5e12a diff --git a/tests/ace_pin_level/ace_narrow_burst_test.cpp b/tests/ace_pin_level/ace_narrow_burst_test.cpp index 5800a76..7b2517a 100644 --- a/tests/ace_pin_level/ace_narrow_burst_test.cpp +++ b/tests/ace_pin_level/ace_narrow_burst_test.cpp @@ -10,6 +10,21 @@ using namespace sc_core; factory::add tb; +struct { + unsigned int ResetCycles{4}; + unsigned int BurstLengthByte{16}; +// unsigned int BurstLengthByte{32}; + unsigned int BurstSizeBytes{8}; +// unsigned int NumberOfIterations{8}; + unsigned int NumberOfIterations{2}; + std::unordered_map, std::vector>> read_tx; + std::unordered_map, std::vector>> write_tx; + std::unordered_map, std::vector>> snoop_tx; + unsigned resp_cnt{0}; +} state; + +int snoop_id=0; + bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b){ auto ret = true; ret &= a.get_command() == b.get_command(); @@ -78,6 +93,31 @@ inline void randomize(tlm::tlm_generic_payload& gp) { req_cnt++; } +unsigned testbench::transport(tlm::tlm_generic_payload& trans) { + SCCDEBUG(__FUNCTION__)<<" update trans for snoop, with snoop_id = " << snoop_id; + // SCCDEBUG(__FUNCTION__)<<" in transport with trans " << trans; + // extracting address and snoop_e from ac_trans and pack them into cache data trans + auto ac_address = trans.get_address(); + auto ext = trans.get_extension(); + auto ac_snoop=ext->get_snoop(); + + for(size_t i = 0; i < trans.get_data_length(); ++i) { + *(trans.get_data_ptr() + i) = i % 2 ? 123 : 128; + } + SCCDEBUG(__FUNCTION__)<<" vector size " <set_snoop_data_transfer(true); + ext->set_snoop_error(false); + ext->set_pass_dirty(false); + ext->set_shared(false); + ext->set_snoop_was_unique(false); + */ + return 1; + +} + template unsigned run_scenario(STATE& state){ auto& dut = factory::get(); @@ -97,8 +137,6 @@ unsigned run_scenario(STATE& state){ return 0; }); - - dut.rst.write(false); sc_start(state.ResetCycles*dut.clk.period()); dut.rst.write(true); @@ -116,7 +154,7 @@ unsigned run_scenario(STATE& state){ StartAddr += state.BurstSizeBytes; } }); -/* + auto run2 = sc_spawn([&dut, &state](){ unsigned int StartAddr{0x2000}; for(int i = 0; i < state.NumberOfIterations; ++i) { @@ -152,10 +190,26 @@ unsigned run_scenario(STATE& state){ StartAddr += state.BurstSizeBytes; } }); -*/ + + + auto run5 = sc_spawn([&dut, &state](){ + unsigned int StartAddr{0x0}; + for(int i = 0; i < state.NumberOfIterations; ++i) { + // tlm::scc::tlm_gp_shared_ptr trans = prepare_trans(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1); + tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1); + trans->set_command(tlm::TLM_READ_COMMAND); + SCCDEBUG(__FUNCTION__) << "run1, iteration " << i << "snoop_id = " << snoop_id <<" TX: "<<*trans; + dut.ace_tgt_pe.snoop(*trans); + state.snoop_tx[snoop_id].first.emplace_back(trans); + snoop_id++; + StartAddr += state.BurstSizeBytes; + } + }); + + unsigned cycles{0}; - // while(cycles<1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())){ - while(cycles<1000 && !(run1.terminated())){ + while(cycles<1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())){ + // while(cycles<1000 && !(run1.terminated())){ sc_start(10 * dut.clk.period()); cycles+=10; } @@ -163,25 +217,16 @@ unsigned run_scenario(STATE& state){ } TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") { - struct { - unsigned int ResetCycles{4}; - // unsigned int BurstLengthByte{16}; - unsigned int BurstLengthByte{32}; - unsigned int BurstSizeBytes{8}; -// unsigned int NumberOfIterations{8}; - unsigned int NumberOfIterations{1}; - std::unordered_map, std::vector>> read_tx; - std::unordered_map, std::vector>> write_tx; - unsigned resp_cnt{0}; - } state; + state.resp_cnt=0; auto cycles = run_scenario(state); REQUIRE(cycles<1000); REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0); REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0); - REQUIRE(state.resp_cnt==4*state.NumberOfIterations); + REQUIRE(state.resp_cnt==4*state.NumberOfIterations); + // REQUIRE(state.resp_cnt==1*state.NumberOfIterations); for(auto& e: state.write_tx) { auto const& send_tx = e.second.first; auto const& recv_tx = e.second.second; @@ -192,22 +237,40 @@ TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") { } } + for(auto& e: state.read_tx) { auto const& send_tx = e.second.first; auto const& recv_tx = e.second.second; REQUIRE(send_tx.size() == recv_tx.size()); for(auto i = 0; iget_response_status() == tlm::TLM_OK_RESPONSE); + SCCDEBUG(__FUNCTION__) << " index = " << i ; + // SCCDEBUG(__FUNCTION__) <<" send value = "<<*send_tx[i]; + // SCCDEBUG(__FUNCTION__) <<" received value = "<<*recv_tx[i]; CHECK(*send_tx[i] == *recv_tx[i]); } } + + for(auto& e: state.snoop_tx) { + auto const& snoop_tx = e.second.first; + auto const& recv_tx = e.second.second; + REQUIRE(snoop_tx.size() == recv_tx.size()); + for(auto i = 0; iget_response_status() == tlm::TLM_OK_RESPONSE); + SCCDEBUG(__FUNCTION__) << " index = " << i ; + SCCDEBUG(__FUNCTION__) <<" send snoop value = "<<*snoop_tx[i]; + SCCDEBUG(__FUNCTION__) <<" received value = "<<*recv_tx[i]; + // CHECK(*snoop_tx[i] == *recv_tx[i]); + } + } + } TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { - struct { + /* struct { unsigned int ResetCycles{4}; - unsigned int BurstLengthByte{32}; - // unsigned int BurstLengthByte{16}; + // unsigned int BurstLengthByte{32}; + unsigned int BurstLengthByte{16}; unsigned int BurstSizeBytes{4}; // unsigned int NumberOfIterations{8}; unsigned int NumberOfIterations{1}; @@ -215,7 +278,8 @@ TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { std::unordered_map, std::vector>> write_tx; unsigned resp_cnt{0}; } state; - +*/ + state.resp_cnt=0; auto cycles = run_scenario(state); REQUIRE(cycles<1000); @@ -240,3 +304,5 @@ TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { } } + + diff --git a/tests/ace_pin_level/testbench.h b/tests/ace_pin_level/testbench.h index faf5fa0..9e39696 100644 --- a/tests/ace_pin_level/testbench.h +++ b/tests/ace_pin_level/testbench.h @@ -13,16 +13,18 @@ using namespace sc_core; using namespace axi; using namespace axi::pe; -class testbench : public sc_core::sc_module { +class testbench : public sc_core::sc_module + ,public tlm::scc::pe::intor_bw_b { public: using bus_cfg = axi::ace_cfg; sc_core::sc_time clk_period{10, sc_core::SC_NS}; sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true}; sc_core::sc_signal rst{"rst"}; + // test interface, which is bound to initiator bw_o + sc_core::sc_export bw_i{"bw_i"}; // initiator side axi::ace_initiator_socket intor{"ace_intor"}; - axi::pin::ace_initiator intor_bfm{"ace_intor_bfm"}; // signal accurate bus axi::aw_ch_ace aw; @@ -30,6 +32,9 @@ public: axi::b_ch_ace b; axi::ar_ch_ace ar; axi::rresp_ch_ace rresp; + axi::ac_ch_ace ac; + axi::cr_ch_ace cr; + axi::cd_ch_ace cd; axi::pin::ace_target tgt_bfm{"ace_tgt_bfm"}; // target side @@ -48,6 +53,8 @@ public: , intor_pe("ace_intor_pe", intor) , ace_tgt_pe("ace_tgt_pe", tgt_ace) , axi_tgt_pe("axi_tgt_pe", tgt_axi) { + + bw_i.bind(*this); intor_pe.clk_i(clk); intor_bfm.clk_i(clk); tgt_bfm.clk_i(clk); @@ -62,20 +69,31 @@ public: intor_bfm.bind_b(b); intor_bfm.bind_ar(ar); intor_bfm.bind_r(rresp); + + intor_bfm.bind_ac(ac); + intor_bfm.bind_cr(cr); + intor_bfm.bind_cd(cd); + // signals to bfm tgt_bfm.bind_aw(aw); tgt_bfm.bind_w(wdata); tgt_bfm.bind_b(b); tgt_bfm.bind_ar(ar); tgt_bfm.bind_r(rresp); - // bfm to recorder - tgt_bfm.isckt(tgt_ace); + tgt_bfm.bind_ac(ac); + tgt_bfm.bind_cr(cr); + tgt_bfm.bind_cd(cd); + + // bfm to ace target + tgt_bfm.isckt(tgt_ace); ace_tgt_pe.isckt_axi(tgt_axi); + // for updating snooop transaction + intor_pe.bw_o(bw_i); } - + unsigned transport(tlm::tlm_generic_payload& trans) override ; void run1() { } }; From f83e61aa1fcc7a3908c55986776f152787f7b411 Mon Sep 17 00:00:00 2001 From: Hongyu Liu Date: Thu, 5 Oct 2023 15:36:33 +0200 Subject: [PATCH 5/5] updates ace_pin_level testcase with cacheline and scc --- scc | 2 +- tests/ace_pin_level/ace_narrow_burst_test.cpp | 56 +++++-------------- tests/ace_pin_level/testbench.h | 2 +- 3 files changed, 16 insertions(+), 44 deletions(-) diff --git a/scc b/scc index b205dce..77a9f22 160000 --- a/scc +++ b/scc @@ -1 +1 @@ -Subproject commit b205dce627b36cc865c9da372a2e84e927a5e12a +Subproject commit 77a9f223d7dc8cf838d95155f6023385bd6fdd03 diff --git a/tests/ace_pin_level/ace_narrow_burst_test.cpp b/tests/ace_pin_level/ace_narrow_burst_test.cpp index 7b2517a..8202712 100644 --- a/tests/ace_pin_level/ace_narrow_burst_test.cpp +++ b/tests/ace_pin_level/ace_narrow_burst_test.cpp @@ -15,8 +15,9 @@ struct { unsigned int BurstLengthByte{16}; // unsigned int BurstLengthByte{32}; unsigned int BurstSizeBytes{8}; -// unsigned int NumberOfIterations{8}; - unsigned int NumberOfIterations{2}; + // unsigned int NumberOfIterations{8}; + unsigned int NumberOfIterations{2}; + unsigned int CachelineSizeBytes={64}; // std::unordered_map, std::vector>> read_tx; std::unordered_map, std::vector>> write_tx; std::unordered_map, std::vector>> snoop_tx; @@ -42,26 +43,6 @@ bool operator==(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload cons return ret; } -template -tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) { - auto trans = tlm::scc::tlm_mm<>::get().allocate(len); - trans->set_address(start_address); - tlm::scc::setId(*trans, id); - auto ext = trans->get_extension(); - trans->set_data_length(len); - trans->set_streaming_width(len); - ext->set_size(scc::ilog2(width)); - sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0); - auto length = (len * 8 - 1) / (8*width); - if(width==(bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8)) - length++; - ext->set_length(length); - // ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED); - ext->set_burst(axi::burst_e::INCR); - ext->set_id(id); - return trans; -} - template tlm::tlm_generic_payload* prepare_trans_ace(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) { auto trans = tlm::scc::tlm_mm<>::get().allocate(len); @@ -77,7 +58,10 @@ tlm::tlm_generic_payload* prepare_trans_ace(uint64_t start_address, unsigned add length++; ext->set_length(length); // ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED); - ext->set_burst(axi::burst_e::INCR); + // here len is CachelineSizeBytes + // here burtst for read/write_trans and snoop_trans are different + ext->set_burst(axi::burst_e::INCR); //TBD??? + //ext->set_burst(len*8 > bus_cfg::BUSWIDTH ? axi::burst_e::WRAP : axi::burst_e::INCR); ext->set_id(id); ext->set_snoop(axi::snoop_e::READ_SHARED); // set it so that is_data_less return true??? return trans; @@ -94,7 +78,7 @@ inline void randomize(tlm::tlm_generic_payload& gp) { } unsigned testbench::transport(tlm::tlm_generic_payload& trans) { - SCCDEBUG(__FUNCTION__)<<" update trans for snoop, with snoop_id = " << snoop_id; + SCCDEBUG(__FUNCTION__)<<" update snoop trans, with snoop_id = " << snoop_id; // SCCDEBUG(__FUNCTION__)<<" in transport with trans " << trans; // extracting address and snoop_e from ac_trans and pack them into cache data trans auto ac_address = trans.get_address(); @@ -102,9 +86,9 @@ unsigned testbench::transport(tlm::tlm_generic_payload& trans) { auto ac_snoop=ext->get_snoop(); for(size_t i = 0; i < trans.get_data_length(); ++i) { - *(trans.get_data_ptr() + i) = i % 2 ? 123 : 128; + *(trans.get_data_ptr() + i) = i % 2 ? i : 128; } - SCCDEBUG(__FUNCTION__)<<" vector size " <(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1); - tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1); + tlm::scc::tlm_gp_shared_ptr trans = prepare_trans_ace(StartAddr, 4, state.CachelineSizeBytes, state.BurstSizeBytes, 5); trans->set_command(tlm::TLM_READ_COMMAND); SCCDEBUG(__FUNCTION__) << "run1, iteration " << i << "snoop_id = " << snoop_id <<" TX: "<<*trans; dut.ace_tgt_pe.snoop(*trans); + SCCDEBUG(__FUNCTION__) << "run1, after iteration "<< i ; state.snoop_tx[snoop_id].first.emplace_back(trans); snoop_id++; StartAddr += state.BurstSizeBytes; @@ -209,7 +193,7 @@ unsigned run_scenario(STATE& state){ unsigned cycles{0}; while(cycles<1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())){ - // while(cycles<1000 && !(run1.terminated())){ + // while(cycles<1000 && !(run5.terminated())){ sc_start(10 * dut.clk.period()); cycles+=10; } @@ -221,7 +205,7 @@ TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") { state.resp_cnt=0; auto cycles = run_scenario(state); - REQUIRE(cycles<1000); + // REQUIRE(cycles<1000); REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0); REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0); @@ -267,18 +251,6 @@ TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") { } TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { - /* struct { - unsigned int ResetCycles{4}; - // unsigned int BurstLengthByte{32}; - unsigned int BurstLengthByte{16}; - unsigned int BurstSizeBytes{4}; - // unsigned int NumberOfIterations{8}; - unsigned int NumberOfIterations{1}; - std::unordered_map, std::vector>> read_tx; - std::unordered_map, std::vector>> write_tx; - unsigned resp_cnt{0}; - } state; -*/ state.resp_cnt=0; auto cycles = run_scenario(state); diff --git a/tests/ace_pin_level/testbench.h b/tests/ace_pin_level/testbench.h index 9e39696..c0e23cf 100644 --- a/tests/ace_pin_level/testbench.h +++ b/tests/ace_pin_level/testbench.h @@ -16,7 +16,7 @@ using namespace axi::pe; class testbench : public sc_core::sc_module ,public tlm::scc::pe::intor_bw_b { public: - using bus_cfg = axi::ace_cfg; + using bus_cfg = axi::ace_cfg; sc_core::sc_time clk_period{10, sc_core::SC_NS}; sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true};