137 lines
4.0 KiB
C++
137 lines
4.0 KiB
C++
// -*- C++ -*- <this line is for emacs to recognize it as C++ code>
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/*****************************************************************************
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Licensed to Accellera Systems Initiative Inc. (Accellera)
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under one or more contributor license agreements. See the
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NOTICE file distributed with this work for additional
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information regarding copyright ownership. Accellera licenses
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this file to you under the Apache License, Version 2.0 (the
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"License"); you may not use this file except in compliance
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with the License. You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing,
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software distributed under the License is distributed on an
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"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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KIND, either express or implied. See the License for the
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specific language governing permissions and limitations
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under the License.
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*****************************************************************************/
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// this code compiles and runs with our latest prototype for this specification
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#include <scv.h>
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#include <systemc.h>
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// hack to fake a true fifo_mutex
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#define fifo_mutex sc_mutex
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const unsigned ram_size = 256;
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class rw_task_if : virtual public sc_interface {
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public:
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typedef sc_uint<8> addr_t;
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typedef sc_uint<8> data_t;
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struct write_t {
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addr_t addr;
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data_t data;
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};
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virtual data_t read(const addr_t*) = 0;
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virtual void write(const write_t*) = 0;
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};
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SCV_EXTENSIONS(rw_task_if::write_t) {
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public:
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scv_extensions<rw_task_if::addr_t> addr;
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scv_extensions<rw_task_if::data_t> data;
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SCV_EXTENSIONS_CTOR(rw_task_if::write_t) {
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SCV_FIELD(addr);
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SCV_FIELD(data);
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}
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};
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class pipelined_bus_ports : public sc_module {
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public:
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sc_in< bool > clk;
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sc_inout< bool > rw;
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sc_inout< bool > addr_req;
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sc_inout< bool > addr_ack;
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sc_inout< sc_uint<8> > bus_addr;
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sc_inout< bool > data_rdy;
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sc_inout< sc_uint<8> > bus_data;
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SC_CTOR(pipelined_bus_ports)
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: clk("clk"), rw("rw"),
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addr_req("addr_req"),
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addr_ack("addr_ack"), bus_addr("bus_addr"),
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data_rdy("data_rdy"), bus_data("bus_data") {}
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};
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class rw_pipelined_transactor
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: public rw_task_if,
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public pipelined_bus_ports {
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fifo_mutex addr_phase;
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fifo_mutex data_phase;
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scv_tr_stream pipelined_stream;
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scv_tr_stream addr_stream;
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scv_tr_stream data_stream;
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scv_tr_generator<sc_uint<8>, sc_uint<8> > read_gen;
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scv_tr_generator<sc_uint<8>, sc_uint<8> > write_gen;
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scv_tr_generator<sc_uint<8> > addr_gen;
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scv_tr_generator<sc_uint<8> > data_gen;
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public:
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rw_pipelined_transactor(sc_module_name nm) :
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pipelined_bus_ports(nm),
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addr_phase("addr_phase"),
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data_phase("data_phase"),
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pipelined_stream("pipelined_stream", "transactor"),
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addr_stream("addr_stream", "transactor"),
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data_stream("data_stream", "transactor"),
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read_gen("read",pipelined_stream,"addr","data"),
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write_gen("write",pipelined_stream,"addr","data"),
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addr_gen("addr",addr_stream,"addr"),
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data_gen("data",data_stream,"data")
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{}
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virtual data_t read(const addr_t* p_addr);
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virtual void write(const write_t * req);
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};
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class test : public sc_module {
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public:
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sc_port< rw_task_if > transactor;
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SC_CTOR(test) {
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SC_THREAD(main);
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}
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void main();
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};
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class write_constraint : virtual public scv_constraint_base {
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public:
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scv_smart_ptr<rw_task_if::write_t> write;
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SCV_CONSTRAINT_CTOR(write_constraint) {
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SCV_CONSTRAINT( write->addr() <= ram_size );
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SCV_CONSTRAINT( write->addr() != write->data() );
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}
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};
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inline void process(scv_smart_ptr<int> data) {}
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class design : public pipelined_bus_ports {
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std::list< sc_uint<8> > outstandingAddresses;
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std::list< bool > outstandingType;
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sc_uint<8> memory[ram_size];
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public:
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SC_HAS_PROCESS(design);
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design(sc_module_name nm) : pipelined_bus_ports(nm) {
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for (unsigned i=0; i<ram_size; ++i) { memory[i] = i; }
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SC_THREAD(addr_phase);
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SC_THREAD(data_phase);
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}
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void addr_phase();
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void data_phase();
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};
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