diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml index fa7a16b..f7167aa 100644 --- a/.settings/language.settings.xml +++ b/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + @@ -19,7 +19,7 @@ - + diff --git a/components/CMakeLists.txt b/components/CMakeLists.txt index ea1c1af..7e747a5 100644 --- a/components/CMakeLists.txt +++ b/components/CMakeLists.txt @@ -2,6 +2,8 @@ set(LIB_SOURCES initiator.cpp logging.cpp target.cpp + clkgen.cpp + resetgen.cpp ) # Define two variables in order not to repeat ourselves. diff --git a/components/clkgen.cpp b/components/clkgen.cpp new file mode 100644 index 0000000..1a44a65 --- /dev/null +++ b/components/clkgen.cpp @@ -0,0 +1,23 @@ +/* + * clkgen.cpp + * + * Created on: 02.01.2019 + * Author: eyck + */ + +#include +#include + +ClkGen::ClkGen(const sc_core::sc_module_name& nm) +: sc_core::sc_module(nm) +, clk_o("clk_o") +{ +} + +ClkGen::~ClkGen() { + // TODO Auto-generated destructor stub +} + +void ClkGen::end_of_elabortation() { + clk_o.write(10_ns); +} diff --git a/components/clkgen.h b/components/clkgen.h new file mode 100644 index 0000000..47edca9 --- /dev/null +++ b/components/clkgen.h @@ -0,0 +1,23 @@ +/* + * clkgen.h + * + * Created on: 02.01.2019 + * Author: eyck + */ + +#ifndef COMPONENTS_CLKGEN_H_ +#define COMPONENTS_CLKGEN_H_ + +#include + +class ClkGen: public sc_core::sc_module { +public: + sc_core::sc_out clk_o; + + ClkGen(const sc_core::sc_module_name&); + virtual ~ClkGen(); +protected: + void end_of_elabortation(); +}; + +#endif /* COMPONENTS_CLKGEN_H_ */ diff --git a/components/components.h b/components/components.h index 9ce61eb..ea11817 100644 --- a/components/components.h +++ b/components/components.h @@ -8,8 +8,8 @@ #ifndef COMPONENTS_H_ #define COMPONENTS_H_ -//#include "tx_example_mods.h" -//#include "logging.h" +#include "clkgen.h" +#include "resetgen.h" #include "initiator.h" #include "router.h" #include "target.h" diff --git a/components/initiator.cpp b/components/initiator.cpp index f47a4a7..90f64f1 100644 --- a/components/initiator.cpp +++ b/components/initiator.cpp @@ -12,6 +12,8 @@ Initiator::Initiator(::sc_core::sc_module_name nm) : socket("socket") // Construct and name socket +, clk_i("clk_i") +, reset_i("reset_i") , dmi_ptr_valid(false) { // Register callbacks for incoming interface method calls @@ -21,6 +23,7 @@ Initiator::Initiator(::sc_core::sc_module_name nm) } void Initiator::thread_process() { + wait(reset_i.negedge_event()); { // TLM-2 generic payload transaction, reused across calls to b_transport, DMI and debug tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload; diff --git a/components/initiator.h b/components/initiator.h index b47d11f..95b7854 100644 --- a/components/initiator.h +++ b/components/initiator.h @@ -17,6 +17,9 @@ struct Initiator: sc_module // TLM-2 socket, defaults to 32-bits wide, base protocol tlm_utils::simple_initiator_socket socket; + sc_core::sc_in clk_i; + sc_core::sc_in reset_i; + SC_HAS_PROCESS(Initiator); Initiator( ::sc_core::sc_module_name ); diff --git a/components/resetgen.cpp b/components/resetgen.cpp new file mode 100644 index 0000000..8c86b01 --- /dev/null +++ b/components/resetgen.cpp @@ -0,0 +1,25 @@ +/* + * resetgen.cpp + * + * Created on: 02.01.2019 + * Author: eyck + */ + +#include +#include + +ResetGen::ResetGen(const sc_core::sc_module_name& nm) +: sc_core::sc_module(nm) +, reset_o("reset_o") +{ + SC_THREAD(thread); +} + +ResetGen::~ResetGen() { +} + +void ResetGen::thread() { + reset_o=sc_dt::SC_LOGIC_1; + wait(100_ns); + reset_o=sc_dt::SC_LOGIC_0; +} diff --git a/components/resetgen.h b/components/resetgen.h new file mode 100644 index 0000000..4148ba4 --- /dev/null +++ b/components/resetgen.h @@ -0,0 +1,26 @@ +/* + * resetgen.h + * + * Created on: 02.01.2019 + * Author: eyck + */ + +#ifndef COMPONENTS_RESETGEN_H_ +#define COMPONENTS_RESETGEN_H_ + +#include + +class ResetGen: public sc_core::sc_module { +public: + SC_HAS_PROCESS(ResetGen); + + sc_core::sc_out reset_o; + + ResetGen(const sc_core::sc_module_name&); + virtual ~ResetGen(); +protected: + + void thread(); +}; + +#endif /* COMPONENTS_RESETGEN_H_ */ diff --git a/components/router.h b/components/router.h index 3b9ebaa..34e62b8 100644 --- a/components/router.h +++ b/components/router.h @@ -27,9 +27,14 @@ struct Router: sc_module sc_core::sc_vector> initiator_socket; + sc_core::sc_in clk_i; + sc_core::sc_in reset_i; + SC_CTOR(Router) : target_socket("target_socket") , initiator_socket("socket", N_TARGETS) + , clk_i("clk_i") + , reset_i("reset_i") { // Register callbacks for incoming interface method calls target_socket.register_b_transport( this, &Router::b_transport); diff --git a/components/router_example.cpp b/components/router_example.cpp deleted file mode 100644 index 7dc6f5b..0000000 --- a/components/router_example.cpp +++ /dev/null @@ -1,18 +0,0 @@ -/* - * router_example.cpp - * - * Created on: 02.12.2018 - * Author: eyck - */ - - -#include "top.h" - -int sc_main(int argc, char* argv[]) -{ - Top top("top"); - sc_start(); - return 0; -} - - diff --git a/components/target.cpp b/components/target.cpp index ffeb36b..402c2fc 100644 --- a/components/target.cpp +++ b/components/target.cpp @@ -66,7 +66,10 @@ bool Memory::get_direct_mem_ptr(tlm::tlm_generic_payload& trans, } Memory::Memory(sc_core::sc_module_name nm) -: socket("socket"), LATENCY(10, SC_NS) +: socket("socket") +, clk_i("clk_i") +, reset_i("reset_i") +, LATENCY(10, SC_NS) { // Register callbacks for incoming interface method calls socket.register_b_transport( this, &Memory::b_transport); diff --git a/components/target.h b/components/target.h index 8f9d85e..da11a70 100644 --- a/components/target.h +++ b/components/target.h @@ -19,6 +19,9 @@ struct Memory: sc_module { // TLM-2 socket, defaults to 32-bits wide, base protocol tlm_utils::simple_target_socket socket; + sc_core::sc_in clk_i; + sc_core::sc_in reset_i; + enum { SIZE = 256 }; const sc_time LATENCY; diff --git a/components/top.h b/components/top.h deleted file mode 100644 index a4b995d..0000000 --- a/components/top.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef TOP_H -#define TOP_H - -#include "initiator.h" -#include "target.h" -#include "router.h" - -SC_MODULE(Top) -{ - Initiator* initiator; - Router<4>* router; - Memory* memory[4]; - - SC_CTOR(Top) - { - // Instantiate components - initiator = new Initiator("initiator"); - router = new Router<4>("router"); - for (int i = 0; i < 4; i++) - { - char txt[20]; - sprintf(txt, "memory_%d", i); - memory[i] = new Memory(txt); - } - - // Bind sockets - initiator->socket.bind( router->target_socket ); - for (int i = 0; i < 4; i++) - router->initiator_socket[i].bind( memory[i]->socket ); - } -}; - -#endif diff --git a/components/tx_example.cpp b/components/tx_example.cpp deleted file mode 100644 index 27642ed..0000000 --- a/components/tx_example.cpp +++ /dev/null @@ -1,44 +0,0 @@ -// -*- C++ -*- -/***************************************************************************** - - Licensed to Accellera Systems Initiative Inc. (Accellera) - under one or more contributor license agreements. See the - NOTICE file distributed with this work for additional - information regarding copyright ownership. Accellera licenses - this file to you under the Apache License, Version 2.0 (the - "License"); you may not use this file except in compliance - with the License. You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, - software distributed under the License is distributed on an - "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - KIND, either express or implied. See the License for the - specific language governing permissions and limitations - under the License. - - *****************************************************************************/ -// this code compiles and runs with our latest prototype for this specification - -#include "txtop.h" - -int sc_main (int argc , char *argv[]) -{ - scv_startup(); - - scv_tr_text_init(); - scv_tr_db db("transaction_example.txlog"); - scv_tr_db::set_default_db(&db); - - tx_top top("top"); - - // Accellera SystemC >=2.2 got picky about multiple drivers. - // Disable check for bus simulation. - sc_report_handler::set_actions(SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, SC_DO_NOTHING); - // run the simulation - sc_start(1.0, SC_MS); - - return 0; -} - diff --git a/components/tx_example_mods.cpp b/components/tx_example_mods.cpp deleted file mode 100644 index d7d746a..0000000 --- a/components/tx_example_mods.cpp +++ /dev/null @@ -1,140 +0,0 @@ -// -*- C++ -*- -/***************************************************************************** - - Licensed to Accellera Systems Initiative Inc. (Accellera) - under one or more contributor license agreements. See the - NOTICE file distributed with this work for additional - information regarding copyright ownership. Accellera licenses - this file to you under the Apache License, Version 2.0 (the - "License"); you may not use this file except in compliance - with the License. You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, - software distributed under the License is distributed on an - "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - KIND, either express or implied. See the License for the - specific language governing permissions and limitations - under the License. - - *****************************************************************************/ -// this code compiles and runs with our latest prototype for this specification - -#include "tx_example_mods.h" - -rw_task_if::data_t rw_pipelined_transactor::read(const rw_task_if::addr_t* -addr) { - addr_phase.lock(); - scv_tr_handle h = read_gen.begin_transaction(*addr); - - scv_tr_handle h1 = addr_gen.begin_transaction(*addr,"addr_phase",h); - wait(clk->posedge_event()); - bus_addr = *addr; - addr_req = 1; - wait(addr_ack->posedge_event()); - wait(clk->negedge_event()); - addr_req = 0; - wait(addr_ack->negedge_event()); - addr_gen.end_transaction(h1); - addr_phase.unlock(); - - data_phase.lock(); - scv_tr_handle h2 = data_gen.begin_transaction("data_phase",h); - wait(data_rdy->posedge_event()); - data_t data = bus_data.read(); - wait(data_rdy->negedge_event()); - data_gen.end_transaction(h2); - read_gen.end_transaction(h,data); - data_phase.unlock(); - - return data; -} - -void rw_pipelined_transactor::write(const write_t * req) { - scv_tr_handle h = write_gen.begin_transaction(req->addr); - // ... - write_gen.end_transaction(h,req->data); -} - -void test::main() { - // simple sequential tests - for (int i=0; i<3; i++) { - rw_task_if::addr_t addr = i; - rw_task_if::data_t data = transactor->read(&addr); - cout << "at time " << sc_time_stamp() << ": "; - cout << "received data : " << data << endl; - } - - scv_smart_ptr addr; - for (int i=0; i<3; i++) { - - addr->next(); - rw_task_if::data_t data = transactor->read( addr->get_instance() ); - cout << "data for address " << *addr << " is " << data << endl; - } - - scv_smart_ptr write; - for (int i=0; i<3; i++) { - write->next(); - transactor->write( write->get_instance() ); - cout << "send data : " << write->data << endl; - } - - scv_smart_ptr data; - scv_bag distribution; - distribution.push(1,40); - distribution.push(2,60); - data->set_mode(distribution); - for (int i=0;i<3; i++) { data->next(); process(data); } -} - -void design::addr_phase() { - while (1) { - while (addr_req.read() != 1) { - wait(addr_req->value_changed_event()); - } - sc_uint<8> _addr = bus_addr.read(); - bool _rw = rw.read(); - - int cycle = rand() % 10 + 1; - while (cycle-- > 0) { - wait(clk->posedge_event()); - } - - addr_ack = 1; - wait(clk->posedge_event()); - addr_ack = 0; - - outstandingAddresses.push_back(_addr); - outstandingType.push_back(_rw); - cout << "at time " << sc_time_stamp() << ": "; - cout << "received request for memory address " << _addr << endl; - } -} - -void design::data_phase() { - while (1) { - while (outstandingAddresses.empty()) { - wait(clk->posedge_event()); - } - int cycle = rand() % 10 + 1; - while (cycle-- > 0) { - wait(clk->posedge_event()); - } - if (outstandingType.front() == 0) { - cout << "reading memory address " << outstandingAddresses.front() - << " with value " << memory[outstandingAddresses.front().to_ulong()] << endl; - bus_data = memory[outstandingAddresses.front().to_ulong()]; - data_rdy = 1; - wait(clk->posedge_event()); - data_rdy = 0; - - } else { - cout << "not implemented yet" << endl; - } - outstandingAddresses.pop_front(); - outstandingType.pop_front(); - } -} - diff --git a/components/tx_example_mods.h b/components/tx_example_mods.h deleted file mode 100644 index 341c5cf..0000000 --- a/components/tx_example_mods.h +++ /dev/null @@ -1,136 +0,0 @@ -// -*- C++ -*- -/***************************************************************************** - - Licensed to Accellera Systems Initiative Inc. (Accellera) - under one or more contributor license agreements. See the - NOTICE file distributed with this work for additional - information regarding copyright ownership. Accellera licenses - this file to you under the Apache License, Version 2.0 (the - "License"); you may not use this file except in compliance - with the License. You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, - software distributed under the License is distributed on an - "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY - KIND, either express or implied. See the License for the - specific language governing permissions and limitations - under the License. - - *****************************************************************************/ -// this code compiles and runs with our latest prototype for this specification - -#include -#include - -// hack to fake a true fifo_mutex -#define fifo_mutex sc_mutex - -const unsigned ram_size = 256; - -class rw_task_if : virtual public sc_interface { -public: - typedef sc_uint<8> addr_t; - typedef sc_uint<8> data_t; - struct write_t { - addr_t addr; - data_t data; - }; - - virtual data_t read(const addr_t*) = 0; - virtual void write(const write_t*) = 0; -}; - -SCV_EXTENSIONS(rw_task_if::write_t) { -public: - scv_extensions addr; - scv_extensions data; - SCV_EXTENSIONS_CTOR(rw_task_if::write_t) { - SCV_FIELD(addr); - SCV_FIELD(data); - } -}; - -class pipelined_bus_ports : public sc_module { -public: - sc_in< bool > clk; - sc_inout< bool > rw; - sc_inout< bool > addr_req; - sc_inout< bool > addr_ack; - sc_inout< sc_uint<8> > bus_addr; - sc_inout< bool > data_rdy; - sc_inout< sc_uint<8> > bus_data; - - SC_CTOR(pipelined_bus_ports) - : clk("clk"), rw("rw"), - addr_req("addr_req"), - addr_ack("addr_ack"), bus_addr("bus_addr"), - data_rdy("data_rdy"), bus_data("bus_data") {} -}; - -class rw_pipelined_transactor - : public rw_task_if, - public pipelined_bus_ports { - - fifo_mutex addr_phase; - fifo_mutex data_phase; - - scv_tr_stream pipelined_stream; - scv_tr_stream addr_stream; - scv_tr_stream data_stream; - scv_tr_generator, sc_uint<8> > read_gen; - scv_tr_generator, sc_uint<8> > write_gen; - scv_tr_generator > addr_gen; - scv_tr_generator > data_gen; - -public: - rw_pipelined_transactor(sc_module_name nm) : - pipelined_bus_ports(nm), - addr_phase("addr_phase"), - data_phase("data_phase"), - pipelined_stream("pipelined_stream", "transactor"), - addr_stream("addr_stream", "transactor"), - data_stream("data_stream", "transactor"), - read_gen("read",pipelined_stream,"addr","data"), - write_gen("write",pipelined_stream,"addr","data"), - addr_gen("addr",addr_stream,"addr"), - data_gen("data",data_stream,"data") - {} - virtual data_t read(const addr_t* p_addr); - virtual void write(const write_t * req); -}; -class test : public sc_module { -public: - sc_port< rw_task_if > transactor; - SC_CTOR(test) { - SC_THREAD(main); - } - void main(); -}; - -class write_constraint : virtual public scv_constraint_base { -public: - scv_smart_ptr write; - SCV_CONSTRAINT_CTOR(write_constraint) { - SCV_CONSTRAINT( write->addr() <= ram_size ); - SCV_CONSTRAINT( write->addr() != write->data() ); - } -}; - -inline void process(scv_smart_ptr data) {} -class design : public pipelined_bus_ports { - std::list< sc_uint<8> > outstandingAddresses; - std::list< bool > outstandingType; - sc_uint<8> memory[ram_size]; - -public: - SC_HAS_PROCESS(design); - design(sc_module_name nm) : pipelined_bus_ports(nm) { - for (unsigned i=0; i - -class tx_top: public sc_core::sc_module { -public: - tx_top(sc_core::sc_module_name nm); - virtual ~tx_top(); - sc_core::sc_clock clk; - sc_core::sc_signal< bool > rw; - sc_core::sc_signal< bool > addr_req; - sc_core::sc_signal< bool > addr_ack; - sc_core::sc_signal< sc_dt::sc_uint<8> > bus_addr; - sc_core::sc_signal< bool > data_rdy; - sc_core::sc_signal< sc_dt::sc_uint<8> > bus_data; - test t; - rw_pipelined_transactor tr; - design duv; - -}; - -#endif /* TXTOP_H_ */ diff --git a/router_example.py b/router_example.py index 19486c5..4abe540 100644 --- a/router_example.py +++ b/router_example.py @@ -1,41 +1,56 @@ import os.path -import cppyy +import logging from cppyy import gbl as cpp -import pysysc as scpy +import pysysc ############################################################################### # setup and load ############################################################################### myDir = os.path.dirname( os.path.realpath(__file__)) -conan_err = scpy.read_config_from_conan(os.path.join(myDir, 'conanfile.txt')) -scpy.load_systemc() -print("Loading SC-Components lib") -scpy.add_include_path(os.path.join(myDir, 'sc-components/incl')) -scpy.add_library('scc.h', os.path.join(myDir, 'build/Debug/lib/libsc-components.so')) -print("Loading Components lib") -scpy.add_include_path(os.path.join(myDir, 'components')) -scpy.add_library('components.h', os.path.join(myDir, 'build/Debug/lib/libcomponents.so')) +conan_err = pysysc.read_config_from_conan(os.path.join(myDir, 'conanfile.txt')) +pysysc.load_systemc() +logging.debug("Loading SC-Components lib") +pysysc.add_include_path(os.path.join(myDir, 'sc-components/incl')) +pysysc.add_library('scc.h', os.path.join(myDir, 'build/Debug/lib/libsc-components.so')) +logging.debug("Loading Components lib") +pysysc.add_include_path(os.path.join(myDir, 'components')) +pysysc.add_library('components.h', os.path.join(myDir, 'build/Debug/lib/libcomponents.so')) ############################################################################### # configure ############################################################################### -#cpp.IoRedirector.get().start() cpp.scc.init_logging(cpp.logging.INFO, False); +#cpp.scc.init_logging(cpp.logging.WARNING, False); cpp.sc_core.sc_report_handler.set_actions(cpp.sc_core.SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, cpp.sc_core.SC_DO_NOTHING); ############################################################################### # instantiate ############################################################################### +clkgen = cpp.ClkGen(cpp.sc_core.sc_module_name("clk_gen")) +rstgen = cpp.ResetGen(cpp.sc_core.sc_module_name("rst_gen")) initiator = cpp.Initiator(cpp.sc_core.sc_module_name("initiator")) memories = [cpp.Memory(cpp.sc_core.sc_module_name(name)) for name in ["mem0", "mem1", "mem2", "mem3"]] router = cpp.Router[4](cpp.sc_core.sc_module_name("router")) ############################################################################### +# signals +##################‚‚‚sS############################################################# +sig_clk = cpp.sc_core.sc_signal[cpp.sc_core.sc_time]("clk") +sig_rst = cpp.sc_core.sc_signal[cpp.sc_dt.sc_logic]("rst") +############################################################################### # connect it ############################################################################### +clkgen.clk_o(sig_clk) +rstgen.reset_o(sig_rst) initiator.socket.bind(router.target_socket) +initiator.clk_i(sig_clk) +initiator.reset_i(sig_rst) +router.clk_i(sig_clk) +router.reset_i(sig_rst) for idx,m in enumerate(memories): router.initiator_socket.at(idx).bind(m.socket) + m.clk_i(sig_clk) + m.reset_i(sig_rst) ############################################################################### # run if it is standalone ############################################################################### if __name__ == "__main__": cpp.sc_core.sc_in_action=True cpp.sc_core.sc_start() - print("Done") + logging.debug("Done") diff --git a/router_example2.py b/router_example2.py new file mode 100644 index 0000000..7ccd04c --- /dev/null +++ b/router_example2.py @@ -0,0 +1,49 @@ +import os.path +import logging +from cppyy import gbl as cpp +import pysysc +from pysysc.structural import Connection, Module, Signal +############################################################################### +# setup and load +############################################################################### +myDir = os.path.dirname( os.path.realpath(__file__)) +conan_err = pysysc.read_config_from_conan(os.path.join(myDir, 'conanfile.txt')) +pysysc.load_systemc() +logging.debug("Loading SC-Components lib") +pysysc.add_include_path(os.path.join(myDir, 'sc-components/incl')) +pysysc.add_library('scc.h', os.path.join(myDir, 'build/Debug/lib/libsc-components.so')) +logging.debug("Loading Components lib") +pysysc.add_include_path(os.path.join(myDir, 'components')) +pysysc.add_library('components.h', os.path.join(myDir, 'build/Debug/lib/libcomponents.so')) +############################################################################### +# configure +############################################################################### +cpp.scc.init_logging(cpp.logging.INFO, False); +#cpp.scc.init_logging(cpp.logging.WARNING, False); +cpp.sc_core.sc_report_handler.set_actions(cpp.sc_core.SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, cpp.sc_core.SC_DO_NOTHING); +############################################################################### +# instantiate +############################################################################### +clk_gen = Module(cpp.ClkGen).create("clk_gen") +rst_gen = Module(cpp.ResetGen).create("rst_gen") +initiator = Module(cpp.Initiator).create("initiator") +memories = [Module(cpp.Memory).create(name) for name in ["mem0", "mem1", "mem2", "mem3"]] +router = Module(cpp.Router[4]).create("router") +############################################################################### +# connect it +############################################################################### +clk = Signal("clk").src(clk_gen.clk_o).sink(initiator.clk_i).sink(router.clk_i) +[clk.sink(m.clk_i) for m in memories] +rst = Signal("rst").src(rst_gen.reset_o).sink(initiator.reset_i).sink(router.reset_i) +[rst.sink(m.reset_i) for m in memories] +Connection().src(initiator.socket).sink(router.target_socket) +for idx,m in enumerate(memories): + Connection().src(router.initiator_socket.at(idx)).sink(m.socket) + +############################################################################### +# run if it is standalone +############################################################################### +if __name__ == "__main__": + cpp.sc_core.sc_in_action=True + cpp.sc_core.sc_start() + logging.debug("Done") diff --git a/top/sc_main.cpp b/top/sc_main.cpp index ed65ad2..1c5faae 100644 --- a/top/sc_main.cpp +++ b/top/sc_main.cpp @@ -30,6 +30,7 @@ int sc_main(int argc, char *argv[]) { // configure logging /////////////////////////////////////////////////////////////////////////// scc::init_logging(logging::INFO); + //scc::init_logging(logging::WARNING); /////////////////////////////////////////////////////////////////////////// // instantiate top level diff --git a/top/top.h b/top/top.h new file mode 100644 index 0000000..0b5ea74 --- /dev/null +++ b/top/top.h @@ -0,0 +1,56 @@ +#ifndef TOP_H +#define TOP_H + +#include +#include +#include +#include +#include + +SC_MODULE(Top) { + + ClkGen * clk_gen; + ResetGen* reset_gen; + Initiator* initiator; + Router<4>* router; + Memory* memory[4]; + + Top(const sc_core::sc_module_name& nm) + : sc_core::sc_module() + , clk("clk") + , reset("reset") + { + // Instantiate components + clk_gen=new ClkGen("clk_gen"); + reset_gen=new ResetGen("reset_gen"); + initiator = new Initiator("initiator"); + router = new Router<4>("router"); + for (int i = 0; i < 4; i++) { + char txt[20]; + sprintf(txt, "memory_%d", i); + memory[i] = new Memory(txt); + } + + // Bind sockets + initiator->socket.bind(router->target_socket); + for (int i = 0; i < 4; i++) + router->initiator_socket[i].bind(memory[i]->socket); + // connect signals + clk_gen->clk_o(clk); + reset_gen->reset_o(reset); + initiator->clk_i(clk); + initiator->reset_i(reset); + + router->clk_i(clk); + router->reset_i(reset); + + for(auto& m: memory){ + m->clk_i(clk); + m->reset_i(reset); + } +} + sc_core::sc_signal clk; + sc_core::sc_signal reset; +}; + +#endif