From fe82238d291e43e3b688ee3ec2922f6424c4ad45 Mon Sep 17 00:00:00 2001 From: Vladimir Kondratiev Date: Mon, 23 Feb 2026 16:54:48 +0200 Subject: [PATCH] platform: generic: mips p8700: access CM registers via match data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Modify the coherence manager register accessors to use the global variable p8700_cm_info instead of the statically declared GLOBAL_CM_BASE array. Also use p8700_cm_info to get the number of coherence managers and their base addresses in mips_p8700_early_init() and mips_p8700_nascent_init(). Clean up the hard-coded values in mips/board.h, access to the coherence manager is now fully based on information provided by platform compatible from the device tree. Signed-off-by: Benoît Monin Signed-off-by: Vladimir Kondratiev Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-9-621d004d1a21@mobileye.com Signed-off-by: Anup Patel --- platform/generic/include/mips/board.h | 15 ------------- platform/generic/include/mips/mips-cm.h | 9 ++++---- platform/generic/mips/p8700.c | 28 +++++++++++++------------ 3 files changed, 19 insertions(+), 33 deletions(-) diff --git a/platform/generic/include/mips/board.h b/platform/generic/include/mips/board.h index 6fe7b8b6..b72d77d6 100644 --- a/platform/generic/include/mips/board.h +++ b/platform/generic/include/mips/board.h @@ -10,21 +10,6 @@ /* Please review all defines to change for your board. */ -/* Use in stw.S, p8700.c, p8700.h, mips-cm.h */ -#define CM_BASE 0x16100000 - -/* Use in mips-cm.h, p8700.c */ -#define CLUSTERS_IN_PLATFORM 1 -#if CLUSTERS_IN_PLATFORM > 1 -/* Define global CM bases for cluster 0, 1, 2, and more. */ -#define GLOBAL_CM_BASE0 0 -#define GLOBAL_CM_BASE1 0 -#define GLOBAL_CM_BASE2 0 -#endif - -/* Use in stw.S */ -#define TIMER_ADDR (CM_BASE + 0x8050) - /* Use in cps-vec.S */ #define DRAM_ADDRESS 0x80000000 #define DRAM_SIZE 0x80000000 diff --git a/platform/generic/include/mips/mips-cm.h b/platform/generic/include/mips/mips-cm.h index 624298f3..b3e056e8 100644 --- a/platform/generic/include/mips/mips-cm.h +++ b/platform/generic/include/mips/mips-cm.h @@ -14,16 +14,14 @@ /* Define 1 to print out CM read and write info */ #define DEBUG_CM 0 -extern long GLOBAL_CM_BASE[]; - - #define CPS_ACCESSOR_R(unit, sz, off, name) \ static inline u##sz read_##unit##_##name(u32 hartid) \ { \ u##sz value; \ int cl = cpu_cluster(hartid); \ int co = cpu_core(hartid); \ - long cmd_reg = GLOBAL_CM_BASE[cl] + (co << CM_BASE_CORE_SHIFT) \ + long cmd_reg = p8700_cm_info->gcr_base[cl] \ + + (co << CM_BASE_CORE_SHIFT) \ + off; \ if (DEBUG_CM) \ sbi_printf("CM_READ%d(0x%lx) ...\n", sz, cmd_reg); \ @@ -42,7 +40,8 @@ static inline void write_##unit##_##name(u32 hartid, u##sz value) \ { \ int cl = cpu_cluster(hartid); \ int co = cpu_core(hartid); \ - long cmd_reg = GLOBAL_CM_BASE[cl] + (co << CM_BASE_CORE_SHIFT) \ + long cmd_reg = p8700_cm_info->gcr_base[cl] \ + + (co << CM_BASE_CORE_SHIFT) \ + off; \ if (DEBUG_CM) \ sbi_printf("CM_WRITE%d(0x%lx, 0x%lx)\n", sz, \ diff --git a/platform/generic/mips/p8700.c b/platform/generic/mips/p8700.c index 75e19416..5129d089 100644 --- a/platform/generic/mips/p8700.c +++ b/platform/generic/mips/p8700.c @@ -23,9 +23,6 @@ extern void mips_warm_boot(void); #define MMIO_BASE 0x00000000 #define MMIO_SIZE 0x80000000 -/* FIXME! Please change GLOBAL_CM_BASE for your platform */ -long GLOBAL_CM_BASE[CLUSTERS_IN_PLATFORM] = {CM_BASE}; - static void mips_p8700_pmp_set(unsigned int n, unsigned long flags, unsigned long prot, unsigned long addr, unsigned long log2len) @@ -49,9 +46,10 @@ static void mips_p8700_pmp_set(unsigned int n, unsigned long flags, static void power_up_other_cluster(u32 hartid) { unsigned int cl = cpu_cluster(hartid); + unsigned long cm_base = p8700_cm_info->gcr_base[cl]; /* remap local cluster address to its global address */ - writeq(GLOBAL_CM_BASE[cl], (void*)GLOBAL_CM_BASE[cl] + GCR_BASE_OFFSET); + writeq(cm_base, (void*)cm_base + GCR_BASE_OFFSET); wmb(); /* Power up CM in cluster */ write_cpc_pwrup_ctl(hartid, 1); @@ -161,13 +159,17 @@ static int mips_p8700_early_init(bool cold_boot) if (!cold_boot) return 0; - sbi_dprintf("Remap Cluster %d CM 0x%lx -> 0x%lx\n", 0, - readq((void*)GLOBAL_CM_BASE[0] + GCR_BASE_OFFSET), - GLOBAL_CM_BASE[0]); - writeq(GLOBAL_CM_BASE[0], (void*)GLOBAL_CM_BASE[0] + GCR_BASE_OFFSET); - wmb(); + { /* cluster 0 - only remap, already up */ + unsigned long cm_base = p8700_cm_info->gcr_base[0]; + + sbi_dprintf("Remap Cluster %d CM 0x%lx -> 0x%lx\n", 0, + readq((void*)cm_base + GCR_BASE_OFFSET), + cm_base); + writeq(cm_base, (void*)cm_base + GCR_BASE_OFFSET); + wmb(); + } /* Power up other clusters in the platform. */ - for (i = 1; i < CLUSTERS_IN_PLATFORM; i++) { + for (i = 1; i < p8700_cm_info->num_cm; i++) { power_up_other_cluster(i << NEW_CLUSTER_SHIFT); } @@ -185,8 +187,8 @@ static int mips_p8700_early_init(bool cold_boot) * 0x10_00000000 0x20_00000000 M:---- S:IRW- PCI64 BARs */ - for (i = 0; i < CLUSTERS_IN_PLATFORM; i++) { - unsigned long cm_base = GLOBAL_CM_BASE[i]; + for (i = 0; i < p8700_cm_info->num_cm; i++) { + unsigned long cm_base = p8700_cm_info->gcr_base[i]; /* CM and MTIMER */ rc = sbi_domain_root_add_memrange(cm_base, SIZE_FOR_CPC_MTIME, @@ -225,7 +227,7 @@ static int mips_p8700_nascent_init(void) { u64 hartid = current_hartid(); int cl = cpu_cluster(hartid); - u64 cm_base = GLOBAL_CM_BASE[cl]; + u64 cm_base = p8700_cm_info->gcr_base[cl]; int i; /* Coherence enable for every core */