From b31a0a24279d46ae4981e1691fe56e245b6d39a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Date: Mon, 19 May 2025 10:39:48 +0200 Subject: [PATCH] lib: sbi: pmu: Add SSE register/unregister() callbacks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As soon as the SSE event is registered, there is no reason not to delegate the interrupt. Split the PMU SSE enable/disable() callbacks by moving MIDELEG setting to register/unregister(). Signed-off-by: Clément Léger Reviewed-by: Atish Patra Reviewed-by: Samuel Holland Link: https://lore.kernel.org/r/20250519083950.739044-2-cleger@rivosinc.com Signed-off-by: Anup Patel --- lib/sbi/sbi_pmu.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c index 6ca4efdb..9b779c5a 100644 --- a/lib/sbi/sbi_pmu.c +++ b/lib/sbi/sbi_pmu.c @@ -1102,24 +1102,18 @@ void sbi_pmu_exit(struct sbi_scratch *scratch) static void pmu_sse_enable(uint32_t event_id) { - struct sbi_pmu_hart_state *phs = pmu_thishart_state_ptr(); unsigned long irq_mask = sbi_pmu_irq_mask(); - phs->sse_enabled = true; - csr_clear(CSR_MIDELEG, irq_mask); csr_clear(CSR_MIP, irq_mask); csr_set(CSR_MIE, irq_mask); } static void pmu_sse_disable(uint32_t event_id) { - struct sbi_pmu_hart_state *phs = pmu_thishart_state_ptr(); unsigned long irq_mask = sbi_pmu_irq_mask(); csr_clear(CSR_MIE, irq_mask); csr_clear(CSR_MIP, irq_mask); - csr_set(CSR_MIDELEG, irq_mask); - phs->sse_enabled = false; } static void pmu_sse_complete(uint32_t event_id) @@ -1127,7 +1121,25 @@ static void pmu_sse_complete(uint32_t event_id) csr_set(CSR_MIE, sbi_pmu_irq_mask()); } +static void pmu_sse_register(uint32_t event_id) +{ + struct sbi_pmu_hart_state *phs = pmu_thishart_state_ptr(); + + phs->sse_enabled = true; + csr_clear(CSR_MIDELEG, sbi_pmu_irq_mask()); +} + +static void pmu_sse_unregister(uint32_t event_id) +{ + struct sbi_pmu_hart_state *phs = pmu_thishart_state_ptr(); + + phs->sse_enabled = false; + csr_set(CSR_MIDELEG, sbi_pmu_irq_mask()); +} + static const struct sbi_sse_cb_ops pmu_sse_cb_ops = { + .register_cb = pmu_sse_register, + .unregister_cb = pmu_sse_unregister, .enable_cb = pmu_sse_enable, .disable_cb = pmu_sse_disable, .complete_cb = pmu_sse_complete,