diff --git a/include/sbi_utils/serial/uart8250.h b/include/sbi_utils/serial/uart8250.h
index d4a8c136..70cd2912 100644
--- a/include/sbi_utils/serial/uart8250.h
+++ b/include/sbi_utils/serial/uart8250.h
@@ -12,7 +12,9 @@
 
 #include <sbi/sbi_types.h>
 
+#define UART_CAP_UUE	BIT(0)	/* Check UUE capability for XScale PXA UARTs */
+
 int uart8250_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
-		  u32 reg_width, u32 reg_offset);
+		  u32 reg_width, u32 reg_offset, u32 caps);
 
 #endif
diff --git a/lib/utils/serial/fdt_serial_uart8250.c b/lib/utils/serial/fdt_serial_uart8250.c
index af5ceac9..3a6650d6 100644
--- a/lib/utils/serial/fdt_serial_uart8250.c
+++ b/lib/utils/serial/fdt_serial_uart8250.c
@@ -14,8 +14,9 @@
 static int serial_uart8250_init(const void *fdt, int nodeoff,
 				const struct fdt_match *match)
 {
-	int rc;
 	struct platform_uart_data uart = { 0 };
+	ulong caps = (ulong)match->data;
+	int rc;
 
 	rc = fdt_parse_uart_node(fdt, nodeoff, &uart);
 	if (rc)
@@ -23,13 +24,15 @@ static int serial_uart8250_init(const void *fdt, int nodeoff,
 
 	return uart8250_init(uart.addr, uart.freq, uart.baud,
 			     uart.reg_shift, uart.reg_io_width,
-			     uart.reg_offset);
+			     uart.reg_offset, caps);
 }
 
 static const struct fdt_match serial_uart8250_match[] = {
 	{ .compatible = "ns16550" },
 	{ .compatible = "ns16550a" },
 	{ .compatible = "snps,dw-apb-uart" },
+	{ .compatible = "intel,xscale-uart",
+	  .data = (void *)UART_CAP_UUE },
 	{ },
 };
 
diff --git a/lib/utils/serial/uart8250.c b/lib/utils/serial/uart8250.c
index 1fe053f8..82fb142a 100644
--- a/lib/utils/serial/uart8250.c
+++ b/lib/utils/serial/uart8250.c
@@ -39,6 +39,12 @@
 #define UART_LSR_DR		0x01	/* Receiver data ready */
 #define UART_LSR_BRK_ERROR_BITS	0x1E	/* BI, FE, PE, OE bits */
 
+/* The XScale PXA UARTs define these bits */
+#define UART_IER_DMAE		0x80	/* DMA Requests Enable */
+#define UART_IER_UUE		0x40	/* UART Unit Enable */
+#define UART_IER_NRZE		0x20	/* NRZ coding Enable */
+#define UART_IER_RTOIE		0x10	/* Receiver Time Out Interrupt Enable */
+
 /* clang-format on */
 
 static volatile char *uart8250_base;
@@ -93,7 +99,7 @@ static struct sbi_console_device uart8250_console = {
 };
 
 int uart8250_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
-		  u32 reg_width, u32 reg_offset)
+		  u32 reg_width, u32 reg_offset, u32 caps)
 {
 	u16 bdiv = 0;
 
@@ -109,7 +115,8 @@ int uart8250_init(unsigned long base, u32 in_freq, u32 baudrate, u32 reg_shift,
 	}
 
 	/* Disable all interrupts */
-	set_reg(UART_IER_OFFSET, 0x00);
+	set_reg(UART_IER_OFFSET, (caps & UART_CAP_UUE) ?
+				 UART_IER_UUE : 0x00);
 	/* Enable DLAB */
 	set_reg(UART_LCR_OFFSET, 0x80);
 
diff --git a/platform/fpga/ariane/platform.c b/platform/fpga/ariane/platform.c
index 0b4455f1..4bc1c5be 100644
--- a/platform/fpga/ariane/platform.c
+++ b/platform/fpga/ariane/platform.c
@@ -23,6 +23,7 @@
 #define ARIANE_UART_REG_SHIFT			2
 #define ARIANE_UART_REG_WIDTH			4
 #define ARIANE_UART_REG_OFFSET			0
+#define ARIANE_UART_CAPS			0
 #define ARIANE_PLIC_ADDR			0xc000000
 #define ARIANE_PLIC_SIZE			(0x200000 + \
 						 (ARIANE_HART_COUNT * 0x1000))
@@ -78,7 +79,8 @@ static int ariane_early_init(bool cold_boot)
 			     ARIANE_UART_BAUDRATE,
 			     ARIANE_UART_REG_SHIFT,
 			     ARIANE_UART_REG_WIDTH,
-			     ARIANE_UART_REG_OFFSET);
+			     ARIANE_UART_REG_OFFSET,
+			     ARIANE_UART_CAPS);
 }
 
 /*
diff --git a/platform/fpga/openpiton/platform.c b/platform/fpga/openpiton/platform.c
index 9f4378a4..d2cf3e32 100644
--- a/platform/fpga/openpiton/platform.c
+++ b/platform/fpga/openpiton/platform.c
@@ -22,6 +22,7 @@
 #define OPENPITON_DEFAULT_UART_REG_SHIFT	0
 #define OPENPITON_DEFAULT_UART_REG_WIDTH	1
 #define OPENPITON_DEFAULT_UART_REG_OFFSET	0
+#define OPENPITON_DEFAULT_UART_CAPS		0
 #define OPENPITON_DEFAULT_PLIC_ADDR		0xfff1100000
 #define OPENPITON_DEFAULT_PLIC_SIZE		(0x200000 + \
 				(OPENPITON_DEFAULT_HART_COUNT * 0x1000))
@@ -111,7 +112,8 @@ static int openpiton_early_init(bool cold_boot)
 	return uart8250_init(uart.addr, uart.freq, uart.baud,
 			     OPENPITON_DEFAULT_UART_REG_SHIFT,
 			     OPENPITON_DEFAULT_UART_REG_WIDTH,
-			     OPENPITON_DEFAULT_UART_REG_OFFSET);
+			     OPENPITON_DEFAULT_UART_REG_OFFSET,
+			     OPENPITON_DEFAULT_UART_CAPS);
 }
 
 /*
diff --git a/platform/template/platform.c b/platform/template/platform.c
index bc351bc9..292889d2 100644
--- a/platform/template/platform.c
+++ b/platform/template/platform.c
@@ -75,7 +75,7 @@ static int platform_early_init(bool cold_boot)
 
 	/* Example if the generic UART8250 driver is used */
 	return uart8250_init(PLATFORM_UART_ADDR, PLATFORM_UART_INPUT_FREQ,
-			     PLATFORM_UART_BAUDRATE, 0, 1, 0);
+			     PLATFORM_UART_BAUDRATE, 0, 1, 0, 0);
 }
 
 /*