# ThreadX Port for the TGFS cores and accompanying Virtual prototypes

This repositiory contains a RISC-V implementation of ThreadX designed to run on the TGFS cores or the RISC-V VP by MINRES (available on [Github](https://github.com/Minres/RISCV-VP/tree/d96cd4a01de1f4bcc77db3eceb57f5c144395847)).

**Note**: SMP support additionally requires a VP variant that allows the number of cores to be configured.

## Building the RTOS

A set of presets is provided, targetting 32 and 64-bit systems.

E.g. building for the RV64IMAC configuration:

```bash
cmake --preset Debug
cmake --build --preset Debug --parallel
```

## Running on the VP

A run command can look like this:

```bash
riscv-vp --isa=rv64imac_m -f build/Debug/thread_demo.elf
```

## Running the Regression Suites

The regression suites live in test/. Both suites register their cases with CTest and require the path to the MINRES `riscv-vp` simulator to be provided through `THREADX_TEST_SIMULATOR`.

The SMP regression suite additionally requires a `riscv-vp` variant that supports a configurable number of cores.

Examples:

```bash
cmake -S test/threadx --preset Debug32 -DTHREADX_TEST_SIMULATOR=/opt/riscv-vp/bin/riscv-vp
cmake --build --preset Debug32 --parallel 
ctest --test-dir ../../build/Debug32/test/threadx --output-on-failure --parallel 4
```

## Demo Applications

The repository currently provides three demo applications:

- `thread_demo`: a basic single-kernel ThreadX demo based on the standard ThreadX sample application
- `smp_demo`: the same basic demo application for running on a ThreadX SMP kernel
- `tcp_demo`: a NetX Duo demo that exercises the TCP/IP stack on top of ThreadX