/* * Copyright (c) 2023 - 2026 MINRES Technologies GmbH * * SPDX-License-Identifier: Apache-2.0 * * Generated at 2026-01-26 15:33:03 UTC * by peakrdl_mnrs version 1.3.1 */ #ifndef _BSP_ETHMAC_H #define _BSP_ETHMAC_H #include typedef struct { volatile uint32_t MAC_CTRL; uint8_t fill0[12]; volatile uint32_t MAC_TX; volatile uint32_t MAC_TX_AVAILABILITY; uint8_t fill1[8]; volatile uint32_t MAC_RX; uint8_t fill2[8]; volatile uint32_t MAC_RX_STATS; volatile uint32_t MAC_INTR; uint8_t fill3[12]; volatile uint32_t MDIO_DATA; volatile uint32_t MDIO_STATUS; volatile uint32_t MDIO_CONFIG; volatile uint32_t MDIO_INTR; uint8_t fill4[16]; volatile uint32_t MDIO_SCLK_CONFIG; volatile uint32_t MDIO_SSGEN_SETUP; volatile uint32_t MDIO_SSGEN_HOLD; volatile uint32_t MDIO_SSGEN_DISABLE; volatile uint32_t MDIO_SSGEN_ACTIVE_HIGH; uint8_t fill5[28]; volatile uint32_t MDIO_DIRECT_WRITE; volatile uint32_t MDIO_DIRECT_READ_WRITE; volatile uint32_t MDIO_DIRECT_READ; }ethmac_t; #define ETHMAC_MAC_CTRL_TX_FLUSH_OFFS 0 #define ETHMAC_MAC_CTRL_TX_FLUSH_MASK 0x1 #define ETHMAC_MAC_CTRL_TX_FLUSH(V) ((V & ETHMAC_MAC_CTRL_TX_FLUSH_MASK) << ETHMAC_MAC_CTRL_TX_FLUSH_OFFS) #define ETHMAC_MAC_CTRL_TX_READY_OFFS 1 #define ETHMAC_MAC_CTRL_TX_READY_MASK 0x1 #define ETHMAC_MAC_CTRL_TX_READY(V) ((V & ETHMAC_MAC_CTRL_TX_READY_MASK) << ETHMAC_MAC_CTRL_TX_READY_OFFS) #define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_OFFS 2 #define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_MASK 0x1 #define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE(V) ((V & ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_MASK) << ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_OFFS) #define ETHMAC_MAC_CTRL_RX_FLUSH_OFFS 4 #define ETHMAC_MAC_CTRL_RX_FLUSH_MASK 0x1 #define ETHMAC_MAC_CTRL_RX_FLUSH(V) ((V & ETHMAC_MAC_CTRL_RX_FLUSH_MASK) << ETHMAC_MAC_CTRL_RX_FLUSH_OFFS) #define ETHMAC_MAC_CTRL_RX_PENDING_OFFS 5 #define ETHMAC_MAC_CTRL_RX_PENDING_MASK 0x1 #define ETHMAC_MAC_CTRL_RX_PENDING(V) ((V & ETHMAC_MAC_CTRL_RX_PENDING_MASK) << ETHMAC_MAC_CTRL_RX_PENDING_OFFS) #define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_OFFS 6 #define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_MASK 0x1 #define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE(V) ((V & ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_MASK) << ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_OFFS) #define ETHMAC_MAC_TX_OFFS 0 #define ETHMAC_MAC_TX_MASK 0xffffffff #define ETHMAC_MAC_TX(V) ((V & ETHMAC_MAC_TX_MASK) << ETHMAC_MAC_TX_OFFS) #define ETHMAC_MAC_TX_AVAILABILITY_OFFS 0 #define ETHMAC_MAC_TX_AVAILABILITY_MASK 0x7ff #define ETHMAC_MAC_TX_AVAILABILITY(V) ((V & ETHMAC_MAC_TX_AVAILABILITY_MASK) << ETHMAC_MAC_TX_AVAILABILITY_OFFS) #define ETHMAC_MAC_RX_OFFS 0 #define ETHMAC_MAC_RX_MASK 0xffffffff #define ETHMAC_MAC_RX(V) ((V & ETHMAC_MAC_RX_MASK) << ETHMAC_MAC_RX_OFFS) #define ETHMAC_MAC_RX_STATS_RX_ERRORS_OFFS 0 #define ETHMAC_MAC_RX_STATS_RX_ERRORS_MASK 0xff #define ETHMAC_MAC_RX_STATS_RX_ERRORS(V) ((V & ETHMAC_MAC_RX_STATS_RX_ERRORS_MASK) << ETHMAC_MAC_RX_STATS_RX_ERRORS_OFFS) #define ETHMAC_MAC_RX_STATS_RX_DROPS_OFFS 8 #define ETHMAC_MAC_RX_STATS_RX_DROPS_MASK 0xff #define ETHMAC_MAC_RX_STATS_RX_DROPS(V) ((V & ETHMAC_MAC_RX_STATS_RX_DROPS_MASK) << ETHMAC_MAC_RX_STATS_RX_DROPS_OFFS) #define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_OFFS 0 #define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_MASK 0x1 #define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE(V) ((V & ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_MASK) << ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_OFFS) #define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_OFFS 1 #define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_MASK 0x1 #define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE(V) ((V & ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_MASK) << ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_OFFS) #define ETHMAC_MDIO_DATA_DATA_OFFS 0 #define ETHMAC_MDIO_DATA_DATA_MASK 0xff #define ETHMAC_MDIO_DATA_DATA(V) ((V & ETHMAC_MDIO_DATA_DATA_MASK) << ETHMAC_MDIO_DATA_DATA_OFFS) #define ETHMAC_MDIO_DATA_WRITE_OFFS 8 #define ETHMAC_MDIO_DATA_WRITE_MASK 0x1 #define ETHMAC_MDIO_DATA_WRITE(V) ((V & ETHMAC_MDIO_DATA_WRITE_MASK) << ETHMAC_MDIO_DATA_WRITE_OFFS) #define ETHMAC_MDIO_DATA_READ_OFFS 9 #define ETHMAC_MDIO_DATA_READ_MASK 0x1 #define ETHMAC_MDIO_DATA_READ(V) ((V & ETHMAC_MDIO_DATA_READ_MASK) << ETHMAC_MDIO_DATA_READ_OFFS) #define ETHMAC_MDIO_DATA_SSGEN_OFFS 11 #define ETHMAC_MDIO_DATA_SSGEN_MASK 0x1 #define ETHMAC_MDIO_DATA_SSGEN(V) ((V & ETHMAC_MDIO_DATA_SSGEN_MASK) << ETHMAC_MDIO_DATA_SSGEN_OFFS) #define ETHMAC_MDIO_DATA_RX_DATA_INVALID_OFFS 31 #define ETHMAC_MDIO_DATA_RX_DATA_INVALID_MASK 0x1 #define ETHMAC_MDIO_DATA_RX_DATA_INVALID(V) ((V & ETHMAC_MDIO_DATA_RX_DATA_INVALID_MASK) << ETHMAC_MDIO_DATA_RX_DATA_INVALID_OFFS) #define ETHMAC_MDIO_STATUS_TX_FREE_OFFS 0 #define ETHMAC_MDIO_STATUS_TX_FREE_MASK 0x3f #define ETHMAC_MDIO_STATUS_TX_FREE(V) ((V & ETHMAC_MDIO_STATUS_TX_FREE_MASK) << ETHMAC_MDIO_STATUS_TX_FREE_OFFS) #define ETHMAC_MDIO_STATUS_RX_AVAIL_OFFS 16 #define ETHMAC_MDIO_STATUS_RX_AVAIL_MASK 0x3f #define ETHMAC_MDIO_STATUS_RX_AVAIL(V) ((V & ETHMAC_MDIO_STATUS_RX_AVAIL_MASK) << ETHMAC_MDIO_STATUS_RX_AVAIL_OFFS) #define ETHMAC_MDIO_CONFIG_CPOL_OFFS 0 #define ETHMAC_MDIO_CONFIG_CPOL_MASK 0x1 #define ETHMAC_MDIO_CONFIG_CPOL(V) ((V & ETHMAC_MDIO_CONFIG_CPOL_MASK) << ETHMAC_MDIO_CONFIG_CPOL_OFFS) #define ETHMAC_MDIO_CONFIG_CPHA_OFFS 1 #define ETHMAC_MDIO_CONFIG_CPHA_MASK 0x1 #define ETHMAC_MDIO_CONFIG_CPHA(V) ((V & ETHMAC_MDIO_CONFIG_CPHA_MASK) << ETHMAC_MDIO_CONFIG_CPHA_OFFS) #define ETHMAC_MDIO_CONFIG_MODE_OFFS 4 #define ETHMAC_MDIO_CONFIG_MODE_MASK 0x1 #define ETHMAC_MDIO_CONFIG_MODE(V) ((V & ETHMAC_MDIO_CONFIG_MODE_MASK) << ETHMAC_MDIO_CONFIG_MODE_OFFS) #define ETHMAC_MDIO_INTR_TX_IE_OFFS 0 #define ETHMAC_MDIO_INTR_TX_IE_MASK 0x1 #define ETHMAC_MDIO_INTR_TX_IE(V) ((V & ETHMAC_MDIO_INTR_TX_IE_MASK) << ETHMAC_MDIO_INTR_TX_IE_OFFS) #define ETHMAC_MDIO_INTR_RX_IE_OFFS 1 #define ETHMAC_MDIO_INTR_RX_IE_MASK 0x1 #define ETHMAC_MDIO_INTR_RX_IE(V) ((V & ETHMAC_MDIO_INTR_RX_IE_MASK) << ETHMAC_MDIO_INTR_RX_IE_OFFS) #define ETHMAC_MDIO_INTR_TX_IP_OFFS 8 #define ETHMAC_MDIO_INTR_TX_IP_MASK 0x1 #define ETHMAC_MDIO_INTR_TX_IP(V) ((V & ETHMAC_MDIO_INTR_TX_IP_MASK) << ETHMAC_MDIO_INTR_TX_IP_OFFS) #define ETHMAC_MDIO_INTR_RX_IP_OFFS 9 #define ETHMAC_MDIO_INTR_RX_IP_MASK 0x1 #define ETHMAC_MDIO_INTR_RX_IP(V) ((V & ETHMAC_MDIO_INTR_RX_IP_MASK) << ETHMAC_MDIO_INTR_RX_IP_OFFS) #define ETHMAC_MDIO_INTR_TX_ACTIVE_OFFS 16 #define ETHMAC_MDIO_INTR_TX_ACTIVE_MASK 0x1 #define ETHMAC_MDIO_INTR_TX_ACTIVE(V) ((V & ETHMAC_MDIO_INTR_TX_ACTIVE_MASK) << ETHMAC_MDIO_INTR_TX_ACTIVE_OFFS) #define ETHMAC_MDIO_SCLK_CONFIG_OFFS 0 #define ETHMAC_MDIO_SCLK_CONFIG_MASK 0xfff #define ETHMAC_MDIO_SCLK_CONFIG(V) ((V & ETHMAC_MDIO_SCLK_CONFIG_MASK) << ETHMAC_MDIO_SCLK_CONFIG_OFFS) #define ETHMAC_MDIO_SSGEN_SETUP_OFFS 0 #define ETHMAC_MDIO_SSGEN_SETUP_MASK 0xfff #define ETHMAC_MDIO_SSGEN_SETUP(V) ((V & ETHMAC_MDIO_SSGEN_SETUP_MASK) << ETHMAC_MDIO_SSGEN_SETUP_OFFS) #define ETHMAC_MDIO_SSGEN_HOLD_OFFS 0 #define ETHMAC_MDIO_SSGEN_HOLD_MASK 0xfff #define ETHMAC_MDIO_SSGEN_HOLD(V) ((V & ETHMAC_MDIO_SSGEN_HOLD_MASK) << ETHMAC_MDIO_SSGEN_HOLD_OFFS) #define ETHMAC_MDIO_SSGEN_DISABLE_OFFS 0 #define ETHMAC_MDIO_SSGEN_DISABLE_MASK 0xfff #define ETHMAC_MDIO_SSGEN_DISABLE(V) ((V & ETHMAC_MDIO_SSGEN_DISABLE_MASK) << ETHMAC_MDIO_SSGEN_DISABLE_OFFS) #define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_OFFS 0 #define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_MASK 0x1 #define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH(V) ((V & ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_MASK) << ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_OFFS) #define ETHMAC_MDIO_DIRECT_WRITE_OFFS 0 #define ETHMAC_MDIO_DIRECT_WRITE_MASK 0xff #define ETHMAC_MDIO_DIRECT_WRITE(V) ((V & ETHMAC_MDIO_DIRECT_WRITE_MASK) << ETHMAC_MDIO_DIRECT_WRITE_OFFS) #define ETHMAC_MDIO_DIRECT_READ_WRITE_OFFS 0 #define ETHMAC_MDIO_DIRECT_READ_WRITE_MASK 0xff #define ETHMAC_MDIO_DIRECT_READ_WRITE(V) ((V & ETHMAC_MDIO_DIRECT_READ_WRITE_MASK) << ETHMAC_MDIO_DIRECT_READ_WRITE_OFFS) #define ETHMAC_MDIO_DIRECT_READ_OFFS 0 #define ETHMAC_MDIO_DIRECT_READ_MASK 0xff #define ETHMAC_MDIO_DIRECT_READ(V) ((V & ETHMAC_MDIO_DIRECT_READ_MASK) << ETHMAC_MDIO_DIRECT_READ_OFFS) //ETHMAC_MAC_CTRL static inline uint32_t get_ethmac_mac_ctrl(volatile ethmac_t* reg){ return reg->MAC_CTRL; } static inline void set_ethmac_mac_ctrl(volatile ethmac_t* reg, uint32_t value){ reg->MAC_CTRL = value; } static inline uint32_t get_ethmac_mac_ctrl_tx_flush(volatile ethmac_t* reg){ return (reg->MAC_CTRL >> 0) & 0x1; } static inline void set_ethmac_mac_ctrl_tx_flush(volatile ethmac_t* reg, uint8_t value){ reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 0)) | (value << 0); } static inline uint32_t get_ethmac_mac_ctrl_tx_ready(volatile ethmac_t* reg){ return (reg->MAC_CTRL >> 1) & 0x1; } static inline uint32_t get_ethmac_mac_ctrl_tx_aligner_enable(volatile ethmac_t* reg){ return (reg->MAC_CTRL >> 2) & 0x1; } static inline void set_ethmac_mac_ctrl_tx_aligner_enable(volatile ethmac_t* reg, uint8_t value){ reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 2)) | (value << 2); } static inline uint32_t get_ethmac_mac_ctrl_rx_flush(volatile ethmac_t* reg){ return (reg->MAC_CTRL >> 4) & 0x1; } static inline void set_ethmac_mac_ctrl_rx_flush(volatile ethmac_t* reg, uint8_t value){ reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 4)) | (value << 4); } static inline uint32_t get_ethmac_mac_ctrl_rx_pending(volatile ethmac_t* reg){ return (reg->MAC_CTRL >> 5) & 0x1; } static inline uint32_t get_ethmac_mac_ctrl_rx_aligner_enable(volatile ethmac_t* reg){ return (reg->MAC_CTRL >> 6) & 0x1; } static inline void set_ethmac_mac_ctrl_rx_aligner_enable(volatile ethmac_t* reg, uint8_t value){ reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 6)) | (value << 6); } //ETHMAC_MAC_TX static inline uint32_t get_ethmac_mac_tx(volatile ethmac_t* reg){ return (reg->MAC_TX >> 0) & 0xffffffff; } static inline void set_ethmac_mac_tx(volatile ethmac_t* reg, uint32_t value){ reg->MAC_TX = (reg->MAC_TX & ~(0xffffffffU << 0)) | (value << 0); } //ETHMAC_MAC_TX_AVAILABILITY static inline uint32_t get_ethmac_mac_tx_availability(volatile ethmac_t* reg){ return reg->MAC_TX_AVAILABILITY; } static inline uint32_t get_ethmac_mac_tx_availability_words_avail(volatile ethmac_t* reg){ return (reg->MAC_TX_AVAILABILITY >> 0) & 0x7ff; } //ETHMAC_MAC_RX static inline uint32_t get_ethmac_mac_rx(volatile ethmac_t* reg){ return (reg->MAC_RX >> 0) & 0xffffffff; } //ETHMAC_MAC_RX_STATS static inline uint32_t get_ethmac_mac_rx_stats(volatile ethmac_t* reg){ return reg->MAC_RX_STATS; } static inline uint32_t get_ethmac_mac_rx_stats_rx_errors(volatile ethmac_t* reg){ return (reg->MAC_RX_STATS >> 0) & 0xff; } static inline uint32_t get_ethmac_mac_rx_stats_rx_drops(volatile ethmac_t* reg){ return (reg->MAC_RX_STATS >> 8) & 0xff; } //ETHMAC_MAC_INTR static inline uint32_t get_ethmac_mac_intr(volatile ethmac_t* reg){ return reg->MAC_INTR; } static inline void set_ethmac_mac_intr(volatile ethmac_t* reg, uint32_t value){ reg->MAC_INTR = value; } static inline uint32_t get_ethmac_mac_intr_tx_free_intr_enable(volatile ethmac_t* reg){ return (reg->MAC_INTR >> 0) & 0x1; } static inline void set_ethmac_mac_intr_tx_free_intr_enable(volatile ethmac_t* reg, uint8_t value){ reg->MAC_INTR = (reg->MAC_INTR & ~(0x1U << 0)) | (value << 0); } static inline uint32_t get_ethmac_mac_intr_rx_data_avail_intr_enable(volatile ethmac_t* reg){ return (reg->MAC_INTR >> 1) & 0x1; } static inline void set_ethmac_mac_intr_rx_data_avail_intr_enable(volatile ethmac_t* reg, uint8_t value){ reg->MAC_INTR = (reg->MAC_INTR & ~(0x1U << 1)) | (value << 1); } //ETHMAC_MDIO_DATA static inline uint32_t get_ethmac_mdio_data(volatile ethmac_t* reg){ return reg->MDIO_DATA; } static inline void set_ethmac_mdio_data(volatile ethmac_t* reg, uint32_t value){ reg->MDIO_DATA = value; } static inline uint32_t get_ethmac_mdio_data_data(volatile ethmac_t* reg){ return (reg->MDIO_DATA >> 0) & 0xff; } static inline void set_ethmac_mdio_data_data(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_DATA = (reg->MDIO_DATA & ~(0xffU << 0)) | (value << 0); } static inline uint32_t get_ethmac_mdio_data_write(volatile ethmac_t* reg){ return (reg->MDIO_DATA >> 8) & 0x1; } static inline void set_ethmac_mdio_data_write(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 8)) | (value << 8); } static inline uint32_t get_ethmac_mdio_data_read(volatile ethmac_t* reg){ return (reg->MDIO_DATA >> 9) & 0x1; } static inline void set_ethmac_mdio_data_read(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 9)) | (value << 9); } static inline uint32_t get_ethmac_mdio_data_ssgen(volatile ethmac_t* reg){ return (reg->MDIO_DATA >> 11) & 0x1; } static inline void set_ethmac_mdio_data_ssgen(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 11)) | (value << 11); } static inline uint32_t get_ethmac_mdio_data_rx_data_invalid(volatile ethmac_t* reg){ return (reg->MDIO_DATA >> 31) & 0x1; } //ETHMAC_MDIO_STATUS static inline uint32_t get_ethmac_mdio_status(volatile ethmac_t* reg){ return reg->MDIO_STATUS; } static inline uint32_t get_ethmac_mdio_status_tx_free(volatile ethmac_t* reg){ return (reg->MDIO_STATUS >> 0) & 0x3f; } static inline uint32_t get_ethmac_mdio_status_rx_avail(volatile ethmac_t* reg){ return (reg->MDIO_STATUS >> 16) & 0x3f; } //ETHMAC_MDIO_CONFIG static inline uint32_t get_ethmac_mdio_config(volatile ethmac_t* reg){ return reg->MDIO_CONFIG; } static inline void set_ethmac_mdio_config(volatile ethmac_t* reg, uint32_t value){ reg->MDIO_CONFIG = value; } static inline uint32_t get_ethmac_mdio_config_cpol(volatile ethmac_t* reg){ return (reg->MDIO_CONFIG >> 0) & 0x1; } static inline void set_ethmac_mdio_config_cpol(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 0)) | (value << 0); } static inline uint32_t get_ethmac_mdio_config_cpha(volatile ethmac_t* reg){ return (reg->MDIO_CONFIG >> 1) & 0x1; } static inline void set_ethmac_mdio_config_cpha(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 1)) | (value << 1); } static inline uint32_t get_ethmac_mdio_config_mode(volatile ethmac_t* reg){ return (reg->MDIO_CONFIG >> 4) & 0x1; } static inline void set_ethmac_mdio_config_mode(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 4)) | (value << 4); } //ETHMAC_MDIO_INTR static inline uint32_t get_ethmac_mdio_intr(volatile ethmac_t* reg){ return reg->MDIO_INTR; } static inline void set_ethmac_mdio_intr(volatile ethmac_t* reg, uint32_t value){ reg->MDIO_INTR = value; } static inline uint32_t get_ethmac_mdio_intr_tx_ie(volatile ethmac_t* reg){ return (reg->MDIO_INTR >> 0) & 0x1; } static inline void set_ethmac_mdio_intr_tx_ie(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 0)) | (value << 0); } static inline uint32_t get_ethmac_mdio_intr_rx_ie(volatile ethmac_t* reg){ return (reg->MDIO_INTR >> 1) & 0x1; } static inline void set_ethmac_mdio_intr_rx_ie(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 1)) | (value << 1); } static inline uint32_t get_ethmac_mdio_intr_tx_ip(volatile ethmac_t* reg){ return (reg->MDIO_INTR >> 8) & 0x1; } static inline void set_ethmac_mdio_intr_tx_ip(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 8)) | (value << 8); } static inline uint32_t get_ethmac_mdio_intr_rx_ip(volatile ethmac_t* reg){ return (reg->MDIO_INTR >> 9) & 0x1; } static inline void set_ethmac_mdio_intr_rx_ip(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 9)) | (value << 9); } static inline uint32_t get_ethmac_mdio_intr_tx_active(volatile ethmac_t* reg){ return (reg->MDIO_INTR >> 16) & 0x1; } //ETHMAC_MDIO_SCLK_CONFIG static inline uint32_t get_ethmac_mdio_sclk_config(volatile ethmac_t* reg){ return reg->MDIO_SCLK_CONFIG; } static inline void set_ethmac_mdio_sclk_config(volatile ethmac_t* reg, uint32_t value){ reg->MDIO_SCLK_CONFIG = value; } static inline uint32_t get_ethmac_mdio_sclk_config_clk_divider(volatile ethmac_t* reg){ return (reg->MDIO_SCLK_CONFIG >> 0) & 0xfff; } static inline void set_ethmac_mdio_sclk_config_clk_divider(volatile ethmac_t* reg, uint16_t value){ reg->MDIO_SCLK_CONFIG = (reg->MDIO_SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0); } //ETHMAC_MDIO_SSGEN_SETUP static inline uint32_t get_ethmac_mdio_ssgen_setup(volatile ethmac_t* reg){ return reg->MDIO_SSGEN_SETUP; } static inline void set_ethmac_mdio_ssgen_setup(volatile ethmac_t* reg, uint32_t value){ reg->MDIO_SSGEN_SETUP = value; } static inline uint32_t get_ethmac_mdio_ssgen_setup_setup_cycles(volatile ethmac_t* reg){ return (reg->MDIO_SSGEN_SETUP >> 0) & 0xfff; } static inline void set_ethmac_mdio_ssgen_setup_setup_cycles(volatile ethmac_t* reg, uint16_t value){ reg->MDIO_SSGEN_SETUP = (reg->MDIO_SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0); } //ETHMAC_MDIO_SSGEN_HOLD static inline uint32_t get_ethmac_mdio_ssgen_hold(volatile ethmac_t* reg){ return reg->MDIO_SSGEN_HOLD; } static inline void set_ethmac_mdio_ssgen_hold(volatile ethmac_t* reg, uint32_t value){ reg->MDIO_SSGEN_HOLD = value; } static inline uint32_t get_ethmac_mdio_ssgen_hold_hold_cycles(volatile ethmac_t* reg){ return (reg->MDIO_SSGEN_HOLD >> 0) & 0xfff; } static inline void set_ethmac_mdio_ssgen_hold_hold_cycles(volatile ethmac_t* reg, uint16_t value){ reg->MDIO_SSGEN_HOLD = (reg->MDIO_SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0); } //ETHMAC_MDIO_SSGEN_DISABLE static inline uint32_t get_ethmac_mdio_ssgen_disable(volatile ethmac_t* reg){ return reg->MDIO_SSGEN_DISABLE; } static inline void set_ethmac_mdio_ssgen_disable(volatile ethmac_t* reg, uint32_t value){ reg->MDIO_SSGEN_DISABLE = value; } static inline uint32_t get_ethmac_mdio_ssgen_disable_disable_cycles(volatile ethmac_t* reg){ return (reg->MDIO_SSGEN_DISABLE >> 0) & 0xfff; } static inline void set_ethmac_mdio_ssgen_disable_disable_cycles(volatile ethmac_t* reg, uint16_t value){ reg->MDIO_SSGEN_DISABLE = (reg->MDIO_SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0); } //ETHMAC_MDIO_SSGEN_ACTIVE_HIGH static inline uint32_t get_ethmac_mdio_ssgen_active_high(volatile ethmac_t* reg){ return reg->MDIO_SSGEN_ACTIVE_HIGH; } static inline void set_ethmac_mdio_ssgen_active_high(volatile ethmac_t* reg, uint32_t value){ reg->MDIO_SSGEN_ACTIVE_HIGH = value; } static inline uint32_t get_ethmac_mdio_ssgen_active_high_spi_cs_active_high(volatile ethmac_t* reg){ return (reg->MDIO_SSGEN_ACTIVE_HIGH >> 0) & 0x1; } static inline void set_ethmac_mdio_ssgen_active_high_spi_cs_active_high(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_SSGEN_ACTIVE_HIGH = (reg->MDIO_SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0); } //ETHMAC_MDIO_DIRECT_WRITE static inline void set_ethmac_mdio_direct_write(volatile ethmac_t* reg, uint32_t value){ reg->MDIO_DIRECT_WRITE = value; } static inline void set_ethmac_mdio_direct_write_data(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_DIRECT_WRITE = (reg->MDIO_DIRECT_WRITE & ~(0xffU << 0)) | (value << 0); } //ETHMAC_MDIO_DIRECT_READ_WRITE static inline void set_ethmac_mdio_direct_read_write(volatile ethmac_t* reg, uint32_t value){ reg->MDIO_DIRECT_READ_WRITE = value; } static inline void set_ethmac_mdio_direct_read_write_data(volatile ethmac_t* reg, uint8_t value){ reg->MDIO_DIRECT_READ_WRITE = (reg->MDIO_DIRECT_READ_WRITE & ~(0xffU << 0)) | (value << 0); } //ETHMAC_MDIO_DIRECT_READ static inline uint32_t get_ethmac_mdio_direct_read(volatile ethmac_t* reg){ return reg->MDIO_DIRECT_READ; } static inline uint32_t get_ethmac_mdio_direct_read_data(volatile ethmac_t* reg){ return (reg->MDIO_DIRECT_READ >> 0) & 0xff; } #endif /* _BSP_ETHMAC_H */