/* RISC-V machine interrupts. SPDX-License-Identifier: Unlicense https://five-embeddev.com/ */ #ifndef RISCV_TRAPS_H #define RISCV_TRAPS_H enum { RISCV_INT_MSI = 3, RISCV_INT_MTI = 7, RISCV_INT_MEI = 11, RISCV_INT_SSI = 1, RISCV_INT_STI = 5, RISCV_INT_SEI = 9, RISCV_INT_USI = 0, RISCV_INT_UTI = 4, RISCV_INT_UEI = 8, }; enum { RISCV_INT_POS_MSI = 3, RISCV_INT_POS_MTI = 7, RISCV_INT_POS_MEI = 11, RISCV_INT_POS_SSI = 1, RISCV_INT_POS_STI = 5, RISCV_INT_POS_SEI = 9, RISCV_INT_POS_USI = 0, RISCV_INT_POS_UTI = 4, RISCV_INT_POS_UEI = 8, }; enum { RISCV_INT_MASK_MSI = (1UL<