From 1da9671197336d3556e9d21a4f4a36caa030922d Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Thu, 12 Mar 2026 15:57:02 +0100 Subject: [PATCH] adds trap_entry to smp lib --- .../threadx_smp/src/tx_initialize_low_level.S | 81 ++++++++++++++++++- 1 file changed, 80 insertions(+), 1 deletion(-) diff --git a/port/threadx_smp/src/tx_initialize_low_level.S b/port/threadx_smp/src/tx_initialize_low_level.S index 0602ea9..48ed119 100644 --- a/port/threadx_smp/src/tx_initialize_low_level.S +++ b/port/threadx_smp/src/tx_initialize_low_level.S @@ -10,6 +10,85 @@ #include "csr.h" #include "tx_port.h" + + .section .text + .align 4 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* trap_entry RISC-V64/GNU */ +/* 6.2.1 */ +/* AUTHOR */ +/* */ +/* Jer6y , luojun@oerv.isrc.iscas.ac.cn */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for riscv processor trap handle */ +/* It will do the contex save and call c trap_handler and do contex */ +/* load */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* trap_handler */ +/* */ +/* CALLED BY */ +/* */ +/* hardware exception */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 10-25-2024 Jerry Luo */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + .global trap_entry + .extern _tx_thread_context_restore + trap_entry: +#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double) + addi sp, sp, -65*REGBYTES // Allocate space for all registers - with floating point enabled +#else + addi sp, sp, -32*REGBYTES // Allocate space for all registers - without floating point enabled +#endif + + STORE x1, 28*REGBYTES(sp) // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv]) + + call _tx_thread_context_save + + csrr a0, mcause + csrr a1, mepc + csrr a2, mtval + addi sp, sp, -8 + STORE ra, 0(sp) + call trap_handler + LOAD ra, 0(sp) + addi sp, sp, 8 + call _tx_thread_context_restore + // it will nerver return +.weak trap_handler +trap_handler: +1: + j 1b .section .text /**************************************************************************/ /* */ @@ -81,4 +160,4 @@ _tx_initialize_low_level: addi sp, sp, 8 la t0, trap_entry csrw mtvec, t0 - ret \ No newline at end of file + ret