225 lines
7.8 KiB
C
225 lines
7.8 KiB
C
/*
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* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-05-30 18:25:57 UTC
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* by peakrdl_mnrs version 1.2.5
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*/
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#ifndef _BSP_I2S_H
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#define _BSP_I2S_H
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#include <stdint.h>
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typedef struct __attribute((__packed__)) {
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volatile uint32_t LEFT_CH;
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volatile uint32_t RIGHT_CH;
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volatile uint32_t CONTROL;
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volatile uint32_t STATUS;
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volatile uint32_t I2S_CLOCK_CTRL;
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volatile uint32_t PDM_CLOCK_CTRL;
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volatile uint32_t IE;
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volatile uint32_t IP;
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}i2s_t;
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#define I2S_LEFT_CH_OFFS 0
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#define I2S_LEFT_CH_MASK 0xffffffff
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#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS)
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#define I2S_RIGHT_CH_OFFS 0
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#define I2S_RIGHT_CH_MASK 0xffffffff
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#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS)
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#define I2S_CONTROL_MODE_OFFS 0
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#define I2S_CONTROL_MODE_MASK 0x3
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#define I2S_CONTROL_MODE(V) ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS)
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#define I2S_CONTROL_DISABLE_LEFT_OFFS 2
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#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1
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#define I2S_CONTROL_DISABLE_LEFT(V) ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS)
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#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3
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#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
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#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)
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#define I2S_CONTROL_ACTIVE_CLOCK_OFFS 4
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#define I2S_CONTROL_ACTIVE_CLOCK_MASK 0x1
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#define I2S_CONTROL_ACTIVE_CLOCK(V) ((V & I2S_CONTROL_ACTIVE_CLOCK_MASK) << I2S_CONTROL_ACTIVE_CLOCK_OFFS)
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#define I2S_CONTROL_PDM_SCALE_OFFS 5
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#define I2S_CONTROL_PDM_SCALE_MASK 0x7
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#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)
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#define I2S_STATUS_ENABLED_OFFS 0
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#define I2S_STATUS_ENABLED_MASK 0x1
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#define I2S_STATUS_ENABLED(V) ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS)
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#define I2S_STATUS_ACTIVE_OFFS 1
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#define I2S_STATUS_ACTIVE_MASK 0x1
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#define I2S_STATUS_ACTIVE(V) ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS)
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#define I2S_STATUS_LEFT_AVAIL_OFFS 2
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#define I2S_STATUS_LEFT_AVAIL_MASK 0x1
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#define I2S_STATUS_LEFT_AVAIL(V) ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS)
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#define I2S_STATUS_RIGHT_AVAIL_OFFS 3
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#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
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#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
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#define I2S_STATUS_BOTH_AVAIL_OFFS 4
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#define I2S_STATUS_BOTH_AVAIL_MASK 0x1
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#define I2S_STATUS_BOTH_AVAIL(V) ((V & I2S_STATUS_BOTH_AVAIL_MASK) << I2S_STATUS_BOTH_AVAIL_OFFS)
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#define I2S_I2S_CLOCK_CTRL_OFFS 0
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#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
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#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
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#define I2S_PDM_CLOCK_CTRL_OFFS 0
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#define I2S_PDM_CLOCK_CTRL_MASK 0x3ff
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#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
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#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
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#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
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#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
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#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1
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#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1
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#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS)
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#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0
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#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1
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#define I2S_IP_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS)
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#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1
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#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
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#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
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//I2S_LEFT_CH
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inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){
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return (reg->LEFT_CH >> 0) & 0xffffffff;
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}
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inline void set_i2s_left_ch(volatile i2s_t* reg, uint32_t value){
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reg->LEFT_CH = (reg->LEFT_CH & ~(0xffffffffU << 0)) | (value << 0);
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}
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//I2S_RIGHT_CH
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inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){
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return (reg->RIGHT_CH >> 0) & 0xffffffff;
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}
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inline void set_i2s_right_ch(volatile i2s_t* reg, uint32_t value){
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reg->RIGHT_CH = (reg->RIGHT_CH & ~(0xffffffffU << 0)) | (value << 0);
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}
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//I2S_CONTROL
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inline uint32_t get_i2s_control(volatile i2s_t* reg){
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return reg->CONTROL;
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}
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inline void set_i2s_control(volatile i2s_t* reg, uint32_t value){
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reg->CONTROL = value;
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}
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inline uint32_t get_i2s_control_mode(volatile i2s_t* reg){
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return (reg->CONTROL >> 0) & 0x3;
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}
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inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value){
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reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
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}
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inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg){
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return (reg->CONTROL >> 2) & 0x1;
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}
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inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value){
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reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
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}
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inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){
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return (reg->CONTROL >> 3) & 0x1;
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}
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inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){
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reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
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}
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inline uint32_t get_i2s_control_active_clock(volatile i2s_t* reg){
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return (reg->CONTROL >> 4) & 0x1;
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}
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inline void set_i2s_control_active_clock(volatile i2s_t* reg, uint8_t value){
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reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
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}
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inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){
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return (reg->CONTROL >> 5) & 0x7;
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}
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inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
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reg->CONTROL = (reg->CONTROL & ~(0x7U << 5)) | (value << 5);
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}
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//I2S_STATUS
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inline uint32_t get_i2s_status(volatile i2s_t* reg){
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return reg->STATUS;
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}
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inline void set_i2s_status(volatile i2s_t* reg, uint32_t value){
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reg->STATUS = value;
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}
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inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
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return (reg->STATUS >> 0) & 0x1;
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}
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inline uint32_t get_i2s_status_active(volatile i2s_t* reg){
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return (reg->STATUS >> 1) & 0x1;
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}
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inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
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return (reg->STATUS >> 2) & 0x1;
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}
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inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
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return (reg->STATUS >> 3) & 0x1;
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}
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inline uint32_t get_i2s_status_both_avail(volatile i2s_t* reg){
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return (reg->STATUS >> 4) & 0x1;
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}
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//I2S_I2S_CLOCK_CTRL
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inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
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return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
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}
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inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){
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reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
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}
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//I2S_PDM_CLOCK_CTRL
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inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){
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return (reg->PDM_CLOCK_CTRL >> 0) & 0x3ff;
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}
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inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint16_t value){
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reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0x3ffU << 0)) | (value << 0);
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}
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//I2S_IE
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inline uint32_t get_i2s_ie(volatile i2s_t* reg){
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return reg->IE;
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}
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inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value){
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reg->IE = value;
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}
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inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg){
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return (reg->IE >> 0) & 0x1;
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}
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inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value){
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reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
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}
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inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg){
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return (reg->IE >> 1) & 0x1;
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}
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inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value){
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reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
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}
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//I2S_IP
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inline uint32_t get_i2s_ip(volatile i2s_t* reg){
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return reg->IP;
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}
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inline void set_i2s_ip(volatile i2s_t* reg, uint32_t value){
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reg->IP = value;
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}
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inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){
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return (reg->IP >> 0) & 0x1;
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}
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inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg){
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return (reg->IP >> 1) & 0x1;
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}
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#endif /* _BSP_I2S_H */ |