#ifndef _BSP_QSPI_H
#define _BSP_QSPI_H

#include <stdint.h>

#define __IO volatile

typedef struct {
    __IO uint32_t data;             // 0x0/0: data, 8bits, 8:write, 9:read, 11:data/ctrl, 31:rxdata valid
    __IO uint32_t status;           // 0x4/0: txavail, 16: rxused
    __IO uint32_t config;           // 0x8/0:1 cpol/cpha, 4: transfer mode (0-FullDuplex)
    __IO uint32_t intr;             // 0xc/0: txien, 1: rxien, 8: txip, 9: rxip, 16: valid?
    __IO uint32_t __fill0[4];
    __IO uint32_t clk_divider;      // 0x20/0: sclkToogle
    // ssGen config
    __IO uint32_t ss_setup;         // 0x24/0: setup
    __IO uint32_t ss_hold;          // 0x28/0: hold
    __IO uint32_t ss_disable;       // 0x2c/0: disable
    __IO uint32_t ss_activeHigh;    // 0x30/0: disable
    __IO uint32_t __fill1[3];
    __IO uint32_t xip_enable;       // 0x40/0: enable
    __IO uint32_t xip_instr;        // 0x44/0:7 data, 8: enable, 16:23 dummy data, 24:27 dummy count
    __IO uint32_t xip_mode;         // 0x48/0: instr transfer mode, 8: addr transfer mode, 16: dummy transfer mode, 24: data transfer mode
    __IO uint32_t __fill2[2];
    __IO uint32_t xip_write32;      // 0x50
    __IO uint32_t xip_readwrite32;  // 0x54
    __IO uint32_t xip_read32;       // 0x58
}  __attribute((__packed__)) qspi_t;

typedef struct {
    uint32_t cpol;
    uint32_t cpha;
    uint32_t mode;
    uint32_t clkDivider;
    uint32_t ssSetup;
    uint32_t ssHold;
    uint32_t ssDisable;
} spi_cfg;

#define SPI_CMD_WRITE (1 << 8)
#define SPI_CMD_READ (1 << 9)
#define SPI_CMD_SS (1 << 11)

#define SPI_RSP_VALID (1 << 31)

#define SPI_STATUS_CMD_INT_ENABLE = (1 << 0)
#define SPI_STATUS_RSP_INT_ENABLE = (1 << 1)
#define SPI_STATUS_CMD_INT_FLAG = (1 << 8)
#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)

static inline void spi_configure(volatile qspi_t* reg, spi_cfg *config){
    reg->config     = (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4);
    reg->clk_divider = config->clkDivider;
    reg->ss_setup   = config->ssSetup;
    reg->ss_hold    = config->ssHold;
    reg->ss_disable =config->ssDisable;
}

static inline void spi_init(volatile qspi_t* spi){
    spi_cfg spiCfg;
    spiCfg.cpol = 0;
    spiCfg.cpha = 0;
    spiCfg.mode = 0;
    spiCfg.clkDivider = 2;
    spiCfg.ssSetup = 2;
    spiCfg.ssHold = 2;
    spiCfg.ssDisable = 2;
    spi_configure(spi, &spiCfg);
}

static inline uint32_t spi_cmd_avail(volatile qspi_t* reg){
    return reg->status & 0xFFFF;
}
static inline uint32_t spi_rsp_occupied(volatile qspi_t* reg){
    return reg->status >> 16;
}

static inline void spi_write(volatile qspi_t* reg, uint8_t data){
    while(spi_cmd_avail(reg) == 0);
    reg->data = data | SPI_CMD_WRITE;
}

static inline uint8_t spi_write_read(volatile qspi_t* reg, uint8_t data){
    while(spi_cmd_avail(reg) == 0);
    reg->data = data | SPI_CMD_READ | SPI_CMD_WRITE;
    while(spi_rsp_occupied(reg) == 0);
    return reg->data;
}


static inline uint8_t spi_read(volatile qspi_t* reg){
    while(spi_cmd_avail(reg) == 0);
    reg->data = SPI_CMD_READ;
    while(spi_rsp_occupied(reg) == 0);
    while((reg->data & 0x80000000)==0);
    return reg->data;
}

static inline void spi_select(volatile qspi_t* reg, uint32_t slaveId){
    while(spi_cmd_avail(reg) == 0);
    reg->data = slaveId | 0x80 | SPI_CMD_SS;
}

static inline void spi_deselect(volatile qspi_t* reg, uint32_t slaveId){
    while(spi_cmd_avail(reg) == 0);
    reg->data = slaveId | SPI_CMD_SS;
}

static inline void spi_wait_tx_idle(volatile qspi_t* reg){
    while(spi_cmd_avail(reg) < 0x20);
}
#endif /* _BSP_QSPI_H */