From e15e29996823e19b8d6d05d32c42afd315324d67 Mon Sep 17 00:00:00 2001 From: Stanislaw Kaushanski Date: Thu, 3 Sep 2020 11:13:37 +0200 Subject: [PATCH] initial FW setup for Raven validation --- hello/hello | Bin 72016 -> 72016 bytes hello/hello.c | 6 - raven/Makefile | 13 + raven/bsp/Debug/drivers/fe300prci/subdir.mk | 24 + raven/bsp/Debug/drivers/plic/subdir.mk | 24 + .../bsp/Debug/env/freedom-e300-arty/subdir.mk | 24 + .../Debug/env/freedom-e300-hifive1/subdir.mk | 27 + raven/bsp/Debug/env/iss/subdir.mk | 27 + raven/bsp/Debug/env/subdir.mk | 27 + raven/bsp/Debug/libwrap/stdlib/subdir.mk | 27 + raven/bsp/Debug/libwrap/sys/subdir.mk | 98 + raven/bsp/Debug/makefile | 66 + raven/bsp/Debug/objects.mk | 8 + raven/bsp/Debug/sources.mk | 35 + .../bsp/drivers/fe300prci/fe300prci_driver.c | 252 ++ .../bsp/drivers/fe300prci/fe300prci_driver.h | 79 + raven/bsp/drivers/plic/plic_driver.c | 127 + raven/bsp/drivers/plic/plic_driver.h | 51 + raven/bsp/env/common.mk | 62 + raven/bsp/env/encoding.h | 1313 ++++++++++ raven/bsp/env/entry.S | 97 + raven/bsp/env/freedom-e300-arty/init.c | 87 + raven/bsp/env/freedom-e300-arty/link.lds | 167 ++ raven/bsp/env/freedom-e300-arty/openocd.cfg | 30 + raven/bsp/env/freedom-e300-arty/platform.h | 125 + raven/bsp/env/freedom-e300-hifive1/init.c | 238 ++ raven/bsp/env/freedom-e300-hifive1/link.lds | 167 ++ .../bsp/env/freedom-e300-hifive1/openocd.cfg | 34 + raven/bsp/env/freedom-e300-hifive1/platform.h | 133 + raven/bsp/env/hifive1.h | 79 + raven/bsp/env/iss/init.c | 238 ++ raven/bsp/env/iss/link.lds | 168 ++ raven/bsp/env/iss/openocd.cfg | 34 + raven/bsp/env/iss/platform.h | 133 + raven/bsp/env/start.S | 54 + raven/bsp/include/sifive/bits.h | 35 + raven/bsp/include/sifive/const.h | 17 + raven/bsp/include/sifive/devices/aon.h | 88 + raven/bsp/include/sifive/devices/clint.h | 14 + raven/bsp/include/sifive/devices/gpio.h | 24 + raven/bsp/include/sifive/devices/otp.h | 23 + raven/bsp/include/sifive/devices/plic.h | 31 + raven/bsp/include/sifive/devices/prci.h | 56 + raven/bsp/include/sifive/devices/pwm.h | 37 + raven/bsp/include/sifive/devices/spi.h | 80 + raven/bsp/include/sifive/devices/uart.h | 27 + raven/bsp/include/sifive/sections.h | 16 + raven/bsp/libwrap/libwrap.mk | 53 + raven/bsp/libwrap/stdlib/malloc.c | 17 + raven/bsp/libwrap/sys/_exit.c | 16 + raven/bsp/libwrap/sys/close.c | 9 + raven/bsp/libwrap/sys/execve.c | 9 + raven/bsp/libwrap/sys/fork.c | 9 + raven/bsp/libwrap/sys/fstat.c | 16 + raven/bsp/libwrap/sys/getpid.c | 6 + raven/bsp/libwrap/sys/isatty.c | 11 + raven/bsp/libwrap/sys/kill.c | 9 + raven/bsp/libwrap/sys/link.c | 9 + raven/bsp/libwrap/sys/lseek.c | 14 + raven/bsp/libwrap/sys/open.c | 9 + raven/bsp/libwrap/sys/openat.c | 9 + raven/bsp/libwrap/sys/read.c | 30 + raven/bsp/libwrap/sys/sbrk.c | 16 + raven/bsp/libwrap/sys/stat.c | 10 + raven/bsp/libwrap/sys/stub.h | 10 + raven/bsp/libwrap/sys/times.c | 10 + raven/bsp/libwrap/sys/unlink.c | 9 + raven/bsp/libwrap/sys/wait.c | 9 + raven/bsp/libwrap/sys/write.c | 29 + raven/hello_raven | Bin 0 -> 72096 bytes raven/hello_raven.c | 77 + raven/hello_raven.dis | 2246 +++++++++++++++++ raven/wrap_printf.c | 271 ++ 73 files changed, 7429 insertions(+), 6 deletions(-) create mode 100644 raven/Makefile create mode 100644 raven/bsp/Debug/drivers/fe300prci/subdir.mk create mode 100644 raven/bsp/Debug/drivers/plic/subdir.mk create mode 100644 raven/bsp/Debug/env/freedom-e300-arty/subdir.mk create mode 100644 raven/bsp/Debug/env/freedom-e300-hifive1/subdir.mk create mode 100644 raven/bsp/Debug/env/iss/subdir.mk create mode 100644 raven/bsp/Debug/env/subdir.mk create mode 100644 raven/bsp/Debug/libwrap/stdlib/subdir.mk create mode 100644 raven/bsp/Debug/libwrap/sys/subdir.mk create mode 100644 raven/bsp/Debug/makefile create mode 100644 raven/bsp/Debug/objects.mk create mode 100644 raven/bsp/Debug/sources.mk create mode 100644 raven/bsp/drivers/fe300prci/fe300prci_driver.c create mode 100644 raven/bsp/drivers/fe300prci/fe300prci_driver.h create mode 100644 raven/bsp/drivers/plic/plic_driver.c create mode 100644 raven/bsp/drivers/plic/plic_driver.h create mode 100644 raven/bsp/env/common.mk create mode 100644 raven/bsp/env/encoding.h create mode 100644 raven/bsp/env/entry.S create mode 100644 raven/bsp/env/freedom-e300-arty/init.c create mode 100644 raven/bsp/env/freedom-e300-arty/link.lds create mode 100644 raven/bsp/env/freedom-e300-arty/openocd.cfg create mode 100644 raven/bsp/env/freedom-e300-arty/platform.h create mode 100644 raven/bsp/env/freedom-e300-hifive1/init.c create mode 100644 raven/bsp/env/freedom-e300-hifive1/link.lds create mode 100644 raven/bsp/env/freedom-e300-hifive1/openocd.cfg create mode 100644 raven/bsp/env/freedom-e300-hifive1/platform.h create mode 100644 raven/bsp/env/hifive1.h create mode 100644 raven/bsp/env/iss/init.c create mode 100644 raven/bsp/env/iss/link.lds create mode 100644 raven/bsp/env/iss/openocd.cfg create mode 100644 raven/bsp/env/iss/platform.h create mode 100644 raven/bsp/env/start.S create mode 100644 raven/bsp/include/sifive/bits.h create mode 100644 raven/bsp/include/sifive/const.h create mode 100644 raven/bsp/include/sifive/devices/aon.h create mode 100644 raven/bsp/include/sifive/devices/clint.h create mode 100644 raven/bsp/include/sifive/devices/gpio.h create mode 100644 raven/bsp/include/sifive/devices/otp.h create mode 100644 raven/bsp/include/sifive/devices/plic.h create mode 100644 raven/bsp/include/sifive/devices/prci.h create mode 100644 raven/bsp/include/sifive/devices/pwm.h create mode 100644 raven/bsp/include/sifive/devices/spi.h create mode 100644 raven/bsp/include/sifive/devices/uart.h create mode 100644 raven/bsp/include/sifive/sections.h create mode 100644 raven/bsp/libwrap/libwrap.mk create mode 100644 raven/bsp/libwrap/stdlib/malloc.c create mode 100644 raven/bsp/libwrap/sys/_exit.c create mode 100644 raven/bsp/libwrap/sys/close.c create mode 100644 raven/bsp/libwrap/sys/execve.c create mode 100644 raven/bsp/libwrap/sys/fork.c create mode 100644 raven/bsp/libwrap/sys/fstat.c create mode 100644 raven/bsp/libwrap/sys/getpid.c create mode 100644 raven/bsp/libwrap/sys/isatty.c create mode 100644 raven/bsp/libwrap/sys/kill.c create mode 100644 raven/bsp/libwrap/sys/link.c create mode 100644 raven/bsp/libwrap/sys/lseek.c create mode 100644 raven/bsp/libwrap/sys/open.c create mode 100644 raven/bsp/libwrap/sys/openat.c create mode 100644 raven/bsp/libwrap/sys/read.c create mode 100644 raven/bsp/libwrap/sys/sbrk.c create mode 100644 raven/bsp/libwrap/sys/stat.c create mode 100644 raven/bsp/libwrap/sys/stub.h create mode 100644 raven/bsp/libwrap/sys/times.c create mode 100644 raven/bsp/libwrap/sys/unlink.c create mode 100644 raven/bsp/libwrap/sys/wait.c create mode 100644 raven/bsp/libwrap/sys/write.c create mode 100755 raven/hello_raven create mode 100644 raven/hello_raven.c create mode 100644 raven/hello_raven.dis create mode 100644 raven/wrap_printf.c diff --git a/hello/hello b/hello/hello index 9648454452a1a0d3c22f46b96a5fc737a9f9fd00..305dc2f39f91b29088bfb075f5f13abaab22490a 100755 GIT binary patch delta 71 zcmcbxiRHp3mJNqP7@0R835l~cv|-I;U|^`>bx_yB0RZM#67>K8 delta 71 zcmcbxiRHp3mJNqP7&$i|35l~cbYjh9U|^`>bx_yB0RZXM6Ab_W diff --git a/hello/hello.c b/hello/hello.c index 9ff8ce1..75a83f2 100644 --- a/hello/hello.c +++ b/hello/hello.c @@ -57,12 +57,6 @@ unsigned read_adc(unsigned index){ return result&0x03ff; } -//int read_csr(int csr_num) __attribute__((always_inline)) { -// int result; -// asm("csrr %0, %1" : "=r"(result) : "I"(csr_num)); -// return result; -//} - int main() { GPIO_REG(GPIO_IOF_EN) |= 0x30000; diff --git a/raven/Makefile b/raven/Makefile new file mode 100644 index 0000000..25c627a --- /dev/null +++ b/raven/Makefile @@ -0,0 +1,13 @@ + +TARGET = hello_raven +C_SRCS += $(wildcard *.c) +CFLAGS += -g +#-fno-builtin-printf +LDFLAGS := -Wl,--wrap=scanf -Wl,--wrap=printf + +#BOARD = iss +BOARD=freedom-e300-hifive1 +TOOL_DIR=/opt/shared/riscv/FreedomStudio/20180122/SiFive/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin + +BSP_BASE = ./bsp +include $(BSP_BASE)/env/common.mk diff --git a/raven/bsp/Debug/drivers/fe300prci/subdir.mk b/raven/bsp/Debug/drivers/fe300prci/subdir.mk new file mode 100644 index 0000000..9a05361 --- /dev/null +++ b/raven/bsp/Debug/drivers/fe300prci/subdir.mk @@ -0,0 +1,24 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../drivers/fe300prci/fe300prci_driver.c + +OBJS += \ +./drivers/fe300prci/fe300prci_driver.o + +C_DEPS += \ +./drivers/fe300prci/fe300prci_driver.d + + +# Each subdirectory must supply rules for building sources it contributes +drivers/fe300prci/%.o: ../drivers/fe300prci/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/raven/bsp/Debug/drivers/plic/subdir.mk b/raven/bsp/Debug/drivers/plic/subdir.mk new file mode 100644 index 0000000..be3a955 --- /dev/null +++ b/raven/bsp/Debug/drivers/plic/subdir.mk @@ -0,0 +1,24 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../drivers/plic/plic_driver.c + +OBJS += \ +./drivers/plic/plic_driver.o + +C_DEPS += \ +./drivers/plic/plic_driver.d + + +# Each subdirectory must supply rules for building sources it contributes +drivers/plic/%.o: ../drivers/plic/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/raven/bsp/Debug/env/freedom-e300-arty/subdir.mk b/raven/bsp/Debug/env/freedom-e300-arty/subdir.mk new file mode 100644 index 0000000..c0bee22 --- /dev/null +++ b/raven/bsp/Debug/env/freedom-e300-arty/subdir.mk @@ -0,0 +1,24 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../env/freedom-e300-arty/init.c + +OBJS += \ +./env/freedom-e300-arty/init.o + +C_DEPS += \ +./env/freedom-e300-arty/init.d + + +# Each subdirectory must supply rules for building sources it contributes +env/freedom-e300-arty/%.o: ../env/freedom-e300-arty/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/raven/bsp/Debug/env/freedom-e300-hifive1/subdir.mk b/raven/bsp/Debug/env/freedom-e300-hifive1/subdir.mk new file mode 100644 index 0000000..16eea64 --- /dev/null +++ b/raven/bsp/Debug/env/freedom-e300-hifive1/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../env/freedom-e300-hifive1/init.c + +O_SRCS += \ +../env/freedom-e300-hifive1/init.o + +OBJS += \ +./env/freedom-e300-hifive1/init.o + +C_DEPS += \ +./env/freedom-e300-hifive1/init.d + + +# Each subdirectory must supply rules for building sources it contributes +env/freedom-e300-hifive1/%.o: ../env/freedom-e300-hifive1/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/raven/bsp/Debug/env/iss/subdir.mk b/raven/bsp/Debug/env/iss/subdir.mk new file mode 100644 index 0000000..88f2d87 --- /dev/null +++ b/raven/bsp/Debug/env/iss/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../env/iss/init.c + +O_SRCS += \ +../env/iss/init.o + +OBJS += \ +./env/iss/init.o + +C_DEPS += \ +./env/iss/init.d + + +# Each subdirectory must supply rules for building sources it contributes +env/iss/%.o: ../env/iss/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/raven/bsp/Debug/env/subdir.mk b/raven/bsp/Debug/env/subdir.mk new file mode 100644 index 0000000..b8eaa7a --- /dev/null +++ b/raven/bsp/Debug/env/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +O_SRCS += \ +../env/entry.o \ +../env/start.o + +S_UPPER_SRCS += \ +../env/entry.S \ +../env/start.S + +OBJS += \ +./env/entry.o \ +./env/start.o + + +# Each subdirectory must supply rules for building sources it contributes +env/%.o: ../env/%.S + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Assembler' + riscv32-unknown-elf-as -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/raven/bsp/Debug/libwrap/stdlib/subdir.mk b/raven/bsp/Debug/libwrap/stdlib/subdir.mk new file mode 100644 index 0000000..2327c6d --- /dev/null +++ b/raven/bsp/Debug/libwrap/stdlib/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../libwrap/stdlib/malloc.c + +O_SRCS += \ +../libwrap/stdlib/malloc.o + +OBJS += \ +./libwrap/stdlib/malloc.o + +C_DEPS += \ +./libwrap/stdlib/malloc.d + + +# Each subdirectory must supply rules for building sources it contributes +libwrap/stdlib/%.o: ../libwrap/stdlib/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/raven/bsp/Debug/libwrap/sys/subdir.mk b/raven/bsp/Debug/libwrap/sys/subdir.mk new file mode 100644 index 0000000..a93df2a --- /dev/null +++ b/raven/bsp/Debug/libwrap/sys/subdir.mk @@ -0,0 +1,98 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../libwrap/sys/_exit.c \ +../libwrap/sys/close.c \ +../libwrap/sys/execve.c \ +../libwrap/sys/fork.c \ +../libwrap/sys/fstat.c \ +../libwrap/sys/getpid.c \ +../libwrap/sys/isatty.c \ +../libwrap/sys/kill.c \ +../libwrap/sys/link.c \ +../libwrap/sys/lseek.c \ +../libwrap/sys/open.c \ +../libwrap/sys/openat.c \ +../libwrap/sys/read.c \ +../libwrap/sys/sbrk.c \ +../libwrap/sys/stat.c \ +../libwrap/sys/times.c \ +../libwrap/sys/unlink.c \ +../libwrap/sys/wait.c \ +../libwrap/sys/write.c + +O_SRCS += \ +../libwrap/sys/_exit.o \ +../libwrap/sys/close.o \ +../libwrap/sys/execve.o \ +../libwrap/sys/fork.o \ +../libwrap/sys/fstat.o \ +../libwrap/sys/getpid.o \ +../libwrap/sys/isatty.o \ +../libwrap/sys/kill.o \ +../libwrap/sys/link.o \ +../libwrap/sys/lseek.o \ +../libwrap/sys/open.o \ +../libwrap/sys/read.o \ +../libwrap/sys/sbrk.o \ +../libwrap/sys/stat.o \ +../libwrap/sys/times.o \ +../libwrap/sys/unlink.o \ +../libwrap/sys/wait.o \ +../libwrap/sys/write.o + +OBJS += \ +./libwrap/sys/_exit.o \ +./libwrap/sys/close.o \ +./libwrap/sys/execve.o \ +./libwrap/sys/fork.o \ +./libwrap/sys/fstat.o \ +./libwrap/sys/getpid.o \ +./libwrap/sys/isatty.o \ +./libwrap/sys/kill.o \ +./libwrap/sys/link.o \ +./libwrap/sys/lseek.o \ +./libwrap/sys/open.o \ +./libwrap/sys/openat.o \ +./libwrap/sys/read.o \ +./libwrap/sys/sbrk.o \ +./libwrap/sys/stat.o \ +./libwrap/sys/times.o \ +./libwrap/sys/unlink.o \ +./libwrap/sys/wait.o \ +./libwrap/sys/write.o + +C_DEPS += \ +./libwrap/sys/_exit.d \ +./libwrap/sys/close.d \ +./libwrap/sys/execve.d \ +./libwrap/sys/fork.d \ +./libwrap/sys/fstat.d \ +./libwrap/sys/getpid.d \ +./libwrap/sys/isatty.d \ +./libwrap/sys/kill.d \ +./libwrap/sys/link.d \ +./libwrap/sys/lseek.d \ +./libwrap/sys/open.d \ +./libwrap/sys/openat.d \ +./libwrap/sys/read.d \ +./libwrap/sys/sbrk.d \ +./libwrap/sys/stat.d \ +./libwrap/sys/times.d \ +./libwrap/sys/unlink.d \ +./libwrap/sys/wait.d \ +./libwrap/sys/write.d + + +# Each subdirectory must supply rules for building sources it contributes +libwrap/sys/%.o: ../libwrap/sys/%.c + @echo 'Building file: $<' + @echo 'Invoking: Cross GCC Compiler' + riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" + @echo 'Finished building: $<' + @echo ' ' + + diff --git a/raven/bsp/Debug/makefile b/raven/bsp/Debug/makefile new file mode 100644 index 0000000..34f9759 --- /dev/null +++ b/raven/bsp/Debug/makefile @@ -0,0 +1,66 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include libwrap/sys/subdir.mk +-include libwrap/stdlib/subdir.mk +-include libwrap/misc/subdir.mk +-include env/iss/subdir.mk +-include env/freedom-e300-hifive1/subdir.mk +-include env/freedom-e300-arty/subdir.mk +-include env/subdir.mk +-include drivers/plic/subdir.mk +-include drivers/fe300prci/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables + +# All Target +all: bsp + +# Tool invocations +bsp: $(OBJS) $(USER_OBJS) + @echo 'Building target: $@' + @echo 'Invoking: Cross G++ Linker' + riscv32-unknown-elf-g++ -o "bsp" $(OBJS) $(USER_OBJS) $(LIBS) + @echo 'Finished building target: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(EXECUTABLES)$(OBJS)$(C_UPPER_DEPS)$(CXX_DEPS)$(C_DEPS)$(CPP_DEPS) bsp + -@echo ' ' + +.PHONY: all clean dependents + +-include ../makefile.targets diff --git a/raven/bsp/Debug/objects.mk b/raven/bsp/Debug/objects.mk new file mode 100644 index 0000000..742c2da --- /dev/null +++ b/raven/bsp/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/raven/bsp/Debug/sources.mk b/raven/bsp/Debug/sources.mk new file mode 100644 index 0000000..bfb7eff --- /dev/null +++ b/raven/bsp/Debug/sources.mk @@ -0,0 +1,35 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C_UPPER_SRCS := +CXX_SRCS := +C++_SRCS := +OBJ_SRCS := +CC_SRCS := +ASM_SRCS := +C_SRCS := +CPP_SRCS := +O_SRCS := +S_UPPER_SRCS := +CC_DEPS := +C++_DEPS := +EXECUTABLES := +OBJS := +C_UPPER_DEPS := +CXX_DEPS := +C_DEPS := +CPP_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +drivers/fe300prci \ +drivers/plic \ +env \ +env/freedom-e300-arty \ +env/freedom-e300-hifive1 \ +env/iss \ +libwrap/misc \ +libwrap/stdlib \ +libwrap/sys \ + diff --git a/raven/bsp/drivers/fe300prci/fe300prci_driver.c b/raven/bsp/drivers/fe300prci/fe300prci_driver.c new file mode 100644 index 0000000..2d9c52f --- /dev/null +++ b/raven/bsp/drivers/fe300prci/fe300prci_driver.c @@ -0,0 +1,252 @@ +// See LICENSE file for license details + +#include "platform.h" + +#ifdef PRCI_BASE_ADDR +#include "fe300prci/fe300prci_driver.h" +#include + +#define rdmcycle(x) { \ + uint32_t lo, hi, hi2; \ + __asm__ __volatile__ ("1:\n\t" \ + "csrr %0, mcycleh\n\t" \ + "csrr %1, mcycle\n\t" \ + "csrr %2, mcycleh\n\t" \ + "bne %0, %2, 1b\n\t" \ + : "=r" (hi), "=r" (lo), "=r" (hi2)) ; \ + *(x) = lo | ((uint64_t) hi << 32); \ + } + +uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq) +{ + + uint32_t start_mtime = CLINT_REG(CLINT_MTIME); + uint32_t end_mtime = start_mtime + mtime_ticks + 1; + + // Make sure we won't get rollover. + while (end_mtime < start_mtime){ + start_mtime = CLINT_REG(CLINT_MTIME); + end_mtime = start_mtime + mtime_ticks + 1; + } + + // Don't start measuring until mtime edge. + uint32_t tmp = start_mtime; + do { + start_mtime = CLINT_REG(CLINT_MTIME); + } while (start_mtime == tmp); + + uint64_t start_mcycle; + rdmcycle(&start_mcycle); + + while (CLINT_REG(CLINT_MTIME) < end_mtime) ; + + uint64_t end_mcycle; + rdmcycle(&end_mcycle); + uint32_t difference = (uint32_t) (end_mcycle - start_mcycle); + + uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks; + return (uint32_t) freq & 0xFFFFFFFF; + +} + + +void PRCI_use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + // It is OK to change this even if we are running off of it. + + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0); + + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +void PRCI_use_pll(int refsel, int bypass, + int r, int f, int q, int finaldiv, + int hfroscdiv, int hfrosctrim) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + PRCI_use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if desired. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + + // To overclock, use the hfrosc + if (hfrosctrim >= 0 && hfroscdiv >= 0) { + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + } + + // Set DIV Settings for PLL + + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + if (finaldiv == 1){ + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1)); + } + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = CLINT_REG(CLINT_MTIME); + while (CLINT_REG(CLINT_MTIME) - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0); + + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); + + // If we're running off HFXOSC, turn off the HFROSC to + // save power. + if (refsel) { + PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1); + } + +} + +void PRCI_use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + PRCI_use_hfrosc(4, 16); +} + +void PRCI_use_hfxosc(uint32_t finaldiv) +{ + + PRCI_use_pll(1, // Use HFXTAL + 1, // Bypass = 1 + 0, // PLL settings don't matter + 0, // PLL settings don't matter + 0, // PLL settings don't matter + finaldiv, + -1, + -1); +} + +// This is a generic function, which +// doesn't span the entire range of HFROSC settings. +// It only adjusts the trim, which can span a hundred MHz or so. +// This function does not check the legality of the PLL settings +// at all, and it is quite possible to configure invalid PLL settings +// this way. +// It returns the actual measured CPU frequency. + +uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target ) +{ + + uint32_t hfrosctrim = 0; + uint32_t hfroscdiv = 4; + uint32_t prev_trim = 0; + + // In this function we use PLL settings which + // will give us a 32x multiplier from the output + // of the HFROSC source to the output of the + // PLL. We first measure our HFROSC to get the + // right trim, then finally use it as the PLL source. + // We should really check here that the f_cpu + // requested is something in the limit of the PLL. For + // now that is up to the user. + + // This will undershoot for frequencies not divisible by 16. + uint32_t desired_hfrosc_freq = (f_cpu/ 16); + + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + + // Ignore the first run (for icache reasons) + uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + + cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + uint32_t prev_freq = cpu_freq; + + while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){ + prev_trim = hfrosctrim; + prev_freq = cpu_freq; + hfrosctrim ++; + PRCI_use_hfrosc(hfroscdiv, hfrosctrim); + cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); + } + + // We couldn't go low enough + if (prev_freq > desired_hfrosc_freq){ + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + } + + // We couldn't go high enough + if (cpu_freq < desired_hfrosc_freq){ + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + } + + // Check for over/undershoot + switch(target) { + case(PRCI_FREQ_CLOSEST): + if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) { + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + } else { + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); + } + break; + case(PRCI_FREQ_UNDERSHOOT): + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); + break; + default: + PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); + } + + cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); + return cpu_freq; + +} + +#endif diff --git a/raven/bsp/drivers/fe300prci/fe300prci_driver.h b/raven/bsp/drivers/fe300prci/fe300prci_driver.h new file mode 100644 index 0000000..7100f46 --- /dev/null +++ b/raven/bsp/drivers/fe300prci/fe300prci_driver.h @@ -0,0 +1,79 @@ +// See LICENSE file for license details + +#ifndef _FE300PRCI_DRIVER_H_ +#define _FE300PRCI_DRIVER_H_ + +__BEGIN_DECLS + +#include + +typedef enum prci_freq_target { + + PRCI_FREQ_OVERSHOOT, + PRCI_FREQ_CLOSEST, + PRCI_FREQ_UNDERSHOOT + +} PRCI_freq_target; + +/* Measure and return the approximate frequency of the + * CPU, as given by measuring the mcycle counter against + * the mtime ticks. + */ +uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq); + +/* Safely switch over to the HFROSC using the given div + * and trim settings. + */ +void PRCI_use_hfrosc(int div, int trim); + +/* Safely switch over to the 16MHz HFXOSC, + * applying the finaldiv clock divider (1 is the lowest + * legal value). + */ +void PRCI_use_hfxosc(uint32_t finaldiv); + +/* Safely switch over to the PLL using the given + * settings. + * + * Note that not all combinations of the inputs are actually + * legal, and this function does not check for their + * legality ("safely" means that this function won't turn off + * or glitch the clock the CPU is actually running off, but + * doesn't protect against you making it too fast or slow.) + */ + +void PRCI_use_pll(int refsel, int bypass, + int r, int f, int q, int finaldiv, + int hfroscdiv, int hfrosctrim); + +/* Use the default clocks configured at reset. + * This is ~16Mhz HFROSC and turns off the LFROSC + * (on the current FE310 Dev Platforms, an external LFROSC is + * used as it is more power efficient). + */ +void PRCI_use_default_clocks(); + +/* This routine will adjust the HFROSC trim + * while using HFROSC as the clock source, + * measure the resulting frequency, then + * use it as the PLL clock source, + * in an attempt to get over, under, or close to the + * requested frequency. It returns the actual measured + * frequency. + * + * Note that the requested frequency must be within the + * range supported by the PLL so not all values are + * achievable with this function, and not all + * are guaranteed to actually work. The PLL + * is rated higher than the hardware. + * + * There is no check on the desired f_cpu frequency, it + * is up to the user to specify something reasonable. + */ + +uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target); + +__END_DECLS + +#endif + diff --git a/raven/bsp/drivers/plic/plic_driver.c b/raven/bsp/drivers/plic/plic_driver.c new file mode 100644 index 0000000..b27d7a5 --- /dev/null +++ b/raven/bsp/drivers/plic/plic_driver.c @@ -0,0 +1,127 @@ +// See LICENSE for license details. + +#include "sifive/devices/plic.h" +#include "plic/plic_driver.h" +#include "platform.h" +#include "encoding.h" +#include + + +// Note that there are no assertions or bounds checking on these +// parameter values. + +void volatile_memzero(uint8_t * base, unsigned int size) +{ + volatile uint8_t * ptr; + for (ptr = base; ptr < (base + size); ptr++){ + *ptr = 0; + } +} + +void PLIC_init ( + plic_instance_t * this_plic, + uintptr_t base_addr, + uint32_t num_sources, + uint32_t num_priorities + ) +{ + + this_plic->base_addr = base_addr; + this_plic->num_sources = num_sources; + this_plic->num_priorities = num_priorities; + + // Disable all interrupts (don't assume that these registers are reset). + unsigned long hart_id = read_csr(mhartid); + volatile_memzero((uint8_t*) (this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET)), + (num_sources + 8) / 8); + + // Set all priorities to 0 (equal priority -- don't assume that these are reset). + volatile_memzero ((uint8_t *)(this_plic->base_addr + + PLIC_PRIORITY_OFFSET), + (num_sources + 1) << PLIC_PRIORITY_SHIFT_PER_SOURCE); + + // Set the threshold to 0. + volatile plic_threshold* threshold = (plic_threshold*) + (this_plic->base_addr + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + + *threshold = 0; + +} + +void PLIC_set_threshold (plic_instance_t * this_plic, + plic_threshold threshold){ + + unsigned long hart_id = read_csr(mhartid); + volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr + + PLIC_THRESHOLD_OFFSET + + (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + + *threshold_ptr = threshold; + +} + + +void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (source >> 3)); + uint8_t current = *current_ptr; + current = current | ( 1 << (source & 0x7)); + *current_ptr = current; + +} + +void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr + + PLIC_ENABLE_OFFSET + + (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (source >> 3)); + uint8_t current = *current_ptr; + current = current & ~(( 1 << (source & 0x7))); + *current_ptr = current; + +} + +void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority){ + + if (this_plic->num_priorities > 0) { + volatile plic_priority * priority_ptr = (volatile plic_priority *) + (this_plic->base_addr + + PLIC_PRIORITY_OFFSET + + (source << PLIC_PRIORITY_SHIFT_PER_SOURCE)); + *priority_ptr = priority; + } +} + +plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){ + + unsigned long hart_id = read_csr(mhartid); + + volatile plic_source * claim_addr = (volatile plic_source * ) + (this_plic->base_addr + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + + return *claim_addr; + +} + +void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){ + + unsigned long hart_id = read_csr(mhartid); + volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr + + PLIC_CLAIM_OFFSET + + (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + *claim_addr = source; + +} + diff --git a/raven/bsp/drivers/plic/plic_driver.h b/raven/bsp/drivers/plic/plic_driver.h new file mode 100644 index 0000000..e7d609b --- /dev/null +++ b/raven/bsp/drivers/plic/plic_driver.h @@ -0,0 +1,51 @@ +// See LICENSE file for licence details + +#ifndef PLIC_DRIVER_H +#define PLIC_DRIVER_H + + +__BEGIN_DECLS + +#include "platform.h" + +typedef struct __plic_instance_t +{ + uintptr_t base_addr; + + uint32_t num_sources; + uint32_t num_priorities; + +} plic_instance_t; + +typedef uint32_t plic_source; +typedef uint32_t plic_priority; +typedef uint32_t plic_threshold; + +void PLIC_init ( + plic_instance_t * this_plic, + uintptr_t base_addr, + uint32_t num_sources, + uint32_t num_priorities + ); + +void PLIC_set_threshold (plic_instance_t * this_plic, + plic_threshold threshold); + +void PLIC_enable_interrupt (plic_instance_t * this_plic, + plic_source source); + +void PLIC_disable_interrupt (plic_instance_t * this_plic, + plic_source source); + +void PLIC_set_priority (plic_instance_t * this_plic, + plic_source source, + plic_priority priority); + +plic_source PLIC_claim_interrupt(plic_instance_t * this_plic); + +void PLIC_complete_interrupt(plic_instance_t * this_plic, + plic_source source); + +__END_DECLS + +#endif diff --git a/raven/bsp/env/common.mk b/raven/bsp/env/common.mk new file mode 100644 index 0000000..0995009 --- /dev/null +++ b/raven/bsp/env/common.mk @@ -0,0 +1,62 @@ +# See LICENSE for license details. + +ifndef _SIFIVE_MK_COMMON +_SIFIVE_MK_COMMON := # defined + +.PHONY: all +all: $(TARGET) + +include $(BSP_BASE)/libwrap/libwrap.mk + +BOARD ?= freedom-e300-hifive1 +ENV_DIR = $(BSP_BASE)/env +PLATFORM_DIR = $(ENV_DIR)/$(BOARD) + +#TARGET_FLAVOR := -march=rv32imac -mabi=ilp32 -mcmodel=medany -msmall-data-limit=8 -x assembler-with-cpp +TARGET_FLAVOR := -march=rv32i -mabi=ilp32 + +ASM_SRCS += $(ENV_DIR)/start.S +ASM_SRCS += $(ENV_DIR)/entry.S +C_SRCS += $(PLATFORM_DIR)/init.c + +LINKER_SCRIPT := $(PLATFORM_DIR)/link.lds + +INCLUDES += -I$(BSP_BASE)/include +INCLUDES += -I$(BSP_BASE)/drivers/ +INCLUDES += -I$(ENV_DIR) +INCLUDES += -I$(PLATFORM_DIR) + +TOOL_DIR ?= $(BSP_BASE)/../toolchain/bin + +CC := $(TOOL_DIR)/riscv64-unknown-elf-gcc ${TARGET_FLAVOR} +AR := $(TOOL_DIR)/riscv64-unknown-elf-ar +OBJDUMP := $(TOOL_DIR)/riscv64-unknown-elf-objdump + +LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles +LDFLAGS += -L$(ENV_DIR) + +ASM_OBJS := $(ASM_SRCS:.S=.o) +C_OBJS := $(C_SRCS:.c=.o) + +LINK_OBJS += $(ASM_OBJS) $(C_OBJS) +LINK_DEPS += $(LINKER_SCRIPT) + +CLEAN_OBJS += $(TARGET) $(LINK_OBJS) + +CFLAGS += -g + +$(TARGET): $(LINK_OBJS) $(LINK_DEPS) + $(CC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS) + $(OBJDUMP) -d $(TARGET) > $(TARGET).dis + +$(ASM_OBJS): %.o: %.S $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +$(C_OBJS): %.o: %.c $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $< + +.PHONY: clean +clean: + rm -f $(CLEAN_OBJS) + +endif # _SIFIVE_MK_COMMON diff --git a/raven/bsp/env/encoding.h b/raven/bsp/env/encoding.h new file mode 100644 index 0000000..35e0f9f --- /dev/null +++ b/raven/bsp/env/encoding.h @@ -0,0 +1,1313 @@ +// See LICENSE for license details. + +#ifndef RISCV_CSR_ENCODING_H +#define RISCV_CSR_ENCODING_H + +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000 + +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000 + +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + +#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) +#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) +#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) + +#define MCONTROL_SELECT (1<<19) +#define MCONTROL_TIMING (1<<18) +#define MCONTROL_ACTION (0x3f<<12) +#define MCONTROL_CHAIN (1<<11) +#define MCONTROL_MATCH (0xf<<7) +#define MCONTROL_M (1<<6) +#define MCONTROL_H (1<<5) +#define MCONTROL_S (1<<4) +#define MCONTROL_U (1<<3) +#define MCONTROL_EXECUTE (1<<2) +#define MCONTROL_STORE (1<<1) +#define MCONTROL_LOAD (1<<0) + +#define MCONTROL_TYPE_NONE 0 +#define MCONTROL_TYPE_MATCH 2 + +#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 +#define MCONTROL_ACTION_DEBUG_MODE 1 +#define MCONTROL_ACTION_TRACE_START 2 +#define MCONTROL_ACTION_TRACE_STOP 3 +#define MCONTROL_ACTION_TRACE_EMIT 4 + +#define MCONTROL_MATCH_EQUAL 0 +#define MCONTROL_MATCH_NAPOT 1 +#define MCONTROL_MATCH_GE 2 +#define MCONTROL_MATCH_LT 3 +#define MCONTROL_MATCH_MASK_LOW 4 +#define MCONTROL_MATCH_MASK_HIGH 5 + +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +#define VM_MBARE 0 +#define VM_MBB 1 +#define VM_MBBID 2 +#define VM_SV32 8 +#define VM_SV39 9 +#define VM_SV48 10 + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Valid +#define PTE_R 0x002 // Read +#define PTE_W 0x004 // Write +#define PTE_X 0x008 // Execute +#define PTE_U 0x010 // User +#define PTE_G 0x020 // Global +#define PTE_A 0x040 // Accessed +#define PTE_D 0x080 // Dirty +#define PTE_SOFT 0x300 // Reserved for Software + +#define PTE_PPN_SHIFT 10 + +#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) + +#ifdef __riscv + +#ifdef __riscv64 +# define MSTATUS_SD MSTATUS64_SD +# define SSTATUS_SD SSTATUS64_SD +# define RISCV_PGLEVEL_BITS 9 +#else +# define MSTATUS_SD MSTATUS32_SD +# define SSTATUS_SD SSTATUS32_SD +# define RISCV_PGLEVEL_BITS 10 +#endif +#define RISCV_PGSHIFT 12 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#ifdef __GNUC__ + +#define read_csr(reg) ({ unsigned long __tmp; \ + asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + __tmp; }) + +#define write_csr(reg, val) ({ \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ + else \ + asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) + +#define swap_csr(reg, val) ({ unsigned long __tmp; \ + if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ + else \ + asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ + __tmp; }) + +#define set_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define clear_csr(reg, bit) ({ unsigned long __tmp; \ + if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ + else \ + asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ + __tmp; }) + +#define rdtime() read_csr(time) +#define rdcycle() read_csr(cycle) +#define rdinstret() read_csr(instret) + +#endif + +#endif + +#endif + +#endif +/* Automatically generated by parse-opcodes */ +#ifndef RISCV_ENCODING_H +#define RISCV_ENCODING_H +#define MATCH_BEQ 0x63 +#define MASK_BEQ 0x707f +#define MATCH_BNE 0x1063 +#define MASK_BNE 0x707f +#define MATCH_BLT 0x4063 +#define MASK_BLT 0x707f +#define MATCH_BGE 0x5063 +#define MASK_BGE 0x707f +#define MATCH_BLTU 0x6063 +#define MASK_BLTU 0x707f +#define MATCH_BGEU 0x7063 +#define MASK_BGEU 0x707f +#define MATCH_JALR 0x67 +#define MASK_JALR 0x707f +#define MATCH_JAL 0x6f +#define MASK_JAL 0x7f +#define MATCH_LUI 0x37 +#define MASK_LUI 0x7f +#define MATCH_AUIPC 0x17 +#define MASK_AUIPC 0x7f +#define MATCH_ADDI 0x13 +#define MASK_ADDI 0x707f +#define MATCH_SLLI 0x1013 +#define MASK_SLLI 0xfc00707f +#define MATCH_SLTI 0x2013 +#define MASK_SLTI 0x707f +#define MATCH_SLTIU 0x3013 +#define MASK_SLTIU 0x707f +#define MATCH_XORI 0x4013 +#define MASK_XORI 0x707f +#define MATCH_SRLI 0x5013 +#define MASK_SRLI 0xfc00707f +#define MATCH_SRAI 0x40005013 +#define MASK_SRAI 0xfc00707f +#define MATCH_ORI 0x6013 +#define MASK_ORI 0x707f +#define MATCH_ANDI 0x7013 +#define MASK_ANDI 0x707f +#define MATCH_ADD 0x33 +#define MASK_ADD 0xfe00707f +#define MATCH_SUB 0x40000033 +#define MASK_SUB 0xfe00707f +#define MATCH_SLL 0x1033 +#define MASK_SLL 0xfe00707f +#define MATCH_SLT 0x2033 +#define MASK_SLT 0xfe00707f +#define MATCH_SLTU 0x3033 +#define MASK_SLTU 0xfe00707f +#define MATCH_XOR 0x4033 +#define MASK_XOR 0xfe00707f +#define MATCH_SRL 0x5033 +#define MASK_SRL 0xfe00707f +#define MATCH_SRA 0x40005033 +#define MASK_SRA 0xfe00707f +#define MATCH_OR 0x6033 +#define MASK_OR 0xfe00707f +#define MATCH_AND 0x7033 +#define MASK_AND 0xfe00707f +#define MATCH_ADDIW 0x1b +#define MASK_ADDIW 0x707f +#define MATCH_SLLIW 0x101b +#define MASK_SLLIW 0xfe00707f +#define MATCH_SRLIW 0x501b +#define MASK_SRLIW 0xfe00707f +#define MATCH_SRAIW 0x4000501b +#define MASK_SRAIW 0xfe00707f +#define MATCH_ADDW 0x3b +#define MASK_ADDW 0xfe00707f +#define MATCH_SUBW 0x4000003b +#define MASK_SUBW 0xfe00707f +#define MATCH_SLLW 0x103b +#define MASK_SLLW 0xfe00707f +#define MATCH_SRLW 0x503b +#define MASK_SRLW 0xfe00707f +#define MATCH_SRAW 0x4000503b +#define MASK_SRAW 0xfe00707f +#define MATCH_LB 0x3 +#define MASK_LB 0x707f +#define MATCH_LH 0x1003 +#define MASK_LH 0x707f +#define MATCH_LW 0x2003 +#define MASK_LW 0x707f +#define MATCH_LD 0x3003 +#define MASK_LD 0x707f +#define MATCH_LBU 0x4003 +#define MASK_LBU 0x707f +#define MATCH_LHU 0x5003 +#define MASK_LHU 0x707f +#define MATCH_LWU 0x6003 +#define MASK_LWU 0x707f +#define MATCH_SB 0x23 +#define MASK_SB 0x707f +#define MATCH_SH 0x1023 +#define MASK_SH 0x707f +#define MATCH_SW 0x2023 +#define MASK_SW 0x707f +#define MATCH_SD 0x3023 +#define MASK_SD 0x707f +#define MATCH_FENCE 0xf +#define MASK_FENCE 0x707f +#define MATCH_FENCE_I 0x100f +#define MASK_FENCE_I 0x707f +#define MATCH_MUL 0x2000033 +#define MASK_MUL 0xfe00707f +#define MATCH_MULH 0x2001033 +#define MASK_MULH 0xfe00707f +#define MATCH_MULHSU 0x2002033 +#define MASK_MULHSU 0xfe00707f +#define MATCH_MULHU 0x2003033 +#define MASK_MULHU 0xfe00707f +#define MATCH_DIV 0x2004033 +#define MASK_DIV 0xfe00707f +#define MATCH_DIVU 0x2005033 +#define MASK_DIVU 0xfe00707f +#define MATCH_REM 0x2006033 +#define MASK_REM 0xfe00707f +#define MATCH_REMU 0x2007033 +#define MASK_REMU 0xfe00707f +#define MATCH_MULW 0x200003b +#define MASK_MULW 0xfe00707f +#define MATCH_DIVW 0x200403b +#define MASK_DIVW 0xfe00707f +#define MATCH_DIVUW 0x200503b +#define MASK_DIVUW 0xfe00707f +#define MATCH_REMW 0x200603b +#define MASK_REMW 0xfe00707f +#define MATCH_REMUW 0x200703b +#define MASK_REMUW 0xfe00707f +#define MATCH_AMOADD_W 0x202f +#define MASK_AMOADD_W 0xf800707f +#define MATCH_AMOXOR_W 0x2000202f +#define MASK_AMOXOR_W 0xf800707f +#define MATCH_AMOOR_W 0x4000202f +#define MASK_AMOOR_W 0xf800707f +#define MATCH_AMOAND_W 0x6000202f +#define MASK_AMOAND_W 0xf800707f +#define MATCH_AMOMIN_W 0x8000202f +#define MASK_AMOMIN_W 0xf800707f +#define MATCH_AMOMAX_W 0xa000202f +#define MASK_AMOMAX_W 0xf800707f +#define MATCH_AMOMINU_W 0xc000202f +#define MASK_AMOMINU_W 0xf800707f +#define MATCH_AMOMAXU_W 0xe000202f +#define MASK_AMOMAXU_W 0xf800707f +#define MATCH_AMOSWAP_W 0x800202f +#define MASK_AMOSWAP_W 0xf800707f +#define MATCH_LR_W 0x1000202f +#define MASK_LR_W 0xf9f0707f +#define MATCH_SC_W 0x1800202f +#define MASK_SC_W 0xf800707f +#define MATCH_AMOADD_D 0x302f +#define MASK_AMOADD_D 0xf800707f +#define MATCH_AMOXOR_D 0x2000302f +#define MASK_AMOXOR_D 0xf800707f +#define MATCH_AMOOR_D 0x4000302f +#define MASK_AMOOR_D 0xf800707f +#define MATCH_AMOAND_D 0x6000302f +#define MASK_AMOAND_D 0xf800707f +#define MATCH_AMOMIN_D 0x8000302f +#define MASK_AMOMIN_D 0xf800707f +#define MATCH_AMOMAX_D 0xa000302f +#define MASK_AMOMAX_D 0xf800707f +#define MATCH_AMOMINU_D 0xc000302f +#define MASK_AMOMINU_D 0xf800707f +#define MATCH_AMOMAXU_D 0xe000302f +#define MASK_AMOMAXU_D 0xf800707f +#define MATCH_AMOSWAP_D 0x800302f +#define MASK_AMOSWAP_D 0xf800707f +#define MATCH_LR_D 0x1000302f +#define MASK_LR_D 0xf9f0707f +#define MATCH_SC_D 0x1800302f +#define MASK_SC_D 0xf800707f +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff +#define MATCH_SRET 0x10200073 +#define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff +#define MATCH_SFENCE_VM 0x10400073 +#define MASK_SFENCE_VM 0xfff07fff +#define MATCH_WFI 0x10500073 +#define MASK_WFI 0xffffffff +#define MATCH_CSRRW 0x1073 +#define MASK_CSRRW 0x707f +#define MATCH_CSRRS 0x2073 +#define MASK_CSRRS 0x707f +#define MATCH_CSRRC 0x3073 +#define MASK_CSRRC 0x707f +#define MATCH_CSRRWI 0x5073 +#define MASK_CSRRWI 0x707f +#define MATCH_CSRRSI 0x6073 +#define MASK_CSRRSI 0x707f +#define MATCH_CSRRCI 0x7073 +#define MASK_CSRRCI 0x707f +#define MATCH_FADD_S 0x53 +#define MASK_FADD_S 0xfe00007f +#define MATCH_FSUB_S 0x8000053 +#define MASK_FSUB_S 0xfe00007f +#define MATCH_FMUL_S 0x10000053 +#define MASK_FMUL_S 0xfe00007f +#define MATCH_FDIV_S 0x18000053 +#define MASK_FDIV_S 0xfe00007f +#define MATCH_FSGNJ_S 0x20000053 +#define MASK_FSGNJ_S 0xfe00707f +#define MATCH_FSGNJN_S 0x20001053 +#define MASK_FSGNJN_S 0xfe00707f +#define MATCH_FSGNJX_S 0x20002053 +#define MASK_FSGNJX_S 0xfe00707f +#define MATCH_FMIN_S 0x28000053 +#define MASK_FMIN_S 0xfe00707f +#define MATCH_FMAX_S 0x28001053 +#define MASK_FMAX_S 0xfe00707f +#define MATCH_FSQRT_S 0x58000053 +#define MASK_FSQRT_S 0xfff0007f +#define MATCH_FADD_D 0x2000053 +#define MASK_FADD_D 0xfe00007f +#define MATCH_FSUB_D 0xa000053 +#define MASK_FSUB_D 0xfe00007f +#define MATCH_FMUL_D 0x12000053 +#define MASK_FMUL_D 0xfe00007f +#define MATCH_FDIV_D 0x1a000053 +#define MASK_FDIV_D 0xfe00007f +#define MATCH_FSGNJ_D 0x22000053 +#define MASK_FSGNJ_D 0xfe00707f +#define MATCH_FSGNJN_D 0x22001053 +#define MASK_FSGNJN_D 0xfe00707f +#define MATCH_FSGNJX_D 0x22002053 +#define MASK_FSGNJX_D 0xfe00707f +#define MATCH_FMIN_D 0x2a000053 +#define MASK_FMIN_D 0xfe00707f +#define MATCH_FMAX_D 0x2a001053 +#define MASK_FMAX_D 0xfe00707f +#define MATCH_FCVT_S_D 0x40100053 +#define MASK_FCVT_S_D 0xfff0007f +#define MATCH_FCVT_D_S 0x42000053 +#define MASK_FCVT_D_S 0xfff0007f +#define MATCH_FSQRT_D 0x5a000053 +#define MASK_FSQRT_D 0xfff0007f +#define MATCH_FLE_S 0xa0000053 +#define MASK_FLE_S 0xfe00707f +#define MATCH_FLT_S 0xa0001053 +#define MASK_FLT_S 0xfe00707f +#define MATCH_FEQ_S 0xa0002053 +#define MASK_FEQ_S 0xfe00707f +#define MATCH_FLE_D 0xa2000053 +#define MASK_FLE_D 0xfe00707f +#define MATCH_FLT_D 0xa2001053 +#define MASK_FLT_D 0xfe00707f +#define MATCH_FEQ_D 0xa2002053 +#define MASK_FEQ_D 0xfe00707f +#define MATCH_FCVT_W_S 0xc0000053 +#define MASK_FCVT_W_S 0xfff0007f +#define MATCH_FCVT_WU_S 0xc0100053 +#define MASK_FCVT_WU_S 0xfff0007f +#define MATCH_FCVT_L_S 0xc0200053 +#define MASK_FCVT_L_S 0xfff0007f +#define MATCH_FCVT_LU_S 0xc0300053 +#define MASK_FCVT_LU_S 0xfff0007f +#define MATCH_FMV_X_S 0xe0000053 +#define MASK_FMV_X_S 0xfff0707f +#define MATCH_FCLASS_S 0xe0001053 +#define MASK_FCLASS_S 0xfff0707f +#define MATCH_FCVT_W_D 0xc2000053 +#define MASK_FCVT_W_D 0xfff0007f +#define MATCH_FCVT_WU_D 0xc2100053 +#define MASK_FCVT_WU_D 0xfff0007f +#define MATCH_FCVT_L_D 0xc2200053 +#define MASK_FCVT_L_D 0xfff0007f +#define MATCH_FCVT_LU_D 0xc2300053 +#define MASK_FCVT_LU_D 0xfff0007f +#define MATCH_FMV_X_D 0xe2000053 +#define MASK_FMV_X_D 0xfff0707f +#define MATCH_FCLASS_D 0xe2001053 +#define MASK_FCLASS_D 0xfff0707f +#define MATCH_FCVT_S_W 0xd0000053 +#define MASK_FCVT_S_W 0xfff0007f +#define MATCH_FCVT_S_WU 0xd0100053 +#define MASK_FCVT_S_WU 0xfff0007f +#define MATCH_FCVT_S_L 0xd0200053 +#define MASK_FCVT_S_L 0xfff0007f +#define MATCH_FCVT_S_LU 0xd0300053 +#define MASK_FCVT_S_LU 0xfff0007f +#define MATCH_FMV_S_X 0xf0000053 +#define MASK_FMV_S_X 0xfff0707f +#define MATCH_FCVT_D_W 0xd2000053 +#define MASK_FCVT_D_W 0xfff0007f +#define MATCH_FCVT_D_WU 0xd2100053 +#define MASK_FCVT_D_WU 0xfff0007f +#define MATCH_FCVT_D_L 0xd2200053 +#define MASK_FCVT_D_L 0xfff0007f +#define MATCH_FCVT_D_LU 0xd2300053 +#define MASK_FCVT_D_LU 0xfff0007f +#define MATCH_FMV_D_X 0xf2000053 +#define MASK_FMV_D_X 0xfff0707f +#define MATCH_FLW 0x2007 +#define MASK_FLW 0x707f +#define MATCH_FLD 0x3007 +#define MASK_FLD 0x707f +#define MATCH_FSW 0x2027 +#define MASK_FSW 0x707f +#define MATCH_FSD 0x3027 +#define MASK_FSD 0x707f +#define MATCH_FMADD_S 0x43 +#define MASK_FMADD_S 0x600007f +#define MATCH_FMSUB_S 0x47 +#define MASK_FMSUB_S 0x600007f +#define MATCH_FNMSUB_S 0x4b +#define MASK_FNMSUB_S 0x600007f +#define MATCH_FNMADD_S 0x4f +#define MASK_FNMADD_S 0x600007f +#define MATCH_FMADD_D 0x2000043 +#define MASK_FMADD_D 0x600007f +#define MATCH_FMSUB_D 0x2000047 +#define MASK_FMSUB_D 0x600007f +#define MATCH_FNMSUB_D 0x200004b +#define MASK_FNMSUB_D 0x600007f +#define MATCH_FNMADD_D 0x200004f +#define MASK_FNMADD_D 0x600007f +#define MATCH_C_NOP 0x1 +#define MASK_C_NOP 0xffff +#define MATCH_C_ADDI16SP 0x6101 +#define MASK_C_ADDI16SP 0xef83 +#define MATCH_C_JR 0x8002 +#define MASK_C_JR 0xf07f +#define MATCH_C_JALR 0x9002 +#define MASK_C_JALR 0xf07f +#define MATCH_C_EBREAK 0x9002 +#define MASK_C_EBREAK 0xffff +#define MATCH_C_LD 0x6000 +#define MASK_C_LD 0xe003 +#define MATCH_C_SD 0xe000 +#define MASK_C_SD 0xe003 +#define MATCH_C_ADDIW 0x2001 +#define MASK_C_ADDIW 0xe003 +#define MATCH_C_LDSP 0x6002 +#define MASK_C_LDSP 0xe003 +#define MATCH_C_SDSP 0xe002 +#define MASK_C_SDSP 0xe003 +#define MATCH_C_ADDI4SPN 0x0 +#define MASK_C_ADDI4SPN 0xe003 +#define MATCH_C_FLD 0x2000 +#define MASK_C_FLD 0xe003 +#define MATCH_C_LW 0x4000 +#define MASK_C_LW 0xe003 +#define MATCH_C_FLW 0x6000 +#define MASK_C_FLW 0xe003 +#define MATCH_C_FSD 0xa000 +#define MASK_C_FSD 0xe003 +#define MATCH_C_SW 0xc000 +#define MASK_C_SW 0xe003 +#define MATCH_C_FSW 0xe000 +#define MASK_C_FSW 0xe003 +#define MATCH_C_ADDI 0x1 +#define MASK_C_ADDI 0xe003 +#define MATCH_C_JAL 0x2001 +#define MASK_C_JAL 0xe003 +#define MATCH_C_LI 0x4001 +#define MASK_C_LI 0xe003 +#define MATCH_C_LUI 0x6001 +#define MASK_C_LUI 0xe003 +#define MATCH_C_SRLI 0x8001 +#define MASK_C_SRLI 0xec03 +#define MATCH_C_SRAI 0x8401 +#define MASK_C_SRAI 0xec03 +#define MATCH_C_ANDI 0x8801 +#define MASK_C_ANDI 0xec03 +#define MATCH_C_SUB 0x8c01 +#define MASK_C_SUB 0xfc63 +#define MATCH_C_XOR 0x8c21 +#define MASK_C_XOR 0xfc63 +#define MATCH_C_OR 0x8c41 +#define MASK_C_OR 0xfc63 +#define MATCH_C_AND 0x8c61 +#define MASK_C_AND 0xfc63 +#define MATCH_C_SUBW 0x9c01 +#define MASK_C_SUBW 0xfc63 +#define MATCH_C_ADDW 0x9c21 +#define MASK_C_ADDW 0xfc63 +#define MATCH_C_J 0xa001 +#define MASK_C_J 0xe003 +#define MATCH_C_BEQZ 0xc001 +#define MASK_C_BEQZ 0xe003 +#define MATCH_C_BNEZ 0xe001 +#define MASK_C_BNEZ 0xe003 +#define MATCH_C_SLLI 0x2 +#define MASK_C_SLLI 0xe003 +#define MATCH_C_FLDSP 0x2002 +#define MASK_C_FLDSP 0xe003 +#define MATCH_C_LWSP 0x4002 +#define MASK_C_LWSP 0xe003 +#define MATCH_C_FLWSP 0x6002 +#define MASK_C_FLWSP 0xe003 +#define MATCH_C_MV 0x8002 +#define MASK_C_MV 0xf003 +#define MATCH_C_ADD 0x9002 +#define MASK_C_ADD 0xf003 +#define MATCH_C_FSDSP 0xa002 +#define MASK_C_FSDSP 0xe003 +#define MATCH_C_SWSP 0xc002 +#define MASK_C_SWSP 0xe003 +#define MATCH_C_FSWSP 0xe002 +#define MASK_C_FSWSP 0xe003 +#define MATCH_CUSTOM0 0xb +#define MASK_CUSTOM0 0x707f +#define MATCH_CUSTOM0_RS1 0x200b +#define MASK_CUSTOM0_RS1 0x707f +#define MATCH_CUSTOM0_RS1_RS2 0x300b +#define MASK_CUSTOM0_RS1_RS2 0x707f +#define MATCH_CUSTOM0_RD 0x400b +#define MASK_CUSTOM0_RD 0x707f +#define MATCH_CUSTOM0_RD_RS1 0x600b +#define MASK_CUSTOM0_RD_RS1 0x707f +#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b +#define MASK_CUSTOM0_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM1 0x2b +#define MASK_CUSTOM1 0x707f +#define MATCH_CUSTOM1_RS1 0x202b +#define MASK_CUSTOM1_RS1 0x707f +#define MATCH_CUSTOM1_RS1_RS2 0x302b +#define MASK_CUSTOM1_RS1_RS2 0x707f +#define MATCH_CUSTOM1_RD 0x402b +#define MASK_CUSTOM1_RD 0x707f +#define MATCH_CUSTOM1_RD_RS1 0x602b +#define MASK_CUSTOM1_RD_RS1 0x707f +#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b +#define MASK_CUSTOM1_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM2 0x5b +#define MASK_CUSTOM2 0x707f +#define MATCH_CUSTOM2_RS1 0x205b +#define MASK_CUSTOM2_RS1 0x707f +#define MATCH_CUSTOM2_RS1_RS2 0x305b +#define MASK_CUSTOM2_RS1_RS2 0x707f +#define MATCH_CUSTOM2_RD 0x405b +#define MASK_CUSTOM2_RD 0x707f +#define MATCH_CUSTOM2_RD_RS1 0x605b +#define MASK_CUSTOM2_RD_RS1 0x707f +#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b +#define MASK_CUSTOM2_RD_RS1_RS2 0x707f +#define MATCH_CUSTOM3 0x7b +#define MASK_CUSTOM3 0x707f +#define MATCH_CUSTOM3_RS1 0x207b +#define MASK_CUSTOM3_RS1 0x707f +#define MATCH_CUSTOM3_RS1_RS2 0x307b +#define MASK_CUSTOM3_RS1_RS2 0x707f +#define MATCH_CUSTOM3_RD 0x407b +#define MASK_CUSTOM3_RD 0x707f +#define MATCH_CUSTOM3_RD_RS1 0x607b +#define MASK_CUSTOM3_RD_RS1 0x707f +#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b +#define MASK_CUSTOM3_RD_RS1_RS2 0x707f +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#endif +#ifdef DECLARE_INSN +DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) +DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) +DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) +DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) +DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) +DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) +DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) +DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) +DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) +DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) +DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) +DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) +DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) +DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) +DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) +DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) +DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) +DECLARE_INSN(add, MATCH_ADD, MASK_ADD) +DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) +DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) +DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) +DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) +DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) +DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) +DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) +DECLARE_INSN(or, MATCH_OR, MASK_OR) +DECLARE_INSN(and, MATCH_AND, MASK_AND) +DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) +DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) +DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) +DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) +DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) +DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) +DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) +DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) +DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) +DECLARE_INSN(lb, MATCH_LB, MASK_LB) +DECLARE_INSN(lh, MATCH_LH, MASK_LH) +DECLARE_INSN(lw, MATCH_LW, MASK_LW) +DECLARE_INSN(ld, MATCH_LD, MASK_LD) +DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) +DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) +DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) +DECLARE_INSN(sb, MATCH_SB, MASK_SB) +DECLARE_INSN(sh, MATCH_SH, MASK_SH) +DECLARE_INSN(sw, MATCH_SW, MASK_SW) +DECLARE_INSN(sd, MATCH_SD, MASK_SD) +DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) +DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) +DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) +DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) +DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) +DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) +DECLARE_INSN(div, MATCH_DIV, MASK_DIV) +DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) +DECLARE_INSN(rem, MATCH_REM, MASK_REM) +DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) +DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) +DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) +DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) +DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) +DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) +DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) +DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) +DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) +DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) +DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) +DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) +DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) +DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) +DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) +DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) +DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) +DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) +DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) +DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) +DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) +DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) +DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) +DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) +DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) +DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) +DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) +DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) +DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) +DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) +DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) +DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) +DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) +DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) +DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) +DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) +DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) +DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) +DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) +DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) +DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) +DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) +DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) +DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) +DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) +DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) +DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) +DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) +DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) +DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) +DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) +DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) +DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) +DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) +DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) +DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) +DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) +DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) +DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) +DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) +DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) +DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) +DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) +DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) +DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) +DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) +DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) +DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) +DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) +DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) +DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) +DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) +DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) +DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) +DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) +DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) +DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) +DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) +DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) +DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) +DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) +DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) +DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) +DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) +DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) +DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) +DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) +DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) +DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) +DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) +DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) +DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) +DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) +DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) +DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) +DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) +DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) +DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) +DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) +DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) +DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) +DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) +DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) +DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) +DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) +DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) +DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) +DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) +DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) +DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) +DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) +DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) +DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) +DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) +DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) +DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) +DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) +DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) +DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) +DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) +DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) +DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) +DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) +DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) +DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) +DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) +DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) +DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) +DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) +DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) +DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) +DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) +DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) +DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) +DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) +DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) +DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) +DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) +DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) +DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) +DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) +DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) +DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) +DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) +DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) +DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) +DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) +DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) +DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) +DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) +DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) +DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) +DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) +DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) +DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) +DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) +DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) +DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) +DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) +DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) +DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) +DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) +DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) +DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) +DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) +#endif +#ifdef DECLARE_CSR +DECLARE_CSR(fflags, CSR_FFLAGS) +DECLARE_CSR(frm, CSR_FRM) +DECLARE_CSR(fcsr, CSR_FCSR) +DECLARE_CSR(cycle, CSR_CYCLE) +DECLARE_CSR(time, CSR_TIME) +DECLARE_CSR(instret, CSR_INSTRET) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) +DECLARE_CSR(sstatus, CSR_SSTATUS) +DECLARE_CSR(sie, CSR_SIE) +DECLARE_CSR(stvec, CSR_STVEC) +DECLARE_CSR(sscratch, CSR_SSCRATCH) +DECLARE_CSR(sepc, CSR_SEPC) +DECLARE_CSR(scause, CSR_SCAUSE) +DECLARE_CSR(sbadaddr, CSR_SBADADDR) +DECLARE_CSR(sip, CSR_SIP) +DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(mstatus, CSR_MSTATUS) +DECLARE_CSR(misa, CSR_MISA) +DECLARE_CSR(medeleg, CSR_MEDELEG) +DECLARE_CSR(mideleg, CSR_MIDELEG) +DECLARE_CSR(mie, CSR_MIE) +DECLARE_CSR(mtvec, CSR_MTVEC) +DECLARE_CSR(mscratch, CSR_MSCRATCH) +DECLARE_CSR(mepc, CSR_MEPC) +DECLARE_CSR(mcause, CSR_MCAUSE) +DECLARE_CSR(mbadaddr, CSR_MBADADDR) +DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(tselect, CSR_TSELECT) +DECLARE_CSR(tdata1, CSR_TDATA1) +DECLARE_CSR(tdata2, CSR_TDATA2) +DECLARE_CSR(tdata3, CSR_TDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(mcycle, CSR_MCYCLE) +DECLARE_CSR(minstret, CSR_MINSTRET) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) +DECLARE_CSR(mvendorid, CSR_MVENDORID) +DECLARE_CSR(marchid, CSR_MARCHID) +DECLARE_CSR(mimpid, CSR_MIMPID) +DECLARE_CSR(mhartid, CSR_MHARTID) +DECLARE_CSR(cycleh, CSR_CYCLEH) +DECLARE_CSR(timeh, CSR_TIMEH) +DECLARE_CSR(instreth, CSR_INSTRETH) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) +DECLARE_CSR(mcycleh, CSR_MCYCLEH) +DECLARE_CSR(minstreth, CSR_MINSTRETH) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) +#endif +#ifdef DECLARE_CAUSE +DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) +DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) +DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) +DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) +DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) +DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) +DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) +DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) +DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) +DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) +DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) +DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) +#endif diff --git a/raven/bsp/env/entry.S b/raven/bsp/env/entry.S new file mode 100644 index 0000000..1f5de24 --- /dev/null +++ b/raven/bsp/env/entry.S @@ -0,0 +1,97 @@ +// See LICENSE for license details + +#ifndef ENTRY_S +#define ENTRY_S + +#include "encoding.h" +#include "sifive/bits.h" + + .section .text.entry + .align 2 + .global trap_entry +trap_entry: + addi sp, sp, -32*REGBYTES + + STORE x1, 1*REGBYTES(sp) + STORE x2, 2*REGBYTES(sp) + STORE x3, 3*REGBYTES(sp) + STORE x4, 4*REGBYTES(sp) + STORE x5, 5*REGBYTES(sp) + STORE x6, 6*REGBYTES(sp) + STORE x7, 7*REGBYTES(sp) + STORE x8, 8*REGBYTES(sp) + STORE x9, 9*REGBYTES(sp) + STORE x10, 10*REGBYTES(sp) + STORE x11, 11*REGBYTES(sp) + STORE x12, 12*REGBYTES(sp) + STORE x13, 13*REGBYTES(sp) + STORE x14, 14*REGBYTES(sp) + STORE x15, 15*REGBYTES(sp) + STORE x16, 16*REGBYTES(sp) + STORE x17, 17*REGBYTES(sp) + STORE x18, 18*REGBYTES(sp) + STORE x19, 19*REGBYTES(sp) + STORE x20, 20*REGBYTES(sp) + STORE x21, 21*REGBYTES(sp) + STORE x22, 22*REGBYTES(sp) + STORE x23, 23*REGBYTES(sp) + STORE x24, 24*REGBYTES(sp) + STORE x25, 25*REGBYTES(sp) + STORE x26, 26*REGBYTES(sp) + STORE x27, 27*REGBYTES(sp) + STORE x28, 28*REGBYTES(sp) + STORE x29, 29*REGBYTES(sp) + STORE x30, 30*REGBYTES(sp) + STORE x31, 31*REGBYTES(sp) + + csrr a0, mcause + csrr a1, mepc + mv a2, sp + call handle_trap + csrw mepc, a0 + + # Remain in M-mode after mret + li t0, MSTATUS_MPP + csrs mstatus, t0 + + LOAD x1, 1*REGBYTES(sp) + LOAD x2, 2*REGBYTES(sp) + LOAD x3, 3*REGBYTES(sp) + LOAD x4, 4*REGBYTES(sp) + LOAD x5, 5*REGBYTES(sp) + LOAD x6, 6*REGBYTES(sp) + LOAD x7, 7*REGBYTES(sp) + LOAD x8, 8*REGBYTES(sp) + LOAD x9, 9*REGBYTES(sp) + LOAD x10, 10*REGBYTES(sp) + LOAD x11, 11*REGBYTES(sp) + LOAD x12, 12*REGBYTES(sp) + LOAD x13, 13*REGBYTES(sp) + LOAD x14, 14*REGBYTES(sp) + LOAD x15, 15*REGBYTES(sp) + LOAD x16, 16*REGBYTES(sp) + LOAD x17, 17*REGBYTES(sp) + LOAD x18, 18*REGBYTES(sp) + LOAD x19, 19*REGBYTES(sp) + LOAD x20, 20*REGBYTES(sp) + LOAD x21, 21*REGBYTES(sp) + LOAD x22, 22*REGBYTES(sp) + LOAD x23, 23*REGBYTES(sp) + LOAD x24, 24*REGBYTES(sp) + LOAD x25, 25*REGBYTES(sp) + LOAD x26, 26*REGBYTES(sp) + LOAD x27, 27*REGBYTES(sp) + LOAD x28, 28*REGBYTES(sp) + LOAD x29, 29*REGBYTES(sp) + LOAD x30, 30*REGBYTES(sp) + LOAD x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES + mret + +.weak handle_trap +handle_trap: +1: + j 1b + +#endif diff --git a/raven/bsp/env/freedom-e300-arty/init.c b/raven/bsp/env/freedom-e300-arty/init.c new file mode 100644 index 0000000..a6f4b39 --- /dev/null +++ b/raven/bsp/env/freedom-e300-arty/init.c @@ -0,0 +1,87 @@ +//See LICENSE for license details. +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long get_cpu_freq() +{ + return 65000000; +} + +unsigned long get_timer_freq() +{ + return get_cpu_freq(); +} + +uint64_t get_timer_value() +{ +#if __riscv_xlen == 32 + while (1) { + uint32_t hi = read_csr(mcycleh); + uint32_t lo = read_csr(mcycle); + if (hi == read_csr(mcycleh)) + return ((uint64_t)hi << 32) | lo; + } +#else + return read_csr(mcycle); +#endif +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "Unhandled Trap:\n", 16); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + #ifndef NO_INIT + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + #endif +} + +void _fini() +{ +} diff --git a/raven/bsp/env/freedom-e300-arty/link.lds b/raven/bsp/env/freedom-e300-arty/link.lds new file mode 100644 index 0000000..90e5c8f --- /dev/null +++ b/raven/bsp/env/freedom-e300-arty/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/freedom-e300-arty/openocd.cfg b/raven/bsp/env/freedom-e300-arty/openocd.cfg new file mode 100644 index 0000000..f4b28ed --- /dev/null +++ b/raven/bsp/env/freedom-e300-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off diff --git a/raven/bsp/env/freedom-e300-arty/platform.h b/raven/bsp/env/freedom-e300-arty/platform.h new file mode 100644 index 0000000..d5d6dda --- /dev/null +++ b/raven/bsp/env/freedom-e300-arty/platform.h @@ -0,0 +1,125 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF Mappings +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt Numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#define HAS_BOARD_BUTTONS +#include "hifive1.h" + +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/raven/bsp/env/freedom-e300-hifive1/init.c b/raven/bsp/env/freedom-e300-hifive1/init.c new file mode 100644 index 0000000..de046cc --- /dev/null +++ b/raven/bsp/env/freedom-e300-hifive1/init.c @@ -0,0 +1,238 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long mtime_lo(void) +{ + return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); +} + +#ifdef __riscv32 + +static uint32_t mtime_hi(void) +{ + return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); +} + +uint64_t get_timer_value() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + if (hi == mtime_hi()) + return ((uint64_t)hi << 32) | lo; + } +} + +#else /* __riscv32 */ + +uint64_t get_timer_value() +{ + return mtime_lo(); +} + +#endif + +unsigned long get_timer_freq() +{ + return 32768; +} + +static void use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ; + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +static void use_pll(int refsel, int bypass, int r, int f, int q) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if available. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + // In case we are executing from QSPI, + // (which is quite likely) we need to + // set the QSPI clock divider appropriately + // before boosting the clock frequency. + + // Div = f_sck/2 + SPI0_REG(SPI_REG_SCKDIV) = 8; + + // Set DIV Settings for PLL + // Both HFROSC and HFXOSC are modeled as ideal + // 16MHz sources (assuming dividers are set properly for + // HFROSC). + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = mtime_lo(); + while (mtime_lo() - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ; + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); +} + +static void use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + use_hfrosc(4, 16); +} + +static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n) +{ + unsigned long start_mtime, delta_mtime; + unsigned long mtime_freq = get_timer_freq(); + + // Don't start measuruing until we see an mtime tick + unsigned long tmp = mtime_lo(); + do { + start_mtime = mtime_lo(); + } while (start_mtime == tmp); + + unsigned long start_mcycle = read_csr(mcycle); + + do { + delta_mtime = mtime_lo() - start_mtime; + } while (delta_mtime < n); + + unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle; + + return (delta_mcycle / delta_mtime) * mtime_freq + + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; +} + +unsigned long get_cpu_freq() +{ + static uint32_t cpu_freq; + + if (!cpu_freq) { + // warm up I$ + measure_cpu_freq(1); + // measure for real + cpu_freq = measure_cpu_freq(10); + } + + return cpu_freq; +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "trap\n", 5); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + + #ifndef NO_INIT + use_default_clocks(); + use_pll(0, 0, 1, 31, 1); + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present + write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping + write_csr(fcsr, 0); // initialize rounding mode, undefined at reset + } + #endif + +} + +void _fini() +{ +} diff --git a/raven/bsp/env/freedom-e300-hifive1/link.lds b/raven/bsp/env/freedom-e300-hifive1/link.lds new file mode 100644 index 0000000..90e5c8f --- /dev/null +++ b/raven/bsp/env/freedom-e300-hifive1/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/freedom-e300-hifive1/openocd.cfg b/raven/bsp/env/freedom-e300-hifive1/openocd.cfg new file mode 100644 index 0000000..b531e9c --- /dev/null +++ b/raven/bsp/env/freedom-e300-hifive1/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +#flash protect 0 64 last off diff --git a/raven/bsp/env/freedom-e300-hifive1/platform.h b/raven/bsp/env/freedom-e300-hifive1/platform.h new file mode 100644 index 0000000..63efc9e --- /dev/null +++ b/raven/bsp/env/freedom-e300-hifive1/platform.h @@ -0,0 +1,133 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/otp.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/prci.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define MASKROM_BASE_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define OTP_MMAP_ADDR _AC(0x00020000,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define PRCI_BASE_ADDR _AC(0x10008000,UL) +#define OTP_BASE_ADDR _AC(0x10010000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF masks +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +//#define IOF0_I2C_MASK _AC(0x00003000,UL) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#include "hifive1.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/raven/bsp/env/hifive1.h b/raven/bsp/env/hifive1.h new file mode 100644 index 0000000..cfd7099 --- /dev/null +++ b/raven/bsp/env/hifive1.h @@ -0,0 +1,79 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_HIFIVE1_H +#define _SIFIVE_HIFIVE1_H + +#include + +/**************************************************************************** + * GPIO Connections + *****************************************************************************/ + +// These are the GPIO bit offsets for the RGB LED on HiFive1 Board. +// These are also mapped to RGB LEDs on the Freedom E300 Arty +// FPGA +// Dev Kit. + +#define RED_LED_OFFSET 22 +#define GREEN_LED_OFFSET 19 +#define BLUE_LED_OFFSET 21 + +// These are the GPIO bit offsets for the differen digital pins +// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit. +#define PIN_0_OFFSET 16 +#define PIN_1_OFFSET 17 +#define PIN_2_OFFSET 18 +#define PIN_3_OFFSET 19 +#define PIN_4_OFFSET 20 +#define PIN_5_OFFSET 21 +#define PIN_6_OFFSET 22 +#define PIN_7_OFFSET 23 +#define PIN_8_OFFSET 0 +#define PIN_9_OFFSET 1 +#define PIN_10_OFFSET 2 +#define PIN_11_OFFSET 3 +#define PIN_12_OFFSET 4 +#define PIN_13_OFFSET 5 +//#define PIN_14_OFFSET 8 //This pin is not connected on either board. +#define PIN_15_OFFSET 9 +#define PIN_16_OFFSET 10 +#define PIN_17_OFFSET 11 +#define PIN_18_OFFSET 12 +#define PIN_19_OFFSET 13 + +// These are *PIN* numbers, not +// GPIO Offset Numbers. +#define PIN_SPI1_SCK (13u) +#define PIN_SPI1_MISO (12u) +#define PIN_SPI1_MOSI (11u) +#define PIN_SPI1_SS0 (10u) +#define PIN_SPI1_SS1 (14u) +#define PIN_SPI1_SS2 (15u) +#define PIN_SPI1_SS3 (16u) + +#define SS_PIN_TO_CS_ID(x) \ + ((x==PIN_SPI1_SS0 ? 0 : \ + (x==PIN_SPI1_SS1 ? 1 : \ + (x==PIN_SPI1_SS2 ? 2 : \ + (x==PIN_SPI1_SS3 ? 3 : \ + -1))))) + + +// These buttons are present only on the Freedom E300 Arty Dev Kit. +#ifdef HAS_BOARD_BUTTONS +#define BUTTON_0_OFFSET 15 +#define BUTTON_1_OFFSET 30 +#define BUTTON_2_OFFSET 31 + +#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET) +#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET) +#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET) + +#endif + +#define HAS_HFXOSC 1 +#define HAS_LFROSC_BYPASS 1 + +#define RTC_FREQ 32768 + +#endif /* _SIFIVE_HIFIVE1_H */ diff --git a/raven/bsp/env/iss/init.c b/raven/bsp/env/iss/init.c new file mode 100644 index 0000000..de046cc --- /dev/null +++ b/raven/bsp/env/iss/init.c @@ -0,0 +1,238 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long mtime_lo(void) +{ + return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); +} + +#ifdef __riscv32 + +static uint32_t mtime_hi(void) +{ + return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); +} + +uint64_t get_timer_value() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + if (hi == mtime_hi()) + return ((uint64_t)hi << 32) | lo; + } +} + +#else /* __riscv32 */ + +uint64_t get_timer_value() +{ + return mtime_lo(); +} + +#endif + +unsigned long get_timer_freq() +{ + return 32768; +} + +static void use_hfrosc(int div, int trim) +{ + // Make sure the HFROSC is running at its default setting + PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); + while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ; + PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); +} + +static void use_pll(int refsel, int bypass, int r, int f, int q) +{ + // Ensure that we aren't running off the PLL before we mess with it. + if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { + // Make sure the HFROSC is running at its default setting + use_hfrosc(4, 16); + } + + // Set PLL Source to be HFXOSC if available. + uint32_t config_value = 0; + + config_value |= PLL_REFSEL(refsel); + + if (bypass) { + // Bypass + config_value |= PLL_BYPASS(1); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // If we don't have an HFXTAL, this doesn't really matter. + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + } else { + // In case we are executing from QSPI, + // (which is quite likely) we need to + // set the QSPI clock divider appropriately + // before boosting the clock frequency. + + // Div = f_sck/2 + SPI0_REG(SPI_REG_SCKDIV) = 8; + + // Set DIV Settings for PLL + // Both HFROSC and HFXOSC are modeled as ideal + // 16MHz sources (assuming dividers are set properly for + // HFROSC). + // (Legal values of f_REF are 6-48MHz) + + // Set DIVR to divide-by-2 to get 8MHz frequency + // (legal values of f_R are 6-12 MHz) + + config_value |= PLL_BYPASS(1); + config_value |= PLL_R(r); + + // Set DIVF to get 512Mhz frequncy + // There is an implied multiply-by-2, 16Mhz. + // So need to write 32-1 + // (legal values of f_F are 384-768 MHz) + config_value |= PLL_F(f); + + // Set DIVQ to divide-by-2 to get 256 MHz frequency + // (legal values of f_Q are 50-400Mhz) + config_value |= PLL_Q(q); + + // Set our Final output divide to divide-by-1: + PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); + + PRCI_REG(PRCI_PLLCFG) = config_value; + + // Un-Bypass the PLL. + PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); + + // Wait for PLL Lock + // Note that the Lock signal can be glitchy. + // Need to wait 100 us + // RTC is running at 32kHz. + // So wait 4 ticks of RTC. + uint32_t now = mtime_lo(); + while (mtime_lo() - now < 4) ; + + // Now it is safe to check for PLL Lock + while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ; + } + + // Switch over to PLL Clock source + PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); +} + +static void use_default_clocks() +{ + // Turn off the LFROSC + AON_REG(AON_LFROSC) &= ~ROSC_EN(1); + + // Use HFROSC + use_hfrosc(4, 16); +} + +static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n) +{ + unsigned long start_mtime, delta_mtime; + unsigned long mtime_freq = get_timer_freq(); + + // Don't start measuruing until we see an mtime tick + unsigned long tmp = mtime_lo(); + do { + start_mtime = mtime_lo(); + } while (start_mtime == tmp); + + unsigned long start_mcycle = read_csr(mcycle); + + do { + delta_mtime = mtime_lo() - start_mtime; + } while (delta_mtime < n); + + unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle; + + return (delta_mcycle / delta_mtime) * mtime_freq + + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; +} + +unsigned long get_cpu_freq() +{ + static uint32_t cpu_freq; + + if (!cpu_freq) { + // warm up I$ + measure_cpu_freq(1); + // measure for real + cpu_freq = measure_cpu_freq(10); + } + + return cpu_freq; +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "trap\n", 5); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + + #ifndef NO_INIT + use_default_clocks(); + use_pll(0, 0, 1, 31, 1); + uart_init(115200); + + printf("core freq at %d Hz\n", get_cpu_freq()); + + write_csr(mtvec, &trap_entry); + if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present + write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping + write_csr(fcsr, 0); // initialize rounding mode, undefined at reset + } + #endif + +} + +void _fini() +{ +} diff --git a/raven/bsp/env/iss/link.lds b/raven/bsp/env/iss/link.lds new file mode 100644 index 0000000..bc60026 --- /dev/null +++ b/raven/bsp/env/iss/link.lds @@ -0,0 +1,168 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + /*flash (rxai!w) : ORIGIN = 0x00000000, LENGTH = 1M*/ + flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/iss/openocd.cfg b/raven/bsp/env/iss/openocd.cfg new file mode 100644 index 0000000..b531e9c --- /dev/null +++ b/raven/bsp/env/iss/openocd.cfg @@ -0,0 +1,34 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +halt +#flash protect 0 64 last off diff --git a/raven/bsp/env/iss/platform.h b/raven/bsp/env/iss/platform.h new file mode 100644 index 0000000..63efc9e --- /dev/null +++ b/raven/bsp/env/iss/platform.h @@ -0,0 +1,133 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "sifive/const.h" +#include "sifive/devices/aon.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/otp.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/prci.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define MASKROM_BASE_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define OTP_MMAP_ADDR _AC(0x00020000,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define PRCI_BASE_ADDR _AC(0x10008000,UL) +#define OTP_BASE_ADDR _AC(0x10010000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF masks +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +//#define IOF0_I2C_MASK _AC(0x00003000,UL) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + +#define NUM_GPIO 32 + +#define PLIC_NUM_INTERRUPTS 52 +#define PLIC_NUM_PRIORITIES 7 + +#include "hifive1.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/raven/bsp/env/start.S b/raven/bsp/env/start.S new file mode 100644 index 0000000..b526411 --- /dev/null +++ b/raven/bsp/env/start.S @@ -0,0 +1,54 @@ +// See LICENSE for license details. + + .section .init + .globl _start + .type _start,@function + +_start: + la gp, _gp + la sp, _sp + + /* Load data section */ + la a0, _data_lma + la a1, _data + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: + + /* Clear bss section */ + la a0, __bss_start + la a1, _end + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: + + /* Call global constructors */ + la a0, __libc_fini_array + call atexit + call __libc_init_array + +#ifndef __riscv_float_abi_soft + /* Enable FPU */ + li t0, MSTATUS_FS + csrs mstatus, t0 + csrr t1, mstatus + and t1, t1, t0 + beqz t1, 1f + fssr x0 +1: +#endif + + /* argc = argv = 0 */ + li a0, 0 + li a1, 0 + call main + tail exit diff --git a/raven/bsp/include/sifive/bits.h b/raven/bsp/include/sifive/bits.h new file mode 100644 index 0000000..e550f80 --- /dev/null +++ b/raven/bsp/include/sifive/bits.h @@ -0,0 +1,35 @@ +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#ifdef __riscv64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/raven/bsp/include/sifive/const.h b/raven/bsp/include/sifive/const.h new file mode 100644 index 0000000..3e0a681 --- /dev/null +++ b/raven/bsp/include/sifive/const.h @@ -0,0 +1,17 @@ +/* Derived from */ + +#ifndef _SIFIVE_CONST_H +#define _SIFIVE_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _SIFIVE_CONST_H */ diff --git a/raven/bsp/include/sifive/devices/aon.h b/raven/bsp/include/sifive/devices/aon.h new file mode 100644 index 0000000..63f1db3 --- /dev/null +++ b/raven/bsp/include/sifive/devices/aon.h @@ -0,0 +1,88 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_AON_H +#define _SIFIVE_AON_H + +/* Register offsets */ + +#define AON_WDOGCFG 0x000 +#define AON_WDOGCOUNT 0x008 +#define AON_WDOGS 0x010 +#define AON_WDOGFEED 0x018 +#define AON_WDOGKEY 0x01C +#define AON_WDOGCMP 0x020 + +#define AON_RTCCFG 0x040 +#define AON_RTCLO 0x048 +#define AON_RTCHI 0x04C +#define AON_RTCS 0x050 +#define AON_RTCCMP 0x060 + +#define AON_BACKUP0 0x080 +#define AON_BACKUP1 0x084 +#define AON_BACKUP2 0x088 +#define AON_BACKUP3 0x08C +#define AON_BACKUP4 0x090 +#define AON_BACKUP5 0x094 +#define AON_BACKUP6 0x098 +#define AON_BACKUP7 0x09C +#define AON_BACKUP8 0x0A0 +#define AON_BACKUP9 0x0A4 +#define AON_BACKUP10 0x0A8 +#define AON_BACKUP11 0x0AC +#define AON_BACKUP12 0x0B0 +#define AON_BACKUP13 0x0B4 +#define AON_BACKUP14 0x0B8 +#define AON_BACKUP15 0x0BC + +#define AON_PMUWAKEUPI0 0x100 +#define AON_PMUWAKEUPI1 0x104 +#define AON_PMUWAKEUPI2 0x108 +#define AON_PMUWAKEUPI3 0x10C +#define AON_PMUWAKEUPI4 0x110 +#define AON_PMUWAKEUPI5 0x114 +#define AON_PMUWAKEUPI6 0x118 +#define AON_PMUWAKEUPI7 0x11C +#define AON_PMUSLEEPI0 0x120 +#define AON_PMUSLEEPI1 0x124 +#define AON_PMUSLEEPI2 0x128 +#define AON_PMUSLEEPI3 0x12C +#define AON_PMUSLEEPI4 0x130 +#define AON_PMUSLEEPI5 0x134 +#define AON_PMUSLEEPI6 0x138 +#define AON_PMUSLEEPI7 0x13C +#define AON_PMUIE 0x140 +#define AON_PMUCAUSE 0x144 +#define AON_PMUSLEEP 0x148 +#define AON_PMUKEY 0x14C + +#define AON_LFROSC 0x070 +/* Constants */ + +#define AON_WDOGKEY_VALUE 0x51F15E +#define AON_WDOGFEED_VALUE 0xD09F00D + +#define AON_WDOGCFG_SCALE 0x0000000F +#define AON_WDOGCFG_RSTEN 0x00000100 +#define AON_WDOGCFG_ZEROCMP 0x00000200 +#define AON_WDOGCFG_ENALWAYS 0x00001000 +#define AON_WDOGCFG_ENCOREAWAKE 0x00002000 +#define AON_WDOGCFG_CMPIP 0x10000000 + +#define AON_RTCCFG_SCALE 0x0000000F +#define AON_RTCCFG_ENALWAYS 0x00001000 +#define AON_RTCCFG_CMPIP 0x10000000 + +#define AON_WAKEUPCAUSE_RESET 0x00 +#define AON_WAKEUPCAUSE_RTC 0x01 +#define AON_WAKEUPCAUSE_DWAKEUP 0x02 +#define AON_WAKEUPCAUSE_AWAKEUP 0x03 + +#define AON_RESETCAUSE_POWERON 0x0000 +#define AON_RESETCAUSE_EXTERNAL 0x0100 +#define AON_RESETCAUSE_WATCHDOG 0x0200 + +#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF +#define AON_PMUCAUSE_RESETCAUSE 0xFF00 + +#endif /* _SIFIVE_AON_H */ diff --git a/raven/bsp/include/sifive/devices/clint.h b/raven/bsp/include/sifive/devices/clint.h new file mode 100644 index 0000000..cd3e0c7 --- /dev/null +++ b/raven/bsp/include/sifive/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE for license details + +#ifndef _SIFIVE_CLINT_H +#define _SIFIVE_CLINT_H + + +#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8 + +#endif /* _SIFIVE_CLINT_H */ diff --git a/raven/bsp/include/sifive/devices/gpio.h b/raven/bsp/include/sifive/devices/gpio.h new file mode 100644 index 0000000..f7f0acb --- /dev/null +++ b/raven/bsp/include/sifive/devices/gpio.h @@ -0,0 +1,24 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_GPIO_H +#define _SIFIVE_GPIO_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#endif /* _SIFIVE_GPIO_H */ diff --git a/raven/bsp/include/sifive/devices/otp.h b/raven/bsp/include/sifive/devices/otp.h new file mode 100644 index 0000000..93833e2 --- /dev/null +++ b/raven/bsp/include/sifive/devices/otp.h @@ -0,0 +1,23 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_OTP_H +#define _SIFIVE_OTP_H + +/* Register offsets */ + +#define OTP_LOCK 0x00 +#define OTP_CK 0x04 +#define OTP_OE 0x08 +#define OTP_SEL 0x0C +#define OTP_WE 0x10 +#define OTP_MR 0x14 +#define OTP_MRR 0x18 +#define OTP_MPP 0x1C +#define OTP_VRREN 0x20 +#define OTP_VPPEN 0x24 +#define OTP_A 0x28 +#define OTP_D 0x2C +#define OTP_Q 0x30 +#define OTP_READ_TIMINGS 0x34 + +#endif diff --git a/raven/bsp/include/sifive/devices/plic.h b/raven/bsp/include/sifive/devices/plic.h new file mode 100644 index 0000000..e1ca5d6 --- /dev/null +++ b/raven/bsp/include/sifive/devices/plic.h @@ -0,0 +1,31 @@ +// See LICENSE for license details. + +#ifndef PLIC_H +#define PLIC_H + +#include + +// 32 bits per source +#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 +// 1 bit per source (1 address) +#define PLIC_PENDING_OFFSET _AC(0x1000,UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +//0x80 per target +#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + + +#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) +#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#define PLIC_MAX_SOURCE 1023 +#define PLIC_SOURCE_MASK 0x3FF + +#define PLIC_MAX_TARGET 15871 +#define PLIC_TARGET_MASK 0x3FFF + +#endif /* PLIC_H */ diff --git a/raven/bsp/include/sifive/devices/prci.h b/raven/bsp/include/sifive/devices/prci.h new file mode 100644 index 0000000..1a3de58 --- /dev/null +++ b/raven/bsp/include/sifive/devices/prci.h @@ -0,0 +1,56 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PRCI_H +#define _SIFIVE_PRCI_H + +/* Register offsets */ + +#define PRCI_HFROSCCFG (0x0000) +#define PRCI_HFXOSCCFG (0x0004) +#define PRCI_PLLCFG (0x0008) +#define PRCI_PLLDIV (0x000C) +#define PRCI_PROCMONCFG (0x00F0) + +/* Fields */ +#define ROSC_DIV(x) (((x) & 0x2F) << 0 ) +#define ROSC_TRIM(x) (((x) & 0x1F) << 16) +#define ROSC_EN(x) (((x) & 0x1 ) << 30) +#define ROSC_RDY(x) (((x) & 0x1 ) << 31) + +#define XOSC_EN(x) (((x) & 0x1) << 30) +#define XOSC_RDY(x) (((x) & 0x1) << 31) + +#define PLL_R(x) (((x) & 0x7) << 0) +// single reserved bit for F LSB. +#define PLL_F(x) (((x) & 0x3F) << 4) +#define PLL_Q(x) (((x) & 0x3) << 10) +#define PLL_SEL(x) (((x) & 0x1) << 16) +#define PLL_REFSEL(x) (((x) & 0x1) << 17) +#define PLL_BYPASS(x) (((x) & 0x1) << 18) +#define PLL_LOCK(x) (((x) & 0x1) << 31) + +#define PLL_R_default 0x1 +#define PLL_F_default 0x1F +#define PLL_Q_default 0x3 + +#define PLL_REFSEL_HFROSC 0x0 +#define PLL_REFSEL_HFXOSC 0x1 + +#define PLL_SEL_HFROSC 0x0 +#define PLL_SEL_PLL 0x1 + +#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0) +#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8) + +#define PROCMON_DIV(x) (((x) & 0x1F) << 0) +#define PROCMON_TRIM(x) (((x) & 0x1F) << 8) +#define PROCMON_EN(x) (((x) & 0x1) << 16) +#define PROCMON_SEL(x) (((x) & 0x3) << 24) +#define PROCMON_NT_EN(x) (((x) & 0x1) << 28) + +#define PROCMON_SEL_HFCLK 0 +#define PROCMON_SEL_HFXOSCIN 1 +#define PROCMON_SEL_PLLOUTDIV 2 +#define PROCMON_SEL_PROCMON 3 + +#endif // _SIFIVE_PRCI_H diff --git a/raven/bsp/include/sifive/devices/pwm.h b/raven/bsp/include/sifive/devices/pwm.h new file mode 100644 index 0000000..067889a --- /dev/null +++ b/raven/bsp/include/sifive/devices/pwm.h @@ -0,0 +1,37 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PWM_H +#define _SIFIVE_PWM_H + +/* Register offsets */ + +#define PWM_CFG 0x00 +#define PWM_COUNT 0x08 +#define PWM_S 0x10 +#define PWM_CMP0 0x20 +#define PWM_CMP1 0x24 +#define PWM_CMP2 0x28 +#define PWM_CMP3 0x2C + +/* Constants */ + +#define PWM_CFG_SCALE 0x0000000F +#define PWM_CFG_STICKY 0x00000100 +#define PWM_CFG_ZEROCMP 0x00000200 +#define PWM_CFG_DEGLITCH 0x00000400 +#define PWM_CFG_ENALWAYS 0x00001000 +#define PWM_CFG_ONESHOT 0x00002000 +#define PWM_CFG_CMP0CENTER 0x00010000 +#define PWM_CFG_CMP1CENTER 0x00020000 +#define PWM_CFG_CMP2CENTER 0x00040000 +#define PWM_CFG_CMP3CENTER 0x00080000 +#define PWM_CFG_CMP0GANG 0x01000000 +#define PWM_CFG_CMP1GANG 0x02000000 +#define PWM_CFG_CMP2GANG 0x04000000 +#define PWM_CFG_CMP3GANG 0x08000000 +#define PWM_CFG_CMP0IP 0x10000000 +#define PWM_CFG_CMP1IP 0x20000000 +#define PWM_CFG_CMP2IP 0x40000000 +#define PWM_CFG_CMP3IP 0x80000000 + +#endif /* _SIFIVE_PWM_H */ diff --git a/raven/bsp/include/sifive/devices/spi.h b/raven/bsp/include/sifive/devices/spi.h new file mode 100644 index 0000000..916d86b --- /dev/null +++ b/raven/bsp/include/sifive/devices/spi.h @@ -0,0 +1,80 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_SPI_H +#define _SIFIVE_SPI_H + +/* Register offsets */ + +#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18 + +#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e + +#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54 + +#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64 + +#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74 + +/* Fields */ + +#define SPI_SCK_POL 0x1 +#define SPI_SCK_PHA 0x2 + +#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) + +/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff) + +#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2 + +#define SPI_FCTRL_EN 0x1 + +#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) +#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) + +#define SPI_TXFIFO_FULL (1 << 31) +#define SPI_RXFIFO_EMPTY (1 << 31) + +/* Values */ + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + + +#endif /* _SIFIVE_SPI_H */ diff --git a/raven/bsp/include/sifive/devices/uart.h b/raven/bsp/include/sifive/devices/uart.h new file mode 100644 index 0000000..71bea6f --- /dev/null +++ b/raven/bsp/include/sifive/devices/uart.h @@ -0,0 +1,27 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ diff --git a/raven/bsp/include/sifive/sections.h b/raven/bsp/include/sifive/sections.h new file mode 100644 index 0000000..848c237 --- /dev/null +++ b/raven/bsp/include/sifive/sections.h @@ -0,0 +1,16 @@ +#ifndef _SECTIONS_H +#define _SECTIONS_H + +extern unsigned char _rom[]; +extern unsigned char _rom_end[]; + +extern unsigned char _ram[]; +extern unsigned char _ram_end[]; + +extern unsigned char _ftext[]; +extern unsigned char _etext[]; +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; +extern unsigned char _end[]; + +#endif /* _SECTIONS_H */ diff --git a/raven/bsp/libwrap/libwrap.mk b/raven/bsp/libwrap/libwrap.mk new file mode 100644 index 0000000..add3285 --- /dev/null +++ b/raven/bsp/libwrap/libwrap.mk @@ -0,0 +1,53 @@ +# See LICENSE for license details. + +ifndef _SIFIVE_MK_LIBWRAP +_SIFIVE_MK_LIBWRAP := # defined + +LIBWRAP_DIR := $(dir $(lastword $(MAKEFILE_LIST))) +LIBWRAP_DIR := $(LIBWRAP_DIR:/=) + +LIBWRAP_SRCS := \ + stdlib/malloc.c \ + sys/open.c \ + sys/lseek.c \ + sys/read.c \ + sys/write.c \ + sys/fstat.c \ + sys/stat.c \ + sys/close.c \ + sys/link.c \ + sys/unlink.c \ + sys/execve.c \ + sys/fork.c \ + sys/getpid.c \ + sys/kill.c \ + sys/wait.c \ + sys/isatty.c \ + sys/times.c \ + sys/sbrk.c \ + sys/_exit.c + +LIBWRAP_SRCS := $(foreach f,$(LIBWRAP_SRCS),$(LIBWRAP_DIR)/$(f)) +LIBWRAP_OBJS := $(LIBWRAP_SRCS:.c=.o) + +LIBWRAP_SYMS := malloc free \ + open lseek read write fstat stat close link unlink \ + execve fork getpid kill wait \ + isatty times sbrk _exit + +LIBWRAP := libwrap.a + +LINK_DEPS += $(LIBWRAP) + +LDFLAGS += $(foreach s,$(LIBWRAP_SYMS),-Wl,--wrap=$(s)) +LDFLAGS += -L. -Wl,--start-group -lwrap -lc -Wl,--end-group + +CLEAN_OBJS += $(LIBWRAP_OBJS) + +$(LIBWRAP_OBJS): %.o: %.c $(HEADERS) + $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< + +$(LIBWRAP): $(LIBWRAP_OBJS) + $(AR) rcs $@ $^ + +endif # _SIFIVE_MK_LIBWRAP diff --git a/raven/bsp/libwrap/stdlib/malloc.c b/raven/bsp/libwrap/stdlib/malloc.c new file mode 100644 index 0000000..8f4f432 --- /dev/null +++ b/raven/bsp/libwrap/stdlib/malloc.c @@ -0,0 +1,17 @@ +/* See LICENSE for license details. */ + +/* These functions are intended for embedded RV32 systems and are + obviously incorrect in general. */ + +void* __wrap_malloc(unsigned long sz) +{ + extern void* sbrk(long); + void* res = sbrk(sz); + if ((long)res == -1) + return 0; + return res; +} + +void __wrap_free(void* ptr) +{ +} diff --git a/raven/bsp/libwrap/sys/_exit.c b/raven/bsp/libwrap/sys/_exit.c new file mode 100644 index 0000000..ceb0b82 --- /dev/null +++ b/raven/bsp/libwrap/sys/_exit.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ + +#include +#include "platform.h" + +void __wrap__exit(int code) +{ +//volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET); + const char message[] = "\nProgam has exited with code:"; +//*leds = (~(code)); + + write(STDERR_FILENO, message, sizeof(message) - 1); + write(STDERR_FILENO, "\n", 1); + + for (;;); +} diff --git a/raven/bsp/libwrap/sys/close.c b/raven/bsp/libwrap/sys/close.c new file mode 100644 index 0000000..e4f8e14 --- /dev/null +++ b/raven/bsp/libwrap/sys/close.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_close(int fd) +{ + return _stub(EBADF); +} diff --git a/raven/bsp/libwrap/sys/execve.c b/raven/bsp/libwrap/sys/execve.c new file mode 100644 index 0000000..6178a01 --- /dev/null +++ b/raven/bsp/libwrap/sys/execve.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_execve(const char* name, char* const argv[], char* const env[]) +{ + return _stub(ENOMEM); +} diff --git a/raven/bsp/libwrap/sys/fork.c b/raven/bsp/libwrap/sys/fork.c new file mode 100644 index 0000000..13a3e65 --- /dev/null +++ b/raven/bsp/libwrap/sys/fork.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int fork(void) +{ + return _stub(EAGAIN); +} diff --git a/raven/bsp/libwrap/sys/fstat.c b/raven/bsp/libwrap/sys/fstat.c new file mode 100644 index 0000000..6ea3e6a --- /dev/null +++ b/raven/bsp/libwrap/sys/fstat.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include "stub.h" + +int __wrap_fstat(int fd, struct stat* st) +{ + if (isatty(fd)) { + st->st_mode = S_IFCHR; + return 0; + } + + return _stub(EBADF); +} diff --git a/raven/bsp/libwrap/sys/getpid.c b/raven/bsp/libwrap/sys/getpid.c new file mode 100644 index 0000000..5aa510b --- /dev/null +++ b/raven/bsp/libwrap/sys/getpid.c @@ -0,0 +1,6 @@ +/* See LICENSE of license details. */ + +int __wrap_getpid(void) +{ + return 1; +} diff --git a/raven/bsp/libwrap/sys/isatty.c b/raven/bsp/libwrap/sys/isatty.c new file mode 100644 index 0000000..55eab0a --- /dev/null +++ b/raven/bsp/libwrap/sys/isatty.c @@ -0,0 +1,11 @@ +/* See LICENSE of license details. */ + +#include + +int __wrap_isatty(int fd) +{ + if (fd == STDOUT_FILENO || fd == STDERR_FILENO) + return 1; + + return 0; +} diff --git a/raven/bsp/libwrap/sys/kill.c b/raven/bsp/libwrap/sys/kill.c new file mode 100644 index 0000000..9c56632 --- /dev/null +++ b/raven/bsp/libwrap/sys/kill.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_kill(int pid, int sig) +{ + return _stub(EINVAL); +} diff --git a/raven/bsp/libwrap/sys/link.c b/raven/bsp/libwrap/sys/link.c new file mode 100644 index 0000000..9340cad --- /dev/null +++ b/raven/bsp/libwrap/sys/link.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_link(const char *old_name, const char *new_name) +{ + return _stub(EMLINK); +} diff --git a/raven/bsp/libwrap/sys/lseek.c b/raven/bsp/libwrap/sys/lseek.c new file mode 100644 index 0000000..46f58fa --- /dev/null +++ b/raven/bsp/libwrap/sys/lseek.c @@ -0,0 +1,14 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include "stub.h" + +off_t __wrap_lseek(int fd, off_t ptr, int dir) +{ + if (isatty(fd)) + return 0; + + return _stub(EBADF); +} diff --git a/raven/bsp/libwrap/sys/open.c b/raven/bsp/libwrap/sys/open.c new file mode 100644 index 0000000..d1871f9 --- /dev/null +++ b/raven/bsp/libwrap/sys/open.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_open(const char* name, int flags, int mode) +{ + return _stub(ENOENT); +} diff --git a/raven/bsp/libwrap/sys/openat.c b/raven/bsp/libwrap/sys/openat.c new file mode 100644 index 0000000..7f1c945 --- /dev/null +++ b/raven/bsp/libwrap/sys/openat.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_openat(int dirfd, const char* name, int flags, int mode) +{ + return _stub(ENOENT); +} diff --git a/raven/bsp/libwrap/sys/read.c b/raven/bsp/libwrap/sys/read.c new file mode 100644 index 0000000..4e57f08 --- /dev/null +++ b/raven/bsp/libwrap/sys/read.c @@ -0,0 +1,30 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include + +#include "platform.h" +#include "stub.h" + +ssize_t __wrap_read(int fd, void* ptr, size_t len) +{ + uint8_t * current = (uint8_t *)ptr; + volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO); + volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2); + + ssize_t result = 0; + + if (isatty(fd)) { + for (current = (uint8_t *)ptr; + (current < ((uint8_t *)ptr) + len) && (*uart_rx_cnt > 0); + current ++) { + *current = *uart_rx; + result++; + } + return result; + } + + return _stub(EBADF); +} diff --git a/raven/bsp/libwrap/sys/sbrk.c b/raven/bsp/libwrap/sys/sbrk.c new file mode 100644 index 0000000..6e6b36a --- /dev/null +++ b/raven/bsp/libwrap/sys/sbrk.c @@ -0,0 +1,16 @@ +/* See LICENSE of license details. */ + +#include + +void *__wrap_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} diff --git a/raven/bsp/libwrap/sys/stat.c b/raven/bsp/libwrap/sys/stat.c new file mode 100644 index 0000000..1ccc2f4 --- /dev/null +++ b/raven/bsp/libwrap/sys/stat.c @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "stub.h" + +int __wrap_stat(const char* file, struct stat* st) +{ + return _stub(EACCES); +} diff --git a/raven/bsp/libwrap/sys/stub.h b/raven/bsp/libwrap/sys/stub.h new file mode 100644 index 0000000..fb5e5be --- /dev/null +++ b/raven/bsp/libwrap/sys/stub.h @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ +#ifndef _SIFIVE_SYS_STUB_H +#define _SIFIVE_SYS_STUB_H + +static inline int _stub(int err) +{ + return -1; +} + +#endif /* _SIFIVE_SYS_STUB_H */ diff --git a/raven/bsp/libwrap/sys/times.c b/raven/bsp/libwrap/sys/times.c new file mode 100644 index 0000000..26a9566 --- /dev/null +++ b/raven/bsp/libwrap/sys/times.c @@ -0,0 +1,10 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "stub.h" + +clock_t __wrap_times(struct tms* buf) +{ + return _stub(EACCES); +} diff --git a/raven/bsp/libwrap/sys/unlink.c b/raven/bsp/libwrap/sys/unlink.c new file mode 100644 index 0000000..b62b1ba --- /dev/null +++ b/raven/bsp/libwrap/sys/unlink.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int __wrap_unlink(const char* name) +{ + return _stub(ENOENT); +} diff --git a/raven/bsp/libwrap/sys/wait.c b/raven/bsp/libwrap/sys/wait.c new file mode 100644 index 0000000..ea3225b --- /dev/null +++ b/raven/bsp/libwrap/sys/wait.c @@ -0,0 +1,9 @@ +/* See LICENSE of license details. */ + +#include +#include "stub.h" + +int wait(int* status) +{ + return _stub(ECHILD); +} diff --git a/raven/bsp/libwrap/sys/write.c b/raven/bsp/libwrap/sys/write.c new file mode 100644 index 0000000..d00eb17 --- /dev/null +++ b/raven/bsp/libwrap/sys/write.c @@ -0,0 +1,29 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include + +#include "platform.h" +#include "stub.h" + +ssize_t __wrap_write(int fd, const void* ptr, size_t len) +{ + const uint8_t * current = (const char *)ptr; + + if (isatty(fd)) { + for (size_t jj = 0; jj < len; jj++) { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = current[jj]; + + if (current[jj] == '\n') { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = '\r'; + } + } + return len; + } + + return _stub(EBADF); +} diff --git a/raven/hello_raven b/raven/hello_raven new file mode 100755 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zv0L@G5Pp>ihy~?00>nO!H!g?p77HjV=z#MX&cxyLhdMXsU&)F%zujba@mdJ~NWL1m z3zwSgey^MPT`Y>MxE(kVhYKC0u&9GdKPU|M2r2>{GWP9`HQ;4dufTaI5qNuiXG+B3 NwUwoieh+ZF{{eIKx<>#2 literal 0 HcmV?d00001 diff --git a/raven/hello_raven.c b/raven/hello_raven.c new file mode 100644 index 0000000..2bff6a7 --- /dev/null +++ b/raven/hello_raven.c @@ -0,0 +1,77 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +#define IOF_SPI1_MASK (0x38 | 0x4) +int factorial(int i){ + + volatile int result = 1; + for (int ii = 1; ii <= i; ii++) { + result = result * ii; + } + return result; + +} + +unsigned read_adc(unsigned index){ + unsigned char txdata[3]; + unsigned result=0; + volatile int x; + + txdata[0]=0x1; + txdata[1]=(0x8 | (index&0x7))<<4; + txdata[2]=0x0; + + GPIO_REG(GPIO_IOF_SEL) &= ~IOF_SPI1_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF_SPI1_MASK; + + SPI1_REG(SPI_REG_FMT) = + SPI_FMT_PROTO(SPI_PROTO_S) | + SPI_FMT_ENDIAN(SPI_ENDIAN_MSB) | + SPI_FMT_DIR(SPI_DIR_RX) | + SPI_FMT_LEN(8); + SPI1_REG(SPI_REG_CSID) = 0; + SPI1_REG(SPI_REG_CSDEF) = 0xFFFF; + SPI1_REG(SPI_REG_SCKDIV) = 7; + SPI1_REG(SPI_REG_SCKMODE) = SPI_SCK_PHA | SPI_SCK_POL; //shifted on the leading edge, sampled on trailing, Inactive state of SCK is logical 1 + SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_HOLD; + + while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL) ; + SPI1_REG(SPI_REG_TXFIFO) = txdata[0]; + while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY); + + while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL) ; + SPI1_REG(SPI_REG_TXFIFO) = txdata[1]; + while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY); + result = (x & 0xFF)<<8; + + while (SPI1_REG(SPI_REG_TXFIFO) & SPI_TXFIFO_FULL) ; + SPI1_REG(SPI_REG_TXFIFO) = txdata[2]; + while ((x = SPI1_REG(SPI_REG_RXFIFO)) & SPI_RXFIFO_EMPTY); + result += (x & 0xFF); + + SPI1_REG(SPI_REG_CSMODE) = SPI_CSMODE_AUTO; + return result&0x03ff; +} + +//int read_csr(int csr_num) __attribute__((always_inline)) { +// int result; +// asm("csrr %0, %1" : "=r"(result) : "I"(csr_num)); +// return result; +//} + +int main() +{ + GPIO_REG(GPIO_IOF_EN) |= 0x30000; + *(int *)0x90000000 = 0x5AA5; + int result = factorial (10); + printf("Factorial of 10 is %d\n", result); + for(unsigned i=0; i<8; ++i) + printf("ADC%u value read is %u\n", i, read_adc(i)); + printf("Read a value from another thread %x\n", *(int *)0x80000000); + printf("End of execution"); + return 0; +} diff --git a/raven/hello_raven.dis b/raven/hello_raven.dis new file mode 100644 index 0000000..0e71dac --- /dev/null +++ b/raven/hello_raven.dis @@ -0,0 +1,2246 @@ + +hello_raven: file format elf32-littleriscv + + +Disassembly of section .init: + +20400000 <_start>: +20400000: 5fc01197 auipc gp,0x5fc01 +20400004: c2818193 addi gp,gp,-984 # 80000c28 <_gp> +20400008: 5fc04117 auipc sp,0x5fc04 +2040000c: ff810113 addi sp,sp,-8 # 80004000 <_sp> +20400010: 00002517 auipc a0,0x2 +20400014: 4d450513 addi a0,a0,1236 # 204024e4 <__fini_array_end> +20400018: 5fc00597 auipc a1,0x5fc00 +2040001c: fe858593 addi a1,a1,-24 # 80000000 <_data> +20400020: 5fc00617 auipc a2,0x5fc00 +20400024: 41060613 addi a2,a2,1040 # 80000430 <__bss_start> +20400028: 00c5fc63 bgeu a1,a2,20400040 <_start+0x40> +2040002c: 00052283 lw t0,0(a0) +20400030: 0055a023 sw t0,0(a1) +20400034: 00450513 addi a0,a0,4 +20400038: 00458593 addi a1,a1,4 +2040003c: fec5e8e3 bltu a1,a2,2040002c <_start+0x2c> +20400040: 5fc00517 auipc a0,0x5fc00 +20400044: 3f050513 addi a0,a0,1008 # 80000430 <__bss_start> +20400048: 5fc00597 auipc a1,0x5fc00 +2040004c: 3f058593 addi a1,a1,1008 # 80000438 <_end> +20400050: 00b57863 bgeu a0,a1,20400060 <_start+0x60> +20400054: 00052023 sw zero,0(a0) +20400058: 00450513 addi a0,a0,4 +2040005c: feb56ce3 bltu a0,a1,20400054 <_start+0x54> +20400060: 00001517 auipc a0,0x1 +20400064: 62450513 addi a0,a0,1572 # 20401684 <__libc_fini_array> +20400068: 5d0010ef jal ra,20401638 +2040006c: 678010ef jal ra,204016e4 <__libc_init_array> +20400070: 00000513 li a0,0 +20400074: 00000593 li a1,0 +20400078: 505000ef jal ra,20400d7c
+2040007c: 5d00106f j 2040164c + +Disassembly of section .text: + +20400080 : +20400080: dfc00797 auipc a5,0xdfc00 +20400084: f8078793 addi a5,a5,-128 # 0 <__stack_size-0x800> +20400088: 00078863 beqz a5,20400098 +2040008c: 00001517 auipc a0,0x1 +20400090: 5f850513 addi a0,a0,1528 # 20401684 <__libc_fini_array> +20400094: 5a40106f j 20401638 +20400098: 00008067 ret + +2040009c : +2040009c: f8010113 addi sp,sp,-128 +204000a0: 00112223 sw ra,4(sp) +204000a4: 00212423 sw sp,8(sp) +204000a8: 00312623 sw gp,12(sp) +204000ac: 00412823 sw tp,16(sp) +204000b0: 00512a23 sw t0,20(sp) +204000b4: 00612c23 sw t1,24(sp) +204000b8: 00712e23 sw t2,28(sp) +204000bc: 02812023 sw s0,32(sp) +204000c0: 02912223 sw s1,36(sp) +204000c4: 02a12423 sw a0,40(sp) +204000c8: 02b12623 sw a1,44(sp) +204000cc: 02c12823 sw a2,48(sp) +204000d0: 02d12a23 sw a3,52(sp) +204000d4: 02e12c23 sw a4,56(sp) +204000d8: 02f12e23 sw a5,60(sp) +204000dc: 05012023 sw a6,64(sp) +204000e0: 05112223 sw a7,68(sp) +204000e4: 05212423 sw s2,72(sp) +204000e8: 05312623 sw s3,76(sp) +204000ec: 05412823 sw s4,80(sp) +204000f0: 05512a23 sw s5,84(sp) +204000f4: 05612c23 sw s6,88(sp) +204000f8: 05712e23 sw s7,92(sp) +204000fc: 07812023 sw s8,96(sp) +20400100: 07912223 sw s9,100(sp) +20400104: 07a12423 sw s10,104(sp) +20400108: 07b12623 sw s11,108(sp) +2040010c: 07c12823 sw t3,112(sp) +20400110: 07d12a23 sw t4,116(sp) +20400114: 07e12c23 sw t5,120(sp) +20400118: 07f12e23 sw t6,124(sp) +2040011c: 34202573 csrr a0,mcause +20400120: 341025f3 csrr a1,mepc +20400124: 00010613 mv a2,sp +20400128: 260010ef jal ra,20401388 +2040012c: 34151073 csrw mepc,a0 +20400130: 000022b7 lui t0,0x2 +20400134: 80028293 addi t0,t0,-2048 # 1800 <__stack_size+0x1000> +20400138: 3002a073 csrs mstatus,t0 +2040013c: 00412083 lw ra,4(sp) +20400140: 00812103 lw sp,8(sp) +20400144: 00c12183 lw gp,12(sp) +20400148: 01012203 lw tp,16(sp) +2040014c: 01412283 lw t0,20(sp) +20400150: 01812303 lw t1,24(sp) +20400154: 01c12383 lw t2,28(sp) +20400158: 02012403 lw s0,32(sp) +2040015c: 02412483 lw s1,36(sp) +20400160: 02812503 lw a0,40(sp) +20400164: 02c12583 lw a1,44(sp) +20400168: 03012603 lw a2,48(sp) +2040016c: 03412683 lw a3,52(sp) +20400170: 03812703 lw a4,56(sp) +20400174: 03c12783 lw a5,60(sp) +20400178: 04012803 lw a6,64(sp) +2040017c: 04412883 lw a7,68(sp) +20400180: 04812903 lw s2,72(sp) +20400184: 04c12983 lw s3,76(sp) +20400188: 05012a03 lw s4,80(sp) +2040018c: 05412a83 lw s5,84(sp) +20400190: 05812b03 lw s6,88(sp) +20400194: 05c12b83 lw s7,92(sp) +20400198: 06012c03 lw s8,96(sp) +2040019c: 06412c83 lw s9,100(sp) +204001a0: 06812d03 lw s10,104(sp) +204001a4: 06c12d83 lw s11,108(sp) +204001a8: 07012e03 lw t3,112(sp) +204001ac: 07412e83 lw t4,116(sp) +204001b0: 07812f03 lw t5,120(sp) +204001b4: 07c12f83 lw t6,124(sp) +204001b8: 08010113 addi sp,sp,128 +204001bc: 30200073 mret +204001c0: 0000006f j 204001c0 + +204001c4 : +204001c4: fe010113 addi sp,sp,-32 +204001c8: 00112e23 sw ra,28(sp) +204001cc: 00812c23 sw s0,24(sp) +204001d0: 02010413 addi s0,sp,32 +204001d4: fea42623 sw a0,-20(s0) +204001d8: fec40793 addi a5,s0,-20 +204001dc: 00100613 li a2,1 +204001e0: 00078593 mv a1,a5 +204001e4: 00100513 li a0,1 +204001e8: 2ac010ef jal ra,20401494 <__wrap_write> +204001ec: 00050713 mv a4,a0 +204001f0: 00100793 li a5,1 +204001f4: 00f71663 bne a4,a5,20400200 +204001f8: fec42783 lw a5,-20(s0) +204001fc: 0080006f j 20400204 +20400200: fff00793 li a5,-1 +20400204: 00078513 mv a0,a5 +20400208: 01c12083 lw ra,28(sp) +2040020c: 01812403 lw s0,24(sp) +20400210: 02010113 addi sp,sp,32 +20400214: 00008067 ret + +20400218 : +20400218: fd010113 addi sp,sp,-48 +2040021c: 02812623 sw s0,44(sp) +20400220: 03010413 addi s0,sp,48 +20400224: fca42e23 sw a0,-36(s0) +20400228: fcb42c23 sw a1,-40(s0) +2040022c: fd842783 lw a5,-40(s0) +20400230: fef42623 sw a5,-20(s0) +20400234: fec42783 lw a5,-20(s0) +20400238: 0007a783 lw a5,0(a5) +2040023c: fdc42703 lw a4,-36(s0) +20400240: 0ff77713 andi a4,a4,255 +20400244: 00e78023 sb a4,0(a5) +20400248: fec42783 lw a5,-20(s0) +2040024c: 0007a783 lw a5,0(a5) +20400250: 00178713 addi a4,a5,1 +20400254: fec42783 lw a5,-20(s0) +20400258: 00e7a023 sw a4,0(a5) +2040025c: 00000013 nop +20400260: 02c12403 lw s0,44(sp) +20400264: 03010113 addi sp,sp,48 +20400268: 00008067 ret + +2040026c : +2040026c: fe010113 addi sp,sp,-32 +20400270: 00812e23 sw s0,28(sp) +20400274: 02010413 addi s0,sp,32 +20400278: fea42623 sw a0,-20(s0) +2040027c: feb42423 sw a1,-24(s0) +20400280: fe842783 lw a5,-24(s0) +20400284: 02078063 beqz a5,204002a4 +20400288: fec42783 lw a5,-20(s0) +2040028c: 0007a783 lw a5,0(a5) +20400290: 00478693 addi a3,a5,4 +20400294: fec42703 lw a4,-20(s0) +20400298: 00d72023 sw a3,0(a4) +2040029c: 0007a783 lw a5,0(a5) +204002a0: 01c0006f j 204002bc +204002a4: fec42783 lw a5,-20(s0) +204002a8: 0007a783 lw a5,0(a5) +204002ac: 00478693 addi a3,a5,4 +204002b0: fec42703 lw a4,-20(s0) +204002b4: 00d72023 sw a3,0(a4) +204002b8: 0007a783 lw a5,0(a5) +204002bc: 00078513 mv a0,a5 +204002c0: 01c12403 lw s0,28(sp) +204002c4: 02010113 addi sp,sp,32 +204002c8: 00008067 ret + +204002cc : +204002cc: fe010113 addi sp,sp,-32 +204002d0: 00812e23 sw s0,28(sp) +204002d4: 02010413 addi s0,sp,32 +204002d8: fea42623 sw a0,-20(s0) +204002dc: feb42423 sw a1,-24(s0) +204002e0: fe842783 lw a5,-24(s0) +204002e4: 02078063 beqz a5,20400304 +204002e8: fec42783 lw a5,-20(s0) +204002ec: 0007a783 lw a5,0(a5) +204002f0: 00478693 addi a3,a5,4 +204002f4: fec42703 lw a4,-20(s0) +204002f8: 00d72023 sw a3,0(a4) +204002fc: 0007a783 lw a5,0(a5) +20400300: 01c0006f j 2040031c +20400304: fec42783 lw a5,-20(s0) +20400308: 0007a783 lw a5,0(a5) +2040030c: 00478693 addi a3,a5,4 +20400310: fec42703 lw a4,-20(s0) +20400314: 00d72023 sw a3,0(a4) +20400318: 0007a783 lw a5,0(a5) +2040031c: 00078513 mv a0,a5 +20400320: 01c12403 lw s0,28(sp) +20400324: 02010113 addi sp,sp,32 +20400328: 00008067 ret + +2040032c : +2040032c: f4010113 addi sp,sp,-192 +20400330: 0a112e23 sw ra,188(sp) +20400334: 0a812c23 sw s0,184(sp) +20400338: 0a912a23 sw s1,180(sp) +2040033c: 0c010413 addi s0,sp,192 +20400340: f4a42e23 sw a0,-164(s0) +20400344: f4b42c23 sw a1,-168(s0) +20400348: f4c42a23 sw a2,-172(s0) +2040034c: f4d42823 sw a3,-176(s0) +20400350: f4e42623 sw a4,-180(s0) +20400354: f4f42423 sw a5,-184(s0) +20400358: fe042623 sw zero,-20(s0) +2040035c: fec42483 lw s1,-20(s0) +20400360: 00148793 addi a5,s1,1 +20400364: fef42623 sw a5,-20(s0) +20400368: f5442783 lw a5,-172(s0) +2040036c: f5042583 lw a1,-176(s0) +20400370: 00078513 mv a0,a5 +20400374: 569010ef jal ra,204020dc <__umodsi3> +20400378: 00050793 mv a5,a0 +2040037c: 00078713 mv a4,a5 +20400380: 00249793 slli a5,s1,0x2 +20400384: ff040693 addi a3,s0,-16 +20400388: 00f687b3 add a5,a3,a5 +2040038c: f6e7ae23 sw a4,-132(a5) +20400390: f5442703 lw a4,-172(s0) +20400394: f5042783 lw a5,-176(s0) +20400398: 00f76e63 bltu a4,a5,204003b4 +2040039c: f5042583 lw a1,-176(s0) +204003a0: f5442503 lw a0,-172(s0) +204003a4: 4f1010ef jal ra,20402094 <__udivsi3> +204003a8: 00050793 mv a5,a0 +204003ac: f4f42a23 sw a5,-172(s0) +204003b0: fadff06f j 2040035c +204003b4: 00000013 nop +204003b8: 0140006f j 204003cc +204003bc: f5c42783 lw a5,-164(s0) +204003c0: f5842583 lw a1,-168(s0) +204003c4: f4842503 lw a0,-184(s0) +204003c8: 000780e7 jalr a5 +204003cc: f4c42783 lw a5,-180(s0) +204003d0: fff78713 addi a4,a5,-1 +204003d4: f4e42623 sw a4,-180(s0) +204003d8: fec42703 lw a4,-20(s0) +204003dc: fef740e3 blt a4,a5,204003bc +204003e0: 0540006f j 20400434 +204003e4: fec42783 lw a5,-20(s0) +204003e8: 00279793 slli a5,a5,0x2 +204003ec: ff040713 addi a4,s0,-16 +204003f0: 00f707b3 add a5,a4,a5 +204003f4: f7c7a703 lw a4,-132(a5) +204003f8: fec42783 lw a5,-20(s0) +204003fc: 00279793 slli a5,a5,0x2 +20400400: ff040693 addi a3,s0,-16 +20400404: 00f687b3 add a5,a3,a5 +20400408: f7c7a683 lw a3,-132(a5) +2040040c: 00900793 li a5,9 +20400410: 00d7f663 bgeu a5,a3,2040041c +20400414: 05700793 li a5,87 +20400418: 0080006f j 20400420 +2040041c: 03000793 li a5,48 +20400420: 00e787b3 add a5,a5,a4 +20400424: f5c42703 lw a4,-164(s0) +20400428: f5842583 lw a1,-168(s0) +2040042c: 00078513 mv a0,a5 +20400430: 000700e7 jalr a4 +20400434: fec42783 lw a5,-20(s0) +20400438: fff78713 addi a4,a5,-1 +2040043c: fee42623 sw a4,-20(s0) +20400440: faf042e3 bgtz a5,204003e4 +20400444: 00000013 nop +20400448: 0bc12083 lw ra,188(sp) +2040044c: 0b812403 lw s0,184(sp) +20400450: 0b412483 lw s1,180(sp) +20400454: 0c010113 addi sp,sp,192 +20400458: 00008067 ret + +2040045c : +2040045c: f9010113 addi sp,sp,-112 +20400460: 06112623 sw ra,108(sp) +20400464: 06812423 sw s0,104(sp) +20400468: 07212223 sw s2,100(sp) +2040046c: 07312023 sw s3,96(sp) +20400470: 07010413 addi s0,sp,112 +20400474: faa42623 sw a0,-84(s0) +20400478: fab42423 sw a1,-88(s0) +2040047c: fac42023 sw a2,-96(s0) +20400480: fad42223 sw a3,-92(s0) +20400484: f8e42e23 sw a4,-100(s0) +20400488: f8f42c23 sw a5,-104(s0) +2040048c: fa042783 lw a5,-96(s0) +20400490: fa442803 lw a6,-92(s0) +20400494: fcf42c23 sw a5,-40(s0) +20400498: fd042e23 sw a6,-36(s0) +2040049c: fd842783 lw a5,-40(s0) +204004a0: fdc42803 lw a6,-36(s0) +204004a4: 00080793 mv a5,a6 +204004a8: 0207da63 bgez a5,204004dc +204004ac: fac42783 lw a5,-84(s0) +204004b0: fa842583 lw a1,-88(s0) +204004b4: 02d00513 li a0,45 +204004b8: 000780e7 jalr a5 +204004bc: fd842783 lw a5,-40(s0) +204004c0: fdc42803 lw a6,-36(s0) +204004c4: fff7f913 andi s2,a5,-1 +204004c8: 80000737 lui a4,0x80000 +204004cc: fff74713 not a4,a4 +204004d0: 00e879b3 and s3,a6,a4 +204004d4: fd242c23 sw s2,-40(s0) +204004d8: fd342e23 sw s3,-36(s0) +204004dc: fe042623 sw zero,-20(s0) +204004e0: 0400006f j 20400520 +204004e4: fd842783 lw a5,-40(s0) +204004e8: fdc42803 lw a6,-36(s0) +204004ec: 20402737 lui a4,0x20402 +204004f0: 2f072603 lw a2,752(a4) # 204022f0 <__clzsi2+0x1b0> +204004f4: 2f472683 lw a3,756(a4) +204004f8: 00078513 mv a0,a5 +204004fc: 00080593 mv a1,a6 +20400500: 47c010ef jal ra,2040197c <__muldf3> +20400504: 00050793 mv a5,a0 +20400508: 00058813 mv a6,a1 +2040050c: fcf42c23 sw a5,-40(s0) +20400510: fd042e23 sw a6,-36(s0) +20400514: fec42783 lw a5,-20(s0) +20400518: 00178793 addi a5,a5,1 +2040051c: fef42623 sw a5,-20(s0) +20400520: fec42703 lw a4,-20(s0) +20400524: f9842783 lw a5,-104(s0) +20400528: faf74ee3 blt a4,a5,204004e4 +2040052c: fb840793 addi a5,s0,-72 +20400530: faf42a23 sw a5,-76(s0) +20400534: fd842783 lw a5,-40(s0) +20400538: fdc42803 lw a6,-36(s0) +2040053c: 00078513 mv a0,a5 +20400540: 00080593 mv a1,a6 +20400544: 2a9010ef jal ra,20401fec <__fixunsdfsi> +20400548: 00050613 mv a2,a0 +2040054c: fb440593 addi a1,s0,-76 +20400550: 00000793 li a5,0 +20400554: 00000713 li a4,0 +20400558: 00a00693 li a3,10 +2040055c: 20400537 lui a0,0x20400 +20400560: 21850513 addi a0,a0,536 # 20400218 +20400564: dc9ff0ef jal ra,2040032c +20400568: f9842783 lw a5,-104(s0) +2040056c: 06f05863 blez a5,204005dc +20400570: fe042423 sw zero,-24(s0) +20400574: 0380006f j 204005ac +20400578: fb442703 lw a4,-76(s0) +2040057c: fe842783 lw a5,-24(s0) +20400580: fff7c793 not a5,a5 +20400584: 00f70733 add a4,a4,a5 +20400588: fb442783 lw a5,-76(s0) +2040058c: fe842683 lw a3,-24(s0) +20400590: 40d006b3 neg a3,a3 +20400594: 00d787b3 add a5,a5,a3 +20400598: 00074703 lbu a4,0(a4) +2040059c: 00e78023 sb a4,0(a5) +204005a0: fe842783 lw a5,-24(s0) +204005a4: 00178793 addi a5,a5,1 +204005a8: fef42423 sw a5,-24(s0) +204005ac: fe842703 lw a4,-24(s0) +204005b0: f9842783 lw a5,-104(s0) +204005b4: fcf742e3 blt a4,a5,20400578 +204005b8: fb442783 lw a5,-76(s0) +204005bc: f9842703 lw a4,-104(s0) +204005c0: 40e00733 neg a4,a4 +204005c4: 00e787b3 add a5,a5,a4 +204005c8: 02e00713 li a4,46 +204005cc: 00e78023 sb a4,0(a5) +204005d0: fb442783 lw a5,-76(s0) +204005d4: 00178793 addi a5,a5,1 +204005d8: faf42a23 sw a5,-76(s0) +204005dc: fb840793 addi a5,s0,-72 +204005e0: fef42223 sw a5,-28(s0) +204005e4: 0280006f j 2040060c +204005e8: fe442783 lw a5,-28(s0) +204005ec: 0007c783 lbu a5,0(a5) +204005f0: fac42703 lw a4,-84(s0) +204005f4: fa842583 lw a1,-88(s0) +204005f8: 00078513 mv a0,a5 +204005fc: 000700e7 jalr a4 +20400600: fe442783 lw a5,-28(s0) +20400604: 00178793 addi a5,a5,1 +20400608: fef42223 sw a5,-28(s0) +2040060c: fb442783 lw a5,-76(s0) +20400610: fe442703 lw a4,-28(s0) +20400614: fcf76ae3 bltu a4,a5,204005e8 +20400618: 00000013 nop +2040061c: 06c12083 lw ra,108(sp) +20400620: 06812403 lw s0,104(sp) +20400624: 06412903 lw s2,100(sp) +20400628: 06012983 lw s3,96(sp) +2040062c: 07010113 addi sp,sp,112 +20400630: 00008067 ret + +20400634 : +20400634: fc010113 addi sp,sp,-64 +20400638: 02112e23 sw ra,60(sp) +2040063c: 02812c23 sw s0,56(sp) +20400640: 02912a23 sw s1,52(sp) +20400644: 03212823 sw s2,48(sp) +20400648: 04010413 addi s0,sp,64 +2040064c: fca42623 sw a0,-52(s0) +20400650: fcb42423 sw a1,-56(s0) +20400654: fcc42223 sw a2,-60(s0) +20400658: fcd42023 sw a3,-64(s0) +2040065c: 0240006f j 20400680 +20400660: 3a048863 beqz s1,20400a10 +20400664: fc442783 lw a5,-60(s0) +20400668: 00178793 addi a5,a5,1 +2040066c: fcf42223 sw a5,-60(s0) +20400670: fcc42783 lw a5,-52(s0) +20400674: fc842583 lw a1,-56(s0) +20400678: 00048513 mv a0,s1 +2040067c: 000780e7 jalr a5 +20400680: fc442783 lw a5,-60(s0) +20400684: 0007c783 lbu a5,0(a5) +20400688: 00078493 mv s1,a5 +2040068c: 02500793 li a5,37 +20400690: fcf498e3 bne s1,a5,20400660 +20400694: fc442783 lw a5,-60(s0) +20400698: 00178793 addi a5,a5,1 +2040069c: fcf42223 sw a5,-60(s0) +204006a0: fc442783 lw a5,-60(s0) +204006a4: fcf42a23 sw a5,-44(s0) +204006a8: 02000793 li a5,32 +204006ac: fcf40da3 sb a5,-37(s0) +204006b0: fff00793 li a5,-1 +204006b4: fef42023 sw a5,-32(s0) +204006b8: fff00793 li a5,-1 +204006bc: fcf42e23 sw a5,-36(s0) +204006c0: fe042223 sw zero,-28(s0) +204006c4: fc042823 sw zero,-48(s0) +204006c8: fc442783 lw a5,-60(s0) +204006cc: 00178713 addi a4,a5,1 +204006d0: fce42223 sw a4,-60(s0) +204006d4: 0007c783 lbu a5,0(a5) +204006d8: 00078493 mv s1,a5 +204006dc: fdd48793 addi a5,s1,-35 +204006e0: 05500713 li a4,85 +204006e4: 30f76663 bltu a4,a5,204009f0 +204006e8: 00279713 slli a4,a5,0x2 +204006ec: 204027b7 lui a5,0x20402 +204006f0: 19878793 addi a5,a5,408 # 20402198 <__clzsi2+0x58> +204006f4: 00f707b3 add a5,a4,a5 +204006f8: 0007a783 lw a5,0(a5) +204006fc: 00078067 jr a5 +20400700: 02d00793 li a5,45 +20400704: fcf40da3 sb a5,-37(s0) +20400708: fc1ff06f j 204006c8 +2040070c: 03000793 li a5,48 +20400710: fcf40da3 sb a5,-37(s0) +20400714: fb5ff06f j 204006c8 +20400718: fc042e23 sw zero,-36(s0) +2040071c: fdc42703 lw a4,-36(s0) +20400720: 00070793 mv a5,a4 +20400724: 00279793 slli a5,a5,0x2 +20400728: 00e787b3 add a5,a5,a4 +2040072c: 00179793 slli a5,a5,0x1 +20400730: 00f487b3 add a5,s1,a5 +20400734: fd078793 addi a5,a5,-48 +20400738: fcf42e23 sw a5,-36(s0) +2040073c: fc442783 lw a5,-60(s0) +20400740: 0007c783 lbu a5,0(a5) +20400744: 00078493 mv s1,a5 +20400748: 02f00793 li a5,47 +2040074c: 0497d863 bge a5,s1,2040079c +20400750: 03900793 li a5,57 +20400754: 0497c463 blt a5,s1,2040079c +20400758: fc442783 lw a5,-60(s0) +2040075c: 00178793 addi a5,a5,1 +20400760: fcf42223 sw a5,-60(s0) +20400764: fb9ff06f j 2040071c +20400768: fc042783 lw a5,-64(s0) +2040076c: 00478713 addi a4,a5,4 +20400770: fce42023 sw a4,-64(s0) +20400774: 0007a783 lw a5,0(a5) +20400778: fcf42e23 sw a5,-36(s0) +2040077c: 0240006f j 204007a0 +20400780: fe042783 lw a5,-32(s0) +20400784: f407d2e3 bgez a5,204006c8 +20400788: fe042023 sw zero,-32(s0) +2040078c: f3dff06f j 204006c8 +20400790: 00100793 li a5,1 +20400794: fcf42823 sw a5,-48(s0) +20400798: f31ff06f j 204006c8 +2040079c: 00000013 nop +204007a0: fe042783 lw a5,-32(s0) +204007a4: f207d2e3 bgez a5,204006c8 +204007a8: fdc42783 lw a5,-36(s0) +204007ac: fef42023 sw a5,-32(s0) +204007b0: fff00793 li a5,-1 +204007b4: fcf42e23 sw a5,-36(s0) +204007b8: f11ff06f j 204006c8 +204007bc: fe442783 lw a5,-28(s0) +204007c0: 22079663 bnez a5,204009ec +204007c4: f05ff06f j 204006c8 +204007c8: fc042783 lw a5,-64(s0) +204007cc: 00478713 addi a4,a5,4 +204007d0: fce42023 sw a4,-64(s0) +204007d4: 0007a783 lw a5,0(a5) +204007d8: fcc42703 lw a4,-52(s0) +204007dc: fc842583 lw a1,-56(s0) +204007e0: 00078513 mv a0,a5 +204007e4: 000700e7 jalr a4 +204007e8: 2240006f j 20400a0c +204007ec: fc042783 lw a5,-64(s0) +204007f0: 00778793 addi a5,a5,7 +204007f4: ff87f793 andi a5,a5,-8 +204007f8: 00878713 addi a4,a5,8 +204007fc: fce42023 sw a4,-64(s0) +20400800: 0007a603 lw a2,0(a5) +20400804: 0047a683 lw a3,4(a5) +20400808: fdc42783 lw a5,-36(s0) +2040080c: fe042703 lw a4,-32(s0) +20400810: fc842583 lw a1,-56(s0) +20400814: fcc42503 lw a0,-52(s0) +20400818: c45ff0ef jal ra,2040045c +2040081c: 1f00006f j 20400a0c +20400820: fc042783 lw a5,-64(s0) +20400824: 00478713 addi a4,a5,4 +20400828: fce42023 sw a4,-64(s0) +2040082c: 0007a903 lw s2,0(a5) +20400830: 00091663 bnez s2,2040083c +20400834: 204027b7 lui a5,0x20402 +20400838: 19078913 addi s2,a5,400 # 20402190 <__clzsi2+0x50> +2040083c: fe042783 lw a5,-32(s0) +20400840: 08f05063 blez a5,204008c0 +20400844: fdb44703 lbu a4,-37(s0) +20400848: 02d00793 li a5,45 +2040084c: 06f70a63 beq a4,a5,204008c0 +20400850: fdc42783 lw a5,-36(s0) +20400854: 00078593 mv a1,a5 +20400858: 00090513 mv a0,s2 +2040085c: 71d000ef jal ra,20401778 +20400860: 00050713 mv a4,a0 +20400864: fe042783 lw a5,-32(s0) +20400868: 40e787b3 sub a5,a5,a4 +2040086c: fef42023 sw a5,-32(s0) +20400870: 0240006f j 20400894 +20400874: fdb44783 lbu a5,-37(s0) +20400878: fcc42703 lw a4,-52(s0) +2040087c: fc842583 lw a1,-56(s0) +20400880: 00078513 mv a0,a5 +20400884: 000700e7 jalr a4 +20400888: fe042783 lw a5,-32(s0) +2040088c: fff78793 addi a5,a5,-1 +20400890: fef42023 sw a5,-32(s0) +20400894: fe042783 lw a5,-32(s0) +20400898: fcf04ee3 bgtz a5,20400874 +2040089c: 0240006f j 204008c0 +204008a0: fcc42783 lw a5,-52(s0) +204008a4: fc842583 lw a1,-56(s0) +204008a8: 00048513 mv a0,s1 +204008ac: 000780e7 jalr a5 +204008b0: 00190913 addi s2,s2,1 +204008b4: fe042783 lw a5,-32(s0) +204008b8: fff78793 addi a5,a5,-1 +204008bc: fef42023 sw a5,-32(s0) +204008c0: 00094783 lbu a5,0(s2) +204008c4: 00078493 mv s1,a5 +204008c8: 04048063 beqz s1,20400908 +204008cc: fdc42783 lw a5,-36(s0) +204008d0: fc07c8e3 bltz a5,204008a0 +204008d4: fdc42783 lw a5,-36(s0) +204008d8: fff78793 addi a5,a5,-1 +204008dc: fcf42e23 sw a5,-36(s0) +204008e0: fdc42783 lw a5,-36(s0) +204008e4: fa07dee3 bgez a5,204008a0 +204008e8: 0200006f j 20400908 +204008ec: fcc42783 lw a5,-52(s0) +204008f0: fc842583 lw a1,-56(s0) +204008f4: 02000513 li a0,32 +204008f8: 000780e7 jalr a5 +204008fc: fe042783 lw a5,-32(s0) +20400900: fff78793 addi a5,a5,-1 +20400904: fef42023 sw a5,-32(s0) +20400908: fe042783 lw a5,-32(s0) +2040090c: fef040e3 bgtz a5,204008ec +20400910: 0fc0006f j 20400a0c +20400914: fc040793 addi a5,s0,-64 +20400918: fe442583 lw a1,-28(s0) +2040091c: 00078513 mv a0,a5 +20400920: 9adff0ef jal ra,204002cc +20400924: 00050793 mv a5,a0 +20400928: fef42623 sw a5,-20(s0) +2040092c: fec42783 lw a5,-20(s0) +20400930: 0207d063 bgez a5,20400950 +20400934: fcc42783 lw a5,-52(s0) +20400938: fc842583 lw a1,-56(s0) +2040093c: 02d00513 li a0,45 +20400940: 000780e7 jalr a5 +20400944: fec42783 lw a5,-20(s0) +20400948: 40f007b3 neg a5,a5 +2040094c: fef42623 sw a5,-20(s0) +20400950: 00a00793 li a5,10 +20400954: fef42423 sw a5,-24(s0) +20400958: 0600006f j 204009b8 +2040095c: 00a00793 li a5,10 +20400960: fef42423 sw a5,-24(s0) +20400964: 0400006f j 204009a4 +20400968: 00800793 li a5,8 +2040096c: fef42423 sw a5,-24(s0) +20400970: 0340006f j 204009a4 +20400974: 00100793 li a5,1 +20400978: fef42223 sw a5,-28(s0) +2040097c: fcc42783 lw a5,-52(s0) +20400980: fc842583 lw a1,-56(s0) +20400984: 03000513 li a0,48 +20400988: 000780e7 jalr a5 +2040098c: fcc42783 lw a5,-52(s0) +20400990: fc842583 lw a1,-56(s0) +20400994: 07800513 li a0,120 +20400998: 000780e7 jalr a5 +2040099c: 01000793 li a5,16 +204009a0: fef42423 sw a5,-24(s0) +204009a4: fc040793 addi a5,s0,-64 +204009a8: fe442583 lw a1,-28(s0) +204009ac: 00078513 mv a0,a5 +204009b0: 8bdff0ef jal ra,2040026c +204009b4: fea42623 sw a0,-20(s0) +204009b8: fe842683 lw a3,-24(s0) +204009bc: fdb44783 lbu a5,-37(s0) +204009c0: fe042703 lw a4,-32(s0) +204009c4: fec42603 lw a2,-20(s0) +204009c8: fc842583 lw a1,-56(s0) +204009cc: fcc42503 lw a0,-52(s0) +204009d0: 95dff0ef jal ra,2040032c +204009d4: 0380006f j 20400a0c +204009d8: fcc42783 lw a5,-52(s0) +204009dc: fc842583 lw a1,-56(s0) +204009e0: 00048513 mv a0,s1 +204009e4: 000780e7 jalr a5 +204009e8: 0240006f j 20400a0c +204009ec: 00000013 nop +204009f0: fcc42783 lw a5,-52(s0) +204009f4: fc842583 lw a1,-56(s0) +204009f8: 02500513 li a0,37 +204009fc: 000780e7 jalr a5 +20400a00: fd442783 lw a5,-44(s0) +20400a04: fcf42223 sw a5,-60(s0) +20400a08: 00000013 nop +20400a0c: c75ff06f j 20400680 +20400a10: 00000013 nop +20400a14: 03c12083 lw ra,60(sp) +20400a18: 03812403 lw s0,56(sp) +20400a1c: 03412483 lw s1,52(sp) +20400a20: 03012903 lw s2,48(sp) +20400a24: 04010113 addi sp,sp,64 +20400a28: 00008067 ret + +20400a2c <__wrap_printf>: +20400a2c: fb010113 addi sp,sp,-80 +20400a30: 02112623 sw ra,44(sp) +20400a34: 02812423 sw s0,40(sp) +20400a38: 03010413 addi s0,sp,48 +20400a3c: fca42e23 sw a0,-36(s0) +20400a40: 00b42223 sw a1,4(s0) +20400a44: 00c42423 sw a2,8(s0) +20400a48: 00d42623 sw a3,12(s0) +20400a4c: 00e42823 sw a4,16(s0) +20400a50: 00f42a23 sw a5,20(s0) +20400a54: 01042c23 sw a6,24(s0) +20400a58: 01142e23 sw a7,28(s0) +20400a5c: 02040793 addi a5,s0,32 +20400a60: fe478793 addi a5,a5,-28 +20400a64: fef42623 sw a5,-20(s0) +20400a68: fec42783 lw a5,-20(s0) +20400a6c: 00078693 mv a3,a5 +20400a70: fdc42603 lw a2,-36(s0) +20400a74: 00000593 li a1,0 +20400a78: 204007b7 lui a5,0x20400 +20400a7c: 1c478513 addi a0,a5,452 # 204001c4 +20400a80: bb5ff0ef jal ra,20400634 +20400a84: 00000793 li a5,0 +20400a88: 00078513 mv a0,a5 +20400a8c: 02c12083 lw ra,44(sp) +20400a90: 02812403 lw s0,40(sp) +20400a94: 05010113 addi sp,sp,80 +20400a98: 00008067 ret + +20400a9c <__wrap_sprintf>: +20400a9c: fb010113 addi sp,sp,-80 +20400aa0: 02112623 sw ra,44(sp) +20400aa4: 02812423 sw s0,40(sp) +20400aa8: 03010413 addi s0,sp,48 +20400aac: fca42e23 sw a0,-36(s0) +20400ab0: fcb42c23 sw a1,-40(s0) +20400ab4: 00c42423 sw a2,8(s0) +20400ab8: 00d42623 sw a3,12(s0) +20400abc: 00e42823 sw a4,16(s0) +20400ac0: 00f42a23 sw a5,20(s0) +20400ac4: 01042c23 sw a6,24(s0) +20400ac8: 01142e23 sw a7,28(s0) +20400acc: fdc42783 lw a5,-36(s0) +20400ad0: fef42623 sw a5,-20(s0) +20400ad4: 02040793 addi a5,s0,32 +20400ad8: fe878793 addi a5,a5,-24 +20400adc: fef42423 sw a5,-24(s0) +20400ae0: fe842703 lw a4,-24(s0) +20400ae4: fdc40793 addi a5,s0,-36 +20400ae8: 00070693 mv a3,a4 +20400aec: fd842603 lw a2,-40(s0) +20400af0: 00078593 mv a1,a5 +20400af4: 204007b7 lui a5,0x20400 +20400af8: 21878513 addi a0,a5,536 # 20400218 +20400afc: b39ff0ef jal ra,20400634 +20400b00: fdc42783 lw a5,-36(s0) +20400b04: 00078023 sb zero,0(a5) +20400b08: fdc42703 lw a4,-36(s0) +20400b0c: fec42783 lw a5,-20(s0) +20400b10: 40f707b3 sub a5,a4,a5 +20400b14: 00078513 mv a0,a5 +20400b18: 02c12083 lw ra,44(sp) +20400b1c: 02812403 lw s0,40(sp) +20400b20: 05010113 addi sp,sp,80 +20400b24: 00008067 ret + +20400b28 : +20400b28: fd010113 addi sp,sp,-48 +20400b2c: 02112623 sw ra,44(sp) +20400b30: 02812423 sw s0,40(sp) +20400b34: 03010413 addi s0,sp,48 +20400b38: fca42e23 sw a0,-36(s0) +20400b3c: 00100793 li a5,1 +20400b40: fef42423 sw a5,-24(s0) +20400b44: 00100793 li a5,1 +20400b48: fef42623 sw a5,-20(s0) +20400b4c: 0280006f j 20400b74 +20400b50: fe842783 lw a5,-24(s0) +20400b54: fec42583 lw a1,-20(s0) +20400b58: 00078513 mv a0,a5 +20400b5c: 50c010ef jal ra,20402068 <__mulsi3> +20400b60: 00050793 mv a5,a0 +20400b64: fef42423 sw a5,-24(s0) +20400b68: fec42783 lw a5,-20(s0) +20400b6c: 00178793 addi a5,a5,1 +20400b70: fef42623 sw a5,-20(s0) +20400b74: fec42703 lw a4,-20(s0) +20400b78: fdc42783 lw a5,-36(s0) +20400b7c: fce7dae3 bge a5,a4,20400b50 +20400b80: fe842783 lw a5,-24(s0) +20400b84: 00078513 mv a0,a5 +20400b88: 02c12083 lw ra,44(sp) +20400b8c: 02812403 lw s0,40(sp) +20400b90: 03010113 addi sp,sp,48 +20400b94: 00008067 ret + +20400b98 : +20400b98: fd010113 addi sp,sp,-48 +20400b9c: 02812623 sw s0,44(sp) +20400ba0: 03010413 addi s0,sp,48 +20400ba4: fca42e23 sw a0,-36(s0) +20400ba8: fe042623 sw zero,-20(s0) +20400bac: 00100793 li a5,1 +20400bb0: fef40423 sb a5,-24(s0) +20400bb4: fdc42783 lw a5,-36(s0) +20400bb8: 0ff7f793 andi a5,a5,255 +20400bbc: 00479793 slli a5,a5,0x4 +20400bc0: 0ff7f793 andi a5,a5,255 +20400bc4: 0707f793 andi a5,a5,112 +20400bc8: 0ff7f793 andi a5,a5,255 +20400bcc: f807e793 ori a5,a5,-128 +20400bd0: 0ff7f793 andi a5,a5,255 +20400bd4: fef404a3 sb a5,-23(s0) +20400bd8: fe040523 sb zero,-22(s0) +20400bdc: 100127b7 lui a5,0x10012 +20400be0: 03c78793 addi a5,a5,60 # 1001203c <__stack_size+0x1001183c> +20400be4: 0007a703 lw a4,0(a5) +20400be8: 100127b7 lui a5,0x10012 +20400bec: 03c78793 addi a5,a5,60 # 1001203c <__stack_size+0x1001183c> +20400bf0: fc377713 andi a4,a4,-61 +20400bf4: 00e7a023 sw a4,0(a5) +20400bf8: 100127b7 lui a5,0x10012 +20400bfc: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> +20400c00: 0007a703 lw a4,0(a5) +20400c04: 100127b7 lui a5,0x10012 +20400c08: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> +20400c0c: 03c76713 ori a4,a4,60 +20400c10: 00e7a023 sw a4,0(a5) +20400c14: 100247b7 lui a5,0x10024 +20400c18: 04078793 addi a5,a5,64 # 10024040 <__stack_size+0x10023840> +20400c1c: 00080737 lui a4,0x80 +20400c20: 00e7a023 sw a4,0(a5) +20400c24: 100247b7 lui a5,0x10024 +20400c28: 01078793 addi a5,a5,16 # 10024010 <__stack_size+0x10023810> +20400c2c: 0007a023 sw zero,0(a5) +20400c30: 100247b7 lui a5,0x10024 +20400c34: 01478793 addi a5,a5,20 # 10024014 <__stack_size+0x10023814> +20400c38: 00010737 lui a4,0x10 +20400c3c: fff70713 addi a4,a4,-1 # ffff <__stack_size+0xf7ff> +20400c40: 00e7a023 sw a4,0(a5) +20400c44: 100247b7 lui a5,0x10024 +20400c48: 00700713 li a4,7 +20400c4c: 00e7a023 sw a4,0(a5) # 10024000 <__stack_size+0x10023800> +20400c50: 100247b7 lui a5,0x10024 +20400c54: 00478793 addi a5,a5,4 # 10024004 <__stack_size+0x10023804> +20400c58: 00300713 li a4,3 +20400c5c: 00e7a023 sw a4,0(a5) +20400c60: 100247b7 lui a5,0x10024 +20400c64: 01878793 addi a5,a5,24 # 10024018 <__stack_size+0x10023818> +20400c68: 00200713 li a4,2 +20400c6c: 00e7a023 sw a4,0(a5) +20400c70: 00000013 nop +20400c74: 100247b7 lui a5,0x10024 +20400c78: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +20400c7c: 0007a783 lw a5,0(a5) +20400c80: fe07cae3 bltz a5,20400c74 +20400c84: fe844703 lbu a4,-24(s0) +20400c88: 100247b7 lui a5,0x10024 +20400c8c: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +20400c90: 00e7a023 sw a4,0(a5) +20400c94: 00000013 nop +20400c98: 100247b7 lui a5,0x10024 +20400c9c: 04c78793 addi a5,a5,76 # 1002404c <__stack_size+0x1002384c> +20400ca0: 0007a783 lw a5,0(a5) +20400ca4: fef42223 sw a5,-28(s0) +20400ca8: fe07c8e3 bltz a5,20400c98 +20400cac: 00000013 nop +20400cb0: 100247b7 lui a5,0x10024 +20400cb4: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +20400cb8: 0007a783 lw a5,0(a5) +20400cbc: fe07cae3 bltz a5,20400cb0 +20400cc0: fe944703 lbu a4,-23(s0) +20400cc4: 100247b7 lui a5,0x10024 +20400cc8: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +20400ccc: 00e7a023 sw a4,0(a5) +20400cd0: 00000013 nop +20400cd4: 100247b7 lui a5,0x10024 +20400cd8: 04c78793 addi a5,a5,76 # 1002404c <__stack_size+0x1002384c> +20400cdc: 0007a783 lw a5,0(a5) +20400ce0: fef42223 sw a5,-28(s0) +20400ce4: fe07c8e3 bltz a5,20400cd4 +20400ce8: fe442783 lw a5,-28(s0) +20400cec: 00879793 slli a5,a5,0x8 +20400cf0: 00078713 mv a4,a5 +20400cf4: 000107b7 lui a5,0x10 +20400cf8: f0078793 addi a5,a5,-256 # ff00 <__stack_size+0xf700> +20400cfc: 00f777b3 and a5,a4,a5 +20400d00: fef42623 sw a5,-20(s0) +20400d04: 00000013 nop +20400d08: 100247b7 lui a5,0x10024 +20400d0c: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +20400d10: 0007a783 lw a5,0(a5) +20400d14: fe07cae3 bltz a5,20400d08 +20400d18: fea44703 lbu a4,-22(s0) +20400d1c: 100247b7 lui a5,0x10024 +20400d20: 04878793 addi a5,a5,72 # 10024048 <__stack_size+0x10023848> +20400d24: 00e7a023 sw a4,0(a5) +20400d28: 00000013 nop +20400d2c: 100247b7 lui a5,0x10024 +20400d30: 04c78793 addi a5,a5,76 # 1002404c <__stack_size+0x1002384c> +20400d34: 0007a783 lw a5,0(a5) +20400d38: fef42223 sw a5,-28(s0) +20400d3c: fe07c8e3 bltz a5,20400d2c +20400d40: fe442783 lw a5,-28(s0) +20400d44: 0ff7f793 andi a5,a5,255 +20400d48: 00078713 mv a4,a5 +20400d4c: fec42783 lw a5,-20(s0) +20400d50: 00e787b3 add a5,a5,a4 +20400d54: fef42623 sw a5,-20(s0) +20400d58: 100247b7 lui a5,0x10024 +20400d5c: 01878793 addi a5,a5,24 # 10024018 <__stack_size+0x10023818> +20400d60: 0007a023 sw zero,0(a5) +20400d64: fec42783 lw a5,-20(s0) +20400d68: 3ff7f793 andi a5,a5,1023 +20400d6c: 00078513 mv a0,a5 +20400d70: 02c12403 lw s0,44(sp) +20400d74: 03010113 addi sp,sp,48 +20400d78: 00008067 ret + +20400d7c
: +20400d7c: fe010113 addi sp,sp,-32 +20400d80: 00112e23 sw ra,28(sp) +20400d84: 00812c23 sw s0,24(sp) +20400d88: 02010413 addi s0,sp,32 +20400d8c: 100127b7 lui a5,0x10012 +20400d90: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> +20400d94: 0007a683 lw a3,0(a5) +20400d98: 100127b7 lui a5,0x10012 +20400d9c: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> +20400da0: 00030737 lui a4,0x30 +20400da4: 00e6e733 or a4,a3,a4 +20400da8: 00e7a023 sw a4,0(a5) +20400dac: 900007b7 lui a5,0x90000 +20400db0: 00006737 lui a4,0x6 +20400db4: aa570713 addi a4,a4,-1371 # 5aa5 <__stack_size+0x52a5> +20400db8: 00e7a023 sw a4,0(a5) # 90000000 <_sp+0xfffc000> +20400dbc: 00a00513 li a0,10 +20400dc0: d69ff0ef jal ra,20400b28 +20400dc4: fea42423 sw a0,-24(s0) +20400dc8: fe842583 lw a1,-24(s0) +20400dcc: 204027b7 lui a5,0x20402 +20400dd0: 2f878513 addi a0,a5,760 # 204022f8 <__clzsi2+0x1b8> +20400dd4: c59ff0ef jal ra,20400a2c <__wrap_printf> +20400dd8: fe042623 sw zero,-20(s0) +20400ddc: 0300006f j 20400e0c +20400de0: fec42503 lw a0,-20(s0) +20400de4: db5ff0ef jal ra,20400b98 +20400de8: 00050793 mv a5,a0 +20400dec: 00078613 mv a2,a5 +20400df0: fec42583 lw a1,-20(s0) +20400df4: 204027b7 lui a5,0x20402 +20400df8: 31078513 addi a0,a5,784 # 20402310 <__clzsi2+0x1d0> +20400dfc: c31ff0ef jal ra,20400a2c <__wrap_printf> +20400e00: fec42783 lw a5,-20(s0) +20400e04: 00178793 addi a5,a5,1 +20400e08: fef42623 sw a5,-20(s0) +20400e0c: fec42703 lw a4,-20(s0) +20400e10: 00700793 li a5,7 +20400e14: fce7f6e3 bgeu a5,a4,20400de0 +20400e18: 800007b7 lui a5,0x80000 +20400e1c: 0007a783 lw a5,0(a5) # 80000000 <_sp+0xffffc000> +20400e20: 00078593 mv a1,a5 +20400e24: 204027b7 lui a5,0x20402 +20400e28: 32878513 addi a0,a5,808 # 20402328 <__clzsi2+0x1e8> +20400e2c: c01ff0ef jal ra,20400a2c <__wrap_printf> +20400e30: 204027b7 lui a5,0x20402 +20400e34: 35078513 addi a0,a5,848 # 20402350 <__clzsi2+0x210> +20400e38: bf5ff0ef jal ra,20400a2c <__wrap_printf> +20400e3c: 00000793 li a5,0 +20400e40: 00078513 mv a0,a5 +20400e44: 01c12083 lw ra,28(sp) +20400e48: 01812403 lw s0,24(sp) +20400e4c: 02010113 addi sp,sp,32 +20400e50: 00008067 ret + +20400e54 : +20400e54: ff010113 addi sp,sp,-16 +20400e58: 00812623 sw s0,12(sp) +20400e5c: 01010413 addi s0,sp,16 +20400e60: 0200c7b7 lui a5,0x200c +20400e64: ff878793 addi a5,a5,-8 # 200bff8 <__stack_size+0x200b7f8> +20400e68: 0007a783 lw a5,0(a5) +20400e6c: 00078513 mv a0,a5 +20400e70: 00c12403 lw s0,12(sp) +20400e74: 01010113 addi sp,sp,16 +20400e78: 00008067 ret + +20400e7c : +20400e7c: ff010113 addi sp,sp,-16 +20400e80: 00112623 sw ra,12(sp) +20400e84: 00812423 sw s0,8(sp) +20400e88: 01212223 sw s2,4(sp) +20400e8c: 01312023 sw s3,0(sp) +20400e90: 01010413 addi s0,sp,16 +20400e94: fc1ff0ef jal ra,20400e54 +20400e98: 00050793 mv a5,a0 +20400e9c: 00078913 mv s2,a5 +20400ea0: 00000993 li s3,0 +20400ea4: 00090793 mv a5,s2 +20400ea8: 00098813 mv a6,s3 +20400eac: 00078513 mv a0,a5 +20400eb0: 00080593 mv a1,a6 +20400eb4: 00c12083 lw ra,12(sp) +20400eb8: 00812403 lw s0,8(sp) +20400ebc: 00412903 lw s2,4(sp) +20400ec0: 00012983 lw s3,0(sp) +20400ec4: 01010113 addi sp,sp,16 +20400ec8: 00008067 ret + +20400ecc : +20400ecc: ff010113 addi sp,sp,-16 +20400ed0: 00812623 sw s0,12(sp) +20400ed4: 01010413 addi s0,sp,16 +20400ed8: 000087b7 lui a5,0x8 +20400edc: 00078513 mv a0,a5 +20400ee0: 00c12403 lw s0,12(sp) +20400ee4: 01010113 addi sp,sp,16 +20400ee8: 00008067 ret + +20400eec : +20400eec: fe010113 addi sp,sp,-32 +20400ef0: 00812e23 sw s0,28(sp) +20400ef4: 02010413 addi s0,sp,32 +20400ef8: fea42623 sw a0,-20(s0) +20400efc: feb42423 sw a1,-24(s0) +20400f00: fec42783 lw a5,-20(s0) +20400f04: 02f7f713 andi a4,a5,47 +20400f08: fe842783 lw a5,-24(s0) +20400f0c: 01079693 slli a3,a5,0x10 +20400f10: 001f07b7 lui a5,0x1f0 +20400f14: 00f6f7b3 and a5,a3,a5 +20400f18: 00f76733 or a4,a4,a5 +20400f1c: 400007b7 lui a5,0x40000 +20400f20: 00f76733 or a4,a4,a5 +20400f24: 100087b7 lui a5,0x10008 +20400f28: 00e7a023 sw a4,0(a5) # 10008000 <__stack_size+0x10007800> +20400f2c: 00000013 nop +20400f30: 100087b7 lui a5,0x10008 +20400f34: 0007a783 lw a5,0(a5) # 10008000 <__stack_size+0x10007800> +20400f38: fe07dce3 bgez a5,20400f30 +20400f3c: 100087b7 lui a5,0x10008 +20400f40: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20400f44: 0007a683 lw a3,0(a5) +20400f48: 100087b7 lui a5,0x10008 +20400f4c: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20400f50: ffff0737 lui a4,0xffff0 +20400f54: fff70713 addi a4,a4,-1 # fffeffff <_sp+0x7ffebfff> +20400f58: 00e6f733 and a4,a3,a4 +20400f5c: 00e7a023 sw a4,0(a5) +20400f60: 00000013 nop +20400f64: 01c12403 lw s0,28(sp) +20400f68: 02010113 addi sp,sp,32 +20400f6c: 00008067 ret + +20400f70 : +20400f70: fc010113 addi sp,sp,-64 +20400f74: 02112e23 sw ra,60(sp) +20400f78: 02812c23 sw s0,56(sp) +20400f7c: 04010413 addi s0,sp,64 +20400f80: fca42e23 sw a0,-36(s0) +20400f84: fcb42c23 sw a1,-40(s0) +20400f88: fcc42a23 sw a2,-44(s0) +20400f8c: fcd42823 sw a3,-48(s0) +20400f90: fce42623 sw a4,-52(s0) +20400f94: 100087b7 lui a5,0x10008 +20400f98: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20400f9c: 0007a703 lw a4,0(a5) +20400fa0: 000107b7 lui a5,0x10 +20400fa4: 00f777b3 and a5,a4,a5 +20400fa8: 00078863 beqz a5,20400fb8 +20400fac: 01000593 li a1,16 +20400fb0: 00400513 li a0,4 +20400fb4: f39ff0ef jal ra,20400eec +20400fb8: fe042623 sw zero,-20(s0) +20400fbc: fdc42783 lw a5,-36(s0) +20400fc0: 01179793 slli a5,a5,0x11 +20400fc4: 00078713 mv a4,a5 +20400fc8: 000207b7 lui a5,0x20 +20400fcc: 00f777b3 and a5,a4,a5 +20400fd0: fec42703 lw a4,-20(s0) +20400fd4: 00f767b3 or a5,a4,a5 +20400fd8: fef42623 sw a5,-20(s0) +20400fdc: fd842783 lw a5,-40(s0) +20400fe0: 02078c63 beqz a5,20401018 +20400fe4: fec42703 lw a4,-20(s0) +20400fe8: 000407b7 lui a5,0x40 +20400fec: 00f767b3 or a5,a4,a5 +20400ff0: fef42623 sw a5,-20(s0) +20400ff4: 100087b7 lui a5,0x10008 +20400ff8: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20400ffc: fec42703 lw a4,-20(s0) +20401000: 00e7a023 sw a4,0(a5) +20401004: 100087b7 lui a5,0x10008 +20401008: 00c78793 addi a5,a5,12 # 1000800c <__stack_size+0x1000780c> +2040100c: 10000713 li a4,256 +20401010: 00e7a023 sw a4,0(a5) +20401014: 0ec0006f j 20401100 +20401018: 100147b7 lui a5,0x10014 +2040101c: 00800713 li a4,8 +20401020: 00e7a023 sw a4,0(a5) # 10014000 <__stack_size+0x10013800> +20401024: fec42703 lw a4,-20(s0) +20401028: 000407b7 lui a5,0x40 +2040102c: 00f767b3 or a5,a4,a5 +20401030: fef42623 sw a5,-20(s0) +20401034: fd442783 lw a5,-44(s0) +20401038: 0077f793 andi a5,a5,7 +2040103c: fec42703 lw a4,-20(s0) +20401040: 00f767b3 or a5,a4,a5 +20401044: fef42623 sw a5,-20(s0) +20401048: fd042783 lw a5,-48(s0) +2040104c: 00479793 slli a5,a5,0x4 +20401050: 3f07f793 andi a5,a5,1008 +20401054: fec42703 lw a4,-20(s0) +20401058: 00f767b3 or a5,a4,a5 +2040105c: fef42623 sw a5,-20(s0) +20401060: fcc42783 lw a5,-52(s0) +20401064: 00a79793 slli a5,a5,0xa +20401068: 00078713 mv a4,a5 +2040106c: 000017b7 lui a5,0x1 +20401070: c0078793 addi a5,a5,-1024 # c00 <__stack_size+0x400> +20401074: 00f777b3 and a5,a4,a5 +20401078: fec42703 lw a4,-20(s0) +2040107c: 00f767b3 or a5,a4,a5 +20401080: fef42623 sw a5,-20(s0) +20401084: 100087b7 lui a5,0x10008 +20401088: 00c78793 addi a5,a5,12 # 1000800c <__stack_size+0x1000780c> +2040108c: 10000713 li a4,256 +20401090: 00e7a023 sw a4,0(a5) +20401094: 100087b7 lui a5,0x10008 +20401098: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +2040109c: fec42703 lw a4,-20(s0) +204010a0: 00e7a023 sw a4,0(a5) +204010a4: 100087b7 lui a5,0x10008 +204010a8: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +204010ac: 0007a683 lw a3,0(a5) +204010b0: 100087b7 lui a5,0x10008 +204010b4: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +204010b8: fffc0737 lui a4,0xfffc0 +204010bc: fff70713 addi a4,a4,-1 # fffbffff <_sp+0x7ffbbfff> +204010c0: 00e6f733 and a4,a3,a4 +204010c4: 00e7a023 sw a4,0(a5) +204010c8: d8dff0ef jal ra,20400e54 +204010cc: fea42423 sw a0,-24(s0) +204010d0: 00000013 nop +204010d4: d81ff0ef jal ra,20400e54 +204010d8: 00050713 mv a4,a0 +204010dc: fe842783 lw a5,-24(s0) +204010e0: 40f70733 sub a4,a4,a5 +204010e4: 00300793 li a5,3 +204010e8: fee7f6e3 bgeu a5,a4,204010d4 +204010ec: 00000013 nop +204010f0: 100087b7 lui a5,0x10008 +204010f4: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +204010f8: 0007a783 lw a5,0(a5) +204010fc: fe07dae3 bgez a5,204010f0 +20401100: 100087b7 lui a5,0x10008 +20401104: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20401108: 0007a683 lw a3,0(a5) +2040110c: 100087b7 lui a5,0x10008 +20401110: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> +20401114: 00010737 lui a4,0x10 +20401118: 00e6e733 or a4,a3,a4 +2040111c: 00e7a023 sw a4,0(a5) +20401120: 00000013 nop +20401124: 03c12083 lw ra,60(sp) +20401128: 03812403 lw s0,56(sp) +2040112c: 04010113 addi sp,sp,64 +20401130: 00008067 ret + +20401134 : +20401134: ff010113 addi sp,sp,-16 +20401138: 00112623 sw ra,12(sp) +2040113c: 00812423 sw s0,8(sp) +20401140: 01010413 addi s0,sp,16 +20401144: 100007b7 lui a5,0x10000 +20401148: 07078793 addi a5,a5,112 # 10000070 <__stack_size+0xffff870> +2040114c: 0007a683 lw a3,0(a5) +20401150: 100007b7 lui a5,0x10000 +20401154: 07078793 addi a5,a5,112 # 10000070 <__stack_size+0xffff870> +20401158: c0000737 lui a4,0xc0000 +2040115c: fff70713 addi a4,a4,-1 # bfffffff <_sp+0x3fffbfff> +20401160: 00e6f733 and a4,a3,a4 +20401164: 00e7a023 sw a4,0(a5) +20401168: 01000593 li a1,16 +2040116c: 00400513 li a0,4 +20401170: d7dff0ef jal ra,20400eec +20401174: 00000013 nop +20401178: 00c12083 lw ra,12(sp) +2040117c: 00812403 lw s0,8(sp) +20401180: 01010113 addi sp,sp,16 +20401184: 00008067 ret + +20401188 : +20401188: fc010113 addi sp,sp,-64 +2040118c: 02112e23 sw ra,60(sp) +20401190: 02812c23 sw s0,56(sp) +20401194: 02912a23 sw s1,52(sp) +20401198: 04010413 addi s0,sp,64 +2040119c: fca42623 sw a0,-52(s0) +204011a0: d2dff0ef jal ra,20400ecc +204011a4: fea42623 sw a0,-20(s0) +204011a8: cadff0ef jal ra,20400e54 +204011ac: fea42423 sw a0,-24(s0) +204011b0: ca5ff0ef jal ra,20400e54 +204011b4: fea42223 sw a0,-28(s0) +204011b8: fe442703 lw a4,-28(s0) +204011bc: fe842783 lw a5,-24(s0) +204011c0: fef708e3 beq a4,a5,204011b0 +204011c4: b00027f3 csrr a5,mcycle +204011c8: fef42023 sw a5,-32(s0) +204011cc: fe042783 lw a5,-32(s0) +204011d0: fcf42e23 sw a5,-36(s0) +204011d4: c81ff0ef jal ra,20400e54 +204011d8: 00050713 mv a4,a0 +204011dc: fe442783 lw a5,-28(s0) +204011e0: 40f707b3 sub a5,a4,a5 +204011e4: fcf42c23 sw a5,-40(s0) +204011e8: fd842703 lw a4,-40(s0) +204011ec: fcc42783 lw a5,-52(s0) +204011f0: fef762e3 bltu a4,a5,204011d4 +204011f4: b00027f3 csrr a5,mcycle +204011f8: fcf42a23 sw a5,-44(s0) +204011fc: fd442703 lw a4,-44(s0) +20401200: fdc42783 lw a5,-36(s0) +20401204: 40f707b3 sub a5,a4,a5 +20401208: fcf42823 sw a5,-48(s0) +2040120c: fd842583 lw a1,-40(s0) +20401210: fd042503 lw a0,-48(s0) +20401214: 681000ef jal ra,20402094 <__udivsi3> +20401218: 00050793 mv a5,a0 +2040121c: fec42583 lw a1,-20(s0) +20401220: 00078513 mv a0,a5 +20401224: 645000ef jal ra,20402068 <__mulsi3> +20401228: 00050793 mv a5,a0 +2040122c: 00078493 mv s1,a5 +20401230: fd042783 lw a5,-48(s0) +20401234: fd842583 lw a1,-40(s0) +20401238: 00078513 mv a0,a5 +2040123c: 6a1000ef jal ra,204020dc <__umodsi3> +20401240: 00050793 mv a5,a0 +20401244: fec42583 lw a1,-20(s0) +20401248: 00078513 mv a0,a5 +2040124c: 61d000ef jal ra,20402068 <__mulsi3> +20401250: 00050793 mv a5,a0 +20401254: fd842583 lw a1,-40(s0) +20401258: 00078513 mv a0,a5 +2040125c: 639000ef jal ra,20402094 <__udivsi3> +20401260: 00050793 mv a5,a0 +20401264: 00f487b3 add a5,s1,a5 +20401268: 00078513 mv a0,a5 +2040126c: 03c12083 lw ra,60(sp) +20401270: 03812403 lw s0,56(sp) +20401274: 03412483 lw s1,52(sp) +20401278: 04010113 addi sp,sp,64 +2040127c: 00008067 ret + +20401280 : +20401280: ff010113 addi sp,sp,-16 +20401284: 00112623 sw ra,12(sp) +20401288: 00812423 sw s0,8(sp) +2040128c: 01010413 addi s0,sp,16 +20401290: 800007b7 lui a5,0x80000 +20401294: 4307a783 lw a5,1072(a5) # 80000430 <_sp+0xffffc430> +20401298: 02079063 bnez a5,204012b8 +2040129c: 00100513 li a0,1 +204012a0: ee9ff0ef jal ra,20401188 +204012a4: 00a00513 li a0,10 +204012a8: ee1ff0ef jal ra,20401188 +204012ac: 00050713 mv a4,a0 +204012b0: 800007b7 lui a5,0x80000 +204012b4: 42e7a823 sw a4,1072(a5) # 80000430 <_sp+0xffffc430> +204012b8: 800007b7 lui a5,0x80000 +204012bc: 4307a783 lw a5,1072(a5) # 80000430 <_sp+0xffffc430> +204012c0: 00078513 mv a0,a5 +204012c4: 00c12083 lw ra,12(sp) +204012c8: 00812403 lw s0,8(sp) +204012cc: 01010113 addi sp,sp,16 +204012d0: 00008067 ret + +204012d4 : +204012d4: fe010113 addi sp,sp,-32 +204012d8: 00112e23 sw ra,28(sp) +204012dc: 00812c23 sw s0,24(sp) +204012e0: 02010413 addi s0,sp,32 +204012e4: fea42623 sw a0,-20(s0) +204012e8: 100127b7 lui a5,0x10012 +204012ec: 03c78793 addi a5,a5,60 # 1001203c <__stack_size+0x1001183c> +204012f0: 0007a683 lw a3,0(a5) +204012f4: 100127b7 lui a5,0x10012 +204012f8: 03c78793 addi a5,a5,60 # 1001203c <__stack_size+0x1001183c> +204012fc: fffd0737 lui a4,0xfffd0 +20401300: fff70713 addi a4,a4,-1 # fffcffff <_sp+0x7ffcbfff> +20401304: 00e6f733 and a4,a3,a4 +20401308: 00e7a023 sw a4,0(a5) +2040130c: 100127b7 lui a5,0x10012 +20401310: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> +20401314: 0007a683 lw a3,0(a5) +20401318: 100127b7 lui a5,0x10012 +2040131c: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> +20401320: 00030737 lui a4,0x30 +20401324: 00e6e733 or a4,a3,a4 +20401328: 00e7a023 sw a4,0(a5) +2040132c: f55ff0ef jal ra,20401280 +20401330: 00050793 mv a5,a0 +20401334: fec42583 lw a1,-20(s0) +20401338: 00078513 mv a0,a5 +2040133c: 559000ef jal ra,20402094 <__udivsi3> +20401340: 00050793 mv a5,a0 +20401344: 00078713 mv a4,a5 +20401348: 100137b7 lui a5,0x10013 +2040134c: 01878793 addi a5,a5,24 # 10013018 <__stack_size+0x10012818> +20401350: fff70713 addi a4,a4,-1 # 2ffff <__stack_size+0x2f7ff> +20401354: 00e7a023 sw a4,0(a5) +20401358: 100137b7 lui a5,0x10013 +2040135c: 00878793 addi a5,a5,8 # 10013008 <__stack_size+0x10012808> +20401360: 0007a703 lw a4,0(a5) +20401364: 100137b7 lui a5,0x10013 +20401368: 00878793 addi a5,a5,8 # 10013008 <__stack_size+0x10012808> +2040136c: 00176713 ori a4,a4,1 +20401370: 00e7a023 sw a4,0(a5) +20401374: 00000013 nop +20401378: 01c12083 lw ra,28(sp) +2040137c: 01812403 lw s0,24(sp) +20401380: 02010113 addi sp,sp,32 +20401384: 00008067 ret + +20401388 : +20401388: fe010113 addi sp,sp,-32 +2040138c: 00112e23 sw ra,28(sp) +20401390: 00812c23 sw s0,24(sp) +20401394: 02010413 addi s0,sp,32 +20401398: fea42623 sw a0,-20(s0) +2040139c: feb42423 sw a1,-24(s0) +204013a0: 00500613 li a2,5 +204013a4: 204027b7 lui a5,0x20402 +204013a8: 36478593 addi a1,a5,868 # 20402364 <__clzsi2+0x224> +204013ac: 00100513 li a0,1 +204013b0: 0e4000ef jal ra,20401494 <__wrap_write> +204013b4: fec42783 lw a5,-20(s0) +204013b8: 00178793 addi a5,a5,1 +204013bc: 00078513 mv a0,a5 +204013c0: 1f0000ef jal ra,204015b0 <__wrap__exit> + +204013c4 <_init>: +204013c4: fe010113 addi sp,sp,-32 +204013c8: 00112e23 sw ra,28(sp) +204013cc: 00812c23 sw s0,24(sp) +204013d0: 02010413 addi s0,sp,32 +204013d4: d61ff0ef jal ra,20401134 +204013d8: 00100713 li a4,1 +204013dc: 01f00693 li a3,31 +204013e0: 00100613 li a2,1 +204013e4: 00000593 li a1,0 +204013e8: 00000513 li a0,0 +204013ec: b85ff0ef jal ra,20400f70 +204013f0: 0001c7b7 lui a5,0x1c +204013f4: 20078513 addi a0,a5,512 # 1c200 <__stack_size+0x1ba00> +204013f8: eddff0ef jal ra,204012d4 +204013fc: e85ff0ef jal ra,20401280 +20401400: 00050793 mv a5,a0 +20401404: 00078593 mv a1,a5 +20401408: 204027b7 lui a5,0x20402 +2040140c: 36c78513 addi a0,a5,876 # 2040236c <__clzsi2+0x22c> +20401410: e1cff0ef jal ra,20400a2c <__wrap_printf> +20401414: 204007b7 lui a5,0x20400 +20401418: 09c78793 addi a5,a5,156 # 2040009c +2040141c: 30579073 csrw mtvec,a5 +20401420: 301027f3 csrr a5,misa +20401424: fef42623 sw a5,-20(s0) +20401428: fec42783 lw a5,-20(s0) +2040142c: 0207f793 andi a5,a5,32 +20401430: 00078863 beqz a5,20401440 <_init+0x7c> +20401434: 000067b7 lui a5,0x6 +20401438: 30079073 csrw mstatus,a5 +2040143c: 00305073 csrwi fcsr,0 +20401440: 00000013 nop +20401444: 01c12083 lw ra,28(sp) +20401448: 01812403 lw s0,24(sp) +2040144c: 02010113 addi sp,sp,32 +20401450: 00008067 ret + +20401454 <_fini>: +20401454: ff010113 addi sp,sp,-16 +20401458: 00812623 sw s0,12(sp) +2040145c: 01010413 addi s0,sp,16 +20401460: 00000013 nop +20401464: 00c12403 lw s0,12(sp) +20401468: 01010113 addi sp,sp,16 +2040146c: 00008067 ret + +20401470 <_stub>: +20401470: fe010113 addi sp,sp,-32 +20401474: 00812e23 sw s0,28(sp) +20401478: 02010413 addi s0,sp,32 +2040147c: fea42623 sw a0,-20(s0) +20401480: fff00793 li a5,-1 +20401484: 00078513 mv a0,a5 +20401488: 01c12403 lw s0,28(sp) +2040148c: 02010113 addi sp,sp,32 +20401490: 00008067 ret + +20401494 <__wrap_write>: +20401494: fd010113 addi sp,sp,-48 +20401498: 02112623 sw ra,44(sp) +2040149c: 02812423 sw s0,40(sp) +204014a0: 03010413 addi s0,sp,48 +204014a4: fca42e23 sw a0,-36(s0) +204014a8: fcb42c23 sw a1,-40(s0) +204014ac: fcc42a23 sw a2,-44(s0) +204014b0: fd842783 lw a5,-40(s0) +204014b4: fef42423 sw a5,-24(s0) +204014b8: fdc42503 lw a0,-36(s0) +204014bc: 0b0000ef jal ra,2040156c <__wrap_isatty> +204014c0: 00050793 mv a5,a0 +204014c4: 08078463 beqz a5,2040154c <__wrap_write+0xb8> +204014c8: fe042623 sw zero,-20(s0) +204014cc: 06c0006f j 20401538 <__wrap_write+0xa4> +204014d0: 00000013 nop +204014d4: 100137b7 lui a5,0x10013 +204014d8: 0007a783 lw a5,0(a5) # 10013000 <__stack_size+0x10012800> +204014dc: fe07cce3 bltz a5,204014d4 <__wrap_write+0x40> +204014e0: fe842703 lw a4,-24(s0) +204014e4: fec42783 lw a5,-20(s0) +204014e8: 00f707b3 add a5,a4,a5 +204014ec: 0007c703 lbu a4,0(a5) +204014f0: 100137b7 lui a5,0x10013 +204014f4: 00e7a023 sw a4,0(a5) # 10013000 <__stack_size+0x10012800> +204014f8: fe842703 lw a4,-24(s0) +204014fc: fec42783 lw a5,-20(s0) +20401500: 00f707b3 add a5,a4,a5 +20401504: 0007c703 lbu a4,0(a5) +20401508: 00a00793 li a5,10 +2040150c: 02f71063 bne a4,a5,2040152c <__wrap_write+0x98> +20401510: 00000013 nop +20401514: 100137b7 lui a5,0x10013 +20401518: 0007a783 lw a5,0(a5) # 10013000 <__stack_size+0x10012800> +2040151c: fe07cce3 bltz a5,20401514 <__wrap_write+0x80> +20401520: 100137b7 lui a5,0x10013 +20401524: 00d00713 li a4,13 +20401528: 00e7a023 sw a4,0(a5) # 10013000 <__stack_size+0x10012800> +2040152c: fec42783 lw a5,-20(s0) +20401530: 00178793 addi a5,a5,1 +20401534: fef42623 sw a5,-20(s0) +20401538: fec42703 lw a4,-20(s0) +2040153c: fd442783 lw a5,-44(s0) +20401540: f8f768e3 bltu a4,a5,204014d0 <__wrap_write+0x3c> +20401544: fd442783 lw a5,-44(s0) +20401548: 0100006f j 20401558 <__wrap_write+0xc4> +2040154c: 00900513 li a0,9 +20401550: f21ff0ef jal ra,20401470 <_stub> +20401554: 00050793 mv a5,a0 +20401558: 00078513 mv a0,a5 +2040155c: 02c12083 lw ra,44(sp) +20401560: 02812403 lw s0,40(sp) +20401564: 03010113 addi sp,sp,48 +20401568: 00008067 ret + +2040156c <__wrap_isatty>: +2040156c: fe010113 addi sp,sp,-32 +20401570: 00812e23 sw s0,28(sp) +20401574: 02010413 addi s0,sp,32 +20401578: fea42623 sw a0,-20(s0) +2040157c: fec42703 lw a4,-20(s0) +20401580: 00100793 li a5,1 +20401584: 00f70863 beq a4,a5,20401594 <__wrap_isatty+0x28> +20401588: fec42703 lw a4,-20(s0) +2040158c: 00200793 li a5,2 +20401590: 00f71663 bne a4,a5,2040159c <__wrap_isatty+0x30> +20401594: 00100793 li a5,1 +20401598: 0080006f j 204015a0 <__wrap_isatty+0x34> +2040159c: 00000793 li a5,0 +204015a0: 00078513 mv a0,a5 +204015a4: 01c12403 lw s0,28(sp) +204015a8: 02010113 addi sp,sp,32 +204015ac: 00008067 ret + +204015b0 <__wrap__exit>: +204015b0: fc010113 addi sp,sp,-64 +204015b4: 02112e23 sw ra,60(sp) +204015b8: 02812c23 sw s0,56(sp) +204015bc: 04010413 addi s0,sp,64 +204015c0: fca42623 sw a0,-52(s0) +204015c4: 204027b7 lui a5,0x20402 +204015c8: 38478793 addi a5,a5,900 # 20402384 <__clzsi2+0x244> +204015cc: 0007a883 lw a7,0(a5) +204015d0: 0047a803 lw a6,4(a5) +204015d4: 0087a503 lw a0,8(a5) +204015d8: 00c7a583 lw a1,12(a5) +204015dc: 0107a603 lw a2,16(a5) +204015e0: 0147a683 lw a3,20(a5) +204015e4: 0187a703 lw a4,24(a5) +204015e8: fd142823 sw a7,-48(s0) +204015ec: fd042a23 sw a6,-44(s0) +204015f0: fca42c23 sw a0,-40(s0) +204015f4: fcb42e23 sw a1,-36(s0) +204015f8: fec42023 sw a2,-32(s0) +204015fc: fed42223 sw a3,-28(s0) +20401600: fee42423 sw a4,-24(s0) +20401604: 01c7d783 lhu a5,28(a5) +20401608: fef41623 sh a5,-20(s0) +2040160c: fd040793 addi a5,s0,-48 +20401610: 01d00613 li a2,29 +20401614: 00078593 mv a1,a5 +20401618: 00200513 li a0,2 +2040161c: e79ff0ef jal ra,20401494 <__wrap_write> +20401620: 00100613 li a2,1 +20401624: 204027b7 lui a5,0x20402 +20401628: 38078593 addi a1,a5,896 # 20402380 <__clzsi2+0x240> +2040162c: 00200513 li a0,2 +20401630: e65ff0ef jal ra,20401494 <__wrap_write> +20401634: 0000006f j 20401634 <__wrap__exit+0x84> + +20401638 : +20401638: 00050593 mv a1,a0 +2040163c: 00000693 li a3,0 +20401640: 00000613 li a2,0 +20401644: 00000513 li a0,0 +20401648: 1740006f j 204017bc <__register_exitproc> + +2040164c : +2040164c: ff010113 addi sp,sp,-16 +20401650: 00000593 li a1,0 +20401654: 00812423 sw s0,8(sp) +20401658: 00112623 sw ra,12(sp) +2040165c: 00050413 mv s0,a0 +20401660: 1fc000ef jal ra,2040185c <__call_exitprocs> +20401664: 5fbff797 auipc a5,0x5fbff +20401668: dc478793 addi a5,a5,-572 # 80000428 <_global_impure_ptr> +2040166c: 0007a503 lw a0,0(a5) +20401670: 03c52783 lw a5,60(a0) +20401674: 00078463 beqz a5,2040167c +20401678: 000780e7 jalr a5 +2040167c: 00040513 mv a0,s0 +20401680: f31ff0ef jal ra,204015b0 <__wrap__exit> + +20401684 <__libc_fini_array>: +20401684: ff010113 addi sp,sp,-16 +20401688: 00812423 sw s0,8(sp) +2040168c: 00001797 auipc a5,0x1 +20401690: e5878793 addi a5,a5,-424 # 204024e4 <__fini_array_end> +20401694: 00001417 auipc s0,0x1 +20401698: e5040413 addi s0,s0,-432 # 204024e4 <__fini_array_end> +2040169c: 40f40433 sub s0,s0,a5 +204016a0: 00112623 sw ra,12(sp) +204016a4: 00912223 sw s1,4(sp) +204016a8: 40245413 srai s0,s0,0x2 +204016ac: 02040263 beqz s0,204016d0 <__libc_fini_array+0x4c> +204016b0: 00241493 slli s1,s0,0x2 +204016b4: ffc48493 addi s1,s1,-4 +204016b8: 00f484b3 add s1,s1,a5 +204016bc: 0004a783 lw a5,0(s1) +204016c0: fff40413 addi s0,s0,-1 +204016c4: ffc48493 addi s1,s1,-4 +204016c8: 000780e7 jalr a5 +204016cc: fe0418e3 bnez s0,204016bc <__libc_fini_array+0x38> +204016d0: 00c12083 lw ra,12(sp) +204016d4: 00812403 lw s0,8(sp) +204016d8: 00412483 lw s1,4(sp) +204016dc: 01010113 addi sp,sp,16 +204016e0: 00008067 ret + +204016e4 <__libc_init_array>: +204016e4: ff010113 addi sp,sp,-16 +204016e8: 00812423 sw s0,8(sp) +204016ec: 01212023 sw s2,0(sp) +204016f0: 00001417 auipc s0,0x1 +204016f4: df040413 addi s0,s0,-528 # 204024e0 <__init_array_start> +204016f8: 00001917 auipc s2,0x1 +204016fc: de890913 addi s2,s2,-536 # 204024e0 <__init_array_start> +20401700: 40890933 sub s2,s2,s0 +20401704: 00112623 sw ra,12(sp) +20401708: 00912223 sw s1,4(sp) +2040170c: 40295913 srai s2,s2,0x2 +20401710: 00090e63 beqz s2,2040172c <__libc_init_array+0x48> +20401714: 00000493 li s1,0 +20401718: 00042783 lw a5,0(s0) +2040171c: 00148493 addi s1,s1,1 +20401720: 00440413 addi s0,s0,4 +20401724: 000780e7 jalr a5 +20401728: fe9918e3 bne s2,s1,20401718 <__libc_init_array+0x34> +2040172c: 00001417 auipc s0,0x1 +20401730: db440413 addi s0,s0,-588 # 204024e0 <__init_array_start> +20401734: 00001917 auipc s2,0x1 +20401738: db090913 addi s2,s2,-592 # 204024e4 <__fini_array_end> +2040173c: 40890933 sub s2,s2,s0 +20401740: 40295913 srai s2,s2,0x2 +20401744: 00090e63 beqz s2,20401760 <__libc_init_array+0x7c> +20401748: 00000493 li s1,0 +2040174c: 00042783 lw a5,0(s0) +20401750: 00148493 addi s1,s1,1 +20401754: 00440413 addi s0,s0,4 +20401758: 000780e7 jalr a5 +2040175c: fe9918e3 bne s2,s1,2040174c <__libc_init_array+0x68> +20401760: 00c12083 lw ra,12(sp) +20401764: 00812403 lw s0,8(sp) +20401768: 00412483 lw s1,4(sp) +2040176c: 00012903 lw s2,0(sp) +20401770: 01010113 addi sp,sp,16 +20401774: 00008067 ret + +20401778 : +20401778: 02058463 beqz a1,204017a0 +2040177c: 00054783 lbu a5,0(a0) +20401780: 02078a63 beqz a5,204017b4 +20401784: 00b506b3 add a3,a0,a1 +20401788: 00050793 mv a5,a0 +2040178c: 00c0006f j 20401798 +20401790: 0007c703 lbu a4,0(a5) +20401794: 00070a63 beqz a4,204017a8 +20401798: 00178793 addi a5,a5,1 +2040179c: fed79ae3 bne a5,a3,20401790 +204017a0: 00058513 mv a0,a1 +204017a4: 00008067 ret +204017a8: 40a785b3 sub a1,a5,a0 +204017ac: 00058513 mv a0,a1 +204017b0: 00008067 ret +204017b4: 00000593 li a1,0 +204017b8: fe9ff06f j 204017a0 + +204017bc <__register_exitproc>: +204017bc: 5fbff797 auipc a5,0x5fbff +204017c0: c6c78793 addi a5,a5,-916 # 80000428 <_global_impure_ptr> +204017c4: 0007a703 lw a4,0(a5) +204017c8: 14872783 lw a5,328(a4) +204017cc: 04078c63 beqz a5,20401824 <__register_exitproc+0x68> +204017d0: 0047a703 lw a4,4(a5) +204017d4: 01f00813 li a6,31 +204017d8: 06e84e63 blt a6,a4,20401854 <__register_exitproc+0x98> +204017dc: 00271813 slli a6,a4,0x2 +204017e0: 02050663 beqz a0,2040180c <__register_exitproc+0x50> +204017e4: 01078333 add t1,a5,a6 +204017e8: 08c32423 sw a2,136(t1) +204017ec: 1887a883 lw a7,392(a5) +204017f0: 00100613 li a2,1 +204017f4: 00e61633 sll a2,a2,a4 +204017f8: 00c8e8b3 or a7,a7,a2 +204017fc: 1917a423 sw a7,392(a5) +20401800: 10d32423 sw a3,264(t1) +20401804: 00200693 li a3,2 +20401808: 02d50463 beq a0,a3,20401830 <__register_exitproc+0x74> +2040180c: 00170713 addi a4,a4,1 +20401810: 00e7a223 sw a4,4(a5) +20401814: 010787b3 add a5,a5,a6 +20401818: 00b7a423 sw a1,8(a5) +2040181c: 00000513 li a0,0 +20401820: 00008067 ret +20401824: 14c70793 addi a5,a4,332 +20401828: 14f72423 sw a5,328(a4) +2040182c: fa5ff06f j 204017d0 <__register_exitproc+0x14> +20401830: 18c7a683 lw a3,396(a5) +20401834: 00170713 addi a4,a4,1 +20401838: 00e7a223 sw a4,4(a5) +2040183c: 00c6e633 or a2,a3,a2 +20401840: 18c7a623 sw a2,396(a5) +20401844: 010787b3 add a5,a5,a6 +20401848: 00b7a423 sw a1,8(a5) +2040184c: 00000513 li a0,0 +20401850: 00008067 ret +20401854: fff00513 li a0,-1 +20401858: 00008067 ret + +2040185c <__call_exitprocs>: +2040185c: fd010113 addi sp,sp,-48 +20401860: 5fbff797 auipc a5,0x5fbff +20401864: bc878793 addi a5,a5,-1080 # 80000428 <_global_impure_ptr> +20401868: 01812423 sw s8,8(sp) +2040186c: 0007ac03 lw s8,0(a5) +20401870: 01312e23 sw s3,28(sp) +20401874: 01412c23 sw s4,24(sp) +20401878: 01512a23 sw s5,20(sp) +2040187c: 01612823 sw s6,16(sp) +20401880: 02112623 sw ra,44(sp) +20401884: 02812423 sw s0,40(sp) +20401888: 02912223 sw s1,36(sp) +2040188c: 03212023 sw s2,32(sp) +20401890: 01712623 sw s7,12(sp) +20401894: 00050a93 mv s5,a0 +20401898: 00058b13 mv s6,a1 +2040189c: 00100a13 li s4,1 +204018a0: fff00993 li s3,-1 +204018a4: 148c2903 lw s2,328(s8) +204018a8: 02090863 beqz s2,204018d8 <__call_exitprocs+0x7c> +204018ac: 00492483 lw s1,4(s2) +204018b0: fff48413 addi s0,s1,-1 +204018b4: 02044263 bltz s0,204018d8 <__call_exitprocs+0x7c> +204018b8: 00249493 slli s1,s1,0x2 +204018bc: 009904b3 add s1,s2,s1 +204018c0: 040b0463 beqz s6,20401908 <__call_exitprocs+0xac> +204018c4: 1044a783 lw a5,260(s1) +204018c8: 05678063 beq a5,s6,20401908 <__call_exitprocs+0xac> +204018cc: fff40413 addi s0,s0,-1 +204018d0: ffc48493 addi s1,s1,-4 +204018d4: ff3416e3 bne s0,s3,204018c0 <__call_exitprocs+0x64> +204018d8: 02c12083 lw ra,44(sp) +204018dc: 02812403 lw s0,40(sp) +204018e0: 02412483 lw s1,36(sp) +204018e4: 02012903 lw s2,32(sp) +204018e8: 01c12983 lw s3,28(sp) +204018ec: 01812a03 lw s4,24(sp) +204018f0: 01412a83 lw s5,20(sp) +204018f4: 01012b03 lw s6,16(sp) +204018f8: 00c12b83 lw s7,12(sp) +204018fc: 00812c03 lw s8,8(sp) +20401900: 03010113 addi sp,sp,48 +20401904: 00008067 ret +20401908: 00492783 lw a5,4(s2) +2040190c: 0044a683 lw a3,4(s1) +20401910: fff78793 addi a5,a5,-1 +20401914: 04878a63 beq a5,s0,20401968 <__call_exitprocs+0x10c> +20401918: 0004a223 sw zero,4(s1) +2040191c: fa0688e3 beqz a3,204018cc <__call_exitprocs+0x70> +20401920: 18892783 lw a5,392(s2) +20401924: 008a1733 sll a4,s4,s0 +20401928: 00492b83 lw s7,4(s2) +2040192c: 00f777b3 and a5,a4,a5 +20401930: 00079e63 bnez a5,2040194c <__call_exitprocs+0xf0> +20401934: 000680e7 jalr a3 +20401938: 00492783 lw a5,4(s2) +2040193c: f77794e3 bne a5,s7,204018a4 <__call_exitprocs+0x48> +20401940: 148c2783 lw a5,328(s8) +20401944: f92784e3 beq a5,s2,204018cc <__call_exitprocs+0x70> +20401948: f5dff06f j 204018a4 <__call_exitprocs+0x48> +2040194c: 18c92783 lw a5,396(s2) +20401950: 0844a583 lw a1,132(s1) +20401954: 00f77733 and a4,a4,a5 +20401958: 00071c63 bnez a4,20401970 <__call_exitprocs+0x114> +2040195c: 000a8513 mv a0,s5 +20401960: 000680e7 jalr a3 +20401964: fd5ff06f j 20401938 <__call_exitprocs+0xdc> +20401968: 00892223 sw s0,4(s2) +2040196c: fb1ff06f j 2040191c <__call_exitprocs+0xc0> +20401970: 00058513 mv a0,a1 +20401974: 000680e7 jalr a3 +20401978: fc1ff06f j 20401938 <__call_exitprocs+0xdc> + +2040197c <__muldf3>: +2040197c: fd010113 addi sp,sp,-48 +20401980: 01312e23 sw s3,28(sp) +20401984: 0145d993 srli s3,a1,0x14 +20401988: 02812423 sw s0,40(sp) +2040198c: 02912223 sw s1,36(sp) +20401990: 01412c23 sw s4,24(sp) +20401994: 01512a23 sw s5,20(sp) +20401998: 01612823 sw s6,16(sp) +2040199c: 00c59493 slli s1,a1,0xc +204019a0: 02112623 sw ra,44(sp) +204019a4: 03212023 sw s2,32(sp) +204019a8: 01712623 sw s7,12(sp) +204019ac: 7ff9f993 andi s3,s3,2047 +204019b0: 00050413 mv s0,a0 +204019b4: 00060b13 mv s6,a2 +204019b8: 00068a93 mv s5,a3 +204019bc: 00c4d493 srli s1,s1,0xc +204019c0: 01f5da13 srli s4,a1,0x1f +204019c4: 0a098463 beqz s3,20401a6c <__muldf3+0xf0> +204019c8: 7ff00793 li a5,2047 +204019cc: 10f98263 beq s3,a5,20401ad0 <__muldf3+0x154> +204019d0: 01d55793 srli a5,a0,0x1d +204019d4: 00349493 slli s1,s1,0x3 +204019d8: 0097e4b3 or s1,a5,s1 +204019dc: 008007b7 lui a5,0x800 +204019e0: 00f4e4b3 or s1,s1,a5 +204019e4: 00351913 slli s2,a0,0x3 +204019e8: c0198993 addi s3,s3,-1023 +204019ec: 00000b93 li s7,0 +204019f0: 014ad513 srli a0,s5,0x14 +204019f4: 00ca9413 slli s0,s5,0xc +204019f8: 7ff57513 andi a0,a0,2047 +204019fc: 00c45413 srli s0,s0,0xc +20401a00: 01fada93 srli s5,s5,0x1f +20401a04: 10050263 beqz a0,20401b08 <__muldf3+0x18c> +20401a08: 7ff00793 li a5,2047 +20401a0c: 16f50263 beq a0,a5,20401b70 <__muldf3+0x1f4> +20401a10: 01db5793 srli a5,s6,0x1d +20401a14: 00341413 slli s0,s0,0x3 +20401a18: 0087e433 or s0,a5,s0 +20401a1c: 008007b7 lui a5,0x800 +20401a20: 00f46433 or s0,s0,a5 +20401a24: c0150513 addi a0,a0,-1023 +20401a28: 003b1793 slli a5,s6,0x3 +20401a2c: 00000713 li a4,0 +20401a30: 002b9693 slli a3,s7,0x2 +20401a34: 00e6e6b3 or a3,a3,a4 +20401a38: 00a989b3 add s3,s3,a0 +20401a3c: fff68693 addi a3,a3,-1 +20401a40: 00e00613 li a2,14 +20401a44: 015a4833 xor a6,s4,s5 +20401a48: 00198893 addi a7,s3,1 +20401a4c: 14d66e63 bltu a2,a3,20401ba8 <__muldf3+0x22c> +20401a50: 00001617 auipc a2,0x1 +20401a54: 95460613 addi a2,a2,-1708 # 204023a4 <__clzsi2+0x264> +20401a58: 00269693 slli a3,a3,0x2 +20401a5c: 00c686b3 add a3,a3,a2 +20401a60: 0006a683 lw a3,0(a3) +20401a64: 00c686b3 add a3,a3,a2 +20401a68: 00068067 jr a3 +20401a6c: 00a4e933 or s2,s1,a0 +20401a70: 06090c63 beqz s2,20401ae8 <__muldf3+0x16c> +20401a74: 04048063 beqz s1,20401ab4 <__muldf3+0x138> +20401a78: 00048513 mv a0,s1 +20401a7c: 6c4000ef jal ra,20402140 <__clzsi2> +20401a80: ff550713 addi a4,a0,-11 +20401a84: 01c00793 li a5,28 +20401a88: 02e7cc63 blt a5,a4,20401ac0 <__muldf3+0x144> +20401a8c: 01d00793 li a5,29 +20401a90: ff850913 addi s2,a0,-8 +20401a94: 40e787b3 sub a5,a5,a4 +20401a98: 012494b3 sll s1,s1,s2 +20401a9c: 00f457b3 srl a5,s0,a5 +20401aa0: 0097e4b3 or s1,a5,s1 +20401aa4: 01241933 sll s2,s0,s2 +20401aa8: c0d00993 li s3,-1011 +20401aac: 40a989b3 sub s3,s3,a0 +20401ab0: f3dff06f j 204019ec <__muldf3+0x70> +20401ab4: 68c000ef jal ra,20402140 <__clzsi2> +20401ab8: 02050513 addi a0,a0,32 +20401abc: fc5ff06f j 20401a80 <__muldf3+0x104> +20401ac0: fd850493 addi s1,a0,-40 +20401ac4: 009414b3 sll s1,s0,s1 +20401ac8: 00000913 li s2,0 +20401acc: fddff06f j 20401aa8 <__muldf3+0x12c> +20401ad0: 00a4e933 or s2,s1,a0 +20401ad4: 02090263 beqz s2,20401af8 <__muldf3+0x17c> +20401ad8: 00050913 mv s2,a0 +20401adc: 7ff00993 li s3,2047 +20401ae0: 00300b93 li s7,3 +20401ae4: f0dff06f j 204019f0 <__muldf3+0x74> +20401ae8: 00000493 li s1,0 +20401aec: 00000993 li s3,0 +20401af0: 00100b93 li s7,1 +20401af4: efdff06f j 204019f0 <__muldf3+0x74> +20401af8: 00000493 li s1,0 +20401afc: 7ff00993 li s3,2047 +20401b00: 00200b93 li s7,2 +20401b04: eedff06f j 204019f0 <__muldf3+0x74> +20401b08: 016467b3 or a5,s0,s6 +20401b0c: 06078e63 beqz a5,20401b88 <__muldf3+0x20c> +20401b10: 04040063 beqz s0,20401b50 <__muldf3+0x1d4> +20401b14: 00040513 mv a0,s0 +20401b18: 628000ef jal ra,20402140 <__clzsi2> +20401b1c: ff550693 addi a3,a0,-11 +20401b20: 01c00793 li a5,28 +20401b24: 02d7ce63 blt a5,a3,20401b60 <__muldf3+0x1e4> +20401b28: 01d00713 li a4,29 +20401b2c: ff850793 addi a5,a0,-8 +20401b30: 40d70733 sub a4,a4,a3 +20401b34: 00f41433 sll s0,s0,a5 +20401b38: 00eb5733 srl a4,s6,a4 +20401b3c: 00876433 or s0,a4,s0 +20401b40: 00fb17b3 sll a5,s6,a5 +20401b44: c0d00713 li a4,-1011 +20401b48: 40a70533 sub a0,a4,a0 +20401b4c: ee1ff06f j 20401a2c <__muldf3+0xb0> +20401b50: 000b0513 mv a0,s6 +20401b54: 5ec000ef jal ra,20402140 <__clzsi2> +20401b58: 02050513 addi a0,a0,32 +20401b5c: fc1ff06f j 20401b1c <__muldf3+0x1a0> +20401b60: fd850413 addi s0,a0,-40 +20401b64: 008b1433 sll s0,s6,s0 +20401b68: 00000793 li a5,0 +20401b6c: fd9ff06f j 20401b44 <__muldf3+0x1c8> +20401b70: 016467b3 or a5,s0,s6 +20401b74: 02078263 beqz a5,20401b98 <__muldf3+0x21c> +20401b78: 000b0793 mv a5,s6 +20401b7c: 7ff00513 li a0,2047 +20401b80: 00300713 li a4,3 +20401b84: eadff06f j 20401a30 <__muldf3+0xb4> +20401b88: 00000413 li s0,0 +20401b8c: 00000513 li a0,0 +20401b90: 00100713 li a4,1 +20401b94: e9dff06f j 20401a30 <__muldf3+0xb4> +20401b98: 00000413 li s0,0 +20401b9c: 7ff00513 li a0,2047 +20401ba0: 00200713 li a4,2 +20401ba4: e8dff06f j 20401a30 <__muldf3+0xb4> +20401ba8: 000102b7 lui t0,0x10 +20401bac: fff28313 addi t1,t0,-1 # ffff <__stack_size+0xf7ff> +20401bb0: 01095f13 srli t5,s2,0x10 +20401bb4: 0107df93 srli t6,a5,0x10 +20401bb8: 00697933 and s2,s2,t1 +20401bbc: 0067f7b3 and a5,a5,t1 +20401bc0: 00090513 mv a0,s2 +20401bc4: 00078593 mv a1,a5 +20401bc8: 4a0000ef jal ra,20402068 <__mulsi3> +20401bcc: 00050e93 mv t4,a0 +20401bd0: 000f8593 mv a1,t6 +20401bd4: 00090513 mv a0,s2 +20401bd8: 490000ef jal ra,20402068 <__mulsi3> +20401bdc: 00050e13 mv t3,a0 +20401be0: 00078593 mv a1,a5 +20401be4: 000f0513 mv a0,t5 +20401be8: 480000ef jal ra,20402068 <__mulsi3> +20401bec: 00050a13 mv s4,a0 +20401bf0: 000f8593 mv a1,t6 +20401bf4: 000f0513 mv a0,t5 +20401bf8: 470000ef jal ra,20402068 <__mulsi3> +20401bfc: 010ed713 srli a4,t4,0x10 +20401c00: 014e0e33 add t3,t3,s4 +20401c04: 01c70733 add a4,a4,t3 +20401c08: 00050393 mv t2,a0 +20401c0c: 01477463 bgeu a4,s4,20401c14 <__muldf3+0x298> +20401c10: 005503b3 add t2,a0,t0 +20401c14: 00677e33 and t3,a4,t1 +20401c18: 006efeb3 and t4,t4,t1 +20401c1c: 01045a13 srli s4,s0,0x10 +20401c20: 010e1e13 slli t3,t3,0x10 +20401c24: 00647433 and s0,s0,t1 +20401c28: 01075293 srli t0,a4,0x10 +20401c2c: 01de0e33 add t3,t3,t4 +20401c30: 00090513 mv a0,s2 +20401c34: 00040593 mv a1,s0 +20401c38: 430000ef jal ra,20402068 <__mulsi3> +20401c3c: 00050e93 mv t4,a0 +20401c40: 000a0593 mv a1,s4 +20401c44: 00090513 mv a0,s2 +20401c48: 420000ef jal ra,20402068 <__mulsi3> +20401c4c: 00050713 mv a4,a0 +20401c50: 00040593 mv a1,s0 +20401c54: 000f0513 mv a0,t5 +20401c58: 410000ef jal ra,20402068 <__mulsi3> +20401c5c: 00050313 mv t1,a0 +20401c60: 000a0593 mv a1,s4 +20401c64: 000f0513 mv a0,t5 +20401c68: 400000ef jal ra,20402068 <__mulsi3> +20401c6c: 010ed693 srli a3,t4,0x10 +20401c70: 00670733 add a4,a4,t1 +20401c74: 00e686b3 add a3,a3,a4 +20401c78: 0066f663 bgeu a3,t1,20401c84 <__muldf3+0x308> +20401c7c: 00010737 lui a4,0x10 +20401c80: 00e50533 add a0,a0,a4 +20401c84: 00010ab7 lui s5,0x10 +20401c88: fffa8613 addi a2,s5,-1 # ffff <__stack_size+0xf7ff> +20401c8c: 0106d713 srli a4,a3,0x10 +20401c90: 00c6f6b3 and a3,a3,a2 +20401c94: 01069693 slli a3,a3,0x10 +20401c98: 00cefeb3 and t4,t4,a2 +20401c9c: 00a70f33 add t5,a4,a0 +20401ca0: 01d68eb3 add t4,a3,t4 +20401ca4: 0104d713 srli a4,s1,0x10 +20401ca8: 00c4f4b3 and s1,s1,a2 +20401cac: 01d282b3 add t0,t0,t4 +20401cb0: 00048513 mv a0,s1 +20401cb4: 00078593 mv a1,a5 +20401cb8: 3b0000ef jal ra,20402068 <__mulsi3> +20401cbc: 00050913 mv s2,a0 +20401cc0: 000f8593 mv a1,t6 +20401cc4: 00048513 mv a0,s1 +20401cc8: 3a0000ef jal ra,20402068 <__mulsi3> +20401ccc: 00050313 mv t1,a0 +20401cd0: 00078593 mv a1,a5 +20401cd4: 00070513 mv a0,a4 +20401cd8: 390000ef jal ra,20402068 <__mulsi3> +20401cdc: 00050b13 mv s6,a0 +20401ce0: 000f8593 mv a1,t6 +20401ce4: 00070513 mv a0,a4 +20401ce8: 380000ef jal ra,20402068 <__mulsi3> +20401cec: 01095793 srli a5,s2,0x10 +20401cf0: 01630333 add t1,t1,s6 +20401cf4: 006787b3 add a5,a5,t1 +20401cf8: 0167f463 bgeu a5,s6,20401d00 <__muldf3+0x384> +20401cfc: 01550533 add a0,a0,s5 +20401d00: 00010ab7 lui s5,0x10 +20401d04: fffa8693 addi a3,s5,-1 # ffff <__stack_size+0xf7ff> +20401d08: 00d7f333 and t1,a5,a3 +20401d0c: 0107d613 srli a2,a5,0x10 +20401d10: 00d97933 and s2,s2,a3 +20401d14: 01031313 slli t1,t1,0x10 +20401d18: 00a60fb3 add t6,a2,a0 +20401d1c: 01230333 add t1,t1,s2 +20401d20: 00048513 mv a0,s1 +20401d24: 00040593 mv a1,s0 +20401d28: 340000ef jal ra,20402068 <__mulsi3> +20401d2c: 00050793 mv a5,a0 +20401d30: 000a0593 mv a1,s4 +20401d34: 00048513 mv a0,s1 +20401d38: 330000ef jal ra,20402068 <__mulsi3> +20401d3c: 00050493 mv s1,a0 +20401d40: 00040593 mv a1,s0 +20401d44: 00070513 mv a0,a4 +20401d48: 320000ef jal ra,20402068 <__mulsi3> +20401d4c: 00050913 mv s2,a0 +20401d50: 000a0593 mv a1,s4 +20401d54: 00070513 mv a0,a4 +20401d58: 310000ef jal ra,20402068 <__mulsi3> +20401d5c: 0107d693 srli a3,a5,0x10 +20401d60: 012484b3 add s1,s1,s2 +20401d64: 009686b3 add a3,a3,s1 +20401d68: 0126f463 bgeu a3,s2,20401d70 <__muldf3+0x3f4> +20401d6c: 01550533 add a0,a0,s5 +20401d70: 00010637 lui a2,0x10 +20401d74: fff60613 addi a2,a2,-1 # ffff <__stack_size+0xf7ff> +20401d78: 00c6f733 and a4,a3,a2 +20401d7c: 00c7f7b3 and a5,a5,a2 +20401d80: 01071713 slli a4,a4,0x10 +20401d84: 007282b3 add t0,t0,t2 +20401d88: 00f70733 add a4,a4,a5 +20401d8c: 01d2beb3 sltu t4,t0,t4 +20401d90: 01e70733 add a4,a4,t5 +20401d94: 01d70433 add s0,a4,t4 +20401d98: 006282b3 add t0,t0,t1 +20401d9c: 01f40633 add a2,s0,t6 +20401da0: 0062b333 sltu t1,t0,t1 +20401da4: 006605b3 add a1,a2,t1 +20401da8: 01e73733 sltu a4,a4,t5 +20401dac: 01d43433 sltu s0,s0,t4 +20401db0: 00876433 or s0,a4,s0 +20401db4: 0106d693 srli a3,a3,0x10 +20401db8: 01f63633 sltu a2,a2,t6 +20401dbc: 0065b333 sltu t1,a1,t1 +20401dc0: 00d40433 add s0,s0,a3 +20401dc4: 00666333 or t1,a2,t1 +20401dc8: 00640433 add s0,s0,t1 +20401dcc: 00929793 slli a5,t0,0x9 +20401dd0: 00a40433 add s0,s0,a0 +20401dd4: 01c7e7b3 or a5,a5,t3 +20401dd8: 00941413 slli s0,s0,0x9 +20401ddc: 0175d513 srli a0,a1,0x17 +20401de0: 00f037b3 snez a5,a5 +20401de4: 0172de13 srli t3,t0,0x17 +20401de8: 00959713 slli a4,a1,0x9 +20401dec: 00a46433 or s0,s0,a0 +20401df0: 01c7e7b3 or a5,a5,t3 +20401df4: 00e7e7b3 or a5,a5,a4 +20401df8: 00741713 slli a4,s0,0x7 +20401dfc: 10075263 bgez a4,20401f00 <__muldf3+0x584> +20401e00: 0017d713 srli a4,a5,0x1 +20401e04: 0017f793 andi a5,a5,1 +20401e08: 00f767b3 or a5,a4,a5 +20401e0c: 01f41713 slli a4,s0,0x1f +20401e10: 00e7e7b3 or a5,a5,a4 +20401e14: 00145413 srli s0,s0,0x1 +20401e18: 3ff88693 addi a3,a7,1023 +20401e1c: 0ed05663 blez a3,20401f08 <__muldf3+0x58c> +20401e20: 0077f713 andi a4,a5,7 +20401e24: 02070063 beqz a4,20401e44 <__muldf3+0x4c8> +20401e28: 00f7f713 andi a4,a5,15 +20401e2c: 00400613 li a2,4 +20401e30: 00c70a63 beq a4,a2,20401e44 <__muldf3+0x4c8> +20401e34: 00478713 addi a4,a5,4 # 800004 <__stack_size+0x7ff804> +20401e38: 00f737b3 sltu a5,a4,a5 +20401e3c: 00f40433 add s0,s0,a5 +20401e40: 00070793 mv a5,a4 +20401e44: 00741713 slli a4,s0,0x7 +20401e48: 00075a63 bgez a4,20401e5c <__muldf3+0x4e0> +20401e4c: ff000737 lui a4,0xff000 +20401e50: fff70713 addi a4,a4,-1 # feffffff <_sp+0x7effbfff> +20401e54: 00e47433 and s0,s0,a4 +20401e58: 40088693 addi a3,a7,1024 +20401e5c: 7fe00713 li a4,2046 +20401e60: 16d74663 blt a4,a3,20401fcc <__muldf3+0x650> +20401e64: 0037d713 srli a4,a5,0x3 +20401e68: 01d41793 slli a5,s0,0x1d +20401e6c: 00e7e7b3 or a5,a5,a4 +20401e70: 00345413 srli s0,s0,0x3 +20401e74: 00c41413 slli s0,s0,0xc +20401e78: 7ff6f713 andi a4,a3,2047 +20401e7c: 01471713 slli a4,a4,0x14 +20401e80: 00c45413 srli s0,s0,0xc +20401e84: 00e46433 or s0,s0,a4 +20401e88: 01f81813 slli a6,a6,0x1f +20401e8c: 01046733 or a4,s0,a6 +20401e90: 02c12083 lw ra,44(sp) +20401e94: 02812403 lw s0,40(sp) +20401e98: 02412483 lw s1,36(sp) +20401e9c: 02012903 lw s2,32(sp) +20401ea0: 01c12983 lw s3,28(sp) +20401ea4: 01812a03 lw s4,24(sp) +20401ea8: 01412a83 lw s5,20(sp) +20401eac: 01012b03 lw s6,16(sp) +20401eb0: 00c12b83 lw s7,12(sp) +20401eb4: 00078513 mv a0,a5 +20401eb8: 00070593 mv a1,a4 +20401ebc: 03010113 addi sp,sp,48 +20401ec0: 00008067 ret +20401ec4: 000a0813 mv a6,s4 +20401ec8: 00048413 mv s0,s1 +20401ecc: 00090793 mv a5,s2 +20401ed0: 000b8713 mv a4,s7 +20401ed4: 00200693 li a3,2 +20401ed8: 0ed70a63 beq a4,a3,20401fcc <__muldf3+0x650> +20401edc: 00300693 li a3,3 +20401ee0: 0cd70c63 beq a4,a3,20401fb8 <__muldf3+0x63c> +20401ee4: 00100693 li a3,1 +20401ee8: f2d718e3 bne a4,a3,20401e18 <__muldf3+0x49c> +20401eec: 00000413 li s0,0 +20401ef0: 00000793 li a5,0 +20401ef4: 0880006f j 20401f7c <__muldf3+0x600> +20401ef8: 000a8813 mv a6,s5 +20401efc: fd9ff06f j 20401ed4 <__muldf3+0x558> +20401f00: 00098893 mv a7,s3 +20401f04: f15ff06f j 20401e18 <__muldf3+0x49c> +20401f08: 00100613 li a2,1 +20401f0c: 40d60633 sub a2,a2,a3 +20401f10: 03800713 li a4,56 +20401f14: fcc74ce3 blt a4,a2,20401eec <__muldf3+0x570> +20401f18: 01f00713 li a4,31 +20401f1c: 06c74463 blt a4,a2,20401f84 <__muldf3+0x608> +20401f20: 41e88893 addi a7,a7,1054 +20401f24: 01141733 sll a4,s0,a7 +20401f28: 00c7d6b3 srl a3,a5,a2 +20401f2c: 011797b3 sll a5,a5,a7 +20401f30: 00d76733 or a4,a4,a3 +20401f34: 00f037b3 snez a5,a5 +20401f38: 00f767b3 or a5,a4,a5 +20401f3c: 00c45433 srl s0,s0,a2 +20401f40: 0077f713 andi a4,a5,7 +20401f44: 02070063 beqz a4,20401f64 <__muldf3+0x5e8> +20401f48: 00f7f713 andi a4,a5,15 +20401f4c: 00400693 li a3,4 +20401f50: 00d70a63 beq a4,a3,20401f64 <__muldf3+0x5e8> +20401f54: 00478713 addi a4,a5,4 +20401f58: 00f737b3 sltu a5,a4,a5 +20401f5c: 00f40433 add s0,s0,a5 +20401f60: 00070793 mv a5,a4 +20401f64: 00841713 slli a4,s0,0x8 +20401f68: 06074a63 bltz a4,20401fdc <__muldf3+0x660> +20401f6c: 01d41713 slli a4,s0,0x1d +20401f70: 0037d793 srli a5,a5,0x3 +20401f74: 00f767b3 or a5,a4,a5 +20401f78: 00345413 srli s0,s0,0x3 +20401f7c: 00000693 li a3,0 +20401f80: ef5ff06f j 20401e74 <__muldf3+0x4f8> +20401f84: fe100713 li a4,-31 +20401f88: 40d70733 sub a4,a4,a3 +20401f8c: 02000593 li a1,32 +20401f90: 00e45733 srl a4,s0,a4 +20401f94: 00000693 li a3,0 +20401f98: 00b60663 beq a2,a1,20401fa4 <__muldf3+0x628> +20401f9c: 43e88893 addi a7,a7,1086 +20401fa0: 011416b3 sll a3,s0,a7 +20401fa4: 00f6e7b3 or a5,a3,a5 +20401fa8: 00f037b3 snez a5,a5 +20401fac: 00f767b3 or a5,a4,a5 +20401fb0: 00000413 li s0,0 +20401fb4: f8dff06f j 20401f40 <__muldf3+0x5c4> +20401fb8: 00080437 lui s0,0x80 +20401fbc: 00000793 li a5,0 +20401fc0: 7ff00693 li a3,2047 +20401fc4: 00000813 li a6,0 +20401fc8: eadff06f j 20401e74 <__muldf3+0x4f8> +20401fcc: 00000413 li s0,0 +20401fd0: 00000793 li a5,0 +20401fd4: 7ff00693 li a3,2047 +20401fd8: e9dff06f j 20401e74 <__muldf3+0x4f8> +20401fdc: 00000413 li s0,0 +20401fe0: 00000793 li a5,0 +20401fe4: 00100693 li a3,1 +20401fe8: e8dff06f j 20401e74 <__muldf3+0x4f8> + +20401fec <__fixunsdfsi>: +20401fec: 0145d713 srli a4,a1,0x14 +20401ff0: 001006b7 lui a3,0x100 +20401ff4: 00050613 mv a2,a0 +20401ff8: fff68793 addi a5,a3,-1 # fffff <__stack_size+0xff7ff> +20401ffc: 7ff77713 andi a4,a4,2047 +20402000: 3fe00513 li a0,1022 +20402004: 00b7f7b3 and a5,a5,a1 +20402008: 01f5d593 srli a1,a1,0x1f +2040200c: 04e55a63 bge a0,a4,20402060 <__fixunsdfsi+0x74> +20402010: 00000513 li a0,0 +20402014: 00059863 bnez a1,20402024 <__fixunsdfsi+0x38> +20402018: 41e00593 li a1,1054 +2040201c: fff00513 li a0,-1 +20402020: 00e5d463 bge a1,a4,20402028 <__fixunsdfsi+0x3c> +20402024: 00008067 ret +20402028: 00d7e7b3 or a5,a5,a3 +2040202c: 43300693 li a3,1075 +20402030: 40e686b3 sub a3,a3,a4 +20402034: 01f00593 li a1,31 +20402038: 00d5cc63 blt a1,a3,20402050 <__fixunsdfsi+0x64> +2040203c: bed70713 addi a4,a4,-1043 +20402040: 00e797b3 sll a5,a5,a4 +20402044: 00d65533 srl a0,a2,a3 +20402048: 00a7e533 or a0,a5,a0 +2040204c: 00008067 ret +20402050: 41300513 li a0,1043 +20402054: 40e50533 sub a0,a0,a4 +20402058: 00a7d533 srl a0,a5,a0 +2040205c: 00008067 ret +20402060: 00000513 li a0,0 +20402064: 00008067 ret + +20402068 <__mulsi3>: +20402068: 00050613 mv a2,a0 +2040206c: 00000513 li a0,0 +20402070: 0015f693 andi a3,a1,1 +20402074: 00068463 beqz a3,2040207c <__mulsi3+0x14> +20402078: 00c50533 add a0,a0,a2 +2040207c: 0015d593 srli a1,a1,0x1 +20402080: 00161613 slli a2,a2,0x1 +20402084: fe0596e3 bnez a1,20402070 <__mulsi3+0x8> +20402088: 00008067 ret + +2040208c <__divsi3>: +2040208c: 06054063 bltz a0,204020ec <__umodsi3+0x10> +20402090: 0605c663 bltz a1,204020fc <__umodsi3+0x20> + +20402094 <__udivsi3>: +20402094: 00058613 mv a2,a1 +20402098: 00050593 mv a1,a0 +2040209c: fff00513 li a0,-1 +204020a0: 02060c63 beqz a2,204020d8 <__udivsi3+0x44> +204020a4: 00100693 li a3,1 +204020a8: 00b67a63 bgeu a2,a1,204020bc <__udivsi3+0x28> +204020ac: 00c05863 blez a2,204020bc <__udivsi3+0x28> +204020b0: 00161613 slli a2,a2,0x1 +204020b4: 00169693 slli a3,a3,0x1 +204020b8: feb66ae3 bltu a2,a1,204020ac <__udivsi3+0x18> +204020bc: 00000513 li a0,0 +204020c0: 00c5e663 bltu a1,a2,204020cc <__udivsi3+0x38> +204020c4: 40c585b3 sub a1,a1,a2 +204020c8: 00d56533 or a0,a0,a3 +204020cc: 0016d693 srli a3,a3,0x1 +204020d0: 00165613 srli a2,a2,0x1 +204020d4: fe0696e3 bnez a3,204020c0 <__udivsi3+0x2c> +204020d8: 00008067 ret + +204020dc <__umodsi3>: +204020dc: 00008293 mv t0,ra +204020e0: fb5ff0ef jal ra,20402094 <__udivsi3> +204020e4: 00058513 mv a0,a1 +204020e8: 00028067 jr t0 +204020ec: 40a00533 neg a0,a0 +204020f0: 0005d863 bgez a1,20402100 <__umodsi3+0x24> +204020f4: 40b005b3 neg a1,a1 +204020f8: f9dff06f j 20402094 <__udivsi3> +204020fc: 40b005b3 neg a1,a1 +20402100: 00008293 mv t0,ra +20402104: f91ff0ef jal ra,20402094 <__udivsi3> +20402108: 40a00533 neg a0,a0 +2040210c: 00028067 jr t0 + +20402110 <__modsi3>: +20402110: 00008293 mv t0,ra +20402114: 0005ca63 bltz a1,20402128 <__modsi3+0x18> +20402118: 00054c63 bltz a0,20402130 <__modsi3+0x20> +2040211c: f79ff0ef jal ra,20402094 <__udivsi3> +20402120: 00058513 mv a0,a1 +20402124: 00028067 jr t0 +20402128: 40b005b3 neg a1,a1 +2040212c: fe0558e3 bgez a0,2040211c <__modsi3+0xc> +20402130: 40a00533 neg a0,a0 +20402134: f61ff0ef jal ra,20402094 <__udivsi3> +20402138: 40b00533 neg a0,a1 +2040213c: 00028067 jr t0 + +20402140 <__clzsi2>: +20402140: 000107b7 lui a5,0x10 +20402144: 02f57a63 bgeu a0,a5,20402178 <__clzsi2+0x38> +20402148: 0ff00793 li a5,255 +2040214c: 00a7b7b3 sltu a5,a5,a0 +20402150: 00379793 slli a5,a5,0x3 +20402154: 02000713 li a4,32 +20402158: 40f70733 sub a4,a4,a5 +2040215c: 00f557b3 srl a5,a0,a5 +20402160: 00000517 auipc a0,0x0 +20402164: 28050513 addi a0,a0,640 # 204023e0 <__clz_tab> +20402168: 00f507b3 add a5,a0,a5 +2040216c: 0007c503 lbu a0,0(a5) # 10000 <__stack_size+0xf800> +20402170: 40a70533 sub a0,a4,a0 +20402174: 00008067 ret +20402178: 01000737 lui a4,0x1000 +2040217c: 01000793 li a5,16 +20402180: fce56ae3 bltu a0,a4,20402154 <__clzsi2+0x14> +20402184: 01800793 li a5,24 +20402188: fcdff06f j 20402154 <__clzsi2+0x14> diff --git a/raven/wrap_printf.c b/raven/wrap_printf.c new file mode 100644 index 0000000..025d231 --- /dev/null +++ b/raven/wrap_printf.c @@ -0,0 +1,271 @@ +/* The functions in this file are only meant to support Dhrystone on an + * embedded RV32 system and are obviously incorrect in general. */ + +#include +#include +#include +#include +#include +#include + +#undef putchar +int putchar(int ch) +{ + return write(1, &ch, 1) == 1 ? ch : -1; +} + +static void sprintf_putch(int ch, void** data) +{ + char** pstr = (char**)data; + **pstr = ch; + (*pstr)++; +} + +static unsigned long getuint(va_list *ap, int lflag) +{ + if (lflag) + return va_arg(*ap, unsigned long); + else + return va_arg(*ap, unsigned int); +} + +static long getint(va_list *ap, int lflag) +{ + if (lflag) + return va_arg(*ap, long); + else + return va_arg(*ap, int); +} + +static inline void printnum(void (*putch)(int, void**), void **putdat, + unsigned long num, unsigned base, int width, int padc) +{ + unsigned digs[sizeof(num)*8]; + int pos = 0; + + while (1) + { + digs[pos++] = num % base; + if (num < base) + break; + num /= base; + } + + while (width-- > pos) + putch(padc, putdat); + + while (pos-- > 0) + putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat); +} + +static inline void print_double(void (*putch)(int, void**), void **putdat, + double num, int width, int prec) +{ + union { + double d; + uint64_t u; + } u; + u.d = num; + + if (u.u & (1ULL << 63)) { + putch('-', putdat); + u.u &= ~(1ULL << 63); + } + + for (int i = 0; i < prec; i++) + u.d *= 10; + + char buf[32], *pbuf = buf; + printnum(sprintf_putch, (void**)&pbuf, (unsigned long)u.d, 10, 0, 0); + if (prec > 0) { + for (int i = 0; i < prec; i++) { + pbuf[-i] = pbuf[-i-1]; + } + pbuf[-prec] = '.'; + pbuf++; + } + + for (char* p = buf; p < pbuf; p++) + putch(*p, putdat); +} + +static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap) +{ + register const char* p; + const char* last_fmt; + register int ch, err; + unsigned long num; + int base, lflag, width, precision, altflag; + char padc; + + while (1) { + while ((ch = *(unsigned char *) fmt) != '%') { + if (ch == '\0') + return; + fmt++; + putch(ch, putdat); + } + fmt++; + + // Process a %-escape sequence + last_fmt = fmt; + padc = ' '; + width = -1; + precision = -1; + lflag = 0; + altflag = 0; + reswitch: + switch (ch = *(unsigned char *) fmt++) { + + // flag to pad on the right + case '-': + padc = '-'; + goto reswitch; + + // flag to pad with 0's instead of spaces + case '0': + padc = '0'; + goto reswitch; + + // width field + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + for (precision = 0; ; ++fmt) { + precision = precision * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + goto process_precision; + + case '*': + precision = va_arg(ap, int); + goto process_precision; + + case '.': + if (width < 0) + width = 0; + goto reswitch; + + case '#': + altflag = 1; + goto reswitch; + + process_precision: + if (width < 0) + width = precision, precision = -1; + goto reswitch; + + // long flag + case 'l': + if (lflag) + goto bad; + goto reswitch; + + // character + case 'c': + putch(va_arg(ap, int), putdat); + break; + + // double + case 'f': + print_double(putch, putdat, va_arg(ap, double), width, precision); + break; + + // string + case 's': + if ((p = va_arg(ap, char *)) == NULL) + p = "(null)"; + if (width > 0 && padc != '-') + for (width -= strnlen(p, precision); width > 0; width--) + putch(padc, putdat); + for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) { + putch(ch, putdat); + p++; + } + for (; width > 0; width--) + putch(' ', putdat); + break; + + // (signed) decimal + case 'd': + num = getint(&ap, lflag); + if ((long) num < 0) { + putch('-', putdat); + num = -(long) num; + } + base = 10; + goto signed_number; + + // unsigned decimal + case 'u': + base = 10; + goto unsigned_number; + + // (unsigned) octal + case 'o': + // should do something with padding so it's always 3 octits + base = 8; + goto unsigned_number; + + // pointer + case 'p': + lflag = 1; + putch('0', putdat); + putch('x', putdat); + /* fall through to 'x' */ + + // (unsigned) hexadecimal + case 'x': + base = 16; + unsigned_number: + num = getuint(&ap, lflag); + signed_number: + printnum(putch, putdat, num, base, width, padc); + break; + + // escaped '%' character + case '%': + putch(ch, putdat); + break; + + // unrecognized escape sequence - just print it literally + default: + bad: + putch('%', putdat); + fmt = last_fmt; + break; + } + } +} + +int __wrap_printf(const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + + vprintfmt((void*)putchar, 0, fmt, ap); + + va_end(ap); + return 0; // incorrect return value, but who cares, anyway? +} + +int __wrap_sprintf(char* str, const char* fmt, ...) +{ + va_list ap; + char* str0 = str; + va_start(ap, fmt); + + vprintfmt(sprintf_putch, (void**)&str, fmt, ap); + *str = 0; + + va_end(ap); + return str - str0; +}