From b9e5f33cb664579560042e83003e02e0074c785a Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Fri, 23 May 2025 20:23:23 +0200 Subject: [PATCH] re-applies latest moonlight changes --- env/moonlight/platform.h | 18 +- include/minres/devices/fki_cluster_info.h | 29 +- include/minres/devices/flexki_messages.h | 21 - include/minres/devices/gen/aclint.h | 49 +- include/minres/devices/gen/apb3spi.h | 427 +++++----------- include/minres/devices/gen/camera.h | 307 ++++-------- include/minres/devices/gen/dma.h | 470 +++++------------- include/minres/devices/gen/gpio.h | 428 +++++----------- include/minres/devices/gen/i2s.h | 231 +++------ .../gen/mkcontrolclusterstreamcontroller.h | 261 ++++------ include/minres/devices/gen/msgif.h | 158 ++---- include/minres/devices/gen/timercounter.h | 123 ++--- include/minres/devices/gen/uart.h | 237 +++------ include/minres/devices/gpio.h | 2 +- include/minres/devices/timer.h | 12 +- include/minres/devices/uart.h | 2 +- 16 files changed, 799 insertions(+), 1976 deletions(-) diff --git a/env/moonlight/platform.h b/env/moonlight/platform.h index 8452816..619b62d 100644 --- a/env/moonlight/platform.h +++ b/env/moonlight/platform.h @@ -16,6 +16,7 @@ #include "minres/devices/aclint.h" #include "minres/devices/camera.h" #include "minres/devices/dma.h" +#include "minres/devices/gen/sysctrl.h" #include "minres/devices/gpio.h" #include "minres/devices/i2s.h" #include "minres/devices/msg_if.h" @@ -28,18 +29,25 @@ #define APB_BASE 0xF0000000 #define gpio PERIPH(gpio_t, APB_BASE + 0x0000) -#define uart PERIPH(uart_t, APB_BASE + 0x1000) +#define uart PERIPH(uart_t, APB_BASE + 0x01000) #define timer PERIPH(timercounter_t, APB_BASE + 0x20000) #define aclint PERIPH(aclint_t, APB_BASE + 0x30000) -#define irq PERIPH(irq_t, APB_BASE + 0x40000) +#define sysctrl PERIPH(sysctrl_t, APB_BASE + 0x40000) #define qspi PERIPH(qspi_t, APB_BASE + 0x50000) #define i2s PERIPH(i2s_t, APB_BASE + 0x90000) #define camera PERIPH(camera_t, APB_BASE + 0xA0000) #define dma PERIPH(dma_t, APB_BASE + 0xB0000) -#define msgif PERIPH(msgif_t, APB_BASE + 0xC0000) +#define msgif PERIPH(mkcontrolclusterstreamcontroller_t, APB_BASE + 0xC0000) -#define XIP_START_LOC 0xE0040000 -#define RAM_START_LOC 0x80000000 +#include "minres/devices/fki_cluster_info.h" +#include "minres/devices/flexki_messages.h" + +#ifndef XIP_START_LOC +#define XIP_START_LOC 0xE0000000 +#endif +#ifndef RAM_START_LOC +#define RAM_START_LOC 0xC0000000 +#endif // Misc diff --git a/include/minres/devices/fki_cluster_info.h b/include/minres/devices/fki_cluster_info.h index f8fdad7..93ba304 100644 --- a/include/minres/devices/fki_cluster_info.h +++ b/include/minres/devices/fki_cluster_info.h @@ -13,7 +13,6 @@ static inline uint32_t fki_addr_sram2(uint8_t cluster); static inline uint32_t fki_addr_cntrl_cva5(uint8_t cluster); static inline uint32_t fki_addr_cntrl_tgc(uint8_t cluster); static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster); -static inline uint32_t fki_addr_cacheFlushControl(uint8_t cluster); static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster); static inline uint32_t fki_addr_ccc_idxJobs(uint8_t cluster); static inline uint32_t fki_addr_cntrl_cva5_clusterReg(uint8_t cluster); @@ -57,11 +56,8 @@ static inline uint32_t fki_addr_sram3(uint8_t cluster); #define BYTES_Compute0_cntrl_tgc 8192 #define HIGH_Compute0_cntrl_tgc 0x8000cfff #define ADDR_Compute0_ut_adapter 0x8000e000 -#define BYTES_Compute0_ut_adapter 4096 -#define HIGH_Compute0_ut_adapter 0x8000efff -#define ADDR_Compute0_cacheFlushControl 0x8000f000 -#define BYTES_Compute0_cacheFlushControl 4096 -#define HIGH_Compute0_cacheFlushControl 0x8000ffff +#define BYTES_Compute0_ut_adapter 8192 +#define HIGH_Compute0_ut_adapter 0x8000ffff #define ADDR_Compute0_sram0 0x80010000 #define BYTES_Compute0_sram0 524288 #define HIGH_Compute0_sram0 0x8008ffff @@ -108,11 +104,8 @@ static inline uint32_t fki_addr_sram3(uint8_t cluster); #define BYTES_Compute1_cntrl_tgc 12288 #define HIGH_Compute1_cntrl_tgc 0x9000dfff #define ADDR_Compute1_ut_adapter 0x9000e000 -#define BYTES_Compute1_ut_adapter 4096 -#define HIGH_Compute1_ut_adapter 0x9000efff -#define ADDR_Compute1_cacheFlushControl 0x9000f000 -#define BYTES_Compute1_cacheFlushControl 4096 -#define HIGH_Compute1_cacheFlushControl 0x9000ffff +#define BYTES_Compute1_ut_adapter 8192 +#define HIGH_Compute1_ut_adapter 0x9000ffff #define ADDR_Compute1_sram0 0x90010000 #define BYTES_Compute1_sram0 524288 #define HIGH_Compute1_sram0 0x9008ffff @@ -280,20 +273,6 @@ static inline uint32_t fki_addr_ccc_idxTasks(uint8_t cluster) { } } -static inline uint32_t fki_addr_cacheFlushControl(uint8_t cluster) { - switch(cluster) { - case 3: { - return 0x9000f000; - } - case 2: { - return 0x8000f000; - } - default: { - return -1; - } - } -} - static inline uint32_t fki_addr_cntrl_tgc_clusterReg(uint8_t cluster) { switch(cluster) { case 3: { diff --git a/include/minres/devices/flexki_messages.h b/include/minres/devices/flexki_messages.h index 7ca2424..6826687 100644 --- a/include/minres/devices/flexki_messages.h +++ b/include/minres/devices/flexki_messages.h @@ -36,27 +36,6 @@ static void send_msg(uint32_t cluster, uint32_t component, uint32_t msg_len, uin case 7: set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(msgif, words[i]); break; - case 8: - set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(msgif, words[i]); - break; - case 9: - set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(msgif, words[i]); - break; - case 10: - set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(msgif, words[i]); - break; - case 11: - set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(msgif, words[i]); - break; - case 12: - set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(msgif, words[i]); - break; - case 13: - set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(msgif, words[i]); - break; - case 14: - set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(msgif, words[i]); - break; default: break; } diff --git a/include/minres/devices/gen/aclint.h b/include/minres/devices/gen/aclint.h index f717b9c..e2430c1 100644 --- a/include/minres/devices/gen/aclint.h +++ b/include/minres/devices/gen/aclint.h @@ -28,13 +28,11 @@ typedef struct { #define ACLINT_MTIMECMP0LO_OFFS 0 #define ACLINT_MTIMECMP0LO_MASK 0xffffffff -#define ACLINT_MTIMECMP0LO(V) \ - ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS) +#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS) #define ACLINT_MTIMECMP0HI_OFFS 0 #define ACLINT_MTIMECMP0HI_MASK 0xffffffff -#define ACLINT_MTIMECMP0HI(V) \ - ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS) +#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS) #define ACLINT_MTIME_LO_OFFS 0 #define ACLINT_MTIME_LO_MASK 0xffffffff @@ -45,51 +43,32 @@ typedef struct { #define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS) // ACLINT_MSIP0 -static inline uint32_t get_aclint_msip0(volatile aclint_t *reg) { - return reg->MSIP0; -} -static inline void set_aclint_msip0(volatile aclint_t *reg, uint32_t value) { - reg->MSIP0 = value; -} -static inline uint32_t get_aclint_msip0_msip(volatile aclint_t *reg) { - return (reg->MSIP0 >> 0) & 0x1; -} -static inline void set_aclint_msip0_msip(volatile aclint_t *reg, - uint8_t value) { - reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); -} +static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP0; } +static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP0 = value; } +static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP0 >> 0) & 0x1; } +static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) { reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); } // ACLINT_MTIMECMP0LO -static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t *reg) { - return (reg->MTIMECMP0LO >> 0) & 0xffffffff; -} -static inline void set_aclint_mtimecmp0lo(volatile aclint_t *reg, - uint32_t value) { +static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP0LO >> 0) & 0xffffffff; } +static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) { reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0); } // ACLINT_MTIMECMP0HI -static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t *reg) { - return (reg->MTIMECMP0HI >> 0) & 0xffffffff; -} -static inline void set_aclint_mtimecmp0hi(volatile aclint_t *reg, - uint32_t value) { +static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP0HI >> 0) & 0xffffffff; } +static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) { reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0); } // ACLINT_MTIME_LO -static inline uint32_t get_aclint_mtime_lo(volatile aclint_t *reg) { - return (reg->MTIME_LO >> 0) & 0xffffffff; -} -static inline void set_aclint_mtime_lo(volatile aclint_t *reg, uint32_t value) { +static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; } +static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) { reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0); } // ACLINT_MTIME_HI -static inline uint32_t get_aclint_mtime_hi(volatile aclint_t *reg) { - return (reg->MTIME_HI >> 0) & 0xffffffff; -} -static inline void set_aclint_mtime_hi(volatile aclint_t *reg, uint32_t value) { +static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; } +static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) { reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0); } diff --git a/include/minres/devices/gen/apb3spi.h b/include/minres/devices/gen/apb3spi.h index 7de8692..3fd03f7 100644 --- a/include/minres/devices/gen/apb3spi.h +++ b/include/minres/devices/gen/apb3spi.h @@ -35,479 +35,276 @@ typedef struct { #define APB3SPI_DATA_DATA_OFFS 0 #define APB3SPI_DATA_DATA_MASK 0xff -#define APB3SPI_DATA_DATA(V) \ - ((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS) +#define APB3SPI_DATA_DATA(V) ((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS) #define APB3SPI_DATA_WRITE_OFFS 8 #define APB3SPI_DATA_WRITE_MASK 0x1 -#define APB3SPI_DATA_WRITE(V) \ - ((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS) +#define APB3SPI_DATA_WRITE(V) ((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS) #define APB3SPI_DATA_READ_OFFS 9 #define APB3SPI_DATA_READ_MASK 0x1 -#define APB3SPI_DATA_READ(V) \ - ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS) +#define APB3SPI_DATA_READ(V) ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS) #define APB3SPI_DATA_SSGEN_OFFS 11 #define APB3SPI_DATA_SSGEN_MASK 0x1 -#define APB3SPI_DATA_SSGEN(V) \ - ((V & APB3SPI_DATA_SSGEN_MASK) << APB3SPI_DATA_SSGEN_OFFS) +#define APB3SPI_DATA_SSGEN(V) ((V & APB3SPI_DATA_SSGEN_MASK) << APB3SPI_DATA_SSGEN_OFFS) #define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31 #define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1 -#define APB3SPI_DATA_RX_DATA_INVALID(V) \ - ((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS) +#define APB3SPI_DATA_RX_DATA_INVALID(V) ((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS) #define APB3SPI_STATUS_TX_FREE_OFFS 0 #define APB3SPI_STATUS_TX_FREE_MASK 0x3f -#define APB3SPI_STATUS_TX_FREE(V) \ - ((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS) +#define APB3SPI_STATUS_TX_FREE(V) ((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS) #define APB3SPI_STATUS_RX_AVAIL_OFFS 16 #define APB3SPI_STATUS_RX_AVAIL_MASK 0x3f -#define APB3SPI_STATUS_RX_AVAIL(V) \ - ((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS) +#define APB3SPI_STATUS_RX_AVAIL(V) ((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS) #define APB3SPI_CONFIG_KIND_OFFS 0 #define APB3SPI_CONFIG_KIND_MASK 0x3 -#define APB3SPI_CONFIG_KIND(V) \ - ((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS) +#define APB3SPI_CONFIG_KIND(V) ((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS) #define APB3SPI_CONFIG_MODE_OFFS 4 #define APB3SPI_CONFIG_MODE_MASK 0x3 -#define APB3SPI_CONFIG_MODE(V) \ - ((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS) +#define APB3SPI_CONFIG_MODE(V) ((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS) #define APB3SPI_INTR_TX_IE_OFFS 0 #define APB3SPI_INTR_TX_IE_MASK 0x1 -#define APB3SPI_INTR_TX_IE(V) \ - ((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS) +#define APB3SPI_INTR_TX_IE(V) ((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS) #define APB3SPI_INTR_RX_IE_OFFS 1 #define APB3SPI_INTR_RX_IE_MASK 0x1 -#define APB3SPI_INTR_RX_IE(V) \ - ((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS) +#define APB3SPI_INTR_RX_IE(V) ((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS) #define APB3SPI_INTR_TX_IP_OFFS 8 #define APB3SPI_INTR_TX_IP_MASK 0x1 -#define APB3SPI_INTR_TX_IP(V) \ - ((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS) +#define APB3SPI_INTR_TX_IP(V) ((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS) #define APB3SPI_INTR_RX_IP_OFFS 9 #define APB3SPI_INTR_RX_IP_MASK 0x1 -#define APB3SPI_INTR_RX_IP(V) \ - ((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS) +#define APB3SPI_INTR_RX_IP(V) ((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS) #define APB3SPI_INTR_TX_ACTIVE_OFFS 16 #define APB3SPI_INTR_TX_ACTIVE_MASK 0x1 -#define APB3SPI_INTR_TX_ACTIVE(V) \ - ((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS) +#define APB3SPI_INTR_TX_ACTIVE(V) ((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS) #define APB3SPI_SCLK_CONFIG_OFFS 0 #define APB3SPI_SCLK_CONFIG_MASK 0xfff -#define APB3SPI_SCLK_CONFIG(V) \ - ((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS) +#define APB3SPI_SCLK_CONFIG(V) ((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS) #define APB3SPI_SSGEN_SETUP_OFFS 0 #define APB3SPI_SSGEN_SETUP_MASK 0xfff -#define APB3SPI_SSGEN_SETUP(V) \ - ((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS) +#define APB3SPI_SSGEN_SETUP(V) ((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS) #define APB3SPI_SSGEN_HOLD_OFFS 0 #define APB3SPI_SSGEN_HOLD_MASK 0xfff -#define APB3SPI_SSGEN_HOLD(V) \ - ((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS) +#define APB3SPI_SSGEN_HOLD(V) ((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS) #define APB3SPI_SSGEN_DISABLE_OFFS 0 #define APB3SPI_SSGEN_DISABLE_MASK 0xfff -#define APB3SPI_SSGEN_DISABLE(V) \ - ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS) +#define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS) #define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0 #define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1 -#define APB3SPI_SSGEN_ACTIVE_HIGH(V) \ - ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS) +#define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS) #define APB3SPI_XIP_ENABLE_OFFS 0 #define APB3SPI_XIP_ENABLE_MASK 0x1 -#define APB3SPI_XIP_ENABLE(V) \ - ((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS) +#define APB3SPI_XIP_ENABLE(V) ((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS) #define APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS 0 #define APB3SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff -#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) \ - ((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) \ - << APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS) +#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) ((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) << APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS) #define APB3SPI_XIP_CONFIG_ENABLE_OFFS 8 #define APB3SPI_XIP_CONFIG_ENABLE_MASK 0x1 -#define APB3SPI_XIP_CONFIG_ENABLE(V) \ - ((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS) +#define APB3SPI_XIP_CONFIG_ENABLE(V) ((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS) #define APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16 #define APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff -#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) \ - ((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) \ - << APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS) +#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS) #define APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24 #define APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf -#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) \ - ((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) \ - << APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS) +#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS) #define APB3SPI_XIP_MODE_INSTRUCTION_OFFS 0 #define APB3SPI_XIP_MODE_INSTRUCTION_MASK 0x3 -#define APB3SPI_XIP_MODE_INSTRUCTION(V) \ - ((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS) +#define APB3SPI_XIP_MODE_INSTRUCTION(V) ((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS) #define APB3SPI_XIP_MODE_ADDRESS_OFFS 8 #define APB3SPI_XIP_MODE_ADDRESS_MASK 0x3 -#define APB3SPI_XIP_MODE_ADDRESS(V) \ - ((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS) +#define APB3SPI_XIP_MODE_ADDRESS(V) ((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS) #define APB3SPI_XIP_MODE_DUMMY_OFFS 16 #define APB3SPI_XIP_MODE_DUMMY_MASK 0x3 -#define APB3SPI_XIP_MODE_DUMMY(V) \ - ((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS) +#define APB3SPI_XIP_MODE_DUMMY(V) ((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS) #define APB3SPI_XIP_MODE_PAYLOAD_OFFS 24 #define APB3SPI_XIP_MODE_PAYLOAD_MASK 0x3 -#define APB3SPI_XIP_MODE_PAYLOAD(V) \ - ((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS) +#define APB3SPI_XIP_MODE_PAYLOAD(V) ((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS) #define APB3SPI_XIP_WRITE_OFFS 0 #define APB3SPI_XIP_WRITE_MASK 0xff -#define APB3SPI_XIP_WRITE(V) \ - ((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS) +#define APB3SPI_XIP_WRITE(V) ((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS) #define APB3SPI_XIP_READ_WRITE_OFFS 0 #define APB3SPI_XIP_READ_WRITE_MASK 0xff -#define APB3SPI_XIP_READ_WRITE(V) \ - ((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS) +#define APB3SPI_XIP_READ_WRITE(V) ((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS) #define APB3SPI_XIP_READ_OFFS 0 #define APB3SPI_XIP_READ_MASK 0xff -#define APB3SPI_XIP_READ(V) \ - ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS) +#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS) // APB3SPI_DATA -static inline uint32_t get_apb3spi_data(volatile apb3spi_t *reg) { - return reg->DATA; -} -static inline void set_apb3spi_data(volatile apb3spi_t *reg, uint32_t value) { - reg->DATA = value; -} -static inline void set_apb3spi_data_data(volatile apb3spi_t *reg, - uint8_t value) { - reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); -} -static inline uint32_t get_apb3spi_data_write(volatile apb3spi_t *reg) { - return (reg->DATA >> 8) & 0x1; -} -static inline void set_apb3spi_data_write(volatile apb3spi_t *reg, - uint8_t value) { - reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8); -} -static inline uint32_t get_apb3spi_data_read(volatile apb3spi_t *reg) { - return (reg->DATA >> 9) & 0x1; -} -static inline void set_apb3spi_data_read(volatile apb3spi_t *reg, - uint8_t value) { - reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9); -} -static inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t *reg) { - return (reg->DATA >> 11) & 0x1; -} -static inline void set_apb3spi_data_ssgen(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg) { return reg->DATA; } +static inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value) { reg->DATA = value; } +static inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); } +static inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg) { return (reg->DATA >> 8) & 0x1; } +static inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8); } +static inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg) { return (reg->DATA >> 9) & 0x1; } +static inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9); } +static inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg) { return (reg->DATA >> 11) & 0x1; } +static inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11); } -static inline uint32_t -get_apb3spi_data_rx_data_invalid(volatile apb3spi_t *reg) { - return (reg->DATA >> 31) & 0x1; -} +static inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg) { return (reg->DATA >> 31) & 0x1; } // APB3SPI_STATUS -static inline uint32_t get_apb3spi_status(volatile apb3spi_t *reg) { - return reg->STATUS; -} -static inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t *reg) { - return (reg->STATUS >> 0) & 0x3f; -} -static inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t *reg) { - return (reg->STATUS >> 16) & 0x3f; -} +static inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg) { return reg->STATUS; } +static inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg) { return (reg->STATUS >> 0) & 0x3f; } +static inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg) { return (reg->STATUS >> 16) & 0x3f; } // APB3SPI_CONFIG -static inline uint32_t get_apb3spi_config(volatile apb3spi_t *reg) { - return reg->CONFIG; -} -static inline void set_apb3spi_config(volatile apb3spi_t *reg, uint32_t value) { - reg->CONFIG = value; -} -static inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t *reg) { - return (reg->CONFIG >> 0) & 0x3; -} -static inline void set_apb3spi_config_kind(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg) { return reg->CONFIG; } +static inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value) { reg->CONFIG = value; } +static inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg) { return (reg->CONFIG >> 0) & 0x3; } +static inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0); } -static inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t *reg) { - return (reg->CONFIG >> 4) & 0x3; -} -static inline void set_apb3spi_config_mode(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg) { return (reg->CONFIG >> 4) & 0x3; } +static inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4); } // APB3SPI_INTR -static inline uint32_t get_apb3spi_intr(volatile apb3spi_t *reg) { - return reg->INTR; -} -static inline void set_apb3spi_intr(volatile apb3spi_t *reg, uint32_t value) { - reg->INTR = value; -} -static inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t *reg) { - return (reg->INTR >> 0) & 0x1; -} -static inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t *reg, - uint8_t value) { - reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); -} -static inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t *reg) { - return (reg->INTR >> 1) & 0x1; -} -static inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t *reg, - uint8_t value) { - reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1); -} -static inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t *reg) { - return (reg->INTR >> 8) & 0x1; -} -static inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t *reg, - uint8_t value) { - reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8); -} -static inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t *reg) { - return (reg->INTR >> 9) & 0x1; -} -static inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t *reg, - uint8_t value) { - reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9); -} -static inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t *reg) { - return (reg->INTR >> 16) & 0x1; -} +static inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg) { return reg->INTR; } +static inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value) { reg->INTR = value; } +static inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 0) & 0x1; } +static inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); } +static inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 1) & 0x1; } +static inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1); } +static inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 8) & 0x1; } +static inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8); } +static inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 9) & 0x1; } +static inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9); } +static inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg) { return (reg->INTR >> 16) & 0x1; } // APB3SPI_SCLK_CONFIG -static inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t *reg) { - return reg->SCLK_CONFIG; -} -static inline void set_apb3spi_sclk_config(volatile apb3spi_t *reg, - uint32_t value) { - reg->SCLK_CONFIG = value; -} -static inline uint32_t -get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t *reg) { - return (reg->SCLK_CONFIG >> 0) & 0xfff; -} -static inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t *reg, - uint16_t value) { +static inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg) { return reg->SCLK_CONFIG; } +static inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value) { reg->SCLK_CONFIG = value; } +static inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg) { return (reg->SCLK_CONFIG >> 0) & 0xfff; } +static inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value) { reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0); } // APB3SPI_SSGEN_SETUP -static inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t *reg) { - return reg->SSGEN_SETUP; -} -static inline void set_apb3spi_ssgen_setup(volatile apb3spi_t *reg, - uint32_t value) { - reg->SSGEN_SETUP = value; -} -static inline uint32_t -get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t *reg) { - return (reg->SSGEN_SETUP >> 0) & 0xfff; -} -static inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t *reg, - uint16_t value) { +static inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg) { return reg->SSGEN_SETUP; } +static inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_SETUP = value; } +static inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_SETUP >> 0) & 0xfff; } +static inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value) { reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0); } // APB3SPI_SSGEN_HOLD -static inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t *reg) { - return reg->SSGEN_HOLD; -} -static inline void set_apb3spi_ssgen_hold(volatile apb3spi_t *reg, - uint32_t value) { - reg->SSGEN_HOLD = value; -} -static inline uint32_t -get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t *reg) { - return (reg->SSGEN_HOLD >> 0) & 0xfff; -} -static inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t *reg, - uint16_t value) { +static inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg) { return reg->SSGEN_HOLD; } +static inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_HOLD = value; } +static inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_HOLD >> 0) & 0xfff; } +static inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value) { reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0); } // APB3SPI_SSGEN_DISABLE -static inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t *reg) { - return reg->SSGEN_DISABLE; -} -static inline void set_apb3spi_ssgen_disable(volatile apb3spi_t *reg, - uint32_t value) { - reg->SSGEN_DISABLE = value; -} -static inline uint32_t -get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t *reg) { - return (reg->SSGEN_DISABLE >> 0) & 0xfff; -} -static inline void -set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t *reg, - uint16_t value) { +static inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg) { return reg->SSGEN_DISABLE; } +static inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_DISABLE = value; } +static inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_DISABLE >> 0) & 0xfff; } +static inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value) { reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0); } // APB3SPI_SSGEN_ACTIVE_HIGH -static inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t *reg) { - return reg->SSGEN_ACTIVE_HIGH; -} -static inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t *reg, - uint32_t value) { - reg->SSGEN_ACTIVE_HIGH = value; -} -static inline uint32_t -get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t *reg) { +static inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg) { return reg->SSGEN_ACTIVE_HIGH; } +static inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_ACTIVE_HIGH = value; } +static inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg) { return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1; } -static inline void -set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t *reg, - uint8_t value) { - reg->SSGEN_ACTIVE_HIGH = - (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0); +static inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value) { + reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0); } // APB3SPI_XIP_ENABLE -static inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t *reg) { - return reg->XIP_ENABLE; -} -static inline void set_apb3spi_xip_enable(volatile apb3spi_t *reg, - uint32_t value) { - reg->XIP_ENABLE = value; -} -static inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t *reg) { - return (reg->XIP_ENABLE >> 0) & 0x1; -} -static inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg) { return reg->XIP_ENABLE; } +static inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_ENABLE = value; } +static inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg) { return (reg->XIP_ENABLE >> 0) & 0x1; } +static inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value) { reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0); } // APB3SPI_XIP_CONFIG -static inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t *reg) { - return reg->XIP_CONFIG; -} -static inline void set_apb3spi_xip_config(volatile apb3spi_t *reg, - uint32_t value) { - reg->XIP_CONFIG = value; -} -static inline uint32_t -get_apb3spi_xip_config_instruction(volatile apb3spi_t *reg) { - return (reg->XIP_CONFIG >> 0) & 0xff; -} -static inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg) { return reg->XIP_CONFIG; } +static inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_CONFIG = value; } +static inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 0) & 0xff; } +static inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value) { reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0); } -static inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t *reg) { - return (reg->XIP_CONFIG >> 8) & 0x1; -} -static inline void set_apb3spi_xip_config_enable(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 8) & 0x1; } +static inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value) { reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8); } -static inline uint32_t -get_apb3spi_xip_config_dummy_value(volatile apb3spi_t *reg) { - return (reg->XIP_CONFIG >> 16) & 0xff; -} -static inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 16) & 0xff; } +static inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value) { reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16); } -static inline uint32_t -get_apb3spi_xip_config_dummy_count(volatile apb3spi_t *reg) { - return (reg->XIP_CONFIG >> 24) & 0xf; -} -static inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 24) & 0xf; } +static inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value) { reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24); } // APB3SPI_XIP_MODE -static inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t *reg) { - return reg->XIP_MODE; -} -static inline void set_apb3spi_xip_mode(volatile apb3spi_t *reg, - uint32_t value) { - reg->XIP_MODE = value; -} -static inline uint32_t -get_apb3spi_xip_mode_instruction(volatile apb3spi_t *reg) { - return (reg->XIP_MODE >> 0) & 0x3; -} -static inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg) { return reg->XIP_MODE; } +static inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_MODE = value; } +static inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 0) & 0x3; } +static inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value) { reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0); } -static inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t *reg) { - return (reg->XIP_MODE >> 8) & 0x3; -} -static inline void set_apb3spi_xip_mode_address(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 8) & 0x3; } +static inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value) { reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8); } -static inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t *reg) { - return (reg->XIP_MODE >> 16) & 0x3; -} -static inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 16) & 0x3; } +static inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value) { reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16); } -static inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t *reg) { - return (reg->XIP_MODE >> 24) & 0x3; -} -static inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t *reg, - uint8_t value) { +static inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 24) & 0x3; } +static inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value) { reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24); } // APB3SPI_XIP_WRITE -static inline void set_apb3spi_xip_write(volatile apb3spi_t *reg, - uint32_t value) { - reg->XIP_WRITE = value; -} -static inline void set_apb3spi_xip_write_data(volatile apb3spi_t *reg, - uint8_t value) { +static inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_WRITE = value; } +static inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value) { reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0); } // APB3SPI_XIP_READ_WRITE -static inline void set_apb3spi_xip_read_write(volatile apb3spi_t *reg, - uint32_t value) { - reg->XIP_READ_WRITE = value; -} -static inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t *reg, - uint8_t value) { +static inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_READ_WRITE = value; } +static inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value) { reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0); } // APB3SPI_XIP_READ -static inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t *reg) { - return reg->XIP_READ; -} -static inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t *reg) { - return (reg->XIP_READ >> 0) & 0xff; -} +static inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg) { return reg->XIP_READ; } +static inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg) { return (reg->XIP_READ >> 0) & 0xff; } #endif /* _BSP_APB3SPI_H */ \ No newline at end of file diff --git a/include/minres/devices/gen/camera.h b/include/minres/devices/gen/camera.h index 77c8f41..ad39854 100644 --- a/include/minres/devices/gen/camera.h +++ b/include/minres/devices/gen/camera.h @@ -30,90 +30,71 @@ typedef struct { #define CAMERA_CONFIG_OUTPUT_CURR_OFFS 0 #define CAMERA_CONFIG_OUTPUT_CURR_MASK 0x3 -#define CAMERA_CONFIG_OUTPUT_CURR(V) \ - ((V & CAMERA_CONFIG_OUTPUT_CURR_MASK) << CAMERA_CONFIG_OUTPUT_CURR_OFFS) +#define CAMERA_CONFIG_OUTPUT_CURR(V) ((V & CAMERA_CONFIG_OUTPUT_CURR_MASK) << CAMERA_CONFIG_OUTPUT_CURR_OFFS) #define CAMERA_CONFIG_OFFSET_RAMP_OFFS 2 #define CAMERA_CONFIG_OFFSET_RAMP_MASK 0x3 -#define CAMERA_CONFIG_OFFSET_RAMP(V) \ - ((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS) +#define CAMERA_CONFIG_OFFSET_RAMP(V) ((V & CAMERA_CONFIG_OFFSET_RAMP_MASK) << CAMERA_CONFIG_OFFSET_RAMP_OFFS) #define CAMERA_CONFIG_RAMP_GAIN_OFFS 4 #define CAMERA_CONFIG_RAMP_GAIN_MASK 0x3 -#define CAMERA_CONFIG_RAMP_GAIN(V) \ - ((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS) +#define CAMERA_CONFIG_RAMP_GAIN(V) ((V & CAMERA_CONFIG_RAMP_GAIN_MASK) << CAMERA_CONFIG_RAMP_GAIN_OFFS) #define CAMERA_CONFIG_VRST_PIX_OFFS 6 #define CAMERA_CONFIG_VRST_PIX_MASK 0x3 -#define CAMERA_CONFIG_VRST_PIX(V) \ - ((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS) +#define CAMERA_CONFIG_VRST_PIX(V) ((V & CAMERA_CONFIG_VRST_PIX_MASK) << CAMERA_CONFIG_VRST_PIX_OFFS) #define CAMERA_CONFIG_ROWS_IN_RESET_OFFS 8 #define CAMERA_CONFIG_ROWS_IN_RESET_MASK 0xff -#define CAMERA_CONFIG_ROWS_IN_RESET(V) \ - ((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS) +#define CAMERA_CONFIG_ROWS_IN_RESET(V) ((V & CAMERA_CONFIG_ROWS_IN_RESET_MASK) << CAMERA_CONFIG_ROWS_IN_RESET_OFFS) #define CAMERA_CONFIG_HIGH_SPEED_OFFS 16 #define CAMERA_CONFIG_HIGH_SPEED_MASK 0x1 -#define CAMERA_CONFIG_HIGH_SPEED(V) \ - ((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS) +#define CAMERA_CONFIG_HIGH_SPEED(V) ((V & CAMERA_CONFIG_HIGH_SPEED_MASK) << CAMERA_CONFIG_HIGH_SPEED_OFFS) #define CAMERA_CONFIG_IDLE_MODE_OFFS 17 #define CAMERA_CONFIG_IDLE_MODE_MASK 0x1 -#define CAMERA_CONFIG_IDLE_MODE(V) \ - ((V & CAMERA_CONFIG_IDLE_MODE_MASK) << CAMERA_CONFIG_IDLE_MODE_OFFS) +#define CAMERA_CONFIG_IDLE_MODE(V) ((V & CAMERA_CONFIG_IDLE_MODE_MASK) << CAMERA_CONFIG_IDLE_MODE_OFFS) #define CAMERA_CONFIG_CVC_CURR_OFFS 18 #define CAMERA_CONFIG_CVC_CURR_MASK 0x3 -#define CAMERA_CONFIG_CVC_CURR(V) \ - ((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS) +#define CAMERA_CONFIG_CVC_CURR(V) ((V & CAMERA_CONFIG_CVC_CURR_MASK) << CAMERA_CONFIG_CVC_CURR_OFFS) #define CAMERA_CONFIG_VREF_OFFS 20 #define CAMERA_CONFIG_VREF_MASK 0x3 -#define CAMERA_CONFIG_VREF(V) \ - ((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS) +#define CAMERA_CONFIG_VREF(V) ((V & CAMERA_CONFIG_VREF_MASK) << CAMERA_CONFIG_VREF_OFFS) #define CAMERA_CONFIG_MCLK_MODE_OFFS 22 #define CAMERA_CONFIG_MCLK_MODE_MASK 0x3 -#define CAMERA_CONFIG_MCLK_MODE(V) \ - ((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS) +#define CAMERA_CONFIG_MCLK_MODE(V) ((V & CAMERA_CONFIG_MCLK_MODE_MASK) << CAMERA_CONFIG_MCLK_MODE_OFFS) #define CAMERA_CONFIG_OUTPUT_MODE_OFFS 24 #define CAMERA_CONFIG_OUTPUT_MODE_MASK 0x1 -#define CAMERA_CONFIG_OUTPUT_MODE(V) \ - ((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS) +#define CAMERA_CONFIG_OUTPUT_MODE(V) ((V & CAMERA_CONFIG_OUTPUT_MODE_MASK) << CAMERA_CONFIG_OUTPUT_MODE_OFFS) #define CAMERA_CONFIG_CDS_GAIN_OFFS 25 #define CAMERA_CONFIG_CDS_GAIN_MASK 0x1 -#define CAMERA_CONFIG_CDS_GAIN(V) \ - ((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS) +#define CAMERA_CONFIG_CDS_GAIN(V) ((V & CAMERA_CONFIG_CDS_GAIN_MASK) << CAMERA_CONFIG_CDS_GAIN_OFFS) #define CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS 26 #define CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK 0x1 -#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) \ - ((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) \ - << CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS) +#define CAMERA_CONFIG_BIAS_CURR_INCREASE(V) ((V & CAMERA_CONFIG_BIAS_CURR_INCREASE_MASK) << CAMERA_CONFIG_BIAS_CURR_INCREASE_OFFS) #define CAMERA_CONFIG_ROWS_DELAY_OFFS 27 #define CAMERA_CONFIG_ROWS_DELAY_MASK 0x1f -#define CAMERA_CONFIG_ROWS_DELAY(V) \ - ((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS) +#define CAMERA_CONFIG_ROWS_DELAY(V) ((V & CAMERA_CONFIG_ROWS_DELAY_MASK) << CAMERA_CONFIG_ROWS_DELAY_OFFS) #define CAMERA_CONFIG2_AUTO_IDLE_OFFS 0 #define CAMERA_CONFIG2_AUTO_IDLE_MASK 0x1 -#define CAMERA_CONFIG2_AUTO_IDLE(V) \ - ((V & CAMERA_CONFIG2_AUTO_IDLE_MASK) << CAMERA_CONFIG2_AUTO_IDLE_OFFS) +#define CAMERA_CONFIG2_AUTO_IDLE(V) ((V & CAMERA_CONFIG2_AUTO_IDLE_MASK) << CAMERA_CONFIG2_AUTO_IDLE_OFFS) #define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS 1 #define CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK 0x1 -#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME(V) \ - ((V & CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK) \ - << CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS) +#define CAMERA_CONFIG2_AUTO_DISCARD_FRAME(V) ((V & CAMERA_CONFIG2_AUTO_DISCARD_FRAME_MASK) << CAMERA_CONFIG2_AUTO_DISCARD_FRAME_OFFS) #define CAMERA_DATA_SIZE_OFFS 0 #define CAMERA_DATA_SIZE_MASK 0x3 -#define CAMERA_DATA_SIZE(V) \ - ((V & CAMERA_DATA_SIZE_MASK) << CAMERA_DATA_SIZE_OFFS) +#define CAMERA_DATA_SIZE(V) ((V & CAMERA_DATA_SIZE_MASK) << CAMERA_DATA_SIZE_OFFS) #define CAMERA_START_OFFS 0 #define CAMERA_START_MASK 0x1 @@ -125,265 +106,151 @@ typedef struct { #define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0 #define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfff -#define CAMERA_CAMERA_CLOCK_CTRL(V) \ - ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS) +#define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS) #define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0 #define CAMERA_IE_EN_PIXEL_AVAIL_MASK 0x1 -#define CAMERA_IE_EN_PIXEL_AVAIL(V) \ - ((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS) +#define CAMERA_IE_EN_PIXEL_AVAIL(V) ((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS) #define CAMERA_IE_EN_FRAME_FINISHED_OFFS 1 #define CAMERA_IE_EN_FRAME_FINISHED_MASK 0x1 -#define CAMERA_IE_EN_FRAME_FINISHED(V) \ - ((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS) +#define CAMERA_IE_EN_FRAME_FINISHED(V) ((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS) #define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS 0 #define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK 0x1 -#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) \ - ((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) \ - << CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS) +#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) ((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) << CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS) #define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS 1 #define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1 -#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) \ - ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) \ - << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS) +#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS) // CAMERA_PIXEL -static inline uint32_t get_camera_pixel(volatile camera_t *reg) { - return (reg->PIXEL >> 0) & 0xffffffff; -} -static inline void set_camera_pixel(volatile camera_t *reg, uint32_t value) { +static inline uint32_t get_camera_pixel(volatile camera_t* reg) { return (reg->PIXEL >> 0) & 0xffffffff; } +static inline void set_camera_pixel(volatile camera_t* reg, uint32_t value) { reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0); } // CAMERA_CONFIG -static inline uint32_t get_camera_config(volatile camera_t *reg) { - return reg->CONFIG; -} -static inline void set_camera_config(volatile camera_t *reg, uint32_t value) { - reg->CONFIG = value; -} -static inline uint32_t get_camera_config_output_curr(volatile camera_t *reg) { - return (reg->CONFIG >> 0) & 0x3; -} -static inline void set_camera_config_output_curr(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config(volatile camera_t* reg) { return reg->CONFIG; } +static inline void set_camera_config(volatile camera_t* reg, uint32_t value) { reg->CONFIG = value; } +static inline uint32_t get_camera_config_output_curr(volatile camera_t* reg) { return (reg->CONFIG >> 0) & 0x3; } +static inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0); } -static inline uint32_t get_camera_config_offset_ramp(volatile camera_t *reg) { - return (reg->CONFIG >> 2) & 0x3; -} -static inline void set_camera_config_offset_ramp(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg) { return (reg->CONFIG >> 2) & 0x3; } +static inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2); } -static inline uint32_t get_camera_config_ramp_gain(volatile camera_t *reg) { - return (reg->CONFIG >> 4) & 0x3; -} -static inline void set_camera_config_ramp_gain(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg) { return (reg->CONFIG >> 4) & 0x3; } +static inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4); } -static inline uint32_t get_camera_config_vrst_pix(volatile camera_t *reg) { - return (reg->CONFIG >> 6) & 0x3; -} -static inline void set_camera_config_vrst_pix(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg) { return (reg->CONFIG >> 6) & 0x3; } +static inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6); } -static inline uint32_t get_camera_config_rows_in_reset(volatile camera_t *reg) { - return (reg->CONFIG >> 8) & 0xff; -} -static inline void set_camera_config_rows_in_reset(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg) { return (reg->CONFIG >> 8) & 0xff; } +static inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8); } -static inline uint32_t get_camera_config_high_speed(volatile camera_t *reg) { - return (reg->CONFIG >> 16) & 0x1; -} -static inline void set_camera_config_high_speed(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_high_speed(volatile camera_t* reg) { return (reg->CONFIG >> 16) & 0x1; } +static inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16); } -static inline uint32_t get_camera_config_idle_mode(volatile camera_t *reg) { - return (reg->CONFIG >> 17) & 0x1; -} -static inline void set_camera_config_idle_mode(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg) { return (reg->CONFIG >> 17) & 0x1; } +static inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17); } -static inline uint32_t get_camera_config_cvc_curr(volatile camera_t *reg) { - return (reg->CONFIG >> 18) & 0x3; -} -static inline void set_camera_config_cvc_curr(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg) { return (reg->CONFIG >> 18) & 0x3; } +static inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18); } -static inline uint32_t get_camera_config_vref(volatile camera_t *reg) { - return (reg->CONFIG >> 20) & 0x3; -} -static inline void set_camera_config_vref(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_vref(volatile camera_t* reg) { return (reg->CONFIG >> 20) & 0x3; } +static inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20); } -static inline uint32_t get_camera_config_mclk_mode(volatile camera_t *reg) { - return (reg->CONFIG >> 22) & 0x3; -} -static inline void set_camera_config_mclk_mode(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg) { return (reg->CONFIG >> 22) & 0x3; } +static inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22); } -static inline uint32_t get_camera_config_output_mode(volatile camera_t *reg) { - return (reg->CONFIG >> 24) & 0x1; -} -static inline void set_camera_config_output_mode(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_output_mode(volatile camera_t* reg) { return (reg->CONFIG >> 24) & 0x1; } +static inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24); } -static inline uint32_t get_camera_config_cds_gain(volatile camera_t *reg) { - return (reg->CONFIG >> 25) & 0x1; -} -static inline void set_camera_config_cds_gain(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg) { return (reg->CONFIG >> 25) & 0x1; } +static inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25); } -static inline uint32_t -get_camera_config_bias_curr_increase(volatile camera_t *reg) { - return (reg->CONFIG >> 26) & 0x1; -} -static inline void set_camera_config_bias_curr_increase(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg) { return (reg->CONFIG >> 26) & 0x1; } +static inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26); } -static inline uint32_t get_camera_config_rows_delay(volatile camera_t *reg) { - return (reg->CONFIG >> 27) & 0x1f; -} -static inline void set_camera_config_rows_delay(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg) { return (reg->CONFIG >> 27) & 0x1f; } +static inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27); } // CAMERA_CONFIG2 -static inline uint32_t get_camera_config2(volatile camera_t *reg) { - return reg->CONFIG2; -} -static inline void set_camera_config2(volatile camera_t *reg, uint32_t value) { - reg->CONFIG2 = value; -} -static inline uint32_t get_camera_config2_auto_idle(volatile camera_t *reg) { - return (reg->CONFIG2 >> 0) & 0x1; -} -static inline void set_camera_config2_auto_idle(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config2(volatile camera_t* reg) { return reg->CONFIG2; } +static inline void set_camera_config2(volatile camera_t* reg, uint32_t value) { reg->CONFIG2 = value; } +static inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg) { return (reg->CONFIG2 >> 0) & 0x1; } +static inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value) { reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0); } -static inline uint32_t -get_camera_config2_auto_discard_frame(volatile camera_t *reg) { - return (reg->CONFIG2 >> 1) & 0x1; -} -static inline void set_camera_config2_auto_discard_frame(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg) { return (reg->CONFIG2 >> 1) & 0x1; } +static inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value) { reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1); } // CAMERA_DATA_SIZE -static inline uint32_t get_camera_data_size(volatile camera_t *reg) { - return reg->DATA_SIZE; -} -static inline void set_camera_data_size(volatile camera_t *reg, - uint32_t value) { - reg->DATA_SIZE = value; -} -static inline uint32_t get_camera_data_size_data_size(volatile camera_t *reg) { - return (reg->DATA_SIZE >> 0) & 0x3; -} -static inline void set_camera_data_size_data_size(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_data_size(volatile camera_t* reg) { return reg->DATA_SIZE; } +static inline void set_camera_data_size(volatile camera_t* reg, uint32_t value) { reg->DATA_SIZE = value; } +static inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg) { return (reg->DATA_SIZE >> 0) & 0x3; } +static inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value) { reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0); } // CAMERA_START -static inline uint32_t get_camera_start(volatile camera_t *reg) { - return reg->START; -} -static inline void set_camera_start(volatile camera_t *reg, uint32_t value) { - reg->START = value; -} -static inline uint32_t get_camera_start_start(volatile camera_t *reg) { - return (reg->START >> 0) & 0x1; -} -static inline void set_camera_start_start(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_start(volatile camera_t* reg) { return reg->START; } +static inline void set_camera_start(volatile camera_t* reg, uint32_t value) { reg->START = value; } +static inline uint32_t get_camera_start_start(volatile camera_t* reg) { return (reg->START >> 0) & 0x1; } +static inline void set_camera_start_start(volatile camera_t* reg, uint8_t value) { reg->START = (reg->START & ~(0x1U << 0)) | (value << 0); } // CAMERA_STATUS -static inline uint32_t get_camera_status(volatile camera_t *reg) { - return reg->STATUS; -} -static inline uint32_t get_camera_status_pixel_avail(volatile camera_t *reg) { - return (reg->STATUS >> 0) & 0x1; -} +static inline uint32_t get_camera_status(volatile camera_t* reg) { return reg->STATUS; } +static inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg) { return (reg->STATUS >> 0) & 0x1; } // CAMERA_CAMERA_CLOCK_CTRL -static inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t *reg) { - return reg->CAMERA_CLOCK_CTRL; -} -static inline void set_camera_camera_clock_ctrl(volatile camera_t *reg, - uint32_t value) { - reg->CAMERA_CLOCK_CTRL = value; -} -static inline uint32_t -get_camera_camera_clock_ctrl_divider(volatile camera_t *reg) { - return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff; -} -static inline void set_camera_camera_clock_ctrl_divider(volatile camera_t *reg, - uint16_t value) { - reg->CAMERA_CLOCK_CTRL = - (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0); +static inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg) { return reg->CAMERA_CLOCK_CTRL; } +static inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value) { reg->CAMERA_CLOCK_CTRL = value; } +static inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg) { return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff; } +static inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value) { + reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0); } // CAMERA_IE -static inline uint32_t get_camera_ie(volatile camera_t *reg) { return reg->IE; } -static inline void set_camera_ie(volatile camera_t *reg, uint32_t value) { - reg->IE = value; -} -static inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t *reg) { - return (reg->IE >> 0) & 0x1; -} -static inline void set_camera_ie_en_pixel_avail(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_ie(volatile camera_t* reg) { return reg->IE; } +static inline void set_camera_ie(volatile camera_t* reg, uint32_t value) { reg->IE = value; } +static inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg) { return (reg->IE >> 0) & 0x1; } +static inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value) { reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); } -static inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t *reg) { - return (reg->IE >> 1) & 0x1; -} -static inline void set_camera_ie_en_frame_finished(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg) { return (reg->IE >> 1) & 0x1; } +static inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value) { reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); } // CAMERA_IP -static inline uint32_t get_camera_ip(volatile camera_t *reg) { return reg->IP; } -static inline void set_camera_ip(volatile camera_t *reg, uint32_t value) { - reg->IP = value; -} -static inline uint32_t -get_camera_ip_pixel_avail_irq_pend(volatile camera_t *reg) { - return (reg->IP >> 0) & 0x1; -} -static inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_ip(volatile camera_t* reg) { return reg->IP; } +static inline void set_camera_ip(volatile camera_t* reg, uint32_t value) { reg->IP = value; } +static inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg) { return (reg->IP >> 0) & 0x1; } +static inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value) { reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0); } -static inline uint32_t -get_camera_ip_frame_finished_irq_pend(volatile camera_t *reg) { - return (reg->IP >> 1) & 0x1; -} -static inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t *reg, - uint8_t value) { +static inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg) { return (reg->IP >> 1) & 0x1; } +static inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value) { reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1); } diff --git a/include/minres/devices/gen/dma.h b/include/minres/devices/gen/dma.h index 97ad794..04adf44 100644 --- a/include/minres/devices/gen/dma.h +++ b/include/minres/devices/gen/dma.h @@ -33,520 +33,310 @@ typedef struct { #define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0 #define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1 -#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) \ - ((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) \ - << DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS) +#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS) #define DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1 #define DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1 -#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) \ - ((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) \ - << DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS) +#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS) #define DMA_STATUS_CH0_BUSY_OFFS 0 #define DMA_STATUS_CH0_BUSY_MASK 0x1 -#define DMA_STATUS_CH0_BUSY(V) \ - ((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS) +#define DMA_STATUS_CH0_BUSY(V) ((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS) #define DMA_STATUS_CH1_BUSY_OFFS 1 #define DMA_STATUS_CH1_BUSY_MASK 0x1 -#define DMA_STATUS_CH1_BUSY(V) \ - ((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS) +#define DMA_STATUS_CH1_BUSY(V) ((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS) #define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0 #define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1 -#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) \ - ((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) \ - << DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS) +#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS) #define DMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1 #define DMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1 -#define DMA_IE_CH0_IE_TRANSFER_DONE(V) \ - ((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS) +#define DMA_IE_CH0_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS) #define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2 #define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1 -#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) \ - ((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) \ - << DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS) +#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS) #define DMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3 #define DMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1 -#define DMA_IE_CH1_IE_TRANSFER_DONE(V) \ - ((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS) +#define DMA_IE_CH1_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS) #define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0 #define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1 -#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) \ - ((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) \ - << DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS) +#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS) #define DMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1 #define DMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1 -#define DMA_IP_CH0_IP_TRANSFER_DONE(V) \ - ((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS) +#define DMA_IP_CH0_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS) #define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2 #define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1 -#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) \ - ((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) \ - << DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS) +#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS) #define DMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3 #define DMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1 -#define DMA_IP_CH1_IP_TRANSFER_DONE(V) \ - ((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS) +#define DMA_IP_CH1_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS) #define DMA_CH0_EVENT_SELECT_OFFS 0 #define DMA_CH0_EVENT_SELECT_MASK 0x1f -#define DMA_CH0_EVENT_SELECT(V) \ - ((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS) +#define DMA_CH0_EVENT_SELECT(V) ((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS) #define DMA_CH0_EVENT_COMBINE_OFFS 31 #define DMA_CH0_EVENT_COMBINE_MASK 0x1 -#define DMA_CH0_EVENT_COMBINE(V) \ - ((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS) +#define DMA_CH0_EVENT_COMBINE(V) ((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS) #define DMA_CH0_TRANSFER_WIDTH_OFFS 0 #define DMA_CH0_TRANSFER_WIDTH_MASK 0x3 -#define DMA_CH0_TRANSFER_WIDTH(V) \ - ((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS) +#define DMA_CH0_TRANSFER_WIDTH(V) ((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS) #define DMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2 #define DMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff -#define DMA_CH0_TRANSFER_SEG_LENGTH(V) \ - ((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS) +#define DMA_CH0_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS) #define DMA_CH0_TRANSFER_SEG_COUNT_OFFS 12 #define DMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff -#define DMA_CH0_TRANSFER_SEG_COUNT(V) \ - ((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS) +#define DMA_CH0_TRANSFER_SEG_COUNT(V) ((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS) #define DMA_CH0_SRC_START_ADDR_OFFS 0 #define DMA_CH0_SRC_START_ADDR_MASK 0xffffffff -#define DMA_CH0_SRC_START_ADDR(V) \ - ((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS) +#define DMA_CH0_SRC_START_ADDR(V) ((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS) #define DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0 #define DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff -#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) \ - ((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) \ - << DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS) +#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS) #define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12 #define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff -#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) \ - ((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) \ - << DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS) +#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS) #define DMA_CH0_DST_START_ADDR_OFFS 0 #define DMA_CH0_DST_START_ADDR_MASK 0xffffffff -#define DMA_CH0_DST_START_ADDR(V) \ - ((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS) +#define DMA_CH0_DST_START_ADDR(V) ((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS) #define DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0 #define DMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff -#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) \ - ((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) \ - << DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS) +#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS) #define DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12 #define DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff -#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) \ - ((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) \ - << DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS) +#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS) #define DMA_CH1_EVENT_SELECT_OFFS 0 #define DMA_CH1_EVENT_SELECT_MASK 0x1f -#define DMA_CH1_EVENT_SELECT(V) \ - ((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS) +#define DMA_CH1_EVENT_SELECT(V) ((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS) #define DMA_CH1_EVENT_COMBINE_OFFS 31 #define DMA_CH1_EVENT_COMBINE_MASK 0x1 -#define DMA_CH1_EVENT_COMBINE(V) \ - ((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS) +#define DMA_CH1_EVENT_COMBINE(V) ((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS) #define DMA_CH1_TRANSFER_WIDTH_OFFS 0 #define DMA_CH1_TRANSFER_WIDTH_MASK 0x3 -#define DMA_CH1_TRANSFER_WIDTH(V) \ - ((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS) +#define DMA_CH1_TRANSFER_WIDTH(V) ((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS) #define DMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2 #define DMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff -#define DMA_CH1_TRANSFER_SEG_LENGTH(V) \ - ((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS) +#define DMA_CH1_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS) #define DMA_CH1_TRANSFER_SEG_COUNT_OFFS 12 #define DMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff -#define DMA_CH1_TRANSFER_SEG_COUNT(V) \ - ((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS) +#define DMA_CH1_TRANSFER_SEG_COUNT(V) ((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS) #define DMA_CH1_SRC_START_ADDR_OFFS 0 #define DMA_CH1_SRC_START_ADDR_MASK 0xffffffff -#define DMA_CH1_SRC_START_ADDR(V) \ - ((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS) +#define DMA_CH1_SRC_START_ADDR(V) ((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS) #define DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0 #define DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff -#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) \ - ((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) \ - << DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS) +#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS) #define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12 #define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff -#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) \ - ((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) \ - << DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS) +#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS) #define DMA_CH1_DST_START_ADDR_OFFS 0 #define DMA_CH1_DST_START_ADDR_MASK 0xffffffff -#define DMA_CH1_DST_START_ADDR(V) \ - ((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS) +#define DMA_CH1_DST_START_ADDR(V) ((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS) #define DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0 #define DMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff -#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) \ - ((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) \ - << DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS) +#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS) #define DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12 #define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff -#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) \ - ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) \ - << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS) +#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS) // DMA_CONTROL -static inline uint32_t get_dma_control(volatile dma_t *reg) { - return reg->CONTROL; -} -static inline void set_dma_control(volatile dma_t *reg, uint32_t value) { - reg->CONTROL = value; -} -static inline uint32_t -get_dma_control_ch0_enable_transfer(volatile dma_t *reg) { - return (reg->CONTROL >> 0) & 0x1; -} -static inline void set_dma_control_ch0_enable_transfer(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_control(volatile dma_t* reg) { return reg->CONTROL; } +static inline void set_dma_control(volatile dma_t* reg, uint32_t value) { reg->CONTROL = value; } +static inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 0) & 0x1; } +static inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0); } -static inline uint32_t -get_dma_control_ch1_enable_transfer(volatile dma_t *reg) { - return (reg->CONTROL >> 1) & 0x1; -} -static inline void set_dma_control_ch1_enable_transfer(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 1) & 0x1; } +static inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1); } // DMA_STATUS -static inline uint32_t get_dma_status(volatile dma_t *reg) { - return reg->STATUS; -} -static inline uint32_t get_dma_status_ch0_busy(volatile dma_t *reg) { - return (reg->STATUS >> 0) & 0x1; -} -static inline uint32_t get_dma_status_ch1_busy(volatile dma_t *reg) { - return (reg->STATUS >> 1) & 0x1; -} +static inline uint32_t get_dma_status(volatile dma_t* reg) { return reg->STATUS; } +static inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg) { return (reg->STATUS >> 0) & 0x1; } +static inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg) { return (reg->STATUS >> 1) & 0x1; } // DMA_IE -static inline uint32_t get_dma_ie(volatile dma_t *reg) { return reg->IE; } -static inline void set_dma_ie(volatile dma_t *reg, uint32_t value) { - reg->IE = value; -} -static inline uint32_t -get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t *reg) { - return (reg->IE >> 0) & 0x1; -} -static inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_ie(volatile dma_t* reg) { return reg->IE; } +static inline void set_dma_ie(volatile dma_t* reg, uint32_t value) { reg->IE = value; } +static inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 0) & 0x1; } +static inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) { reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); } -static inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t *reg) { - return (reg->IE >> 1) & 0x1; -} -static inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 1) & 0x1; } +static inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value) { reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); } -static inline uint32_t -get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t *reg) { - return (reg->IE >> 2) & 0x1; -} -static inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 2) & 0x1; } +static inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) { reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2); } -static inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t *reg) { - return (reg->IE >> 3) & 0x1; -} -static inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 3) & 0x1; } +static inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value) { reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3); } // DMA_IP -static inline uint32_t get_dma_ip(volatile dma_t *reg) { return reg->IP; } -static inline uint32_t -get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t *reg) { - return (reg->IP >> 0) & 0x1; -} -static inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t *reg) { - return (reg->IP >> 1) & 0x1; -} -static inline uint32_t -get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t *reg) { - return (reg->IP >> 2) & 0x1; -} -static inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t *reg) { - return (reg->IP >> 3) & 0x1; -} +static inline uint32_t get_dma_ip(volatile dma_t* reg) { return reg->IP; } +static inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 0) & 0x1; } +static inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 1) & 0x1; } +static inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 2) & 0x1; } +static inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 3) & 0x1; } // DMA_CH0_EVENT -static inline uint32_t get_dma_ch0_event(volatile dma_t *reg) { - return reg->CH0_EVENT; -} -static inline void set_dma_ch0_event(volatile dma_t *reg, uint32_t value) { - reg->CH0_EVENT = value; -} -static inline uint32_t get_dma_ch0_event_select(volatile dma_t *reg) { - return (reg->CH0_EVENT >> 0) & 0x1f; -} -static inline void set_dma_ch0_event_select(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_ch0_event(volatile dma_t* reg) { return reg->CH0_EVENT; } +static inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value) { reg->CH0_EVENT = value; } +static inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg) { return (reg->CH0_EVENT >> 0) & 0x1f; } +static inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value) { reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0); } -static inline uint32_t get_dma_ch0_event_combine(volatile dma_t *reg) { - return (reg->CH0_EVENT >> 31) & 0x1; -} -static inline void set_dma_ch0_event_combine(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg) { return (reg->CH0_EVENT >> 31) & 0x1; } +static inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value) { reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31); } // DMA_CH0_TRANSFER -static inline uint32_t get_dma_ch0_transfer(volatile dma_t *reg) { - return reg->CH0_TRANSFER; -} -static inline void set_dma_ch0_transfer(volatile dma_t *reg, uint32_t value) { - reg->CH0_TRANSFER = value; -} -static inline uint32_t get_dma_ch0_transfer_width(volatile dma_t *reg) { - return (reg->CH0_TRANSFER >> 0) & 0x3; -} -static inline void set_dma_ch0_transfer_width(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg) { return reg->CH0_TRANSFER; } +static inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value) { reg->CH0_TRANSFER = value; } +static inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 0) & 0x3; } +static inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value) { reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0); } -static inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t *reg) { - return (reg->CH0_TRANSFER >> 2) & 0x3ff; -} -static inline void set_dma_ch0_transfer_seg_length(volatile dma_t *reg, - uint16_t value) { +static inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 2) & 0x3ff; } +static inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value) { reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2); } -static inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t *reg) { - return (reg->CH0_TRANSFER >> 12) & 0xfffff; -} -static inline void set_dma_ch0_transfer_seg_count(volatile dma_t *reg, - uint32_t value) { +static inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 12) & 0xfffff; } +static inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value) { reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12); } // DMA_CH0_SRC_START_ADDR -static inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t *reg) { - return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff; -} -static inline void set_dma_ch0_src_start_addr(volatile dma_t *reg, - uint32_t value) { - reg->CH0_SRC_START_ADDR = - (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); +static inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg) { return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff; } +static inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value) { + reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); } // DMA_CH0_SRC_ADDR_INC -static inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t *reg) { - return reg->CH0_SRC_ADDR_INC; +static inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg) { return reg->CH0_SRC_ADDR_INC; } +static inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_SRC_ADDR_INC = value; } +static inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff; } +static inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) { + reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0); } -static inline void set_dma_ch0_src_addr_inc(volatile dma_t *reg, - uint32_t value) { - reg->CH0_SRC_ADDR_INC = value; -} -static inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t *reg) { - return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff; -} -static inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t *reg, - uint16_t value) { - reg->CH0_SRC_ADDR_INC = - (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0); -} -static inline uint32_t -get_dma_ch0_src_addr_inc_src_stride(volatile dma_t *reg) { - return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff; -} -static inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t *reg, - uint32_t value) { - reg->CH0_SRC_ADDR_INC = - (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); +static inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff; } +static inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) { + reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); } // DMA_CH0_DST_START_ADDR -static inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t *reg) { - return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff; -} -static inline void set_dma_ch0_dst_start_addr(volatile dma_t *reg, - uint32_t value) { - reg->CH0_DST_START_ADDR = - (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); +static inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg) { return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff; } +static inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value) { + reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); } // DMA_CH0_DST_ADDR_INC -static inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t *reg) { - return reg->CH0_DST_ADDR_INC; +static inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg) { return reg->CH0_DST_ADDR_INC; } +static inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_DST_ADDR_INC = value; } +static inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff; } +static inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) { + reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0); } -static inline void set_dma_ch0_dst_addr_inc(volatile dma_t *reg, - uint32_t value) { - reg->CH0_DST_ADDR_INC = value; -} -static inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t *reg) { - return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff; -} -static inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t *reg, - uint16_t value) { - reg->CH0_DST_ADDR_INC = - (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0); -} -static inline uint32_t -get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t *reg) { - return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff; -} -static inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t *reg, - uint32_t value) { - reg->CH0_DST_ADDR_INC = - (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); +static inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff; } +static inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) { + reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); } // DMA_CH1_EVENT -static inline uint32_t get_dma_ch1_event(volatile dma_t *reg) { - return reg->CH1_EVENT; -} -static inline void set_dma_ch1_event(volatile dma_t *reg, uint32_t value) { - reg->CH1_EVENT = value; -} -static inline uint32_t get_dma_ch1_event_select(volatile dma_t *reg) { - return (reg->CH1_EVENT >> 0) & 0x1f; -} -static inline void set_dma_ch1_event_select(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_ch1_event(volatile dma_t* reg) { return reg->CH1_EVENT; } +static inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value) { reg->CH1_EVENT = value; } +static inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg) { return (reg->CH1_EVENT >> 0) & 0x1f; } +static inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value) { reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0); } -static inline uint32_t get_dma_ch1_event_combine(volatile dma_t *reg) { - return (reg->CH1_EVENT >> 31) & 0x1; -} -static inline void set_dma_ch1_event_combine(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg) { return (reg->CH1_EVENT >> 31) & 0x1; } +static inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value) { reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31); } // DMA_CH1_TRANSFER -static inline uint32_t get_dma_ch1_transfer(volatile dma_t *reg) { - return reg->CH1_TRANSFER; -} -static inline void set_dma_ch1_transfer(volatile dma_t *reg, uint32_t value) { - reg->CH1_TRANSFER = value; -} -static inline uint32_t get_dma_ch1_transfer_width(volatile dma_t *reg) { - return (reg->CH1_TRANSFER >> 0) & 0x3; -} -static inline void set_dma_ch1_transfer_width(volatile dma_t *reg, - uint8_t value) { +static inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg) { return reg->CH1_TRANSFER; } +static inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value) { reg->CH1_TRANSFER = value; } +static inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 0) & 0x3; } +static inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value) { reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0); } -static inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t *reg) { - return (reg->CH1_TRANSFER >> 2) & 0x3ff; -} -static inline void set_dma_ch1_transfer_seg_length(volatile dma_t *reg, - uint16_t value) { +static inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 2) & 0x3ff; } +static inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value) { reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2); } -static inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t *reg) { - return (reg->CH1_TRANSFER >> 12) & 0xfffff; -} -static inline void set_dma_ch1_transfer_seg_count(volatile dma_t *reg, - uint32_t value) { +static inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 12) & 0xfffff; } +static inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value) { reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12); } // DMA_CH1_SRC_START_ADDR -static inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t *reg) { - return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff; -} -static inline void set_dma_ch1_src_start_addr(volatile dma_t *reg, - uint32_t value) { - reg->CH1_SRC_START_ADDR = - (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); +static inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg) { return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff; } +static inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value) { + reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); } // DMA_CH1_SRC_ADDR_INC -static inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t *reg) { - return reg->CH1_SRC_ADDR_INC; +static inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg) { return reg->CH1_SRC_ADDR_INC; } +static inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_SRC_ADDR_INC = value; } +static inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff; } +static inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) { + reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0); } -static inline void set_dma_ch1_src_addr_inc(volatile dma_t *reg, - uint32_t value) { - reg->CH1_SRC_ADDR_INC = value; -} -static inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t *reg) { - return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff; -} -static inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t *reg, - uint16_t value) { - reg->CH1_SRC_ADDR_INC = - (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0); -} -static inline uint32_t -get_dma_ch1_src_addr_inc_src_stride(volatile dma_t *reg) { - return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff; -} -static inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t *reg, - uint32_t value) { - reg->CH1_SRC_ADDR_INC = - (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); +static inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff; } +static inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) { + reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); } // DMA_CH1_DST_START_ADDR -static inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t *reg) { - return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff; -} -static inline void set_dma_ch1_dst_start_addr(volatile dma_t *reg, - uint32_t value) { - reg->CH1_DST_START_ADDR = - (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); +static inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg) { return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff; } +static inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value) { + reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); } // DMA_CH1_DST_ADDR_INC -static inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t *reg) { - return reg->CH1_DST_ADDR_INC; +static inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg) { return reg->CH1_DST_ADDR_INC; } +static inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_DST_ADDR_INC = value; } +static inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff; } +static inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) { + reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0); } -static inline void set_dma_ch1_dst_addr_inc(volatile dma_t *reg, - uint32_t value) { - reg->CH1_DST_ADDR_INC = value; -} -static inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t *reg) { - return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff; -} -static inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t *reg, - uint16_t value) { - reg->CH1_DST_ADDR_INC = - (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0); -} -static inline uint32_t -get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t *reg) { - return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff; -} -static inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t *reg, - uint32_t value) { - reg->CH1_DST_ADDR_INC = - (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); +static inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff; } +static inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) { + reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); } #endif /* _BSP_DMA_H */ diff --git a/include/minres/devices/gen/gpio.h b/include/minres/devices/gen/gpio.h index 103d976..b16efa6 100644 --- a/include/minres/devices/gen/gpio.h +++ b/include/minres/devices/gen/gpio.h @@ -39,8 +39,7 @@ typedef struct { #define GPIO_WRITEENABLE_OFFS 0 #define GPIO_WRITEENABLE_MASK 0xffffffff -#define GPIO_WRITEENABLE(V) \ - ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS) +#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS) #define GPIO_PULLUP_OFFS 0 #define GPIO_PULLUP_MASK 0xffffffff @@ -52,163 +51,131 @@ typedef struct { #define GPIO_DRIVESTRENGTH_0_PIN_0_OFFS 0 #define GPIO_DRIVESTRENGTH_0_PIN_0_MASK 0x7 -#define GPIO_DRIVESTRENGTH_0_PIN_0(V) \ - ((V & GPIO_DRIVESTRENGTH_0_PIN_0_MASK) << GPIO_DRIVESTRENGTH_0_PIN_0_OFFS) +#define GPIO_DRIVESTRENGTH_0_PIN_0(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_0_MASK) << GPIO_DRIVESTRENGTH_0_PIN_0_OFFS) #define GPIO_DRIVESTRENGTH_0_PIN_1_OFFS 4 #define GPIO_DRIVESTRENGTH_0_PIN_1_MASK 0x7 -#define GPIO_DRIVESTRENGTH_0_PIN_1(V) \ - ((V & GPIO_DRIVESTRENGTH_0_PIN_1_MASK) << GPIO_DRIVESTRENGTH_0_PIN_1_OFFS) +#define GPIO_DRIVESTRENGTH_0_PIN_1(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_1_MASK) << GPIO_DRIVESTRENGTH_0_PIN_1_OFFS) #define GPIO_DRIVESTRENGTH_0_PIN_2_OFFS 8 #define GPIO_DRIVESTRENGTH_0_PIN_2_MASK 0x7 -#define GPIO_DRIVESTRENGTH_0_PIN_2(V) \ - ((V & GPIO_DRIVESTRENGTH_0_PIN_2_MASK) << GPIO_DRIVESTRENGTH_0_PIN_2_OFFS) +#define GPIO_DRIVESTRENGTH_0_PIN_2(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_2_MASK) << GPIO_DRIVESTRENGTH_0_PIN_2_OFFS) #define GPIO_DRIVESTRENGTH_0_PIN_3_OFFS 12 #define GPIO_DRIVESTRENGTH_0_PIN_3_MASK 0x7 -#define GPIO_DRIVESTRENGTH_0_PIN_3(V) \ - ((V & GPIO_DRIVESTRENGTH_0_PIN_3_MASK) << GPIO_DRIVESTRENGTH_0_PIN_3_OFFS) +#define GPIO_DRIVESTRENGTH_0_PIN_3(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_3_MASK) << GPIO_DRIVESTRENGTH_0_PIN_3_OFFS) #define GPIO_DRIVESTRENGTH_0_PIN_4_OFFS 16 #define GPIO_DRIVESTRENGTH_0_PIN_4_MASK 0x7 -#define GPIO_DRIVESTRENGTH_0_PIN_4(V) \ - ((V & GPIO_DRIVESTRENGTH_0_PIN_4_MASK) << GPIO_DRIVESTRENGTH_0_PIN_4_OFFS) +#define GPIO_DRIVESTRENGTH_0_PIN_4(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_4_MASK) << GPIO_DRIVESTRENGTH_0_PIN_4_OFFS) #define GPIO_DRIVESTRENGTH_0_PIN_5_OFFS 20 #define GPIO_DRIVESTRENGTH_0_PIN_5_MASK 0x7 -#define GPIO_DRIVESTRENGTH_0_PIN_5(V) \ - ((V & GPIO_DRIVESTRENGTH_0_PIN_5_MASK) << GPIO_DRIVESTRENGTH_0_PIN_5_OFFS) +#define GPIO_DRIVESTRENGTH_0_PIN_5(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_5_MASK) << GPIO_DRIVESTRENGTH_0_PIN_5_OFFS) #define GPIO_DRIVESTRENGTH_0_PIN_6_OFFS 24 #define GPIO_DRIVESTRENGTH_0_PIN_6_MASK 0x7 -#define GPIO_DRIVESTRENGTH_0_PIN_6(V) \ - ((V & GPIO_DRIVESTRENGTH_0_PIN_6_MASK) << GPIO_DRIVESTRENGTH_0_PIN_6_OFFS) +#define GPIO_DRIVESTRENGTH_0_PIN_6(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_6_MASK) << GPIO_DRIVESTRENGTH_0_PIN_6_OFFS) #define GPIO_DRIVESTRENGTH_0_PIN_7_OFFS 28 #define GPIO_DRIVESTRENGTH_0_PIN_7_MASK 0x7 -#define GPIO_DRIVESTRENGTH_0_PIN_7(V) \ - ((V & GPIO_DRIVESTRENGTH_0_PIN_7_MASK) << GPIO_DRIVESTRENGTH_0_PIN_7_OFFS) +#define GPIO_DRIVESTRENGTH_0_PIN_7(V) ((V & GPIO_DRIVESTRENGTH_0_PIN_7_MASK) << GPIO_DRIVESTRENGTH_0_PIN_7_OFFS) #define GPIO_DRIVESTRENGTH_1_PIN_8_OFFS 0 #define GPIO_DRIVESTRENGTH_1_PIN_8_MASK 0x7 -#define GPIO_DRIVESTRENGTH_1_PIN_8(V) \ - ((V & GPIO_DRIVESTRENGTH_1_PIN_8_MASK) << GPIO_DRIVESTRENGTH_1_PIN_8_OFFS) +#define GPIO_DRIVESTRENGTH_1_PIN_8(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_8_MASK) << GPIO_DRIVESTRENGTH_1_PIN_8_OFFS) #define GPIO_DRIVESTRENGTH_1_PIN_9_OFFS 4 #define GPIO_DRIVESTRENGTH_1_PIN_9_MASK 0x7 -#define GPIO_DRIVESTRENGTH_1_PIN_9(V) \ - ((V & GPIO_DRIVESTRENGTH_1_PIN_9_MASK) << GPIO_DRIVESTRENGTH_1_PIN_9_OFFS) +#define GPIO_DRIVESTRENGTH_1_PIN_9(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_9_MASK) << GPIO_DRIVESTRENGTH_1_PIN_9_OFFS) #define GPIO_DRIVESTRENGTH_1_PIN_10_OFFS 8 #define GPIO_DRIVESTRENGTH_1_PIN_10_MASK 0x7 -#define GPIO_DRIVESTRENGTH_1_PIN_10(V) \ - ((V & GPIO_DRIVESTRENGTH_1_PIN_10_MASK) << GPIO_DRIVESTRENGTH_1_PIN_10_OFFS) +#define GPIO_DRIVESTRENGTH_1_PIN_10(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_10_MASK) << GPIO_DRIVESTRENGTH_1_PIN_10_OFFS) #define GPIO_DRIVESTRENGTH_1_PIN_11_OFFS 12 #define GPIO_DRIVESTRENGTH_1_PIN_11_MASK 0x7 -#define GPIO_DRIVESTRENGTH_1_PIN_11(V) \ - ((V & GPIO_DRIVESTRENGTH_1_PIN_11_MASK) << GPIO_DRIVESTRENGTH_1_PIN_11_OFFS) +#define GPIO_DRIVESTRENGTH_1_PIN_11(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_11_MASK) << GPIO_DRIVESTRENGTH_1_PIN_11_OFFS) #define GPIO_DRIVESTRENGTH_1_PIN_12_OFFS 16 #define GPIO_DRIVESTRENGTH_1_PIN_12_MASK 0x7 -#define GPIO_DRIVESTRENGTH_1_PIN_12(V) \ - ((V & GPIO_DRIVESTRENGTH_1_PIN_12_MASK) << GPIO_DRIVESTRENGTH_1_PIN_12_OFFS) +#define GPIO_DRIVESTRENGTH_1_PIN_12(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_12_MASK) << GPIO_DRIVESTRENGTH_1_PIN_12_OFFS) #define GPIO_DRIVESTRENGTH_1_PIN_13_OFFS 20 #define GPIO_DRIVESTRENGTH_1_PIN_13_MASK 0x7 -#define GPIO_DRIVESTRENGTH_1_PIN_13(V) \ - ((V & GPIO_DRIVESTRENGTH_1_PIN_13_MASK) << GPIO_DRIVESTRENGTH_1_PIN_13_OFFS) +#define GPIO_DRIVESTRENGTH_1_PIN_13(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_13_MASK) << GPIO_DRIVESTRENGTH_1_PIN_13_OFFS) #define GPIO_DRIVESTRENGTH_1_PIN_14_OFFS 24 #define GPIO_DRIVESTRENGTH_1_PIN_14_MASK 0x7 -#define GPIO_DRIVESTRENGTH_1_PIN_14(V) \ - ((V & GPIO_DRIVESTRENGTH_1_PIN_14_MASK) << GPIO_DRIVESTRENGTH_1_PIN_14_OFFS) +#define GPIO_DRIVESTRENGTH_1_PIN_14(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_14_MASK) << GPIO_DRIVESTRENGTH_1_PIN_14_OFFS) #define GPIO_DRIVESTRENGTH_1_PIN_15_OFFS 28 #define GPIO_DRIVESTRENGTH_1_PIN_15_MASK 0x7 -#define GPIO_DRIVESTRENGTH_1_PIN_15(V) \ - ((V & GPIO_DRIVESTRENGTH_1_PIN_15_MASK) << GPIO_DRIVESTRENGTH_1_PIN_15_OFFS) +#define GPIO_DRIVESTRENGTH_1_PIN_15(V) ((V & GPIO_DRIVESTRENGTH_1_PIN_15_MASK) << GPIO_DRIVESTRENGTH_1_PIN_15_OFFS) #define GPIO_DRIVESTRENGTH_2_PIN_16_OFFS 0 #define GPIO_DRIVESTRENGTH_2_PIN_16_MASK 0x7 -#define GPIO_DRIVESTRENGTH_2_PIN_16(V) \ - ((V & GPIO_DRIVESTRENGTH_2_PIN_16_MASK) << GPIO_DRIVESTRENGTH_2_PIN_16_OFFS) +#define GPIO_DRIVESTRENGTH_2_PIN_16(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_16_MASK) << GPIO_DRIVESTRENGTH_2_PIN_16_OFFS) #define GPIO_DRIVESTRENGTH_2_PIN_17_OFFS 4 #define GPIO_DRIVESTRENGTH_2_PIN_17_MASK 0x7 -#define GPIO_DRIVESTRENGTH_2_PIN_17(V) \ - ((V & GPIO_DRIVESTRENGTH_2_PIN_17_MASK) << GPIO_DRIVESTRENGTH_2_PIN_17_OFFS) +#define GPIO_DRIVESTRENGTH_2_PIN_17(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_17_MASK) << GPIO_DRIVESTRENGTH_2_PIN_17_OFFS) #define GPIO_DRIVESTRENGTH_2_PIN_18_OFFS 8 #define GPIO_DRIVESTRENGTH_2_PIN_18_MASK 0x7 -#define GPIO_DRIVESTRENGTH_2_PIN_18(V) \ - ((V & GPIO_DRIVESTRENGTH_2_PIN_18_MASK) << GPIO_DRIVESTRENGTH_2_PIN_18_OFFS) +#define GPIO_DRIVESTRENGTH_2_PIN_18(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_18_MASK) << GPIO_DRIVESTRENGTH_2_PIN_18_OFFS) #define GPIO_DRIVESTRENGTH_2_PIN_19_OFFS 12 #define GPIO_DRIVESTRENGTH_2_PIN_19_MASK 0x7 -#define GPIO_DRIVESTRENGTH_2_PIN_19(V) \ - ((V & GPIO_DRIVESTRENGTH_2_PIN_19_MASK) << GPIO_DRIVESTRENGTH_2_PIN_19_OFFS) +#define GPIO_DRIVESTRENGTH_2_PIN_19(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_19_MASK) << GPIO_DRIVESTRENGTH_2_PIN_19_OFFS) #define GPIO_DRIVESTRENGTH_2_PIN_20_OFFS 16 #define GPIO_DRIVESTRENGTH_2_PIN_20_MASK 0x7 -#define GPIO_DRIVESTRENGTH_2_PIN_20(V) \ - ((V & GPIO_DRIVESTRENGTH_2_PIN_20_MASK) << GPIO_DRIVESTRENGTH_2_PIN_20_OFFS) +#define GPIO_DRIVESTRENGTH_2_PIN_20(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_20_MASK) << GPIO_DRIVESTRENGTH_2_PIN_20_OFFS) #define GPIO_DRIVESTRENGTH_2_PIN_21_OFFS 20 #define GPIO_DRIVESTRENGTH_2_PIN_21_MASK 0x7 -#define GPIO_DRIVESTRENGTH_2_PIN_21(V) \ - ((V & GPIO_DRIVESTRENGTH_2_PIN_21_MASK) << GPIO_DRIVESTRENGTH_2_PIN_21_OFFS) +#define GPIO_DRIVESTRENGTH_2_PIN_21(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_21_MASK) << GPIO_DRIVESTRENGTH_2_PIN_21_OFFS) #define GPIO_DRIVESTRENGTH_2_PIN_22_OFFS 24 #define GPIO_DRIVESTRENGTH_2_PIN_22_MASK 0x7 -#define GPIO_DRIVESTRENGTH_2_PIN_22(V) \ - ((V & GPIO_DRIVESTRENGTH_2_PIN_22_MASK) << GPIO_DRIVESTRENGTH_2_PIN_22_OFFS) +#define GPIO_DRIVESTRENGTH_2_PIN_22(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_22_MASK) << GPIO_DRIVESTRENGTH_2_PIN_22_OFFS) #define GPIO_DRIVESTRENGTH_2_PIN_23_OFFS 28 #define GPIO_DRIVESTRENGTH_2_PIN_23_MASK 0x7 -#define GPIO_DRIVESTRENGTH_2_PIN_23(V) \ - ((V & GPIO_DRIVESTRENGTH_2_PIN_23_MASK) << GPIO_DRIVESTRENGTH_2_PIN_23_OFFS) +#define GPIO_DRIVESTRENGTH_2_PIN_23(V) ((V & GPIO_DRIVESTRENGTH_2_PIN_23_MASK) << GPIO_DRIVESTRENGTH_2_PIN_23_OFFS) #define GPIO_DRIVESTRENGTH_3_PIN_24_OFFS 0 #define GPIO_DRIVESTRENGTH_3_PIN_24_MASK 0x7 -#define GPIO_DRIVESTRENGTH_3_PIN_24(V) \ - ((V & GPIO_DRIVESTRENGTH_3_PIN_24_MASK) << GPIO_DRIVESTRENGTH_3_PIN_24_OFFS) +#define GPIO_DRIVESTRENGTH_3_PIN_24(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_24_MASK) << GPIO_DRIVESTRENGTH_3_PIN_24_OFFS) #define GPIO_DRIVESTRENGTH_3_PIN_25_OFFS 4 #define GPIO_DRIVESTRENGTH_3_PIN_25_MASK 0x7 -#define GPIO_DRIVESTRENGTH_3_PIN_25(V) \ - ((V & GPIO_DRIVESTRENGTH_3_PIN_25_MASK) << GPIO_DRIVESTRENGTH_3_PIN_25_OFFS) +#define GPIO_DRIVESTRENGTH_3_PIN_25(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_25_MASK) << GPIO_DRIVESTRENGTH_3_PIN_25_OFFS) #define GPIO_DRIVESTRENGTH_3_PIN_26_OFFS 8 #define GPIO_DRIVESTRENGTH_3_PIN_26_MASK 0x7 -#define GPIO_DRIVESTRENGTH_3_PIN_26(V) \ - ((V & GPIO_DRIVESTRENGTH_3_PIN_26_MASK) << GPIO_DRIVESTRENGTH_3_PIN_26_OFFS) +#define GPIO_DRIVESTRENGTH_3_PIN_26(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_26_MASK) << GPIO_DRIVESTRENGTH_3_PIN_26_OFFS) #define GPIO_DRIVESTRENGTH_3_PIN_27_OFFS 12 #define GPIO_DRIVESTRENGTH_3_PIN_27_MASK 0x7 -#define GPIO_DRIVESTRENGTH_3_PIN_27(V) \ - ((V & GPIO_DRIVESTRENGTH_3_PIN_27_MASK) << GPIO_DRIVESTRENGTH_3_PIN_27_OFFS) +#define GPIO_DRIVESTRENGTH_3_PIN_27(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_27_MASK) << GPIO_DRIVESTRENGTH_3_PIN_27_OFFS) #define GPIO_DRIVESTRENGTH_3_PIN_28_OFFS 16 #define GPIO_DRIVESTRENGTH_3_PIN_28_MASK 0x7 -#define GPIO_DRIVESTRENGTH_3_PIN_28(V) \ - ((V & GPIO_DRIVESTRENGTH_3_PIN_28_MASK) << GPIO_DRIVESTRENGTH_3_PIN_28_OFFS) +#define GPIO_DRIVESTRENGTH_3_PIN_28(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_28_MASK) << GPIO_DRIVESTRENGTH_3_PIN_28_OFFS) #define GPIO_DRIVESTRENGTH_3_PIN_29_OFFS 20 #define GPIO_DRIVESTRENGTH_3_PIN_29_MASK 0x7 -#define GPIO_DRIVESTRENGTH_3_PIN_29(V) \ - ((V & GPIO_DRIVESTRENGTH_3_PIN_29_MASK) << GPIO_DRIVESTRENGTH_3_PIN_29_OFFS) +#define GPIO_DRIVESTRENGTH_3_PIN_29(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_29_MASK) << GPIO_DRIVESTRENGTH_3_PIN_29_OFFS) #define GPIO_DRIVESTRENGTH_3_PIN_30_OFFS 24 #define GPIO_DRIVESTRENGTH_3_PIN_30_MASK 0x7 -#define GPIO_DRIVESTRENGTH_3_PIN_30(V) \ - ((V & GPIO_DRIVESTRENGTH_3_PIN_30_MASK) << GPIO_DRIVESTRENGTH_3_PIN_30_OFFS) +#define GPIO_DRIVESTRENGTH_3_PIN_30(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_30_MASK) << GPIO_DRIVESTRENGTH_3_PIN_30_OFFS) #define GPIO_DRIVESTRENGTH_3_PIN_31_OFFS 28 #define GPIO_DRIVESTRENGTH_3_PIN_31_MASK 0x7 -#define GPIO_DRIVESTRENGTH_3_PIN_31(V) \ - ((V & GPIO_DRIVESTRENGTH_3_PIN_31_MASK) << GPIO_DRIVESTRENGTH_3_PIN_31_OFFS) +#define GPIO_DRIVESTRENGTH_3_PIN_31(V) ((V & GPIO_DRIVESTRENGTH_3_PIN_31_MASK) << GPIO_DRIVESTRENGTH_3_PIN_31_OFFS) #define GPIO_IE_OFFS 0 #define GPIO_IE_MASK 0xffffffff @@ -220,8 +187,7 @@ typedef struct { #define GPIO_IRQ_TRIGGER_OFFS 0 #define GPIO_IRQ_TRIGGER_MASK 0xffffffff -#define GPIO_IRQ_TRIGGER(V) \ - ((V & GPIO_IRQ_TRIGGER_MASK) << GPIO_IRQ_TRIGGER_OFFS) +#define GPIO_IRQ_TRIGGER(V) ((V & GPIO_IRQ_TRIGGER_MASK) << GPIO_IRQ_TRIGGER_OFFS) #define GPIO_IRQ_TYPE_OFFS 0 #define GPIO_IRQ_TYPE_MASK 0xffffffff @@ -232,340 +198,196 @@ typedef struct { #define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS) // GPIO_VALUE -static inline uint32_t get_gpio_value(volatile gpio_t *reg) { - return (reg->VALUE >> 0) & 0xffffffff; -} +static inline uint32_t get_gpio_value(volatile gpio_t* reg) { return (reg->VALUE >> 0) & 0xffffffff; } // GPIO_WRITE -static inline uint32_t get_gpio_write(volatile gpio_t *reg) { - return (reg->WRITE >> 0) & 0xffffffff; -} -static inline void set_gpio_write(volatile gpio_t *reg, uint32_t value) { - reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0); -} +static inline uint32_t get_gpio_write(volatile gpio_t* reg) { return (reg->WRITE >> 0) & 0xffffffff; } +static inline void set_gpio_write(volatile gpio_t* reg, uint32_t value) { reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0); } // GPIO_WRITEENABLE -static inline uint32_t get_gpio_writeEnable(volatile gpio_t *reg) { - return (reg->WRITEENABLE >> 0) & 0xffffffff; -} -static inline void set_gpio_writeEnable(volatile gpio_t *reg, uint32_t value) { +static inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg) { return (reg->WRITEENABLE >> 0) & 0xffffffff; } +static inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value) { reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0); } // GPIO_PULLUP -static inline uint32_t get_gpio_pullup(volatile gpio_t *reg) { - return (reg->PULLUP >> 0) & 0xffffffff; -} -static inline void set_gpio_pullup(volatile gpio_t *reg, uint32_t value) { +static inline uint32_t get_gpio_pullup(volatile gpio_t* reg) { return (reg->PULLUP >> 0) & 0xffffffff; } +static inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value) { reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0); } // GPIO_PULDOWN -static inline uint32_t get_gpio_puldown(volatile gpio_t *reg) { - return (reg->PULDOWN >> 0) & 0xffffffff; -} -static inline void set_gpio_puldown(volatile gpio_t *reg, uint32_t value) { +static inline uint32_t get_gpio_puldown(volatile gpio_t* reg) { return (reg->PULDOWN >> 0) & 0xffffffff; } +static inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value) { reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0); } // GPIO_DRIVESTRENGTH_0 -static inline uint32_t get_gpio_driveStrength_0(volatile gpio_t *reg) { - return reg->DRIVESTRENGTH_0; -} -static inline void set_gpio_driveStrength_0(volatile gpio_t *reg, - uint32_t value) { - reg->DRIVESTRENGTH_0 = value; -} -static inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_0 >> 0) & 0x7; -} -static inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_0; } +static inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_0 = value; } +static inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 0) & 0x7; } +static inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0); } -static inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_0 >> 4) & 0x7; -} -static inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 4) & 0x7; } +static inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4); } -static inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_0 >> 8) & 0x7; -} -static inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 8) & 0x7; } +static inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8); } -static inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_0 >> 12) & 0x7; -} -static inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 12) & 0x7; } +static inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12); } -static inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_0 >> 16) & 0x7; -} -static inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 16) & 0x7; } +static inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16); } -static inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_0 >> 20) & 0x7; -} -static inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 20) & 0x7; } +static inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20); } -static inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_0 >> 24) & 0x7; -} -static inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 24) & 0x7; } +static inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24); } -static inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_0 >> 28) & 0x7; -} -static inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 28) & 0x7; } +static inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28); } // GPIO_DRIVESTRENGTH_1 -static inline uint32_t get_gpio_driveStrength_1(volatile gpio_t *reg) { - return reg->DRIVESTRENGTH_1; -} -static inline void set_gpio_driveStrength_1(volatile gpio_t *reg, - uint32_t value) { - reg->DRIVESTRENGTH_1 = value; -} -static inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_1 >> 0) & 0x7; -} -static inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_1; } +static inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_1 = value; } +static inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 0) & 0x7; } +static inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0); } -static inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_1 >> 4) & 0x7; -} -static inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 4) & 0x7; } +static inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4); } -static inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_1 >> 8) & 0x7; -} -static inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 8) & 0x7; } +static inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8); } -static inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_1 >> 12) & 0x7; -} -static inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 12) & 0x7; } +static inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12); } -static inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_1 >> 16) & 0x7; -} -static inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 16) & 0x7; } +static inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16); } -static inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_1 >> 20) & 0x7; -} -static inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 20) & 0x7; } +static inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20); } -static inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_1 >> 24) & 0x7; -} -static inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 24) & 0x7; } +static inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24); } -static inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_1 >> 28) & 0x7; -} -static inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 28) & 0x7; } +static inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28); } // GPIO_DRIVESTRENGTH_2 -static inline uint32_t get_gpio_driveStrength_2(volatile gpio_t *reg) { - return reg->DRIVESTRENGTH_2; -} -static inline void set_gpio_driveStrength_2(volatile gpio_t *reg, - uint32_t value) { - reg->DRIVESTRENGTH_2 = value; -} -static inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_2 >> 0) & 0x7; -} -static inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_2; } +static inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_2 = value; } +static inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 0) & 0x7; } +static inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0); } -static inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_2 >> 4) & 0x7; -} -static inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 4) & 0x7; } +static inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4); } -static inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_2 >> 8) & 0x7; -} -static inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 8) & 0x7; } +static inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8); } -static inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_2 >> 12) & 0x7; -} -static inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 12) & 0x7; } +static inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12); } -static inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_2 >> 16) & 0x7; -} -static inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 16) & 0x7; } +static inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16); } -static inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_2 >> 20) & 0x7; -} -static inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 20) & 0x7; } +static inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20); } -static inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_2 >> 24) & 0x7; -} -static inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 24) & 0x7; } +static inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24); } -static inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_2 >> 28) & 0x7; -} -static inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 28) & 0x7; } +static inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28); } // GPIO_DRIVESTRENGTH_3 -static inline uint32_t get_gpio_driveStrength_3(volatile gpio_t *reg) { - return reg->DRIVESTRENGTH_3; -} -static inline void set_gpio_driveStrength_3(volatile gpio_t *reg, - uint32_t value) { - reg->DRIVESTRENGTH_3 = value; -} -static inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_3 >> 0) & 0x7; -} -static inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_3; } +static inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_3 = value; } +static inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 0) & 0x7; } +static inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0); } -static inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_3 >> 4) & 0x7; -} -static inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 4) & 0x7; } +static inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4); } -static inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_3 >> 8) & 0x7; -} -static inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 8) & 0x7; } +static inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8); } -static inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_3 >> 12) & 0x7; -} -static inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 12) & 0x7; } +static inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12); } -static inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_3 >> 16) & 0x7; -} -static inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 16) & 0x7; } +static inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16); } -static inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_3 >> 20) & 0x7; -} -static inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 20) & 0x7; } +static inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20); } -static inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_3 >> 24) & 0x7; -} -static inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 24) & 0x7; } +static inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24); } -static inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t *reg) { - return (reg->DRIVESTRENGTH_3 >> 28) & 0x7; -} -static inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t *reg, - uint8_t value) { +static inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 28) & 0x7; } +static inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28); } // GPIO_IE -static inline uint32_t get_gpio_ie(volatile gpio_t *reg) { - return (reg->IE >> 0) & 0xffffffff; -} -static inline void set_gpio_ie(volatile gpio_t *reg, uint32_t value) { - reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0); -} +static inline uint32_t get_gpio_ie(volatile gpio_t* reg) { return (reg->IE >> 0) & 0xffffffff; } +static inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value) { reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0); } // GPIO_IP -static inline uint32_t get_gpio_ip(volatile gpio_t *reg) { - return (reg->IP >> 0) & 0xffffffff; -} -static inline void set_gpio_ip(volatile gpio_t *reg, uint32_t value) { - reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0); -} +static inline uint32_t get_gpio_ip(volatile gpio_t* reg) { return (reg->IP >> 0) & 0xffffffff; } +static inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value) { reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0); } // GPIO_IRQ_TRIGGER -static inline uint32_t get_gpio_irq_trigger(volatile gpio_t *reg) { - return (reg->IRQ_TRIGGER >> 0) & 0xffffffff; -} -static inline void set_gpio_irq_trigger(volatile gpio_t *reg, uint32_t value) { +static inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg) { return (reg->IRQ_TRIGGER >> 0) & 0xffffffff; } +static inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value) { reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0); } // GPIO_IRQ_TYPE -static inline uint32_t get_gpio_irq_type(volatile gpio_t *reg) { - return (reg->IRQ_TYPE >> 0) & 0xffffffff; -} -static inline void set_gpio_irq_type(volatile gpio_t *reg, uint32_t value) { +static inline uint32_t get_gpio_irq_type(volatile gpio_t* reg) { return (reg->IRQ_TYPE >> 0) & 0xffffffff; } +static inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value) { reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0); } // GPIO_BOOT_SEL -static inline uint32_t get_gpio_boot_sel(volatile gpio_t *reg) { - return reg->BOOT_SEL; -} -static inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t *reg) { - return (reg->BOOT_SEL >> 0) & 0x7; -} +static inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg) { return reg->BOOT_SEL; } +static inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg) { return (reg->BOOT_SEL >> 0) & 0x7; } #endif /* _BSP_GPIO_H */ \ No newline at end of file diff --git a/include/minres/devices/gen/i2s.h b/include/minres/devices/gen/i2s.h index 8863c80..9d16cb0 100644 --- a/include/minres/devices/gen/i2s.h +++ b/include/minres/devices/gen/i2s.h @@ -34,266 +34,167 @@ typedef struct { #define I2S_CONTROL_MODE_OFFS 0 #define I2S_CONTROL_MODE_MASK 0x3 -#define I2S_CONTROL_MODE(V) \ - ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS) +#define I2S_CONTROL_MODE(V) ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS) #define I2S_CONTROL_DISABLE_LEFT_OFFS 2 #define I2S_CONTROL_DISABLE_LEFT_MASK 0x1 -#define I2S_CONTROL_DISABLE_LEFT(V) \ - ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS) +#define I2S_CONTROL_DISABLE_LEFT(V) ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS) #define I2S_CONTROL_DISABLE_RIGHT_OFFS 3 #define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1 -#define I2S_CONTROL_DISABLE_RIGHT(V) \ - ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS) +#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS) #define I2S_CONTROL_IS_MASTER_OFFS 4 #define I2S_CONTROL_IS_MASTER_MASK 0x1 -#define I2S_CONTROL_IS_MASTER(V) \ - ((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS) +#define I2S_CONTROL_IS_MASTER(V) ((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS) #define I2S_CONTROL_SAMPLE_SIZE_OFFS 5 #define I2S_CONTROL_SAMPLE_SIZE_MASK 0x3 -#define I2S_CONTROL_SAMPLE_SIZE(V) \ - ((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS) +#define I2S_CONTROL_SAMPLE_SIZE(V) ((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS) #define I2S_CONTROL_PDM_SCALE_OFFS 7 #define I2S_CONTROL_PDM_SCALE_MASK 0x7 -#define I2S_CONTROL_PDM_SCALE(V) \ - ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS) +#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS) #define I2S_STATUS_ENABLED_OFFS 0 #define I2S_STATUS_ENABLED_MASK 0x1 -#define I2S_STATUS_ENABLED(V) \ - ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS) +#define I2S_STATUS_ENABLED(V) ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS) #define I2S_STATUS_ACTIVE_OFFS 1 #define I2S_STATUS_ACTIVE_MASK 0x1 -#define I2S_STATUS_ACTIVE(V) \ - ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS) +#define I2S_STATUS_ACTIVE(V) ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS) #define I2S_STATUS_LEFT_AVAIL_OFFS 2 #define I2S_STATUS_LEFT_AVAIL_MASK 0x1 -#define I2S_STATUS_LEFT_AVAIL(V) \ - ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS) +#define I2S_STATUS_LEFT_AVAIL(V) ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS) #define I2S_STATUS_RIGHT_AVAIL_OFFS 3 #define I2S_STATUS_RIGHT_AVAIL_MASK 0x1 -#define I2S_STATUS_RIGHT_AVAIL(V) \ - ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS) +#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS) #define I2S_STATUS_LEFT_OVERFLOW_OFFS 4 #define I2S_STATUS_LEFT_OVERFLOW_MASK 0x1 -#define I2S_STATUS_LEFT_OVERFLOW(V) \ - ((V & I2S_STATUS_LEFT_OVERFLOW_MASK) << I2S_STATUS_LEFT_OVERFLOW_OFFS) +#define I2S_STATUS_LEFT_OVERFLOW(V) ((V & I2S_STATUS_LEFT_OVERFLOW_MASK) << I2S_STATUS_LEFT_OVERFLOW_OFFS) #define I2S_STATUS_RIGHT_OVERFLOW_OFFS 5 #define I2S_STATUS_RIGHT_OVERFLOW_MASK 0x1 -#define I2S_STATUS_RIGHT_OVERFLOW(V) \ - ((V & I2S_STATUS_RIGHT_OVERFLOW_MASK) << I2S_STATUS_RIGHT_OVERFLOW_OFFS) +#define I2S_STATUS_RIGHT_OVERFLOW(V) ((V & I2S_STATUS_RIGHT_OVERFLOW_MASK) << I2S_STATUS_RIGHT_OVERFLOW_OFFS) #define I2S_I2S_CLOCK_CTRL_OFFS 0 #define I2S_I2S_CLOCK_CTRL_MASK 0xfffff -#define I2S_I2S_CLOCK_CTRL(V) \ - ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS) +#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS) #define I2S_PDM_CLOCK_CTRL_OFFS 0 #define I2S_PDM_CLOCK_CTRL_MASK 0xff -#define I2S_PDM_CLOCK_CTRL(V) \ - ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS) +#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS) #define I2S_PDM_FILTER_CTRL_OFFS 0 #define I2S_PDM_FILTER_CTRL_MASK 0x3ff -#define I2S_PDM_FILTER_CTRL(V) \ - ((V & I2S_PDM_FILTER_CTRL_MASK) << I2S_PDM_FILTER_CTRL_OFFS) +#define I2S_PDM_FILTER_CTRL(V) ((V & I2S_PDM_FILTER_CTRL_MASK) << I2S_PDM_FILTER_CTRL_OFFS) #define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0 #define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1 -#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) \ - ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS) +#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS) #define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1 #define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1 -#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) \ - ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS) +#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS) #define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0 #define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1 -#define I2S_IP_LEFT_SAMPLE_AVAIL(V) \ - ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS) +#define I2S_IP_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS) #define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1 #define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1 -#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) \ - ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS) +#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS) // I2S_LEFT_CH -static inline uint32_t get_i2s_left_ch(volatile i2s_t *reg) { - return (reg->LEFT_CH >> 0) & 0xffffffff; -} +static inline uint32_t get_i2s_left_ch(volatile i2s_t* reg) { return (reg->LEFT_CH >> 0) & 0xffffffff; } // I2S_RIGHT_CH -static inline uint32_t get_i2s_right_ch(volatile i2s_t *reg) { - return (reg->RIGHT_CH >> 0) & 0xffffffff; -} +static inline uint32_t get_i2s_right_ch(volatile i2s_t* reg) { return (reg->RIGHT_CH >> 0) & 0xffffffff; } // I2S_CONTROL -static inline uint32_t get_i2s_control(volatile i2s_t *reg) { - return reg->CONTROL; -} -static inline void set_i2s_control(volatile i2s_t *reg, uint32_t value) { - reg->CONTROL = value; -} -static inline uint32_t get_i2s_control_mode(volatile i2s_t *reg) { - return (reg->CONTROL >> 0) & 0x3; -} -static inline void set_i2s_control_mode(volatile i2s_t *reg, uint8_t value) { - reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0); -} -static inline uint32_t get_i2s_control_disable_left(volatile i2s_t *reg) { - return (reg->CONTROL >> 2) & 0x1; -} -static inline void set_i2s_control_disable_left(volatile i2s_t *reg, - uint8_t value) { +static inline uint32_t get_i2s_control(volatile i2s_t* reg) { return reg->CONTROL; } +static inline void set_i2s_control(volatile i2s_t* reg, uint32_t value) { reg->CONTROL = value; } +static inline uint32_t get_i2s_control_mode(volatile i2s_t* reg) { return (reg->CONTROL >> 0) & 0x3; } +static inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0); } +static inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg) { return (reg->CONTROL >> 2) & 0x1; } +static inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2); } -static inline uint32_t get_i2s_control_disable_right(volatile i2s_t *reg) { - return (reg->CONTROL >> 3) & 0x1; -} -static inline void set_i2s_control_disable_right(volatile i2s_t *reg, - uint8_t value) { +static inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg) { return (reg->CONTROL >> 3) & 0x1; } +static inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3); } -static inline uint32_t get_i2s_control_is_master(volatile i2s_t *reg) { - return (reg->CONTROL >> 4) & 0x1; -} -static inline void set_i2s_control_is_master(volatile i2s_t *reg, - uint8_t value) { +static inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg) { return (reg->CONTROL >> 4) & 0x1; } +static inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4); } -static inline uint32_t get_i2s_control_sample_size(volatile i2s_t *reg) { - return (reg->CONTROL >> 5) & 0x3; -} -static inline void set_i2s_control_sample_size(volatile i2s_t *reg, - uint8_t value) { +static inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg) { return (reg->CONTROL >> 5) & 0x3; } +static inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5); } -static inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t *reg) { - return (reg->CONTROL >> 7) & 0x7; -} -static inline void set_i2s_control_pdm_scale(volatile i2s_t *reg, - uint8_t value) { +static inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg) { return (reg->CONTROL >> 7) & 0x7; } +static inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7); } // I2S_STATUS -static inline uint32_t get_i2s_status(volatile i2s_t *reg) { - return reg->STATUS; -} -static inline void set_i2s_status(volatile i2s_t *reg, uint32_t value) { - reg->STATUS = value; -} -static inline uint32_t get_i2s_status_enabled(volatile i2s_t *reg) { - return (reg->STATUS >> 0) & 0x1; -} -static inline uint32_t get_i2s_status_active(volatile i2s_t *reg) { - return (reg->STATUS >> 1) & 0x1; -} -static inline uint32_t get_i2s_status_left_avail(volatile i2s_t *reg) { - return (reg->STATUS >> 2) & 0x1; -} -static inline uint32_t get_i2s_status_right_avail(volatile i2s_t *reg) { - return (reg->STATUS >> 3) & 0x1; -} -static inline uint32_t get_i2s_status_left_overflow(volatile i2s_t *reg) { - return (reg->STATUS >> 4) & 0x1; -} -static inline void set_i2s_status_left_overflow(volatile i2s_t *reg, - uint8_t value) { +static inline uint32_t get_i2s_status(volatile i2s_t* reg) { return reg->STATUS; } +static inline void set_i2s_status(volatile i2s_t* reg, uint32_t value) { reg->STATUS = value; } +static inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg) { return (reg->STATUS >> 0) & 0x1; } +static inline uint32_t get_i2s_status_active(volatile i2s_t* reg) { return (reg->STATUS >> 1) & 0x1; } +static inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg) { return (reg->STATUS >> 2) & 0x1; } +static inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg) { return (reg->STATUS >> 3) & 0x1; } +static inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 4) & 0x1; } +static inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value) { reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4); } -static inline uint32_t get_i2s_status_right_overflow(volatile i2s_t *reg) { - return (reg->STATUS >> 5) & 0x1; -} -static inline void set_i2s_status_right_overflow(volatile i2s_t *reg, - uint8_t value) { +static inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 5) & 0x1; } +static inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value) { reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5); } // I2S_I2S_CLOCK_CTRL -static inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t *reg) { - return reg->I2S_CLOCK_CTRL; -} -static inline void set_i2s_i2s_clock_ctrl(volatile i2s_t *reg, uint32_t value) { - reg->I2S_CLOCK_CTRL = value; -} -static inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t *reg) { - return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff; -} -static inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t *reg, - uint32_t value) { +static inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg) { return reg->I2S_CLOCK_CTRL; } +static inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->I2S_CLOCK_CTRL = value; } +static inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff; } +static inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value) { reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0); } // I2S_PDM_CLOCK_CTRL -static inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t *reg) { - return reg->PDM_CLOCK_CTRL; -} -static inline void set_i2s_pdm_clock_ctrl(volatile i2s_t *reg, uint32_t value) { - reg->PDM_CLOCK_CTRL = value; -} -static inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t *reg) { - return (reg->PDM_CLOCK_CTRL >> 0) & 0xff; -} -static inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t *reg, - uint8_t value) { +static inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg) { return reg->PDM_CLOCK_CTRL; } +static inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_CLOCK_CTRL = value; } +static inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->PDM_CLOCK_CTRL >> 0) & 0xff; } +static inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value) { reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0); } // I2S_PDM_FILTER_CTRL -static inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t *reg) { - return reg->PDM_FILTER_CTRL; -} -static inline void set_i2s_pdm_filter_ctrl(volatile i2s_t *reg, - uint32_t value) { - reg->PDM_FILTER_CTRL = value; -} -static inline uint32_t -get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t *reg) { - return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff; -} -static inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t *reg, - uint16_t value) { +static inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg) { return reg->PDM_FILTER_CTRL; } +static inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_FILTER_CTRL = value; } +static inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg) { return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff; } +static inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value) { reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0); } // I2S_IE -static inline uint32_t get_i2s_ie(volatile i2s_t *reg) { return reg->IE; } -static inline void set_i2s_ie(volatile i2s_t *reg, uint32_t value) { - reg->IE = value; -} -static inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t *reg) { - return (reg->IE >> 0) & 0x1; -} -static inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t *reg, - uint8_t value) { +static inline uint32_t get_i2s_ie(volatile i2s_t* reg) { return reg->IE; } +static inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value) { reg->IE = value; } +static inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 0) & 0x1; } +static inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value) { reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); } -static inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t *reg) { - return (reg->IE >> 1) & 0x1; -} -static inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t *reg, - uint8_t value) { +static inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 1) & 0x1; } +static inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value) { reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); } // I2S_IP -static inline uint32_t get_i2s_ip(volatile i2s_t *reg) { return reg->IP; } -static inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t *reg) { - return (reg->IP >> 0) & 0x1; -} -static inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t *reg) { - return (reg->IP >> 1) & 0x1; -} +static inline uint32_t get_i2s_ip(volatile i2s_t* reg) { return reg->IP; } +static inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 0) & 0x1; } +static inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 1) & 0x1; } #endif /* _BSP_I2S_H */ \ No newline at end of file diff --git a/include/minres/devices/gen/mkcontrolclusterstreamcontroller.h b/include/minres/devices/gen/mkcontrolclusterstreamcontroller.h index a7b89af..468021b 100644 --- a/include/minres/devices/gen/mkcontrolclusterstreamcontroller.h +++ b/include/minres/devices/gen/mkcontrolclusterstreamcontroller.h @@ -1,11 +1,11 @@ /* -* Copyright (c) 2023 - 2025 MINRES Technologies GmbH -* -* SPDX-License-Identifier: Apache-2.0 -* -* Generated at 2025-05-05 14:06:05 UTC -* by peakrdl_mnrs version 1.2.9 -*/ + * Copyright (c) 2023 - 2025 MINRES Technologies GmbH + * + * SPDX-License-Identifier: Apache-2.0 + * + * Generated at 2025-02-18 11:11:47 UTC + * by peakrdl_mnrs version 1.2.9 + */ #ifndef _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H #define _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H @@ -13,28 +13,20 @@ #include typedef struct { - volatile uint32_t REG_SEND; - volatile uint32_t REG_HEADER; - volatile uint32_t REG_ACK; - volatile uint32_t REG_RECV_ID; - volatile uint32_t REG_RECV_PAYLOAD; - uint8_t fill0[12]; - volatile uint32_t REG_PAYLOAD_0; - volatile uint32_t REG_PAYLOAD_1; - volatile uint32_t REG_PAYLOAD_2; - volatile uint32_t REG_PAYLOAD_3; - volatile uint32_t REG_PAYLOAD_4; - volatile uint32_t REG_PAYLOAD_5; - volatile uint32_t REG_PAYLOAD_6; - volatile uint32_t REG_PAYLOAD_7; - volatile uint32_t REG_PAYLOAD_8; - volatile uint32_t REG_PAYLOAD_9; - volatile uint32_t REG_PAYLOAD_10; - volatile uint32_t REG_PAYLOAD_11; - volatile uint32_t REG_PAYLOAD_12; - volatile uint32_t REG_PAYLOAD_13; - volatile uint32_t REG_PAYLOAD_14; - volatile uint32_t REG_PAYLOAD_15; + volatile uint32_t REG_SEND; + volatile uint32_t REG_HEADER; + volatile uint32_t REG_ACK; + volatile uint32_t REG_RECV_ID; + volatile uint32_t REG_RECV_PAYLOAD; + uint8_t fill0[12]; + volatile uint32_t REG_PAYLOAD_0; + volatile uint32_t REG_PAYLOAD_1; + volatile uint32_t REG_PAYLOAD_2; + volatile uint32_t REG_PAYLOAD_3; + volatile uint32_t REG_PAYLOAD_4; + volatile uint32_t REG_PAYLOAD_5; + volatile uint32_t REG_PAYLOAD_6; + volatile uint32_t REG_PAYLOAD_7; } mkcontrolclusterstreamcontroller_t; #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0 @@ -54,237 +46,186 @@ typedef struct { #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) \ + << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) \ + << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK 0x1 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS 1 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK 0x1 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK 0xf -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS) +#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) \ + ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS) -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS 0 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8_OFFS) - -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS 0 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9_OFFS) - -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS 0 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10_OFFS) - -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS 0 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11_OFFS) - -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS 0 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12_OFFS) - -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS 0 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13_OFFS) - -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS 0 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS) - -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS 0 -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK 0xffffffff -#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS) - -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND static inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_SEND = value; + reg->REG_SEND = value; } static inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { - reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0); + reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0); } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg) { - return reg->REG_HEADER; + return reg->REG_HEADER; } static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_HEADER = value; + reg->REG_HEADER = value; } static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg) { - return (reg->REG_HEADER >> 0) & 0xf; + return (reg->REG_HEADER >> 0) & 0xf; } -static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { - reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0); +static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, + uint8_t value) { + reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0); } static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg) { - return (reg->REG_HEADER >> 4) & 0xf; + return (reg->REG_HEADER >> 4) & 0xf; } -static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { - reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4); +static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, + uint8_t value) { + reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4); } -static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg) { - return (reg->REG_HEADER >> 8) & 0x7; +static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT( + volatile mkcontrolclusterstreamcontroller_t* reg) { + return (reg->REG_HEADER >> 8) & 0x7; } -static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { - reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8); +static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, + uint8_t value) { + reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8); } static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg) { - return (reg->REG_HEADER >> 11) & 0x3; + return (reg->REG_HEADER >> 11) & 0x3; } -static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { - reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11); +static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, + uint8_t value) { + reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11); } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg) { - return reg->REG_ACK; + return reg->REG_ACK; } static inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_ACK = value; + reg->REG_ACK = value; } static inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { - reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0); + reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0); } static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg) { - return (reg->REG_ACK >> 1) & 0x1; + return (reg->REG_ACK >> 1) & 0x1; } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) { - return reg->REG_RECV_ID; + return reg->REG_RECV_ID; } static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) { - return (reg->REG_RECV_ID >> 0) & 0xf; + return (reg->REG_RECV_ID >> 0) & 0xf; } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg) { - return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; + return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0 +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0 static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0); + reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0); } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1 +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1 static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0); + reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0); } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2 +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2 static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0); + reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0); } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3 +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3 static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0); + reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0); } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4 +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4 static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0); + reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0); } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5 +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5 static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0); + reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0); } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6 +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6 static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0); + reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0); } -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7 +// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7 static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0); -} - -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8 -static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_8 = (reg->REG_PAYLOAD_8 & ~(0xffffffffU << 0)) | (value << 0); -} - -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9 -static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_9 = (reg->REG_PAYLOAD_9 & ~(0xffffffffU << 0)) | (value << 0); -} - -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10 -static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_10 = (reg->REG_PAYLOAD_10 & ~(0xffffffffU << 0)) | (value << 0); -} - -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11 -static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_11 = (reg->REG_PAYLOAD_11 & ~(0xffffffffU << 0)) | (value << 0); -} - -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12 -static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_12 = (reg->REG_PAYLOAD_12 & ~(0xffffffffU << 0)) | (value << 0); -} - -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13 -static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_13 = (reg->REG_PAYLOAD_13 & ~(0xffffffffU << 0)) | (value << 0); -} - -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14 -static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_14 = (reg->REG_PAYLOAD_14 & ~(0xffffffffU << 0)) | (value << 0); -} - -//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15 -static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_15(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { - reg->REG_PAYLOAD_15 = (reg->REG_PAYLOAD_15 & ~(0xffffffffU << 0)) | (value << 0); + reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0); } #endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */ \ No newline at end of file diff --git a/include/minres/devices/gen/msgif.h b/include/minres/devices/gen/msgif.h index 0b071a4..8647fc7 100644 --- a/include/minres/devices/gen/msgif.h +++ b/include/minres/devices/gen/msgif.h @@ -35,26 +35,20 @@ typedef struct { #define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 0 #define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf -#define MSGIF_REG_HEADER_MESSAGE_ID(V) \ - ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS) +#define MSGIF_REG_HEADER_MESSAGE_ID(V) ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS) #define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 4 #define MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK 0xf -#define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) \ - ((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) \ - << MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS) +#define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) ((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) << MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS) #define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8 #define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7 -#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) \ - ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) \ - << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS) +#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) \ + ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS) #define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11 #define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3 -#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) \ - ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) \ - << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS) +#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS) #define MSGIF_REG_ACK_OFFS 0 #define MSGIF_REG_ACK_MASK 0x1 @@ -62,177 +56,121 @@ typedef struct { #define MSGIF_REG_RECV_ID_OFFS 0 #define MSGIF_REG_RECV_ID_MASK 0xf -#define MSGIF_REG_RECV_ID(V) \ - ((V & MSGIF_REG_RECV_ID_MASK) << MSGIF_REG_RECV_ID_OFFS) +#define MSGIF_REG_RECV_ID(V) ((V & MSGIF_REG_RECV_ID_MASK) << MSGIF_REG_RECV_ID_OFFS) #define MSGIF_REG_RECV_PAYLOAD_OFFS 0 #define MSGIF_REG_RECV_PAYLOAD_MASK 0xffffffff -#define MSGIF_REG_RECV_PAYLOAD(V) \ - ((V & MSGIF_REG_RECV_PAYLOAD_MASK) << MSGIF_REG_RECV_PAYLOAD_OFFS) +#define MSGIF_REG_RECV_PAYLOAD(V) ((V & MSGIF_REG_RECV_PAYLOAD_MASK) << MSGIF_REG_RECV_PAYLOAD_OFFS) #define MSGIF_REG_PAYLOAD_0_OFFS 0 #define MSGIF_REG_PAYLOAD_0_MASK 0xffffffff -#define MSGIF_REG_PAYLOAD_0(V) \ - ((V & MSGIF_REG_PAYLOAD_0_MASK) << MSGIF_REG_PAYLOAD_0_OFFS) +#define MSGIF_REG_PAYLOAD_0(V) ((V & MSGIF_REG_PAYLOAD_0_MASK) << MSGIF_REG_PAYLOAD_0_OFFS) #define MSGIF_REG_PAYLOAD_1_OFFS 0 #define MSGIF_REG_PAYLOAD_1_MASK 0xffffffff -#define MSGIF_REG_PAYLOAD_1(V) \ - ((V & MSGIF_REG_PAYLOAD_1_MASK) << MSGIF_REG_PAYLOAD_1_OFFS) +#define MSGIF_REG_PAYLOAD_1(V) ((V & MSGIF_REG_PAYLOAD_1_MASK) << MSGIF_REG_PAYLOAD_1_OFFS) #define MSGIF_REG_PAYLOAD_2_OFFS 0 #define MSGIF_REG_PAYLOAD_2_MASK 0xffffffff -#define MSGIF_REG_PAYLOAD_2(V) \ - ((V & MSGIF_REG_PAYLOAD_2_MASK) << MSGIF_REG_PAYLOAD_2_OFFS) +#define MSGIF_REG_PAYLOAD_2(V) ((V & MSGIF_REG_PAYLOAD_2_MASK) << MSGIF_REG_PAYLOAD_2_OFFS) #define MSGIF_REG_PAYLOAD_3_OFFS 0 #define MSGIF_REG_PAYLOAD_3_MASK 0xffffffff -#define MSGIF_REG_PAYLOAD_3(V) \ - ((V & MSGIF_REG_PAYLOAD_3_MASK) << MSGIF_REG_PAYLOAD_3_OFFS) +#define MSGIF_REG_PAYLOAD_3(V) ((V & MSGIF_REG_PAYLOAD_3_MASK) << MSGIF_REG_PAYLOAD_3_OFFS) #define MSGIF_REG_PAYLOAD_4_OFFS 0 #define MSGIF_REG_PAYLOAD_4_MASK 0xffffffff -#define MSGIF_REG_PAYLOAD_4(V) \ - ((V & MSGIF_REG_PAYLOAD_4_MASK) << MSGIF_REG_PAYLOAD_4_OFFS) +#define MSGIF_REG_PAYLOAD_4(V) ((V & MSGIF_REG_PAYLOAD_4_MASK) << MSGIF_REG_PAYLOAD_4_OFFS) #define MSGIF_REG_PAYLOAD_5_OFFS 0 #define MSGIF_REG_PAYLOAD_5_MASK 0xffffffff -#define MSGIF_REG_PAYLOAD_5(V) \ - ((V & MSGIF_REG_PAYLOAD_5_MASK) << MSGIF_REG_PAYLOAD_5_OFFS) +#define MSGIF_REG_PAYLOAD_5(V) ((V & MSGIF_REG_PAYLOAD_5_MASK) << MSGIF_REG_PAYLOAD_5_OFFS) #define MSGIF_REG_PAYLOAD_6_OFFS 0 #define MSGIF_REG_PAYLOAD_6_MASK 0xffffffff -#define MSGIF_REG_PAYLOAD_6(V) \ - ((V & MSGIF_REG_PAYLOAD_6_MASK) << MSGIF_REG_PAYLOAD_6_OFFS) +#define MSGIF_REG_PAYLOAD_6(V) ((V & MSGIF_REG_PAYLOAD_6_MASK) << MSGIF_REG_PAYLOAD_6_OFFS) #define MSGIF_REG_PAYLOAD_7_OFFS 0 #define MSGIF_REG_PAYLOAD_7_MASK 0xffffffff -#define MSGIF_REG_PAYLOAD_7(V) \ - ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS) +#define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS) // MSGIF_REG_SEND -static inline void set_msgif_REG_SEND(volatile msgif_t *reg, uint32_t value) { - reg->REG_SEND = value; -} -static inline void set_msgif_REG_SEND_SEND(volatile msgif_t *reg, - uint8_t value) { +static inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value) { reg->REG_SEND = value; } +static inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value) { reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0); } // MSGIF_REG_HEADER -static inline uint32_t get_msgif_REG_HEADER(volatile msgif_t *reg) { - return reg->REG_HEADER; -} -static inline void set_msgif_REG_HEADER(volatile msgif_t *reg, uint32_t value) { - reg->REG_HEADER = value; -} -static inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t *reg) { - return (reg->REG_HEADER >> 0) & 0xf; -} -static inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t *reg, - uint8_t value) { +static inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg) { return reg->REG_HEADER; } +static inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value) { reg->REG_HEADER = value; } +static inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg) { return (reg->REG_HEADER >> 0) & 0xf; } +static inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value) { reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0); } -static inline uint32_t -get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t *reg) { - return (reg->REG_HEADER >> 4) & 0xf; -} -static inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t *reg, - uint8_t value) { +static inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg) { return (reg->REG_HEADER >> 4) & 0xf; } +static inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value) { reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4); } -static inline uint32_t -get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t *reg) { - return (reg->REG_HEADER >> 8) & 0x7; -} -static inline void -set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t *reg, uint8_t value) { +static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg) { return (reg->REG_HEADER >> 8) & 0x7; } +static inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value) { reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8); } -static inline uint32_t -get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t *reg) { - return (reg->REG_HEADER >> 11) & 0x3; -} -static inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t *reg, - uint8_t value) { +static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg) { return (reg->REG_HEADER >> 11) & 0x3; } +static inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value) { reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11); } // MSGIF_REG_ACK -static inline void set_msgif_REG_ACK(volatile msgif_t *reg, uint32_t value) { - reg->REG_ACK = value; -} -static inline void set_msgif_REG_ACK_ACK(volatile msgif_t *reg, uint8_t value) { +static inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value) { reg->REG_ACK = value; } +static inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value) { reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0); } // MSGIF_REG_RECV_ID -static inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t *reg) { - return reg->REG_RECV_ID; -} -static inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t *reg) { - return (reg->REG_RECV_ID >> 0) & 0xf; -} +static inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg) { return reg->REG_RECV_ID; } +static inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg) { return (reg->REG_RECV_ID >> 0) & 0xf; } // MSGIF_REG_RECV_PAYLOAD -static inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t *reg) { - return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; -} +static inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg) { return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; } // MSGIF_REG_PAYLOAD_0 -static inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t *reg, - uint32_t value) { - reg->REG_PAYLOAD_0 = - (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0); +static inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value) { + reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0); } // MSGIF_REG_PAYLOAD_1 -static inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t *reg, - uint32_t value) { - reg->REG_PAYLOAD_1 = - (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0); +static inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value) { + reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0); } // MSGIF_REG_PAYLOAD_2 -static inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t *reg, - uint32_t value) { - reg->REG_PAYLOAD_2 = - (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0); +static inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value) { + reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0); } // MSGIF_REG_PAYLOAD_3 -static inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t *reg, - uint32_t value) { - reg->REG_PAYLOAD_3 = - (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0); +static inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value) { + reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0); } // MSGIF_REG_PAYLOAD_4 -static inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t *reg, - uint32_t value) { - reg->REG_PAYLOAD_4 = - (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0); +static inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value) { + reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0); } // MSGIF_REG_PAYLOAD_5 -static inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t *reg, - uint32_t value) { - reg->REG_PAYLOAD_5 = - (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0); +static inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value) { + reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0); } // MSGIF_REG_PAYLOAD_6 -static inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t *reg, - uint32_t value) { - reg->REG_PAYLOAD_6 = - (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0); +static inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value) { + reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0); } // MSGIF_REG_PAYLOAD_7 -static inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t *reg, - uint32_t value) { - reg->REG_PAYLOAD_7 = - (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0); +static inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value) { + reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0); } #endif /* _BSP_MSGIF_H */ \ No newline at end of file diff --git a/include/minres/devices/gen/timercounter.h b/include/minres/devices/gen/timercounter.h index 68631a1..12e8060 100644 --- a/include/minres/devices/gen/timercounter.h +++ b/include/minres/devices/gen/timercounter.h @@ -24,147 +24,88 @@ typedef struct { #define TIMERCOUNTER_PRESCALER_OFFS 0 #define TIMERCOUNTER_PRESCALER_MASK 0xffff -#define TIMERCOUNTER_PRESCALER(V) \ - ((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS) +#define TIMERCOUNTER_PRESCALER(V) ((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS) #define TIMERCOUNTER_T0_CTRL_ENABLE_OFFS 0 #define TIMERCOUNTER_T0_CTRL_ENABLE_MASK 0x7 -#define TIMERCOUNTER_T0_CTRL_ENABLE(V) \ - ((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS) +#define TIMERCOUNTER_T0_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS) #define TIMERCOUNTER_T0_CTRL_CLEAR_OFFS 3 #define TIMERCOUNTER_T0_CTRL_CLEAR_MASK 0x3 -#define TIMERCOUNTER_T0_CTRL_CLEAR(V) \ - ((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS) +#define TIMERCOUNTER_T0_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS) #define TIMERCOUNTER_T0_OVERFLOW_OFFS 0 #define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff -#define TIMERCOUNTER_T0_OVERFLOW(V) \ - ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS) +#define TIMERCOUNTER_T0_OVERFLOW(V) ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS) #define TIMERCOUNTER_T0_COUNTER_OFFS 0 #define TIMERCOUNTER_T0_COUNTER_MASK 0xffffffff -#define TIMERCOUNTER_T0_COUNTER(V) \ - ((V & TIMERCOUNTER_T0_COUNTER_MASK) << TIMERCOUNTER_T0_COUNTER_OFFS) +#define TIMERCOUNTER_T0_COUNTER(V) ((V & TIMERCOUNTER_T0_COUNTER_MASK) << TIMERCOUNTER_T0_COUNTER_OFFS) #define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0 #define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7 -#define TIMERCOUNTER_T1_CTRL_ENABLE(V) \ - ((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS) +#define TIMERCOUNTER_T1_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS) #define TIMERCOUNTER_T1_CTRL_CLEAR_OFFS 3 #define TIMERCOUNTER_T1_CTRL_CLEAR_MASK 0x3 -#define TIMERCOUNTER_T1_CTRL_CLEAR(V) \ - ((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS) +#define TIMERCOUNTER_T1_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS) #define TIMERCOUNTER_T1_OVERFLOW_OFFS 0 #define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff -#define TIMERCOUNTER_T1_OVERFLOW(V) \ - ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS) +#define TIMERCOUNTER_T1_OVERFLOW(V) ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS) #define TIMERCOUNTER_T1_COUNTER_OFFS 0 #define TIMERCOUNTER_T1_COUNTER_MASK 0xffffffff -#define TIMERCOUNTER_T1_COUNTER(V) \ - ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS) +#define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS) // TIMERCOUNTER_PRESCALER -static inline uint32_t -get_timercounter_prescaler(volatile timercounter_t *reg) { - return reg->PRESCALER; -} -static inline void set_timercounter_prescaler(volatile timercounter_t *reg, - uint32_t value) { - reg->PRESCALER = value; -} -static inline uint32_t -get_timercounter_prescaler_limit(volatile timercounter_t *reg) { - return (reg->PRESCALER >> 0) & 0xffff; -} -static inline void -set_timercounter_prescaler_limit(volatile timercounter_t *reg, uint16_t value) { +static inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg) { return reg->PRESCALER; } +static inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value) { reg->PRESCALER = value; } +static inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg) { return (reg->PRESCALER >> 0) & 0xffff; } +static inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value) { reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0); } // TIMERCOUNTER_T0_CTRL -static inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t *reg) { - return reg->T0_CTRL; -} -static inline void set_timercounter_t0_ctrl(volatile timercounter_t *reg, - uint32_t value) { - reg->T0_CTRL = value; -} -static inline uint32_t -get_timercounter_t0_ctrl_enable(volatile timercounter_t *reg) { - return (reg->T0_CTRL >> 0) & 0x7; -} -static inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t *reg, - uint8_t value) { +static inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg) { return reg->T0_CTRL; } +static inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T0_CTRL = value; } +static inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 0) & 0x7; } +static inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value) { reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0); } -static inline uint32_t -get_timercounter_t0_ctrl_clear(volatile timercounter_t *reg) { - return (reg->T0_CTRL >> 3) & 0x3; -} -static inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t *reg, - uint8_t value) { +static inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 3) & 0x3; } +static inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value) { reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3); } // TIMERCOUNTER_T0_OVERFLOW -static inline uint32_t -get_timercounter_t0_overflow(volatile timercounter_t *reg) { - return (reg->T0_OVERFLOW >> 0) & 0xffffffff; -} -static inline void set_timercounter_t0_overflow(volatile timercounter_t *reg, - uint32_t value) { +static inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg) { return (reg->T0_OVERFLOW >> 0) & 0xffffffff; } +static inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value) { reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0); } // TIMERCOUNTER_T0_COUNTER -static inline uint32_t -get_timercounter_t0_counter(volatile timercounter_t *reg) { - return (reg->T0_COUNTER >> 0) & 0xffffffff; -} +static inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg) { return (reg->T0_COUNTER >> 0) & 0xffffffff; } // TIMERCOUNTER_T1_CTRL -static inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t *reg) { - return reg->T1_CTRL; -} -static inline void set_timercounter_t1_ctrl(volatile timercounter_t *reg, - uint32_t value) { - reg->T1_CTRL = value; -} -static inline uint32_t -get_timercounter_t1_ctrl_enable(volatile timercounter_t *reg) { - return (reg->T1_CTRL >> 0) & 0x7; -} -static inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t *reg, - uint8_t value) { +static inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg) { return reg->T1_CTRL; } +static inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T1_CTRL = value; } +static inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 0) & 0x7; } +static inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value) { reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0); } -static inline uint32_t -get_timercounter_t1_ctrl_clear(volatile timercounter_t *reg) { - return (reg->T1_CTRL >> 3) & 0x3; -} -static inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t *reg, - uint8_t value) { +static inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 3) & 0x3; } +static inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value) { reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3); } // TIMERCOUNTER_T1_OVERFLOW -static inline uint32_t -get_timercounter_t1_overflow(volatile timercounter_t *reg) { - return (reg->T1_OVERFLOW >> 0) & 0xffffffff; -} -static inline void set_timercounter_t1_overflow(volatile timercounter_t *reg, - uint32_t value) { +static inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg) { return (reg->T1_OVERFLOW >> 0) & 0xffffffff; } +static inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value) { reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0); } // TIMERCOUNTER_T1_COUNTER -static inline uint32_t -get_timercounter_t1_counter(volatile timercounter_t *reg) { - return (reg->T1_COUNTER >> 0) & 0xffffffff; -} +static inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg) { return (reg->T1_COUNTER >> 0) & 0xffffffff; } -#endif /* _BSP_TIMERCOUNTER_H */ +#endif /* _BSP_TIMERCOUNTER_H */ \ No newline at end of file diff --git a/include/minres/devices/gen/uart.h b/include/minres/devices/gen/uart.h index 8976c10..ee3c71d 100644 --- a/include/minres/devices/gen/uart.h +++ b/include/minres/devices/gen/uart.h @@ -22,267 +22,154 @@ typedef struct { #define UART_RX_TX_REG_DATA_OFFS 0 #define UART_RX_TX_REG_DATA_MASK 0xff -#define UART_RX_TX_REG_DATA(V) \ - ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS) +#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS) #define UART_RX_TX_REG_RX_AVAIL_OFFS 14 #define UART_RX_TX_REG_RX_AVAIL_MASK 0x1 -#define UART_RX_TX_REG_RX_AVAIL(V) \ - ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS) +#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS) #define UART_RX_TX_REG_TX_FREE_OFFS 15 #define UART_RX_TX_REG_TX_FREE_MASK 0x1 -#define UART_RX_TX_REG_TX_FREE(V) \ - ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS) +#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS) #define UART_RX_TX_REG_TX_EMPTY_OFFS 16 #define UART_RX_TX_REG_TX_EMPTY_MASK 0x1 -#define UART_RX_TX_REG_TX_EMPTY(V) \ - ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS) +#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS) #define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0 #define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1 -#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) \ - ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) \ - << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS) +#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS) #define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1 #define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1 -#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) \ - ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) \ - << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS) +#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS) #define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2 #define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1 -#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) \ - ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) \ - << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS) +#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS) #define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8 #define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1 -#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) \ - ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) \ - << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS) +#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS) #define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9 #define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1 -#define UART_INT_CTRL_REG_READ_INTR_PEND(V) \ - ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) \ - << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS) +#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS) #define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10 #define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1 -#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) \ - ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) \ - << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS) +#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS) #define UART_CLK_DIVIDER_REG_OFFS 0 #define UART_CLK_DIVIDER_REG_MASK 0xfffff -#define UART_CLK_DIVIDER_REG(V) \ - ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS) +#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS) #define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0 #define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7 -#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) \ - ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) \ - << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS) +#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS) #define UART_FRAME_CONFIG_REG_PARITY_OFFS 3 #define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3 -#define UART_FRAME_CONFIG_REG_PARITY(V) \ - ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS) +#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS) #define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5 #define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1 -#define UART_FRAME_CONFIG_REG_STOP_BIT(V) \ - ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) \ - << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS) +#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS) #define UART_STATUS_REG_READ_ERROR_OFFS 0 #define UART_STATUS_REG_READ_ERROR_MASK 0x1 -#define UART_STATUS_REG_READ_ERROR(V) \ - ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS) +#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS) #define UART_STATUS_REG_STALL_OFFS 1 #define UART_STATUS_REG_STALL_MASK 0x1 -#define UART_STATUS_REG_STALL(V) \ - ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS) +#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS) #define UART_STATUS_REG_BREAK_LINE_OFFS 8 #define UART_STATUS_REG_BREAK_LINE_MASK 0x1 -#define UART_STATUS_REG_BREAK_LINE(V) \ - ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS) +#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS) #define UART_STATUS_REG_BREAK_DETECTED_OFFS 9 #define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1 -#define UART_STATUS_REG_BREAK_DETECTED(V) \ - ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) \ - << UART_STATUS_REG_BREAK_DETECTED_OFFS) +#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS) #define UART_STATUS_REG_SET_BREAK_OFFS 10 #define UART_STATUS_REG_SET_BREAK_MASK 0x1 -#define UART_STATUS_REG_SET_BREAK(V) \ - ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS) +#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS) #define UART_STATUS_REG_CLEAR_BREAK_OFFS 11 #define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1 -#define UART_STATUS_REG_CLEAR_BREAK(V) \ - ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS) +#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS) // UART_RX_TX_REG -static inline uint32_t get_uart_rx_tx_reg(volatile uart_t *reg) { - return reg->RX_TX_REG; -} -static inline void set_uart_rx_tx_reg(volatile uart_t *reg, uint32_t value) { - reg->RX_TX_REG = value; -} -static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t *reg) { - return (reg->RX_TX_REG >> 0) & 0xff; -} -static inline void set_uart_rx_tx_reg_data(volatile uart_t *reg, - uint8_t value) { +static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; } +static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; } +static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; } +static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) { reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0); } -static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t *reg) { - return (reg->RX_TX_REG >> 14) & 0x1; -} -static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t *reg) { - return (reg->RX_TX_REG >> 15) & 0x1; -} -static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t *reg) { - return (reg->RX_TX_REG >> 16) & 0x1; -} +static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; } +static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; } +static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; } // UART_INT_CTRL_REG -static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t *reg) { - return reg->INT_CTRL_REG; -} -static inline void set_uart_int_ctrl_reg(volatile uart_t *reg, uint32_t value) { - reg->INT_CTRL_REG = value; -} -static inline uint32_t -get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t *reg) { - return (reg->INT_CTRL_REG >> 0) & 0x1; -} -static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t *reg, - uint8_t value) { +static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; } +static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; } +static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; } +static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) { reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0); } -static inline uint32_t -get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t *reg) { - return (reg->INT_CTRL_REG >> 1) & 0x1; -} -static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t *reg, - uint8_t value) { +static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; } +static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) { reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1); } -static inline uint32_t -get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t *reg) { - return (reg->INT_CTRL_REG >> 2) & 0x1; -} -static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t *reg, - uint8_t value) { +static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; } +static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) { reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2); } -static inline uint32_t -get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t *reg) { - return (reg->INT_CTRL_REG >> 8) & 0x1; -} -static inline uint32_t -get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t *reg) { - return (reg->INT_CTRL_REG >> 9) & 0x1; -} -static inline uint32_t -get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t *reg) { - return (reg->INT_CTRL_REG >> 10) & 0x1; -} +static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; } +static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; } +static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; } // UART_CLK_DIVIDER_REG -static inline uint32_t get_uart_clk_divider_reg(volatile uart_t *reg) { - return reg->CLK_DIVIDER_REG; -} -static inline void set_uart_clk_divider_reg(volatile uart_t *reg, - uint32_t value) { - reg->CLK_DIVIDER_REG = value; -} -static inline uint32_t -get_uart_clk_divider_reg_clock_divider(volatile uart_t *reg) { - return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; -} -static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t *reg, - uint32_t value) { - reg->CLK_DIVIDER_REG = - (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0); +static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; } +static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; } +static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; } +static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) { + reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0); } // UART_FRAME_CONFIG_REG -static inline uint32_t get_uart_frame_config_reg(volatile uart_t *reg) { - return reg->FRAME_CONFIG_REG; -} -static inline void set_uart_frame_config_reg(volatile uart_t *reg, - uint32_t value) { - reg->FRAME_CONFIG_REG = value; -} -static inline uint32_t -get_uart_frame_config_reg_data_length(volatile uart_t *reg) { - return (reg->FRAME_CONFIG_REG >> 0) & 0x7; -} -static inline void set_uart_frame_config_reg_data_length(volatile uart_t *reg, - uint8_t value) { +static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; } +static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; } +static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; } +static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) { reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0); } -static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t *reg) { - return (reg->FRAME_CONFIG_REG >> 3) & 0x3; -} -static inline void set_uart_frame_config_reg_parity(volatile uart_t *reg, - uint8_t value) { +static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; } +static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) { reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3); } -static inline uint32_t -get_uart_frame_config_reg_stop_bit(volatile uart_t *reg) { - return (reg->FRAME_CONFIG_REG >> 5) & 0x1; -} -static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t *reg, - uint8_t value) { +static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; } +static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) { reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5); } // UART_STATUS_REG -static inline uint32_t get_uart_status_reg(volatile uart_t *reg) { - return reg->STATUS_REG; -} -static inline void set_uart_status_reg(volatile uart_t *reg, uint32_t value) { - reg->STATUS_REG = value; -} -static inline uint32_t get_uart_status_reg_read_error(volatile uart_t *reg) { - return (reg->STATUS_REG >> 0) & 0x1; -} -static inline uint32_t get_uart_status_reg_stall(volatile uart_t *reg) { - return (reg->STATUS_REG >> 1) & 0x1; -} -static inline uint32_t get_uart_status_reg_break_line(volatile uart_t *reg) { - return (reg->STATUS_REG >> 8) & 0x1; -} -static inline uint32_t -get_uart_status_reg_break_detected(volatile uart_t *reg) { - return (reg->STATUS_REG >> 9) & 0x1; -} -static inline void set_uart_status_reg_break_detected(volatile uart_t *reg, - uint8_t value) { +static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; } +static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; } +static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; } +static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; } +static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; } +static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; } +static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) { reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9); } -static inline uint32_t get_uart_status_reg_set_break(volatile uart_t *reg) { - return (reg->STATUS_REG >> 10) & 0x1; -} -static inline void set_uart_status_reg_set_break(volatile uart_t *reg, - uint8_t value) { +static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; } +static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) { reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10); } -static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t *reg) { - return (reg->STATUS_REG >> 11) & 0x1; -} -static inline void set_uart_status_reg_clear_break(volatile uart_t *reg, - uint8_t value) { +static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; } +static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) { reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11); } diff --git a/include/minres/devices/gpio.h b/include/minres/devices/gpio.h index aab506e..e041b18 100644 --- a/include/minres/devices/gpio.h +++ b/include/minres/devices/gpio.h @@ -5,7 +5,7 @@ #include "gen/gpio.h" -static inline void gpio_init(volatile gpio_t *reg) { +static inline void gpio_init(volatile gpio_t* reg) { set_gpio_write(reg, 0); set_gpio_writeEnable(reg, 0); } diff --git a/include/minres/devices/timer.h b/include/minres/devices/timer.h index d09f302..9379af1 100644 --- a/include/minres/devices/timer.h +++ b/include/minres/devices/timer.h @@ -5,16 +5,10 @@ #include "gen/timercounter.h" -static inline void prescaler_init(timercounter_t *reg, uint16_t value) { - set_timercounter_prescaler(reg, value); -} +static inline void prescaler_init(timercounter_t *reg, uint16_t value) { set_timercounter_prescaler(reg, value); } -static inline void timer_t0__init(timercounter_t *reg) { - set_timercounter_t0_overflow(reg, 0xffffffff); -} +static inline void timer_t0__init(timercounter_t *reg) { set_timercounter_t0_overflow(reg, 0xffffffff); } -static inline void timer_t1__init(timercounter_t *reg) { - set_timercounter_t1_overflow(reg, 0xffffffff); -} +static inline void timer_t1__init(timercounter_t *reg) { set_timercounter_t1_overflow(reg, 0xffffffff); } #endif /* _DEVICES_TIMER_H */ diff --git a/include/minres/devices/uart.h b/include/minres/devices/uart.h index 0d9a5cc..be3ccad 100644 --- a/include/minres/devices/uart.h +++ b/include/minres/devices/uart.h @@ -21,7 +21,7 @@ static inline void uart_write(volatile uart_t* reg, uint8_t data){ set_uart_rx_tx_reg_data(reg, data); } -static inline uint8_t uart_read(volatile uart_t* reg){ +static inline inline uint8_t uart_read(volatile uart_t* reg){ uint32_t res = get_uart_rx_tx_reg_data(reg); while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg); return res;