diff --git a/drivers/fe300prci/fe300prci_driver.c b/drivers/fe300prci/fe300prci_driver.c deleted file mode 100644 index 8eeaafc..0000000 --- a/drivers/fe300prci/fe300prci_driver.c +++ /dev/null @@ -1,252 +0,0 @@ -// See LICENSE file for license details - -#include "platform.h" - -#ifdef PRCI_CTRL_ADDR -#include "fe300prci/fe300prci_driver.h" -#include - -#define rdmcycle(x) { \ - uint32_t lo, hi, hi2; \ - __asm__ __volatile__ ("1:\n\t" \ - "csrr %0, mcycleh\n\t" \ - "csrr %1, mcycle\n\t" \ - "csrr %2, mcycleh\n\t" \ - "bne %0, %2, 1b\n\t" \ - : "=r" (hi), "=r" (lo), "=r" (hi2)) ; \ - *(x) = lo | ((uint64_t) hi << 32); \ - } - -uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq) -{ - - uint32_t start_mtime = CLINT_REG(CLINT_MTIME); - uint32_t end_mtime = start_mtime + mtime_ticks + 1; - - // Make sure we won't get rollover. - while (end_mtime < start_mtime){ - start_mtime = CLINT_REG(CLINT_MTIME); - end_mtime = start_mtime + mtime_ticks + 1; - } - - // Don't start measuring until mtime edge. - uint32_t tmp = start_mtime; - do { - start_mtime = CLINT_REG(CLINT_MTIME); - } while (start_mtime == tmp); - - uint64_t start_mcycle; - rdmcycle(&start_mcycle); - - while (CLINT_REG(CLINT_MTIME) < end_mtime) ; - - uint64_t end_mcycle; - rdmcycle(&end_mcycle); - uint32_t difference = (uint32_t) (end_mcycle - start_mcycle); - - uint64_t freq = ((uint64_t) difference * mtime_freq) / mtime_ticks; - return (uint32_t) freq & 0xFFFFFFFF; - -} - - -void PRCI_use_hfrosc(int div, int trim) -{ - // Make sure the HFROSC is running at its default setting - // It is OK to change this even if we are running off of it. - - PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); - - while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0); - - PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); -} - -void PRCI_use_pll(int refsel, int bypass, - int r, int f, int q, int finaldiv, - int hfroscdiv, int hfrosctrim) -{ - // Ensure that we aren't running off the PLL before we mess with it. - if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { - // Make sure the HFROSC is running at its default setting - PRCI_use_hfrosc(4, 16); - } - - // Set PLL Source to be HFXOSC if desired. - uint32_t config_value = 0; - - config_value |= PLL_REFSEL(refsel); - - if (bypass) { - // Bypass - config_value |= PLL_BYPASS(1); - - PRCI_REG(PRCI_PLLCFG) = config_value; - - // If we don't have an HFXTAL, this doesn't really matter. - // Set our Final output divide to divide-by-1: - PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); - } else { - - // To overclock, use the hfrosc - if (hfrosctrim >= 0 && hfroscdiv >= 0) { - PRCI_use_hfrosc(hfroscdiv, hfrosctrim); - } - - // Set DIV Settings for PLL - - // (Legal values of f_REF are 6-48MHz) - - // Set DIVR to divide-by-2 to get 8MHz frequency - // (legal values of f_R are 6-12 MHz) - - config_value |= PLL_BYPASS(1); - config_value |= PLL_R(r); - - // Set DIVF to get 512Mhz frequncy - // There is an implied multiply-by-2, 16Mhz. - // So need to write 32-1 - // (legal values of f_F are 384-768 MHz) - config_value |= PLL_F(f); - - // Set DIVQ to divide-by-2 to get 256 MHz frequency - // (legal values of f_Q are 50-400Mhz) - config_value |= PLL_Q(q); - - // Set our Final output divide to divide-by-1: - if (finaldiv == 1){ - PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); - } else { - PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV(finaldiv-1)); - } - - PRCI_REG(PRCI_PLLCFG) = config_value; - - // Un-Bypass the PLL. - PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); - - // Wait for PLL Lock - // Note that the Lock signal can be glitchy. - // Need to wait 100 us - // RTC is running at 32kHz. - // So wait 4 ticks of RTC. - uint32_t now = CLINT_REG(CLINT_MTIME); - while (CLINT_REG(CLINT_MTIME) - now < 4) ; - - // Now it is safe to check for PLL Lock - while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0); - - } - - // Switch over to PLL Clock source - PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); - - // If we're running off HFXOSC, turn off the HFROSC to - // save power. - if (refsel) { - PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1); - } - -} - -void PRCI_use_default_clocks() -{ - // Turn off the LFROSC - AON_REG(AON_LFROSC) &= ~ROSC_EN(1); - - // Use HFROSC - PRCI_use_hfrosc(4, 16); -} - -void PRCI_use_hfxosc(uint32_t finaldiv) -{ - - PRCI_use_pll(1, // Use HFXTAL - 1, // Bypass = 1 - 0, // PLL settings don't matter - 0, // PLL settings don't matter - 0, // PLL settings don't matter - finaldiv, - -1, - -1); -} - -// This is a generic function, which -// doesn't span the entire range of HFROSC settings. -// It only adjusts the trim, which can span a hundred MHz or so. -// This function does not check the legality of the PLL settings -// at all, and it is quite possible to configure invalid PLL settings -// this way. -// It returns the actual measured CPU frequency. - -uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target ) -{ - - uint32_t hfrosctrim = 0; - uint32_t hfroscdiv = 4; - uint32_t prev_trim = 0; - - // In this function we use PLL settings which - // will give us a 32x multiplier from the output - // of the HFROSC source to the output of the - // PLL. We first measure our HFROSC to get the - // right trim, then finally use it as the PLL source. - // We should really check here that the f_cpu - // requested is something in the limit of the PLL. For - // now that is up to the user. - - // This will undershoot for frequencies not divisible by 16. - uint32_t desired_hfrosc_freq = (f_cpu/ 16); - - PRCI_use_hfrosc(hfroscdiv, hfrosctrim); - - // Ignore the first run (for icache reasons) - uint32_t cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); - - cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); - uint32_t prev_freq = cpu_freq; - - while ((cpu_freq < desired_hfrosc_freq) && (hfrosctrim < 0x1F)){ - prev_trim = hfrosctrim; - prev_freq = cpu_freq; - hfrosctrim ++; - PRCI_use_hfrosc(hfroscdiv, hfrosctrim); - cpu_freq = PRCI_measure_mcycle_freq(3000, RTC_FREQ); - } - - // We couldn't go low enough - if (prev_freq > desired_hfrosc_freq){ - PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); - cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); - return cpu_freq; - } - - // We couldn't go high enough - if (cpu_freq < desired_hfrosc_freq){ - PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); - cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); - return cpu_freq; - } - - // Check for over/undershoot - switch(target) { - case(PRCI_FREQ_CLOSEST): - if ((desired_hfrosc_freq - prev_freq) < (cpu_freq - desired_hfrosc_freq)) { - PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); - } else { - PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); - } - break; - case(PRCI_FREQ_UNDERSHOOT): - PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, prev_trim); - break; - default: - PRCI_use_pll(0, 0, 1, 31, 1, 1, hfroscdiv, hfrosctrim); - } - - cpu_freq = PRCI_measure_mcycle_freq(1000, RTC_FREQ); - return cpu_freq; - -} - -#endif diff --git a/drivers/fe300prci/fe300prci_driver.h b/drivers/fe300prci/fe300prci_driver.h deleted file mode 100644 index 7100f46..0000000 --- a/drivers/fe300prci/fe300prci_driver.h +++ /dev/null @@ -1,79 +0,0 @@ -// See LICENSE file for license details - -#ifndef _FE300PRCI_DRIVER_H_ -#define _FE300PRCI_DRIVER_H_ - -__BEGIN_DECLS - -#include - -typedef enum prci_freq_target { - - PRCI_FREQ_OVERSHOOT, - PRCI_FREQ_CLOSEST, - PRCI_FREQ_UNDERSHOOT - -} PRCI_freq_target; - -/* Measure and return the approximate frequency of the - * CPU, as given by measuring the mcycle counter against - * the mtime ticks. - */ -uint32_t PRCI_measure_mcycle_freq(uint32_t mtime_ticks, uint32_t mtime_freq); - -/* Safely switch over to the HFROSC using the given div - * and trim settings. - */ -void PRCI_use_hfrosc(int div, int trim); - -/* Safely switch over to the 16MHz HFXOSC, - * applying the finaldiv clock divider (1 is the lowest - * legal value). - */ -void PRCI_use_hfxosc(uint32_t finaldiv); - -/* Safely switch over to the PLL using the given - * settings. - * - * Note that not all combinations of the inputs are actually - * legal, and this function does not check for their - * legality ("safely" means that this function won't turn off - * or glitch the clock the CPU is actually running off, but - * doesn't protect against you making it too fast or slow.) - */ - -void PRCI_use_pll(int refsel, int bypass, - int r, int f, int q, int finaldiv, - int hfroscdiv, int hfrosctrim); - -/* Use the default clocks configured at reset. - * This is ~16Mhz HFROSC and turns off the LFROSC - * (on the current FE310 Dev Platforms, an external LFROSC is - * used as it is more power efficient). - */ -void PRCI_use_default_clocks(); - -/* This routine will adjust the HFROSC trim - * while using HFROSC as the clock source, - * measure the resulting frequency, then - * use it as the PLL clock source, - * in an attempt to get over, under, or close to the - * requested frequency. It returns the actual measured - * frequency. - * - * Note that the requested frequency must be within the - * range supported by the PLL so not all values are - * achievable with this function, and not all - * are guaranteed to actually work. The PLL - * is rated higher than the hardware. - * - * There is no check on the desired f_cpu frequency, it - * is up to the user to specify something reasonable. - */ - -uint32_t PRCI_set_hfrosctrim_for_f_cpu(uint32_t f_cpu, PRCI_freq_target target); - -__END_DECLS - -#endif - diff --git a/env/hifive1.h b/env/hifive1.h deleted file mode 100644 index 0db2f0f..0000000 --- a/env/hifive1.h +++ /dev/null @@ -1,81 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_HIFIVE1_H -#define _SIFIVE_HIFIVE1_H - -#include - -/**************************************************************************** - * GPIO Connections - *****************************************************************************/ - -// These are the GPIO bit offsets for the RGB LED on HiFive1 Board. -// These are also mapped to RGB LEDs on the Freedom E300 Arty -// FPGA -// Dev Kit. - -#define RED_LED_OFFSET 22 -#define GREEN_LED_OFFSET 19 -#define BLUE_LED_OFFSET 21 - -// These are the GPIO bit offsets for the differen digital pins -// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit. -#define PIN_0_OFFSET 16 -#define PIN_1_OFFSET 17 -#define PIN_2_OFFSET 18 -#define PIN_3_OFFSET 19 -#define PIN_4_OFFSET 20 -#define PIN_5_OFFSET 21 -#define PIN_6_OFFSET 22 -#define PIN_7_OFFSET 23 -#define PIN_8_OFFSET 0 -#define PIN_9_OFFSET 1 -#define PIN_10_OFFSET 2 -#define PIN_11_OFFSET 3 -#define PIN_12_OFFSET 4 -#define PIN_13_OFFSET 5 -//#define PIN_14_OFFSET 8 //This pin is not connected on either board. -#define PIN_15_OFFSET 9 -#define PIN_16_OFFSET 10 -#define PIN_17_OFFSET 11 -#define PIN_18_OFFSET 12 -#define PIN_19_OFFSET 13 - -// These are *PIN* numbers, not -// GPIO Offset Numbers. -#define PIN_SPI1_SCK (13u) -#define PIN_SPI1_MISO (12u) -#define PIN_SPI1_MOSI (11u) -#define PIN_SPI1_SS0 (10u) -#define PIN_SPI1_SS1 (14u) -#define PIN_SPI1_SS2 (15u) -#define PIN_SPI1_SS3 (16u) - -#define SS_PIN_TO_CS_ID(x) \ - ((x==PIN_SPI1_SS0 ? 0 : \ - (x==PIN_SPI1_SS1 ? 1 : \ - (x==PIN_SPI1_SS2 ? 2 : \ - (x==PIN_SPI1_SS3 ? 3 : \ - -1))))) - - -// These buttons are present only on the Freedom E300 Arty Dev Kit. -#ifdef HAS_BOARD_BUTTONS -#define BUTTON_0_OFFSET 15 -#define BUTTON_1_OFFSET 30 -#define BUTTON_2_OFFSET 31 - -#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET) -#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET) -#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET) - -#endif - -#define HAS_HFXOSC 1 -#define HAS_LFROSC_BYPASS 1 - -#define RTC_FREQ 32768 - -void write_hex(int fd, unsigned long int hex); - -#endif /* _SIFIVE_HIFIVE1_H */ diff --git a/env/hifive1/dhrystone.lds b/env/hifive1/dhrystone.lds deleted file mode 100644 index cc9cd9b..0000000 --- a/env/hifive1/dhrystone.lds +++ /dev/null @@ -1,157 +0,0 @@ -OUTPUT_ARCH( "riscv" ) - -ENTRY( _start ) - -MEMORY -{ - flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M - ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K -} - -PHDRS -{ - flash PT_LOAD; - ram_init PT_LOAD; - ram PT_NULL; -} - -SECTIONS -{ - __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; - - .init : - { - KEEP (*(SORT_NONE(.init))) - } >flash AT>flash :flash - - .text : - { - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - *(.text .text.*) - *(.gnu.linkonce.t.*) - } >flash AT>flash :flash - - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash :flash - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - . = ALIGN(4); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash :flash - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash :flash - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash :flash - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >flash AT>flash :flash - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >flash AT>flash :flash - - .lalign : - { - . = ALIGN(4); - PROVIDE( _data_lma = . ); - } >flash AT>flash :flash - - .dalign : - { - . = ALIGN(4); - PROVIDE( _data = . ); - } >ram AT>flash :ram_init - - .data : - { - *(.rdata) - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800 ); - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - } >ram AT>flash :ram_init - - . = ALIGN(4); - PROVIDE( _edata = . ); - PROVIDE( edata = . ); - - PROVIDE( _fbss = . ); - PROVIDE( __bss_start = . ); - .bss : - { - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >ram AT>ram :ram - - . = ALIGN(8); - PROVIDE( _end = . ); - PROVIDE( end = . ); - - .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : - { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram :ram -} diff --git a/env/hifive1/init.c b/env/hifive1/init.c deleted file mode 100644 index 621a6e2..0000000 --- a/env/hifive1/init.c +++ /dev/null @@ -1,238 +0,0 @@ -#include -#include -#include - -#include "platform.h" -#include "encoding.h" - -extern int main(int argc, char** argv); -extern void trap_entry(); - -static unsigned long mtime_lo(void) -{ - return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME); -} - -#ifdef __riscv32 - -static uint32_t mtime_hi(void) -{ - return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); -} - -uint64_t get_timer_value() -{ - while (1) { - uint32_t hi = mtime_hi(); - uint32_t lo = mtime_lo(); - if (hi == mtime_hi()) - return ((uint64_t)hi << 32) | lo; - } -} - -#else /* __riscv32 */ - -uint64_t get_timer_value() -{ - return mtime_lo(); -} - -#endif - -unsigned long get_timer_freq() -{ - return 32768; -} - -static void use_hfrosc(int div, int trim) -{ - // Make sure the HFROSC is running at its default setting - PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); - while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ; - PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); -} - -static void use_pll(int refsel, int bypass, int r, int f, int q) -{ - // Ensure that we aren't running off the PLL before we mess with it. - if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { - // Make sure the HFROSC is running at its default setting - use_hfrosc(4, 16); - } - - // Set PLL Source to be HFXOSC if available. - uint32_t config_value = 0; - - config_value |= PLL_REFSEL(refsel); - - if (bypass) { - // Bypass - config_value |= PLL_BYPASS(1); - - PRCI_REG(PRCI_PLLCFG) = config_value; - - // If we don't have an HFXTAL, this doesn't really matter. - // Set our Final output divide to divide-by-1: - PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); - } else { - // In case we are executing from QSPI, - // (which is quite likely) we need to - // set the QSPI clock divider appropriately - // before boosting the clock frequency. - - // Div = f_sck/2 - SPI0_REG(SPI_REG_SCKDIV) = 8; - - // Set DIV Settings for PLL - // Both HFROSC and HFXOSC are modeled as ideal - // 16MHz sources (assuming dividers are set properly for - // HFROSC). - // (Legal values of f_REF are 6-48MHz) - - // Set DIVR to divide-by-2 to get 8MHz frequency - // (legal values of f_R are 6-12 MHz) - - config_value |= PLL_BYPASS(1); - config_value |= PLL_R(r); - - // Set DIVF to get 512Mhz frequncy - // There is an implied multiply-by-2, 16Mhz. - // So need to write 32-1 - // (legal values of f_F are 384-768 MHz) - config_value |= PLL_F(f); - - // Set DIVQ to divide-by-2 to get 256 MHz frequency - // (legal values of f_Q are 50-400Mhz) - config_value |= PLL_Q(q); - - // Set our Final output divide to divide-by-1: - PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); - - PRCI_REG(PRCI_PLLCFG) = config_value; - - // Un-Bypass the PLL. - PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); - - // Wait for PLL Lock - // Note that the Lock signal can be glitchy. - // Need to wait 100 us - // RTC is running at 32kHz. - // So wait 4 ticks of RTC. - uint32_t now = mtime_lo(); - while (mtime_lo() - now < 4) ; - - // Now it is safe to check for PLL Lock - while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ; - } - - // Switch over to PLL Clock source - PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); -} - -static void use_default_clocks() -{ - // Turn off the LFROSC - AON_REG(AON_LFROSC) &= ~ROSC_EN(1); - - // Use HFROSC - use_hfrosc(4, 16); -} - -static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n) -{ - unsigned long start_mtime, delta_mtime; - unsigned long mtime_freq = get_timer_freq(); - - // Don't start measuruing until we see an mtime tick - unsigned long tmp = mtime_lo(); - do { - start_mtime = mtime_lo(); - } while (start_mtime == tmp); - - unsigned long start_mcycle = read_csr(mcycle); - - do { - delta_mtime = mtime_lo() - start_mtime; - } while (delta_mtime < n); - - unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle; - - return (delta_mcycle / delta_mtime) * mtime_freq - + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; -} - -unsigned long get_cpu_freq() -{ - static uint32_t cpu_freq; - - if (!cpu_freq) { - // warm up I$ - measure_cpu_freq(1); - // measure for real - cpu_freq = measure_cpu_freq(10); - } - - return cpu_freq; -} - -static void uart_init(size_t baud_rate) -{ - GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; - GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; - UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; - UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; -} - - - -#ifdef USE_PLIC -extern void handle_m_ext_interrupt(); -#endif - -#ifdef USE_M_TIME -extern void handle_m_time_interrupt(); -#endif - -uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) -{ - if (0){ -#ifdef USE_PLIC - // External Machine-Level interrupt from PLIC - } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { - handle_m_ext_interrupt(); -#endif -#ifdef USE_M_TIME - // External Machine-Level interrupt from PLIC - } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ - handle_m_time_interrupt(); -#endif - } - else { - write(1, "trap\n", 5); - _exit(1 + mcause); - } - return epc; -} - -void _init() -{ - - #ifndef NO_INIT - use_default_clocks(); - use_pll(0, 0, 1, 31, 1); - uart_init(115200); - - printf("core freq at %d Hz\n", get_cpu_freq()); - - write_csr(mtvec, &trap_entry); - if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present - write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping - write_csr(fcsr, 0); // initialize rounding mode, undefined at reset - } - #endif - -} - -void _fini() -{ -} diff --git a/env/hifive1/link.lds b/env/hifive1/link.lds deleted file mode 100644 index 22f90c6..0000000 --- a/env/hifive1/link.lds +++ /dev/null @@ -1,166 +0,0 @@ -OUTPUT_ARCH( "riscv" ) - -ENTRY( _start ) - -MEMORY -{ - flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M - ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 512K -} - -PHDRS -{ - flash PT_LOAD; - ram_init PT_LOAD; - ram PT_NULL; -} - -SECTIONS -{ - __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; - - .init : - { - KEEP (*(SORT_NONE(.init))) - } >flash AT>flash :flash - - .text : - { - *(.text.unlikely .text.unlikely.*) - *(.text.startup .text.startup.*) - *(.text .text.*) - *(.gnu.linkonce.t.*) - } >flash AT>flash :flash - - .fini : - { - KEEP (*(SORT_NONE(.fini))) - } >flash AT>flash :flash - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - .rodata : - { - *(.rdata) - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - } >flash AT>flash :flash - - . = ALIGN(4); - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >flash AT>flash :flash - - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) - PROVIDE_HIDDEN (__init_array_end = .); - } >flash AT>flash :flash - - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) - KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) - PROVIDE_HIDDEN (__fini_array_end = .); - } >flash AT>flash :flash - - .ctors : - { - /* gcc uses crtbegin.o to find the start of - the constructors, so we make sure it is - first. Because this is a wildcard, it - doesn't matter if the user does not - actually link against crtbegin.o; the - linker won't look for a file to match a - wildcard. The wildcard also means that it - doesn't matter which directory crtbegin.o - is in. */ - KEEP (*crtbegin.o(.ctors)) - KEEP (*crtbegin?.o(.ctors)) - /* We don't want to include the .ctor section from - the crtend.o file until after the sorted ctors. - The .ctor section from the crtend file contains the - end of ctors marker and it must be last */ - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - } >flash AT>flash :flash - - .dtors : - { - KEEP (*crtbegin.o(.dtors)) - KEEP (*crtbegin?.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - } >flash AT>flash :flash - - .except : - { - *(.gcc_except_table.*) - } >flash AT>flash :flash - - .lalign : - { - . = ALIGN(4); - PROVIDE( _data_lma = . ); - } >flash AT>flash :flash - - .dalign : - { - . = ALIGN(4); - PROVIDE( _data = . ); - } >ram AT>flash :ram_init - - .data : - { - *(.data .data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - PROVIDE( __global_pointer$ = . + 0x800 ); - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - . = ALIGN(8); - *(.srodata.cst16) - *(.srodata.cst8) - *(.srodata.cst4) - *(.srodata.cst2) - *(.srodata .srodata.*) - } >ram AT>flash :ram_init - - . = ALIGN(4); - PROVIDE( _edata = . ); - PROVIDE( edata = . ); - - PROVIDE( _fbss = . ); - PROVIDE( __bss_start = . ); - .bss : - { - *(.sbss*) - *(.gnu.linkonce.sb.*) - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - } >ram AT>ram :ram - - . = ALIGN(8); - PROVIDE( _end = . ); - PROVIDE( end = . ); - - .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : - { - PROVIDE( _heap_end = . ); - . = __stack_size; - PROVIDE( _sp = . ); - } >ram AT>ram :ram -} diff --git a/env/hifive1/openocd.cfg b/env/hifive1/openocd.cfg deleted file mode 100644 index b531e9c..0000000 --- a/env/hifive1/openocd.cfg +++ /dev/null @@ -1,34 +0,0 @@ -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 - -ftdi_layout_init 0x0008 0x001b -ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 - -#Reset Stretcher logic on FE310 is ~1 second long -#This doesn't apply if you use -# ftdi_set_signal, but still good to document -#adapter_nsrst_delay 1500 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME -init -#reset -- This type of reset is not implemented yet -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z - #Wait for the reset stretcher - #It will work without this, but - #will incur lots of delays for later commands. - sleep 1500 -} -halt -#flash protect 0 64 last off diff --git a/env/hifive1/platform.h b/env/hifive1/platform.h deleted file mode 100644 index e3631b0..0000000 --- a/env/hifive1/platform.h +++ /dev/null @@ -1,133 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_PLATFORM_H -#define _SIFIVE_PLATFORM_H - -// Some things missing from the official encoding.h -#define MCAUSE_INT 0x80000000 -#define MCAUSE_CAUSE 0x7FFFFFFF - -#include "bits.h" -#include "sifive/devices/aon.h" -#include "sifive/devices/clint.h" -#include "sifive/devices/gpio.h" -#include "sifive/devices/otp.h" -#include "sifive/devices/plic.h" -#include "sifive/devices/prci.h" -#include "sifive/devices/pwm.h" -#include "sifive/devices/spi.h" -#include "sifive/devices/uart.h" - -/**************************************************************************** - * Platform definitions - *****************************************************************************/ - -// Memory map -#define MASKROM_MEM_ADDR _AC(0x00001000,UL) -#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) -#define OTP_MEM_ADDR _AC(0x00020000,UL) -#define CLINT_CTRL_ADDR _AC(0x02000000,UL) -#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) -#define AON_CTRL_ADDR _AC(0x10000000,UL) -#define PRCI_CTRL_ADDR _AC(0x10008000,UL) -#define OTP_CTRL_ADDR _AC(0x10010000,UL) -#define GPIO_CTRL_ADDR _AC(0x10012000,UL) -#define UART0_CTRL_ADDR _AC(0x10013000,UL) -#define SPI0_CTRL_ADDR _AC(0x10014000,UL) -#define PWM0_CTRL_ADDR _AC(0x10015000,UL) -#define UART1_CTRL_ADDR _AC(0x10023000,UL) -#define SPI1_CTRL_ADDR _AC(0x10024000,UL) -#define PWM1_CTRL_ADDR _AC(0x10025000,UL) -#define SPI2_CTRL_ADDR _AC(0x10034000,UL) -#define PWM2_CTRL_ADDR _AC(0x10035000,UL) -#define SPI0_MEM_ADDR _AC(0x20000000,UL) -#define MEM_CTRL_ADDR _AC(0x80000000,UL) - -// IOF masks -#define IOF0_SPI1_MASK _AC(0x000007FC,UL) -#define SPI11_NUM_SS (4) -#define IOF_SPI1_SS0 (2u) -#define IOF_SPI1_SS1 (8u) -#define IOF_SPI1_SS2 (9u) -#define IOF_SPI1_SS3 (10u) -#define IOF_SPI1_MOSI (3u) -#define IOF_SPI1_MISO (4u) -#define IOF_SPI1_SCK (5u) -#define IOF_SPI1_DQ0 (3u) -#define IOF_SPI1_DQ1 (4u) -#define IOF_SPI1_DQ2 (6u) -#define IOF_SPI1_DQ3 (7u) - -#define IOF0_SPI2_MASK _AC(0xFC000000,UL) -#define SPI2_NUM_SS (1) -#define IOF_SPI2_SS0 (26u) -#define IOF_SPI2_MOSI (27u) -#define IOF_SPI2_MISO (28u) -#define IOF_SPI2_SCK (29u) -#define IOF_SPI2_DQ0 (27u) -#define IOF_SPI2_DQ1 (28u) -#define IOF_SPI2_DQ2 (30u) -#define IOF_SPI2_DQ3 (31u) - -//#define IOF0_I2C_MASK _AC(0x00003000,UL) - -#define IOF0_UART0_MASK _AC(0x00030000, UL) -#define IOF_UART0_RX (16u) -#define IOF_UART0_TX (17u) - -#define IOF0_UART1_MASK _AC(0x03000000, UL) -#define IOF_UART1_RX (24u) -#define IOF_UART1_TX (25u) - -#define IOF1_PWM0_MASK _AC(0x0000000F, UL) -#define IOF1_PWM1_MASK _AC(0x00780000, UL) -#define IOF1_PWM2_MASK _AC(0x00003C00, UL) - -// Interrupt numbers -#define INT_RESERVED 0 -#define INT_WDOGCMP 1 -#define INT_RTCCMP 2 -#define INT_UART0_BASE 3 -#define INT_UART1_BASE 4 -#define INT_SPI0_BASE 5 -#define INT_SPI1_BASE 6 -#define INT_SPI2_BASE 7 -#define INT_GPIO_BASE 8 -#define INT_PWM0_BASE 40 -#define INT_PWM1_BASE 44 -#define INT_PWM2_BASE 48 - -// Helper functions -#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) -#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) -#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset) -#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) -#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) -#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset) -#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) -#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset) -#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) -#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset) -#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset) -#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) -#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset) -#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset) -#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) -#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset) - -// Misc - -#include - -#define NUM_GPIO 32 - -#define PLIC_NUM_INTERRUPTS 52 -#define PLIC_NUM_PRIORITIES 7 - -#include "hifive1.h" - -unsigned long get_cpu_freq(void); -unsigned long get_timer_freq(void); -uint64_t get_timer_value(void); - -#endif /* _SIFIVE_PLATFORM_H */ diff --git a/env/hifive1/settings.mk b/env/hifive1/settings.mk deleted file mode 100644 index 230fccc..0000000 --- a/env/hifive1/settings.mk +++ /dev/null @@ -1,3 +0,0 @@ -# Describes the CPU on this board to the rest of the SDK. -RISCV_ARCH := rv32imac -RISCV_ABI := ilp32 diff --git a/include/sifive/devices/aon.h b/include/sifive/devices/aon.h deleted file mode 100644 index 63f1db3..0000000 --- a/include/sifive/devices/aon.h +++ /dev/null @@ -1,88 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_AON_H -#define _SIFIVE_AON_H - -/* Register offsets */ - -#define AON_WDOGCFG 0x000 -#define AON_WDOGCOUNT 0x008 -#define AON_WDOGS 0x010 -#define AON_WDOGFEED 0x018 -#define AON_WDOGKEY 0x01C -#define AON_WDOGCMP 0x020 - -#define AON_RTCCFG 0x040 -#define AON_RTCLO 0x048 -#define AON_RTCHI 0x04C -#define AON_RTCS 0x050 -#define AON_RTCCMP 0x060 - -#define AON_BACKUP0 0x080 -#define AON_BACKUP1 0x084 -#define AON_BACKUP2 0x088 -#define AON_BACKUP3 0x08C -#define AON_BACKUP4 0x090 -#define AON_BACKUP5 0x094 -#define AON_BACKUP6 0x098 -#define AON_BACKUP7 0x09C -#define AON_BACKUP8 0x0A0 -#define AON_BACKUP9 0x0A4 -#define AON_BACKUP10 0x0A8 -#define AON_BACKUP11 0x0AC -#define AON_BACKUP12 0x0B0 -#define AON_BACKUP13 0x0B4 -#define AON_BACKUP14 0x0B8 -#define AON_BACKUP15 0x0BC - -#define AON_PMUWAKEUPI0 0x100 -#define AON_PMUWAKEUPI1 0x104 -#define AON_PMUWAKEUPI2 0x108 -#define AON_PMUWAKEUPI3 0x10C -#define AON_PMUWAKEUPI4 0x110 -#define AON_PMUWAKEUPI5 0x114 -#define AON_PMUWAKEUPI6 0x118 -#define AON_PMUWAKEUPI7 0x11C -#define AON_PMUSLEEPI0 0x120 -#define AON_PMUSLEEPI1 0x124 -#define AON_PMUSLEEPI2 0x128 -#define AON_PMUSLEEPI3 0x12C -#define AON_PMUSLEEPI4 0x130 -#define AON_PMUSLEEPI5 0x134 -#define AON_PMUSLEEPI6 0x138 -#define AON_PMUSLEEPI7 0x13C -#define AON_PMUIE 0x140 -#define AON_PMUCAUSE 0x144 -#define AON_PMUSLEEP 0x148 -#define AON_PMUKEY 0x14C - -#define AON_LFROSC 0x070 -/* Constants */ - -#define AON_WDOGKEY_VALUE 0x51F15E -#define AON_WDOGFEED_VALUE 0xD09F00D - -#define AON_WDOGCFG_SCALE 0x0000000F -#define AON_WDOGCFG_RSTEN 0x00000100 -#define AON_WDOGCFG_ZEROCMP 0x00000200 -#define AON_WDOGCFG_ENALWAYS 0x00001000 -#define AON_WDOGCFG_ENCOREAWAKE 0x00002000 -#define AON_WDOGCFG_CMPIP 0x10000000 - -#define AON_RTCCFG_SCALE 0x0000000F -#define AON_RTCCFG_ENALWAYS 0x00001000 -#define AON_RTCCFG_CMPIP 0x10000000 - -#define AON_WAKEUPCAUSE_RESET 0x00 -#define AON_WAKEUPCAUSE_RTC 0x01 -#define AON_WAKEUPCAUSE_DWAKEUP 0x02 -#define AON_WAKEUPCAUSE_AWAKEUP 0x03 - -#define AON_RESETCAUSE_POWERON 0x0000 -#define AON_RESETCAUSE_EXTERNAL 0x0100 -#define AON_RESETCAUSE_WATCHDOG 0x0200 - -#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF -#define AON_PMUCAUSE_RESETCAUSE 0xFF00 - -#endif /* _SIFIVE_AON_H */ diff --git a/include/sifive/devices/clic.h b/include/sifive/devices/clic.h deleted file mode 100644 index e8dc2df..0000000 --- a/include/sifive/devices/clic.h +++ /dev/null @@ -1,30 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_CLIC_H -#define _SIFIVE_CLIC_H - -#define CLIC_HART0 0x00800000 -#define CLIC_MSIP 0x0000 -#define CLIC_MSIP_size 0x4 -#define CLIC_MTIMECMP 0x4000 -#define CLIC_MTIMECMP_size 0x8 -#define CLIC_MTIME 0xBFF8 -#define CLIC_MTIME_size 0x8 - -#define CLIC_INTIP 0x000 -#define CLIC_INTIE 0x400 -#define CLIC_INTCFG 0x800 -#define CLIC_CFG 0xc00 - -// These interrupt IDs are consistent across old and new mtvec modes -#define SSIPID 1 -#define MSIPID 3 -#define STIPID 5 -#define MTIPID 7 -#define SEIPID 9 -#define MEIPID 11 -#define CSIPID 12 -#define LOCALINTIDBASE 16 - - -#endif /* _SIFIVE_CLIC_H */ diff --git a/include/sifive/devices/clint.h b/include/sifive/devices/clint.h deleted file mode 100644 index cd3e0c7..0000000 --- a/include/sifive/devices/clint.h +++ /dev/null @@ -1,14 +0,0 @@ -// See LICENSE for license details - -#ifndef _SIFIVE_CLINT_H -#define _SIFIVE_CLINT_H - - -#define CLINT_MSIP 0x0000 -#define CLINT_MSIP_size 0x4 -#define CLINT_MTIMECMP 0x4000 -#define CLINT_MTIMECMP_size 0x8 -#define CLINT_MTIME 0xBFF8 -#define CLINT_MTIME_size 0x8 - -#endif /* _SIFIVE_CLINT_H */ diff --git a/include/sifive/devices/gpio.h b/include/sifive/devices/gpio.h deleted file mode 100644 index f7f0acb..0000000 --- a/include/sifive/devices/gpio.h +++ /dev/null @@ -1,24 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_GPIO_H -#define _SIFIVE_GPIO_H - -#define GPIO_INPUT_VAL (0x00) -#define GPIO_INPUT_EN (0x04) -#define GPIO_OUTPUT_EN (0x08) -#define GPIO_OUTPUT_VAL (0x0C) -#define GPIO_PULLUP_EN (0x10) -#define GPIO_DRIVE (0x14) -#define GPIO_RISE_IE (0x18) -#define GPIO_RISE_IP (0x1C) -#define GPIO_FALL_IE (0x20) -#define GPIO_FALL_IP (0x24) -#define GPIO_HIGH_IE (0x28) -#define GPIO_HIGH_IP (0x2C) -#define GPIO_LOW_IE (0x30) -#define GPIO_LOW_IP (0x34) -#define GPIO_IOF_EN (0x38) -#define GPIO_IOF_SEL (0x3C) -#define GPIO_OUTPUT_XOR (0x40) - -#endif /* _SIFIVE_GPIO_H */ diff --git a/include/sifive/devices/otp.h b/include/sifive/devices/otp.h deleted file mode 100644 index 93833e2..0000000 --- a/include/sifive/devices/otp.h +++ /dev/null @@ -1,23 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_OTP_H -#define _SIFIVE_OTP_H - -/* Register offsets */ - -#define OTP_LOCK 0x00 -#define OTP_CK 0x04 -#define OTP_OE 0x08 -#define OTP_SEL 0x0C -#define OTP_WE 0x10 -#define OTP_MR 0x14 -#define OTP_MRR 0x18 -#define OTP_MPP 0x1C -#define OTP_VRREN 0x20 -#define OTP_VPPEN 0x24 -#define OTP_A 0x28 -#define OTP_D 0x2C -#define OTP_Q 0x30 -#define OTP_READ_TIMINGS 0x34 - -#endif diff --git a/include/sifive/devices/plic.h b/include/sifive/devices/plic.h deleted file mode 100644 index 9b5a3cf..0000000 --- a/include/sifive/devices/plic.h +++ /dev/null @@ -1,31 +0,0 @@ -// See LICENSE for license details. - -#ifndef PLIC_H -#define PLIC_H - -//#include - -// 32 bits per source -#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) -#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 -// 1 bit per source (1 address) -#define PLIC_PENDING_OFFSET _AC(0x1000,UL) -#define PLIC_PENDING_SHIFT_PER_SOURCE 0 - -//0x80 per target -#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) -#define PLIC_ENABLE_SHIFT_PER_TARGET 7 - - -#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) -#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) -#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 -#define PLIC_CLAIM_SHIFT_PER_TARGET 12 - -#define PLIC_MAX_SOURCE 1023 -#define PLIC_SOURCE_MASK 0x3FF - -#define PLIC_MAX_TARGET 15871 -#define PLIC_TARGET_MASK 0x3FFF - -#endif /* PLIC_H */ diff --git a/include/sifive/devices/prci.h b/include/sifive/devices/prci.h deleted file mode 100644 index 1a3de58..0000000 --- a/include/sifive/devices/prci.h +++ /dev/null @@ -1,56 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_PRCI_H -#define _SIFIVE_PRCI_H - -/* Register offsets */ - -#define PRCI_HFROSCCFG (0x0000) -#define PRCI_HFXOSCCFG (0x0004) -#define PRCI_PLLCFG (0x0008) -#define PRCI_PLLDIV (0x000C) -#define PRCI_PROCMONCFG (0x00F0) - -/* Fields */ -#define ROSC_DIV(x) (((x) & 0x2F) << 0 ) -#define ROSC_TRIM(x) (((x) & 0x1F) << 16) -#define ROSC_EN(x) (((x) & 0x1 ) << 30) -#define ROSC_RDY(x) (((x) & 0x1 ) << 31) - -#define XOSC_EN(x) (((x) & 0x1) << 30) -#define XOSC_RDY(x) (((x) & 0x1) << 31) - -#define PLL_R(x) (((x) & 0x7) << 0) -// single reserved bit for F LSB. -#define PLL_F(x) (((x) & 0x3F) << 4) -#define PLL_Q(x) (((x) & 0x3) << 10) -#define PLL_SEL(x) (((x) & 0x1) << 16) -#define PLL_REFSEL(x) (((x) & 0x1) << 17) -#define PLL_BYPASS(x) (((x) & 0x1) << 18) -#define PLL_LOCK(x) (((x) & 0x1) << 31) - -#define PLL_R_default 0x1 -#define PLL_F_default 0x1F -#define PLL_Q_default 0x3 - -#define PLL_REFSEL_HFROSC 0x0 -#define PLL_REFSEL_HFXOSC 0x1 - -#define PLL_SEL_HFROSC 0x0 -#define PLL_SEL_PLL 0x1 - -#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0) -#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8) - -#define PROCMON_DIV(x) (((x) & 0x1F) << 0) -#define PROCMON_TRIM(x) (((x) & 0x1F) << 8) -#define PROCMON_EN(x) (((x) & 0x1) << 16) -#define PROCMON_SEL(x) (((x) & 0x3) << 24) -#define PROCMON_NT_EN(x) (((x) & 0x1) << 28) - -#define PROCMON_SEL_HFCLK 0 -#define PROCMON_SEL_HFXOSCIN 1 -#define PROCMON_SEL_PLLOUTDIV 2 -#define PROCMON_SEL_PROCMON 3 - -#endif // _SIFIVE_PRCI_H diff --git a/include/sifive/devices/pwm.h b/include/sifive/devices/pwm.h deleted file mode 100644 index 067889a..0000000 --- a/include/sifive/devices/pwm.h +++ /dev/null @@ -1,37 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_PWM_H -#define _SIFIVE_PWM_H - -/* Register offsets */ - -#define PWM_CFG 0x00 -#define PWM_COUNT 0x08 -#define PWM_S 0x10 -#define PWM_CMP0 0x20 -#define PWM_CMP1 0x24 -#define PWM_CMP2 0x28 -#define PWM_CMP3 0x2C - -/* Constants */ - -#define PWM_CFG_SCALE 0x0000000F -#define PWM_CFG_STICKY 0x00000100 -#define PWM_CFG_ZEROCMP 0x00000200 -#define PWM_CFG_DEGLITCH 0x00000400 -#define PWM_CFG_ENALWAYS 0x00001000 -#define PWM_CFG_ONESHOT 0x00002000 -#define PWM_CFG_CMP0CENTER 0x00010000 -#define PWM_CFG_CMP1CENTER 0x00020000 -#define PWM_CFG_CMP2CENTER 0x00040000 -#define PWM_CFG_CMP3CENTER 0x00080000 -#define PWM_CFG_CMP0GANG 0x01000000 -#define PWM_CFG_CMP1GANG 0x02000000 -#define PWM_CFG_CMP2GANG 0x04000000 -#define PWM_CFG_CMP3GANG 0x08000000 -#define PWM_CFG_CMP0IP 0x10000000 -#define PWM_CFG_CMP1IP 0x20000000 -#define PWM_CFG_CMP2IP 0x40000000 -#define PWM_CFG_CMP3IP 0x80000000 - -#endif /* _SIFIVE_PWM_H */ diff --git a/include/sifive/devices/spi.h b/include/sifive/devices/spi.h deleted file mode 100644 index 80ef345..0000000 --- a/include/sifive/devices/spi.h +++ /dev/null @@ -1,80 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_SPI_H -#define _SIFIVE_SPI_H - -/* Register offsets */ - -#define SPI_REG_SCKDIV 0x00 -#define SPI_REG_SCKMODE 0x04 -#define SPI_REG_CSID 0x10 -#define SPI_REG_CSDEF 0x14 -#define SPI_REG_CSMODE 0x18 - -#define SPI_REG_DCSSCK 0x28 -#define SPI_REG_DSCKCS 0x2a -#define SPI_REG_DINTERCS 0x2c -#define SPI_REG_DINTERXFR 0x2e - -#define SPI_REG_FMT 0x40 -#define SPI_REG_TXFIFO 0x48 -#define SPI_REG_RXFIFO 0x4c -#define SPI_REG_TXCTRL 0x50 -#define SPI_REG_RXCTRL 0x54 - -#define SPI_REG_FCTRL 0x60 -#define SPI_REG_FFMT 0x64 - -#define SPI_REG_IE 0x70 -#define SPI_REG_IP 0x74 - -/* Fields */ - -#define SPI_SCK_PHA 0x1 -#define SPI_SCK_POL 0x2 - -#define SPI_FMT_PROTO(x) ((x) & 0x3) -#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) -#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) -#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) - -/* TXCTRL register */ -#define SPI_TXWM(x) ((x) & 0xffff) -/* RXCTRL register */ -#define SPI_RXWM(x) ((x) & 0xffff) - -#define SPI_IP_TXWM 0x1 -#define SPI_IP_RXWM 0x2 - -#define SPI_FCTRL_EN 0x1 - -#define SPI_INSN_CMD_EN 0x1 -#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) -#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) -#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) -#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) -#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) -#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) -#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) - -#define SPI_TXFIFO_FULL (1 << 31) -#define SPI_RXFIFO_EMPTY (1 << 31) - -/* Values */ - -#define SPI_CSMODE_AUTO 0 -#define SPI_CSMODE_HOLD 2 -#define SPI_CSMODE_OFF 3 - -#define SPI_DIR_RX 0 -#define SPI_DIR_TX 1 - -#define SPI_PROTO_S 0 -#define SPI_PROTO_D 1 -#define SPI_PROTO_Q 2 - -#define SPI_ENDIAN_MSB 0 -#define SPI_ENDIAN_LSB 1 - - -#endif /* _SIFIVE_SPI_H */ diff --git a/include/sifive/devices/uart.h b/include/sifive/devices/uart.h deleted file mode 100644 index 71bea6f..0000000 --- a/include/sifive/devices/uart.h +++ /dev/null @@ -1,27 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_UART_H -#define _SIFIVE_UART_H - -/* Register offsets */ -#define UART_REG_TXFIFO 0x00 -#define UART_REG_RXFIFO 0x04 -#define UART_REG_TXCTRL 0x08 -#define UART_REG_RXCTRL 0x0c -#define UART_REG_IE 0x10 -#define UART_REG_IP 0x14 -#define UART_REG_DIV 0x18 - -/* TXCTRL register */ -#define UART_TXEN 0x1 -#define UART_TXWM(x) (((x) & 0xffff) << 16) - -/* RXCTRL register */ -#define UART_RXEN 0x1 -#define UART_RXWM(x) (((x) & 0xffff) << 16) - -/* IP register */ -#define UART_IP_TXWM 0x1 -#define UART_IP_RXWM 0x2 - -#endif /* _SIFIVE_UART_H */ diff --git a/include/sifive/smp.h b/include/sifive/smp.h deleted file mode 100644 index 8e34388..0000000 --- a/include/sifive/smp.h +++ /dev/null @@ -1,65 +0,0 @@ -#ifndef SIFIVE_SMP -#define SIFIVE_SMP - -// The maximum number of HARTs this code supports -#ifndef MAX_HARTS -#define MAX_HARTS 32 -#endif -#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4) - -// The hart that non-SMP tests should run on -#ifndef NONSMP_HART -#define NONSMP_HART 0 -#endif - -/* If your test cannot handle multiple-threads, use this: - * smp_disable(reg1) - */ -#define smp_disable(reg1, reg2) \ - csrr reg1, mhartid ;\ - li reg2, NONSMP_HART ;\ - beq reg1, reg2, hart0_entry ;\ -42: ;\ - wfi ;\ - j 42b ;\ -hart0_entry: - -/* If your test needs to temporarily block multiple-threads, do this: - * smp_pause(reg1, reg2) - * ... single-threaded work ... - * smp_resume(reg1, reg2) - * ... multi-threaded work ... - */ - -#define smp_pause(reg1, reg2) \ - li reg2, 0x8 ;\ - csrw mie, reg2 ;\ - csrr reg2, mhartid ;\ - bnez reg2, 42f - -#define smp_resume(reg1, reg2) \ - li reg1, CLINT_CTRL_ADDR ;\ -41: ;\ - li reg2, 1 ;\ - sw reg2, 0(reg1) ;\ - addi reg1, reg1, 4 ;\ - li reg2, CLINT_END_HART_IPI ;\ - blt reg1, reg2, 41b ;\ -42: ;\ - wfi ;\ - csrr reg2, mip ;\ - andi reg2, reg2, 0x8 ;\ - beqz reg2, 42b ;\ - li reg1, CLINT_CTRL_ADDR ;\ - csrr reg2, mhartid ;\ - slli reg2, reg2, 2 ;\ - add reg2, reg2, reg1 ;\ - sw zero, 0(reg2) ;\ -41: ;\ - lw reg2, 0(reg1) ;\ - bnez reg2, 41b ;\ - addi reg1, reg1, 4 ;\ - li reg2, CLINT_END_HART_IPI ;\ - blt reg1, reg2, 41b - -#endif