diff --git a/env/ehrenberg/platform.h b/env/ehrenberg/platform.h index 711bac3..269e086 100644 --- a/env/ehrenberg/platform.h +++ b/env/ehrenberg/platform.h @@ -17,7 +17,6 @@ #include "ehrenberg/devices/uart.h" #include "ehrenberg/devices/timer.h" #include "ehrenberg/devices/aclint.h" -#include "ehrenberg/devices/interrupt.h" #include "ehrenberg/devices/qspi.h" #define PERIPH(TYPE, ADDR) ((volatile TYPE*) (ADDR)) diff --git a/include/ehrenberg/devices/aclint.h b/include/ehrenberg/devices/aclint.h index d8061de..e9337b9 100644 --- a/include/ehrenberg/devices/aclint.h +++ b/include/ehrenberg/devices/aclint.h @@ -1,10 +1,9 @@ -#ifndef _BSP_ACLINT_H -#define _BSP_ACLINT_H +#ifndef _DEVICES_ACLINT_H +#define _DEVICES_ACLINT_H #include -#include "gen/AClintModule.h" +#include "gen/aclint.h" -#define aclint_t apb3aclint_t static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value){ set_aclint_mtime_hi(reg, (uint32_t)(value >> 32)); @@ -26,4 +25,4 @@ static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg){ return value; } -#endif /* _BSP_ACLINT_H */ +#endif /* _DEVICES_ACLINT_H */ diff --git a/include/ehrenberg/devices/gen/AClintModule.h b/include/ehrenberg/devices/gen/AClintModule.h deleted file mode 100644 index 60ff808..0000000 --- a/include/ehrenberg/devices/gen/AClintModule.h +++ /dev/null @@ -1,63 +0,0 @@ -/* -* Copyright (c) 2023 - 2024 MINRES Technologies GmbH -* -* SPDX-License-Identifier: Apache-2.0 -* -* Generated at 2024-04-22 11:11:53 UTC -* by peakrdl_mnrs version 1.2.2 -*/ - -#ifndef _BSP_ACLINTMODULE_H -#define _BSP_ACLINTMODULE_H - -#include - -typedef struct __attribute((__packed__)) { - volatile uint32_t MSIP0; - volatile uint32_t MTIMECMP0LO; - volatile uint32_t MTIMECMP0HI; - volatile uint32_t MTIME_LO; - volatile uint32_t MTIME_HI; -}aclintmodule_t; - -static inline uint32_t get_aclintmodule_msip(volatile aclintmodule_t *reg){ - return (reg->MSIP0 >> 0) & 0x1; -} - -static inline void set_aclintmodule_msip(volatile aclintmodule_t *reg, uint8_t value){ - reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); -} - -static inline uint32_t get_aclintmodule_mtimecmp_lo(volatile aclintmodule_t *reg){ - return (reg->MTIMECMP0LO >> 0) & 0xffffffff; -} - -static inline void set_aclintmodule_mtimecmp_lo(volatile aclintmodule_t *reg, uint32_t value){ - reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0); -} - -static inline uint32_t get_aclintmodule_mtimecmp_hi(volatile aclintmodule_t *reg){ - return (reg->MTIMECMP0HI >> 0) & 0xffffffff; -} - -static inline void set_aclintmodule_mtimecmp_hi(volatile aclintmodule_t *reg, uint32_t value){ - reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0); -} - -static inline uint32_t get_aclintmodule_mtime_ho(volatile aclintmodule_t *reg){ - return (reg->MTIME_LO >> 0) & 0xffffffff; -} - -static inline void set_aclintmodule_mtime_ho(volatile aclintmodule_t *reg, uint32_t value){ - reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0); -} - -static inline uint32_t get_aclintmodule_mtime_hi(volatile aclintmodule_t *reg){ - return (reg->MTIME_HI >> 0) & 0xffffffff; -} - -static inline void set_aclintmodule_mtime_hi(volatile aclintmodule_t *reg, uint32_t value){ - reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0); -} - -#endif /* _BSP_ACLINTMODULE_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/Apb3IrqCtrl.h b/include/ehrenberg/devices/gen/Apb3IrqCtrl.h deleted file mode 100644 index a832395..0000000 --- a/include/ehrenberg/devices/gen/Apb3IrqCtrl.h +++ /dev/null @@ -1,32 +0,0 @@ -/* -* Copyright (c) 2023 - 2024 MINRES Technologies GmbH -* -* SPDX-License-Identifier: Apache-2.0 -* -* Generated at 2024-02-19 14:24:37 UTC -* by peakrdl_mnrs version 1.2.2 -*/ - -#ifndef _BSP_APB3IRQCTRL_H -#define _BSP_APB3IRQCTRL_H - -#include - -typedef struct __attribute((__packed__)) { - volatile uint32_t PENDINGSREG; - volatile uint32_t MASKSREG; -}apb3irqctrl_t; - -inline uint32_t get_irq_pendingsReg(volatile apb3irqctrl_t *reg){ - return (reg->PENDINGSREG >> 0) & 0xf; -} -inline void set_irq_pendingsReg(volatile apb3irqctrl_t *reg, uint8_t value){ - reg->PENDINGSREG = (reg->PENDINGSREG & ~(0xfU << 0)) | (value << 0); -} -inline uint32_t get_irq_masksReg(volatile apb3irqctrl_t *reg){ - return (reg->MASKSREG >> 0) & 0xf; -} -inline void set_irq_masksReg(volatile apb3irqctrl_t *reg, uint8_t value){ - reg->MASKSREG = (reg->MASKSREG & ~(0xfU << 0)) | (value << 0); -} -#endif /* _BSP_APB3IRQCTRL_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/Apb3SpiModule.h b/include/ehrenberg/devices/gen/Apb3SpiModule.h deleted file mode 100644 index 922e04c..0000000 --- a/include/ehrenberg/devices/gen/Apb3SpiModule.h +++ /dev/null @@ -1,241 +0,0 @@ -/* -* Copyright (c) 2023 - 2024 MINRES Technologies GmbH -* -* SPDX-License-Identifier: Apache-2.0 -* -* Generated at 2024-04-22 11:11:53 UTC -* by peakrdl_mnrs version 1.2.2 -*/ - -#ifndef _BSP_APB3SPIMODULE_H -#define _BSP_APB3SPIMODULE_H - -#include - -typedef struct __attribute((__packed__)) { - volatile uint32_t DATA; - volatile uint32_t STATUS; - volatile uint32_t CONFIG; - volatile uint32_t INTR; - volatile uint32_t SCLK_CONFIG; - volatile uint32_t SSGEN_SETUP; - volatile uint32_t SSGEN_HOLD; - volatile uint32_t SSGEN_DISABLE; - volatile uint32_t SSGEN_ACTIVE_HIGH; - volatile uint32_t XIP_ENABLE; - volatile uint32_t XIP_CONFIG; - volatile uint32_t XIP_MODE; - volatile uint32_t XIP_WRITE; - volatile uint32_t XIP_READ_WRITE; - volatile uint32_t XIP_READ; -}apb3spimodule_t; - -static inline void set_apb3spimodule_data(volatile apb3spimodule_t *reg, uint8_t value){ - reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_write(volatile apb3spimodule_t *reg){ - return (reg->DATA >> 8) & 0x1; -} - -static inline void set_apb3spimodule_write(volatile apb3spimodule_t *reg, uint8_t value){ - reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8); -} - -static inline uint32_t get_apb3spimodule_read(volatile apb3spimodule_t *reg){ - return (reg->DATA >> 9) & 0x1; -} - -static inline void set_apb3spimodule_read(volatile apb3spimodule_t *reg, uint8_t value){ - reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9); -} - -static inline uint32_t get_apb3spimodule_kind(volatile apb3spimodule_t *reg){ - return (reg->DATA >> 11) & 0x1; -} - -static inline void set_apb3spimodule_kind(volatile apb3spimodule_t *reg, uint8_t value){ - reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11); -} - -static inline uint32_t get_apb3spimodule_rx_data_invalid(volatile apb3spimodule_t *reg){ - return (reg->DATA >> 31) & 0x1; -} - -static inline uint32_t get_apb3spimodule_tx_free(volatile apb3spimodule_t *reg){ - return (reg->STATUS >> 0) & 0x3f; -} - -static inline uint32_t get_apb3spimodule_rx_avail(volatile apb3spimodule_t *reg){ - return (reg->STATUS >> 16) & 0x3f; -} - -static inline uint32_t get_apb3spimodule_kind(volatile apb3spimodule_t *reg){ - return (reg->CONFIG >> 0) & 0x3; -} - -static inline void set_apb3spimodule_kind(volatile apb3spimodule_t *reg, uint8_t value){ - reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_mode(volatile apb3spimodule_t *reg){ - return (reg->CONFIG >> 4) & 0x3; -} - -static inline void set_apb3spimodule_mode(volatile apb3spimodule_t *reg, uint8_t value){ - reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4); -} - -static inline uint32_t get_apb3spimodule_tx_ie(volatile apb3spimodule_t *reg){ - return (reg->INTR >> 0) & 0x1; -} - -static inline void set_apb3spimodule_tx_ie(volatile apb3spimodule_t *reg, uint8_t value){ - reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_rx_ie(volatile apb3spimodule_t *reg){ - return (reg->INTR >> 1) & 0x1; -} - -static inline void set_apb3spimodule_rx_ie(volatile apb3spimodule_t *reg, uint8_t value){ - reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1); -} - -static inline uint32_t get_apb3spimodule_tx_ip(volatile apb3spimodule_t *reg){ - return (reg->INTR >> 8) & 0x1; -} - -static inline uint32_t get_apb3spimodule_rx_ip(volatile apb3spimodule_t *reg){ - return (reg->INTR >> 9) & 0x1; -} - -static inline uint32_t get_apb3spimodule_tx_active(volatile apb3spimodule_t *reg){ - return (reg->INTR >> 16) & 0x1; -} - -static inline uint32_t get_apb3spimodule_clk_divider(volatile apb3spimodule_t *reg){ - return (reg->SCLK_CONFIG >> 0) & 0xfff; -} - -static inline void set_apb3spimodule_clk_divider(volatile apb3spimodule_t *reg, uint16_t value){ - reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_setup_cycles(volatile apb3spimodule_t *reg){ - return (reg->SSGEN_SETUP >> 0) & 0xfff; -} - -static inline void set_apb3spimodule_setup_cycles(volatile apb3spimodule_t *reg, uint16_t value){ - reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_hold_cycles(volatile apb3spimodule_t *reg){ - return (reg->SSGEN_HOLD >> 0) & 0xfff; -} - -static inline void set_apb3spimodule_hold_cycles(volatile apb3spimodule_t *reg, uint16_t value){ - reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_disable_cycles(volatile apb3spimodule_t *reg){ - return (reg->SSGEN_DISABLE >> 0) & 0xfff; -} - -static inline void set_apb3spimodule_disable_cycles(volatile apb3spimodule_t *reg, uint16_t value){ - reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_high_cycles(volatile apb3spimodule_t *reg){ - return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1; -} - -static inline void set_apb3spimodule_high_cycles(volatile apb3spimodule_t *reg, uint8_t value){ - reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_enable(volatile apb3spimodule_t *reg){ - return (reg->XIP_ENABLE >> 0) & 0x1; -} - -static inline void set_apb3spimodule_enable(volatile apb3spimodule_t *reg, uint8_t value){ - reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_instruction(volatile apb3spimodule_t *reg){ - return (reg->XIP_CONFIG >> 0) & 0xff; -} - -static inline void set_apb3spimodule_instruction(volatile apb3spimodule_t *reg, uint8_t value){ - reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_enable(volatile apb3spimodule_t *reg){ - return (reg->XIP_CONFIG >> 8) & 0x1; -} - -static inline void set_apb3spimodule_enable(volatile apb3spimodule_t *reg, uint8_t value){ - reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8); -} - -static inline uint32_t get_apb3spimodule_dummy_value(volatile apb3spimodule_t *reg){ - return (reg->XIP_CONFIG >> 16) & 0xff; -} - -static inline void set_apb3spimodule_dummy_value(volatile apb3spimodule_t *reg, uint8_t value){ - reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16); -} - -static inline uint32_t get_apb3spimodule_dummy_count(volatile apb3spimodule_t *reg){ - return (reg->XIP_CONFIG >> 24) & 0xf; -} - -static inline void set_apb3spimodule_dummy_count(volatile apb3spimodule_t *reg, uint8_t value){ - reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24); -} - -static inline uint32_t get_apb3spimodule_instruction(volatile apb3spimodule_t *reg){ - return (reg->XIP_MODE >> 0) & 0x3; -} - -static inline void set_apb3spimodule_instruction(volatile apb3spimodule_t *reg, uint8_t value){ - reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_address(volatile apb3spimodule_t *reg){ - return (reg->XIP_MODE >> 8) & 0x3; -} - -static inline void set_apb3spimodule_address(volatile apb3spimodule_t *reg, uint8_t value){ - reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8); -} - -static inline uint32_t get_apb3spimodule_dummy(volatile apb3spimodule_t *reg){ - return (reg->XIP_MODE >> 16) & 0x3; -} - -static inline void set_apb3spimodule_dummy(volatile apb3spimodule_t *reg, uint8_t value){ - reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16); -} - -static inline uint32_t get_apb3spimodule_payload(volatile apb3spimodule_t *reg){ - return (reg->XIP_MODE >> 24) & 0x3; -} - -static inline void set_apb3spimodule_payload(volatile apb3spimodule_t *reg, uint8_t value){ - reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24); -} - -static inline void set_apb3spimodule_data(volatile apb3spimodule_t *reg, uint8_t value){ - reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0); -} - -static inline void set_apb3spimodule_data(volatile apb3spimodule_t *reg, uint8_t value){ - reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0); -} - -static inline uint32_t get_apb3spimodule_data(volatile apb3spimodule_t *reg){ - return (reg->XIP_READ >> 0) & 0xff; -} - -#endif /* _BSP_APB3SPIMODULE_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/GpioModule.h b/include/ehrenberg/devices/gen/GpioModule.h deleted file mode 100644 index 8a5dbad..0000000 --- a/include/ehrenberg/devices/gen/GpioModule.h +++ /dev/null @@ -1,41 +0,0 @@ -/* -* Copyright (c) 2023 - 2024 MINRES Technologies GmbH -* -* SPDX-License-Identifier: Apache-2.0 -* -* Generated at 2024-04-22 11:11:53 UTC -* by peakrdl_mnrs version 1.2.2 -*/ - -#ifndef _BSP_GPIOMODULE_H -#define _BSP_GPIOMODULE_H - -#include - -typedef struct __attribute((__packed__)) { - volatile uint32_t VALUE; - volatile uint32_t WRITE; - volatile uint32_t WRITEENABLE; -}gpiomodule_t; - -static inline uint32_t get_gpiomodule_value(volatile gpiomodule_t *reg){ - return (reg->VALUE >> 0) & 0xffffffff; -} - -static inline uint32_t get_gpiomodule_write(volatile gpiomodule_t *reg){ - return (reg->WRITE >> 0) & 0xffffffff; -} - -static inline void set_gpiomodule_write(volatile gpiomodule_t *reg, uint32_t value){ - reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0); -} - -static inline uint32_t get_gpiomodule_writeEnable(volatile gpiomodule_t *reg){ - return (reg->WRITEENABLE >> 0) & 0xffffffff; -} - -static inline void set_gpiomodule_writeEnable(volatile gpiomodule_t *reg, uint32_t value){ - reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0); -} - -#endif /* _BSP_GPIOMODULE_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/I2SModule.h b/include/ehrenberg/devices/gen/I2SModule.h deleted file mode 100644 index 508d4e7..0000000 --- a/include/ehrenberg/devices/gen/I2SModule.h +++ /dev/null @@ -1,142 +0,0 @@ -/* -* Copyright (c) 2023 - 2024 MINRES Technologies GmbH -* -* SPDX-License-Identifier: Apache-2.0 -* -* Generated at 2024-04-22 11:11:53 UTC -* by peakrdl_mnrs version 1.2.2 -*/ - -#ifndef _BSP_I2SMODULE_H -#define _BSP_I2SMODULE_H - -#include - -typedef struct __attribute((__packed__)) { - volatile uint32_t LEFT_CH; - volatile uint32_t RIGHT_CH; - volatile uint32_t CONTROL; - volatile uint32_t STATUS; - volatile uint32_t I2S_CLOCK_CTRL; - volatile uint32_t PDM_CLOCK_CTRL; - volatile uint32_t IE; - volatile uint32_t IP; -}i2smodule_t; - -static inline uint32_t get_i2smodule_data_left(volatile i2smodule_t *reg){ - return (reg->LEFT_CH >> 0) & 0xffffffff; -} - -static inline void set_i2smodule_data_left(volatile i2smodule_t *reg, uint32_t value){ - reg->LEFT_CH = (reg->LEFT_CH & ~(0xffffffffU << 0)) | (value << 0); -} - -static inline uint32_t get_i2smodule_data_right(volatile i2smodule_t *reg){ - return (reg->RIGHT_CH >> 0) & 0xffffffff; -} - -static inline void set_i2smodule_data_right(volatile i2smodule_t *reg, uint32_t value){ - reg->RIGHT_CH = (reg->RIGHT_CH & ~(0xffffffffU << 0)) | (value << 0); -} - -static inline uint32_t get_i2smodule_mode(volatile i2smodule_t *reg){ - return (reg->CONTROL >> 0) & 0x3; -} - -static inline void set_i2smodule_mode(volatile i2smodule_t *reg, uint8_t value){ - reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0); -} - -static inline uint32_t get_i2smodule_disable_left(volatile i2smodule_t *reg){ - return (reg->CONTROL >> 2) & 0x1; -} - -static inline void set_i2smodule_disable_left(volatile i2smodule_t *reg, uint8_t value){ - reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2); -} - -static inline uint32_t get_i2smodule_disable_right(volatile i2smodule_t *reg){ - return (reg->CONTROL >> 3) & 0x1; -} - -static inline void set_i2smodule_disable_right(volatile i2smodule_t *reg, uint8_t value){ - reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3); -} - -static inline uint32_t get_i2smodule_active_clock(volatile i2smodule_t *reg){ - return (reg->CONTROL >> 4) & 0x1; -} - -static inline void set_i2smodule_active_clock(volatile i2smodule_t *reg, uint8_t value){ - reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4); -} - -static inline uint32_t get_i2smodule_pdm_scale(volatile i2smodule_t *reg){ - return (reg->CONTROL >> 5) & 0x7; -} - -static inline void set_i2smodule_pdm_scale(volatile i2smodule_t *reg, uint8_t value){ - reg->CONTROL = (reg->CONTROL & ~(0x7U << 5)) | (value << 5); -} - -static inline uint32_t get_i2smodule_enabled(volatile i2smodule_t *reg){ - return (reg->STATUS >> 0) & 0x1; -} - -static inline uint32_t get_i2smodule_active(volatile i2smodule_t *reg){ - return (reg->STATUS >> 1) & 0x1; -} - -static inline uint32_t get_i2smodule_left_avail(volatile i2smodule_t *reg){ - return (reg->STATUS >> 2) & 0x1; -} - -static inline uint32_t get_i2smodule_right_avail(volatile i2smodule_t *reg){ - return (reg->STATUS >> 3) & 0x1; -} - -static inline uint32_t get_i2smodule_both_avail(volatile i2smodule_t *reg){ - return (reg->STATUS >> 4) & 0x1; -} - -static inline uint32_t get_i2smodule_divider(volatile i2smodule_t *reg){ - return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff; -} - -static inline void set_i2smodule_divider(volatile i2smodule_t *reg, uint32_t value){ - reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0); -} - -static inline uint32_t get_i2smodule_divider(volatile i2smodule_t *reg){ - return (reg->PDM_CLOCK_CTRL >> 0) & 0x3ff; -} - -static inline void set_i2smodule_divider(volatile i2smodule_t *reg, uint16_t value){ - reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0x3ffU << 0)) | (value << 0); -} - -static inline uint32_t get_i2smodule_en_left_sample_avail(volatile i2smodule_t *reg){ - return (reg->IE >> 0) & 0x1; -} - -static inline void set_i2smodule_en_left_sample_avail(volatile i2smodule_t *reg, uint8_t value){ - reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); -} - -static inline uint32_t get_i2smodule_en_right_sample_avail(volatile i2smodule_t *reg){ - return (reg->IE >> 1) & 0x1; -} - -static inline void set_i2smodule_en_right_sample_avail(volatile i2smodule_t *reg, uint8_t value){ - reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); -} - -static inline uint32_t get_i2smodule_left_sample_avail(volatile i2smodule_t *reg){ - return (reg->IP >> 0) & 0x1; -} - -static inline uint32_t get_i2smodule_right_sample_avail(volatile i2smodule_t *reg){ - return (reg->IP >> 1) & 0x1; -} - -#endif /* _BSP_I2SMODULE_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/SimpleDmaModule.h b/include/ehrenberg/devices/gen/SimpleDmaModule.h deleted file mode 100644 index 8272f15..0000000 --- a/include/ehrenberg/devices/gen/SimpleDmaModule.h +++ /dev/null @@ -1,120 +0,0 @@ -/* -* Copyright (c) 2023 - 2024 MINRES Technologies GmbH -* -* SPDX-License-Identifier: Apache-2.0 -* -* Generated at 2024-04-22 11:11:53 UTC -* by peakrdl_mnrs version 1.2.2 -*/ - -#ifndef _BSP_SIMPLEDMAMODULE_H -#define _BSP_SIMPLEDMAMODULE_H - -#include - -typedef struct __attribute((__packed__)) { - volatile uint32_t CONTROL; - volatile uint32_t STATUS; - volatile uint32_t EVENT_SEL; - volatile uint32_t IE; - volatile uint32_t IP; - volatile uint32_t TRANSFER; - volatile uint32_t SRC_START_ADDR; - volatile uint32_t SRC_STRIDE; - volatile uint32_t DST_START_ADDR; - volatile uint32_t DST_STRIDE; -}simpledmamodule_t; - -static inline uint32_t get_simpledmamodule_enable_transfer(volatile simpledmamodule_t *reg){ - return (reg->CONTROL >> 0) & 0x1; -} - -static inline void set_simpledmamodule_enable_transfer(volatile simpledmamodule_t *reg, uint8_t value){ - reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0); -} - -static inline uint32_t get_simpledmamodule_busy(volatile simpledmamodule_t *reg){ - return (reg->STATUS >> 0) & 0x1; -} - -static inline uint32_t get_simpledmamodule_event_sel(volatile simpledmamodule_t *reg){ - return (reg->EVENT_SEL >> 0) & 0x3; -} - -static inline void set_simpledmamodule_event_sel(volatile simpledmamodule_t *reg, uint8_t value){ - reg->EVENT_SEL = (reg->EVENT_SEL & ~(0x3U << 0)) | (value << 0); -} - -static inline uint32_t get_simpledmamodule_en_seg_transfer_done(volatile simpledmamodule_t *reg){ - return (reg->IE >> 0) & 0x1; -} - -static inline void set_simpledmamodule_en_seg_transfer_done(volatile simpledmamodule_t *reg, uint8_t value){ - reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); -} - -static inline uint32_t get_simpledmamodule_en_transfer_done(volatile simpledmamodule_t *reg){ - return (reg->IE >> 1) & 0x1; -} - -static inline void set_simpledmamodule_en_transfer_done(volatile simpledmamodule_t *reg, uint8_t value){ - reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); -} - -static inline uint32_t get_simpledmamodule_seg_transfer_done(volatile simpledmamodule_t *reg){ - return (reg->IP >> 0) & 0x1; -} - -static inline uint32_t get_simpledmamodule_transfer_done(volatile simpledmamodule_t *reg){ - return (reg->IP >> 1) & 0x1; -} - -static inline uint32_t get_simpledmamodule_length(volatile simpledmamodule_t *reg){ - return (reg->TRANSFER >> 0) & 0x3ff; -} - -static inline void set_simpledmamodule_length(volatile simpledmamodule_t *reg, uint16_t value){ - reg->TRANSFER = (reg->TRANSFER & ~(0x3ffU << 0)) | (value << 0); -} - -static inline uint32_t get_simpledmamodule_count(volatile simpledmamodule_t *reg){ - return (reg->TRANSFER >> 12) & 0xfffff; -} - -static inline void set_simpledmamodule_count(volatile simpledmamodule_t *reg, uint32_t value){ - reg->TRANSFER = (reg->TRANSFER & ~(0xfffffU << 12)) | (value << 12); -} - -static inline uint32_t get_simpledmamodule_src_start_addr(volatile simpledmamodule_t *reg){ - return (reg->SRC_START_ADDR >> 0) & 0xffffffff; -} - -static inline void set_simpledmamodule_src_start_addr(volatile simpledmamodule_t *reg, uint32_t value){ - reg->SRC_START_ADDR = (reg->SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); -} - -static inline uint32_t get_simpledmamodule_src_stride(volatile simpledmamodule_t *reg){ - return (reg->SRC_STRIDE >> 0) & 0xffffffff; -} - -static inline void set_simpledmamodule_src_stride(volatile simpledmamodule_t *reg, uint32_t value){ - reg->SRC_STRIDE = (reg->SRC_STRIDE & ~(0xffffffffU << 0)) | (value << 0); -} - -static inline uint32_t get_simpledmamodule_dst_start_addr(volatile simpledmamodule_t *reg){ - return (reg->DST_START_ADDR >> 0) & 0xffffffff; -} - -static inline void set_simpledmamodule_dst_start_addr(volatile simpledmamodule_t *reg, uint32_t value){ - reg->DST_START_ADDR = (reg->DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); -} - -static inline uint32_t get_simpledmamodule_dst_stride(volatile simpledmamodule_t *reg){ - return (reg->DST_STRIDE >> 0) & 0xffffffff; -} - -static inline void set_simpledmamodule_dst_stride(volatile simpledmamodule_t *reg, uint32_t value){ - reg->DST_STRIDE = (reg->DST_STRIDE & ~(0xffffffffU << 0)) | (value << 0); -} - -#endif /* _BSP_SIMPLEDMAMODULE_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/TimerModule.h b/include/ehrenberg/devices/gen/TimerModule.h deleted file mode 100644 index 3637002..0000000 --- a/include/ehrenberg/devices/gen/TimerModule.h +++ /dev/null @@ -1,89 +0,0 @@ -/* -* Copyright (c) 2023 - 2024 MINRES Technologies GmbH -* -* SPDX-License-Identifier: Apache-2.0 -* -* Generated at 2024-04-22 11:11:53 UTC -* by peakrdl_mnrs version 1.2.2 -*/ - -#ifndef _BSP_TIMERMODULE_H -#define _BSP_TIMERMODULE_H - -#include - -typedef struct __attribute((__packed__)) { - volatile uint32_t PRESCALER; - volatile uint32_t T0_CTRL; - volatile uint32_t T0_OVERFLOW; - volatile uint32_t T0_VALUE; - volatile uint32_t T1_CTRL; - volatile uint32_t T1_OVERFLOW; - volatile uint32_t T1_VALUE; -}timermodule_t; - -static inline uint32_t get_timermodule_limit(volatile timermodule_t *reg){ - return (reg->PRESCALER >> 0) & 0xffff; -} - -static inline void set_timermodule_limit(volatile timermodule_t *reg, uint16_t value){ - reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0); -} - -static inline uint32_t get_timermodule_enable(volatile timermodule_t *reg){ - return (reg->T0_CTRL >> 0) & 0x7; -} - -static inline void set_timermodule_enable(volatile timermodule_t *reg, uint8_t value){ - reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0); -} - -static inline uint32_t get_timermodule_clear(volatile timermodule_t *reg){ - return (reg->T0_CTRL >> 3) & 0x3; -} - -static inline void set_timermodule_clear(volatile timermodule_t *reg, uint8_t value){ - reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3); -} - -static inline uint32_t get_timermodule_limit(volatile timermodule_t *reg){ - return (reg->T0_OVERFLOW >> 0) & 0xffffffff; -} - -static inline void set_timermodule_limit(volatile timermodule_t *reg, uint32_t value){ - reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0); -} - -static inline uint32_t get_timermodule_value(volatile timermodule_t *reg){ - return (reg->T0_VALUE >> 0) & 0xffffffff; -} - -static inline uint32_t get_timermodule_enable(volatile timermodule_t *reg){ - return (reg->T1_CTRL >> 0) & 0x7; -} - -static inline void set_timermodule_enable(volatile timermodule_t *reg, uint8_t value){ - reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0); -} - -static inline uint32_t get_timermodule_clear(volatile timermodule_t *reg){ - return (reg->T1_CTRL >> 3) & 0x3; -} - -static inline void set_timermodule_clear(volatile timermodule_t *reg, uint8_t value){ - reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3); -} - -static inline uint32_t get_timermodule_limit(volatile timermodule_t *reg){ - return (reg->T1_OVERFLOW >> 0) & 0xffffffff; -} - -static inline void set_timermodule_limit(volatile timermodule_t *reg, uint32_t value){ - reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0); -} - -static inline uint32_t get_timermodule_value(volatile timermodule_t *reg){ - return (reg->T1_VALUE >> 0) & 0xffffffff; -} - -#endif /* _BSP_TIMERMODULE_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/UartModule.h b/include/ehrenberg/devices/gen/UartModule.h deleted file mode 100644 index 551ac35..0000000 --- a/include/ehrenberg/devices/gen/UartModule.h +++ /dev/null @@ -1,143 +0,0 @@ -/* -* Copyright (c) 2023 - 2024 MINRES Technologies GmbH -* -* SPDX-License-Identifier: Apache-2.0 -* -* Generated at 2024-04-22 11:11:53 UTC -* by peakrdl_mnrs version 1.2.2 -*/ - -#ifndef _BSP_UARTMODULE_H -#define _BSP_UARTMODULE_H - -#include - -typedef struct __attribute((__packed__)) { - volatile uint32_t RX_TX_REG; - volatile uint32_t INT_CTRL_REG; - volatile uint32_t CLK_DIVIDER_REG; - volatile uint32_t FRAME_CONFIG_REG; - volatile uint32_t STATUS_REG; -}uartmodule_t; - -static inline uint32_t get_uartmodule_data(volatile uartmodule_t *reg){ - return (reg->RX_TX_REG >> 0) & 0xff; -} - -static inline void set_uartmodule_data(volatile uartmodule_t *reg, uint8_t value){ - reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0); -} - -static inline uint32_t get_uartmodule_rx_avail(volatile uartmodule_t *reg){ - return (reg->RX_TX_REG >> 14) & 0x1; -} - -static inline uint32_t get_uartmodule_tx_free(volatile uartmodule_t *reg){ - return (reg->RX_TX_REG >> 15) & 0x1; -} - -static inline uint32_t get_uartmodule_write_intr_enable(volatile uartmodule_t *reg){ - return (reg->INT_CTRL_REG >> 0) & 0x1; -} - -static inline void set_uartmodule_write_intr_enable(volatile uartmodule_t *reg, uint8_t value){ - reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0); -} - -static inline uint32_t get_uartmodule_read_intr_enable(volatile uartmodule_t *reg){ - return (reg->INT_CTRL_REG >> 1) & 0x1; -} - -static inline void set_uartmodule_read_intr_enable(volatile uartmodule_t *reg, uint8_t value){ - reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1); -} - -static inline uint32_t get_uartmodule_break_intr_enable(volatile uartmodule_t *reg){ - return (reg->INT_CTRL_REG >> 2) & 0x1; -} - -static inline void set_uartmodule_break_intr_enable(volatile uartmodule_t *reg, uint8_t value){ - reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2); -} - -static inline uint32_t get_uartmodule_write_intr_pend(volatile uartmodule_t *reg){ - return (reg->INT_CTRL_REG >> 8) & 0x1; -} - -static inline uint32_t get_uartmodule_read_intr_pend(volatile uartmodule_t *reg){ - return (reg->INT_CTRL_REG >> 9) & 0x1; -} - -static inline uint32_t get_uartmodule_break_intr_pend(volatile uartmodule_t *reg){ - return (reg->INT_CTRL_REG >> 10) & 0x1; -} - -static inline uint32_t get_uartmodule_clock_divider(volatile uartmodule_t *reg){ - return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; -} - -static inline void set_uartmodule_clock_divider(volatile uartmodule_t *reg, uint32_t value){ - reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0); -} - -static inline uint32_t get_uartmodule_data_lenght(volatile uartmodule_t *reg){ - return (reg->FRAME_CONFIG_REG >> 0) & 0x7; -} - -static inline void set_uartmodule_data_lenght(volatile uartmodule_t *reg, uint8_t value){ - reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0); -} - -static inline uint32_t get_uartmodule_parity(volatile uartmodule_t *reg){ - return (reg->FRAME_CONFIG_REG >> 3) & 0x3; -} - -static inline void set_uartmodule_parity(volatile uartmodule_t *reg, uint8_t value){ - reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3); -} - -static inline uint32_t get_uartmodule_stop_bit(volatile uartmodule_t *reg){ - return (reg->FRAME_CONFIG_REG >> 5) & 0x1; -} - -static inline void set_uartmodule_stop_bit(volatile uartmodule_t *reg, uint8_t value){ - reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5); -} - -static inline uint32_t get_uartmodule_read_error(volatile uartmodule_t *reg){ - return (reg->STATUS_REG >> 0) & 0x1; -} - -static inline uint32_t get_uartmodule_stall(volatile uartmodule_t *reg){ - return (reg->STATUS_REG >> 1) & 0x1; -} - -static inline uint32_t get_uartmodule_break_line(volatile uartmodule_t *reg){ - return (reg->STATUS_REG >> 8) & 0x1; -} - -static inline uint32_t get_uartmodule_break_detected(volatile uartmodule_t *reg){ - return (reg->STATUS_REG >> 9) & 0x1; -} - -static inline void set_uartmodule_break_detected(volatile uartmodule_t *reg, uint8_t value){ - reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9); -} - -static inline uint32_t get_uartmodule_set_break(volatile uartmodule_t *reg){ - return (reg->STATUS_REG >> 10) & 0x1; -} - -static inline void set_uartmodule_set_break(volatile uartmodule_t *reg, uint8_t value){ - reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10); -} - -static inline uint32_t get_uartmodule_clear_break(volatile uartmodule_t *reg){ - return (reg->STATUS_REG >> 11) & 0x1; -} - -static inline void set_uartmodule_clear_break(volatile uartmodule_t *reg, uint8_t value){ - reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11); -} - -#endif /* _BSP_UARTMODULE_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/aclint.h b/include/ehrenberg/devices/gen/aclint.h new file mode 100644 index 0000000..3aadd05 --- /dev/null +++ b/include/ehrenberg/devices/gen/aclint.h @@ -0,0 +1,85 @@ +/* +* Copyright (c) 2023 - 2024 MINRES Technologies GmbH +* +* SPDX-License-Identifier: Apache-2.0 +* +* Generated at 2024-05-30 18:25:57 UTC +* by peakrdl_mnrs version 1.2.5 +*/ + +#ifndef _BSP_ACLINT_H +#define _BSP_ACLINT_H + +#include + +typedef struct __attribute((__packed__)) { + volatile uint32_t MSIP0; + uint8_t fill0[16380]; + volatile uint32_t MTIMECMP0LO; + volatile uint32_t MTIMECMP0HI; + uint8_t fill1[32752]; + volatile uint32_t MTIME_LO; + volatile uint32_t MTIME_HI; +}aclint_t; + +#define ACLINT_MSIP0_OFFS 0 +#define ACLINT_MSIP0_MASK 0x1 +#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS) + +#define ACLINT_MTIMECMP0LO_OFFS 0 +#define ACLINT_MTIMECMP0LO_MASK 0xffffffff +#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS) + +#define ACLINT_MTIMECMP0HI_OFFS 0 +#define ACLINT_MTIMECMP0HI_MASK 0xffffffff +#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS) + +#define ACLINT_MTIME_LO_OFFS 0 +#define ACLINT_MTIME_LO_MASK 0xffffffff +#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS) + +#define ACLINT_MTIME_HI_OFFS 0 +#define ACLINT_MTIME_HI_MASK 0xffffffff +#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS) + +//ACLINT_MSIP0 +inline uint32_t get_aclint_msip0(volatile aclint_t* reg){ + return (reg->MSIP0 >> 0) & 0x1; +} +inline void set_aclint_msip0(volatile aclint_t* reg, uint8_t value){ + reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); +} + +//ACLINT_MTIMECMP0LO +inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg){ + return (reg->MTIMECMP0LO >> 0) & 0xffffffff; +} +inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value){ + reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0); +} + +//ACLINT_MTIMECMP0HI +inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg){ + return (reg->MTIMECMP0HI >> 0) & 0xffffffff; +} +inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value){ + reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0); +} + +//ACLINT_MTIME_LO +inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg){ + return (reg->MTIME_LO >> 0) & 0xffffffff; +} +inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value){ + reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0); +} + +//ACLINT_MTIME_HI +inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg){ + return (reg->MTIME_HI >> 0) & 0xffffffff; +} +inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value){ + reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0); +} + +#endif /* _BSP_ACLINT_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/apb3spi.h b/include/ehrenberg/devices/gen/apb3spi.h new file mode 100644 index 0000000..78861c4 --- /dev/null +++ b/include/ehrenberg/devices/gen/apb3spi.h @@ -0,0 +1,382 @@ +/* +* Copyright (c) 2023 - 2024 MINRES Technologies GmbH +* +* SPDX-License-Identifier: Apache-2.0 +* +* Generated at 2024-05-30 18:25:57 UTC +* by peakrdl_mnrs version 1.2.5 +*/ + +#ifndef _BSP_APB3SPI_H +#define _BSP_APB3SPI_H + +#include + +typedef struct __attribute((__packed__)) { + volatile uint32_t DATA; + volatile uint32_t STATUS; + volatile uint32_t CONFIG; + volatile uint32_t INTR; + uint8_t fill0[16]; + volatile uint32_t SCLK_CONFIG; + volatile uint32_t SSGEN_SETUP; + volatile uint32_t SSGEN_HOLD; + volatile uint32_t SSGEN_DISABLE; + volatile uint32_t SSGEN_ACTIVE_HIGH; + uint8_t fill1[12]; + volatile uint32_t XIP_ENABLE; + volatile uint32_t XIP_CONFIG; + volatile uint32_t XIP_MODE; + uint8_t fill2[4]; + volatile uint32_t XIP_WRITE; + volatile uint32_t XIP_READ_WRITE; + volatile uint32_t XIP_READ; +}apb3spi_t; + +#define APB3SPI_DATA_DATA_OFFS 0 +#define APB3SPI_DATA_DATA_MASK 0xff +#define APB3SPI_DATA_DATA(V) ((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS) + +#define APB3SPI_DATA_WRITE_OFFS 8 +#define APB3SPI_DATA_WRITE_MASK 0x1 +#define APB3SPI_DATA_WRITE(V) ((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS) + +#define APB3SPI_DATA_READ_OFFS 9 +#define APB3SPI_DATA_READ_MASK 0x1 +#define APB3SPI_DATA_READ(V) ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS) + +#define APB3SPI_DATA_KIND_OFFS 11 +#define APB3SPI_DATA_KIND_MASK 0x1 +#define APB3SPI_DATA_KIND(V) ((V & APB3SPI_DATA_KIND_MASK) << APB3SPI_DATA_KIND_OFFS) + +#define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31 +#define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1 +#define APB3SPI_DATA_RX_DATA_INVALID(V) ((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS) + +#define APB3SPI_STATUS_TX_FREE_OFFS 0 +#define APB3SPI_STATUS_TX_FREE_MASK 0x3f +#define APB3SPI_STATUS_TX_FREE(V) ((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS) + +#define APB3SPI_STATUS_RX_AVAIL_OFFS 16 +#define APB3SPI_STATUS_RX_AVAIL_MASK 0x3f +#define APB3SPI_STATUS_RX_AVAIL(V) ((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS) + +#define APB3SPI_CONFIG_KIND_OFFS 0 +#define APB3SPI_CONFIG_KIND_MASK 0x3 +#define APB3SPI_CONFIG_KIND(V) ((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS) + +#define APB3SPI_CONFIG_MODE_OFFS 4 +#define APB3SPI_CONFIG_MODE_MASK 0x3 +#define APB3SPI_CONFIG_MODE(V) ((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS) + +#define APB3SPI_INTR_TX_IE_OFFS 0 +#define APB3SPI_INTR_TX_IE_MASK 0x1 +#define APB3SPI_INTR_TX_IE(V) ((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS) + +#define APB3SPI_INTR_RX_IE_OFFS 1 +#define APB3SPI_INTR_RX_IE_MASK 0x1 +#define APB3SPI_INTR_RX_IE(V) ((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS) + +#define APB3SPI_INTR_TX_IP_OFFS 8 +#define APB3SPI_INTR_TX_IP_MASK 0x1 +#define APB3SPI_INTR_TX_IP(V) ((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS) + +#define APB3SPI_INTR_RX_IP_OFFS 9 +#define APB3SPI_INTR_RX_IP_MASK 0x1 +#define APB3SPI_INTR_RX_IP(V) ((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS) + +#define APB3SPI_INTR_TX_ACTIVE_OFFS 16 +#define APB3SPI_INTR_TX_ACTIVE_MASK 0x1 +#define APB3SPI_INTR_TX_ACTIVE(V) ((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS) + +#define APB3SPI_SCLK_CONFIG_OFFS 0 +#define APB3SPI_SCLK_CONFIG_MASK 0xfff +#define APB3SPI_SCLK_CONFIG(V) ((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS) + +#define APB3SPI_SSGEN_SETUP_OFFS 0 +#define APB3SPI_SSGEN_SETUP_MASK 0xfff +#define APB3SPI_SSGEN_SETUP(V) ((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS) + +#define APB3SPI_SSGEN_HOLD_OFFS 0 +#define APB3SPI_SSGEN_HOLD_MASK 0xfff +#define APB3SPI_SSGEN_HOLD(V) ((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS) + +#define APB3SPI_SSGEN_DISABLE_OFFS 0 +#define APB3SPI_SSGEN_DISABLE_MASK 0xfff +#define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS) + +#define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0 +#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1 +#define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS) + +#define APB3SPI_XIP_ENABLE_OFFS 0 +#define APB3SPI_XIP_ENABLE_MASK 0x1 +#define APB3SPI_XIP_ENABLE(V) ((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS) + +#define APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS 0 +#define APB3SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff +#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) ((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) << APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS) + +#define APB3SPI_XIP_CONFIG_ENABLE_OFFS 8 +#define APB3SPI_XIP_CONFIG_ENABLE_MASK 0x1 +#define APB3SPI_XIP_CONFIG_ENABLE(V) ((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS) + +#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16 +#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff +#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS) + +#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24 +#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf +#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS) + +#define APB3SPI_XIP_MODE_INSTRUCTION_OFFS 0 +#define APB3SPI_XIP_MODE_INSTRUCTION_MASK 0x3 +#define APB3SPI_XIP_MODE_INSTRUCTION(V) ((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS) + +#define APB3SPI_XIP_MODE_ADDRESS_OFFS 8 +#define APB3SPI_XIP_MODE_ADDRESS_MASK 0x3 +#define APB3SPI_XIP_MODE_ADDRESS(V) ((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS) + +#define APB3SPI_XIP_MODE_DUMMY_OFFS 16 +#define APB3SPI_XIP_MODE_DUMMY_MASK 0x3 +#define APB3SPI_XIP_MODE_DUMMY(V) ((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS) + +#define APB3SPI_XIP_MODE_PAYLOAD_OFFS 24 +#define APB3SPI_XIP_MODE_PAYLOAD_MASK 0x3 +#define APB3SPI_XIP_MODE_PAYLOAD(V) ((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS) + +#define APB3SPI_XIP_WRITE_OFFS 0 +#define APB3SPI_XIP_WRITE_MASK 0xff +#define APB3SPI_XIP_WRITE(V) ((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS) + +#define APB3SPI_XIP_READ_WRITE_OFFS 0 +#define APB3SPI_XIP_READ_WRITE_MASK 0xff +#define APB3SPI_XIP_READ_WRITE(V) ((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS) + +#define APB3SPI_XIP_READ_OFFS 0 +#define APB3SPI_XIP_READ_MASK 0xff +#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS) + +//APB3SPI_DATA +inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg){ + return reg->DATA; +} +inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value){ + reg->DATA = value; +} +inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value){ + reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); +} +inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg){ + return (reg->DATA >> 8) & 0x1; +} +inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value){ + reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8); +} +inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg){ + return (reg->DATA >> 9) & 0x1; +} +inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value){ + reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9); +} +inline uint32_t get_apb3spi_data_kind(volatile apb3spi_t* reg){ + return (reg->DATA >> 11) & 0x1; +} +inline void set_apb3spi_data_kind(volatile apb3spi_t* reg, uint8_t value){ + reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11); +} +inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg){ + return (reg->DATA >> 31) & 0x1; +} + +//APB3SPI_STATUS +inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg){ + return reg->STATUS; +} +inline void set_apb3spi_status(volatile apb3spi_t* reg, uint32_t value){ + reg->STATUS = value; +} +inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg){ + return (reg->STATUS >> 0) & 0x3f; +} +inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg){ + return (reg->STATUS >> 16) & 0x3f; +} + +//APB3SPI_CONFIG +inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg){ + return reg->CONFIG; +} +inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value){ + reg->CONFIG = value; +} +inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg){ + return (reg->CONFIG >> 0) & 0x3; +} +inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value){ + reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0); +} +inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg){ + return (reg->CONFIG >> 4) & 0x3; +} +inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value){ + reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4); +} + +//APB3SPI_INTR +inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg){ + return reg->INTR; +} +inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value){ + reg->INTR = value; +} +inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg){ + return (reg->INTR >> 0) & 0x1; +} +inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value){ + reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); +} +inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg){ + return (reg->INTR >> 1) & 0x1; +} +inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value){ + reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1); +} +inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg){ + return (reg->INTR >> 8) & 0x1; +} +inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg){ + return (reg->INTR >> 9) & 0x1; +} +inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg){ + return (reg->INTR >> 16) & 0x1; +} + +//APB3SPI_SCLK_CONFIG +inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg){ + return (reg->SCLK_CONFIG >> 0) & 0xfff; +} +inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint16_t value){ + reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0); +} + +//APB3SPI_SSGEN_SETUP +inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg){ + return (reg->SSGEN_SETUP >> 0) & 0xfff; +} +inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint16_t value){ + reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0); +} + +//APB3SPI_SSGEN_HOLD +inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg){ + return (reg->SSGEN_HOLD >> 0) & 0xfff; +} +inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint16_t value){ + reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0); +} + +//APB3SPI_SSGEN_DISABLE +inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg){ + return (reg->SSGEN_DISABLE >> 0) & 0xfff; +} +inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint16_t value){ + reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0); +} + +//APB3SPI_SSGEN_ACTIVE_HIGH +inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg){ + return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1; +} +inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint8_t value){ + reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0); +} + +//APB3SPI_XIP_ENABLE +inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg){ + return (reg->XIP_ENABLE >> 0) & 0x1; +} +inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint8_t value){ + reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0); +} + +//APB3SPI_XIP_CONFIG +inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg){ + return reg->XIP_CONFIG; +} +inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value){ + reg->XIP_CONFIG = value; +} +inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg){ + return (reg->XIP_CONFIG >> 0) & 0xff; +} +inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value){ + reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0); +} +inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg){ + return (reg->XIP_CONFIG >> 8) & 0x1; +} +inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value){ + reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8); +} +inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg){ + return (reg->XIP_CONFIG >> 16) & 0xff; +} +inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value){ + reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16); +} +inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg){ + return (reg->XIP_CONFIG >> 24) & 0xf; +} +inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value){ + reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24); +} + +//APB3SPI_XIP_MODE +inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg){ + return reg->XIP_MODE; +} +inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value){ + reg->XIP_MODE = value; +} +inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg){ + return (reg->XIP_MODE >> 0) & 0x3; +} +inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value){ + reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0); +} +inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg){ + return (reg->XIP_MODE >> 8) & 0x3; +} +inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value){ + reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8); +} +inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg){ + return (reg->XIP_MODE >> 16) & 0x3; +} +inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value){ + reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16); +} +inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg){ + return (reg->XIP_MODE >> 24) & 0x3; +} +inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value){ + reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24); +} + +//APB3SPI_XIP_WRITE +inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint8_t value){ + reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0); +} + +//APB3SPI_XIP_READ_WRITE +inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint8_t value){ + reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0); +} + +//APB3SPI_XIP_READ +inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg){ + return (reg->XIP_READ >> 0) & 0xff; +} + +#endif /* _BSP_APB3SPI_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/camera.h b/include/ehrenberg/devices/gen/camera.h new file mode 100644 index 0000000..8de7227 --- /dev/null +++ b/include/ehrenberg/devices/gen/camera.h @@ -0,0 +1,145 @@ +/* +* Copyright (c) 2023 - 2024 MINRES Technologies GmbH +* +* SPDX-License-Identifier: Apache-2.0 +* +* Generated at 2024-05-30 18:25:57 UTC +* by peakrdl_mnrs version 1.2.5 +*/ + +#ifndef _BSP_CAMERA_H +#define _BSP_CAMERA_H + +#include + +typedef struct __attribute((__packed__)) { + volatile uint32_t PIXEL; + volatile uint32_t CONTROL; + volatile uint32_t STATUS; + volatile uint32_t CAMERA_CLOCK_CTRL; + volatile uint32_t IE; + volatile uint32_t IP; +}camera_t; + +#define CAMERA_PIXEL_OFFS 0 +#define CAMERA_PIXEL_MASK 0x7ff +#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS) + +#define CAMERA_CONTROL_OFFS 0 +#define CAMERA_CONTROL_MASK 0x1 +#define CAMERA_CONTROL(V) ((V & CAMERA_CONTROL_MASK) << CAMERA_CONTROL_OFFS) + +#define CAMERA_STATUS_ENABLED_OFFS 0 +#define CAMERA_STATUS_ENABLED_MASK 0x1 +#define CAMERA_STATUS_ENABLED(V) ((V & CAMERA_STATUS_ENABLED_MASK) << CAMERA_STATUS_ENABLED_OFFS) + +#define CAMERA_STATUS_ACTIVE_OFFS 1 +#define CAMERA_STATUS_ACTIVE_MASK 0x1 +#define CAMERA_STATUS_ACTIVE(V) ((V & CAMERA_STATUS_ACTIVE_MASK) << CAMERA_STATUS_ACTIVE_OFFS) + +#define CAMERA_STATUS_PIXEL_AVAIL_OFFS 2 +#define CAMERA_STATUS_PIXEL_AVAIL_MASK 0x1 +#define CAMERA_STATUS_PIXEL_AVAIL(V) ((V & CAMERA_STATUS_PIXEL_AVAIL_MASK) << CAMERA_STATUS_PIXEL_AVAIL_OFFS) + +#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0 +#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfffff +#define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS) + +#define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0 +#define CAMERA_IE_EN_PIXEL_AVAIL_MASK 0x1 +#define CAMERA_IE_EN_PIXEL_AVAIL(V) ((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS) + +#define CAMERA_IE_EN_FRAME_FINISHED_OFFS 1 +#define CAMERA_IE_EN_FRAME_FINISHED_MASK 0x1 +#define CAMERA_IE_EN_FRAME_FINISHED(V) ((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS) + +#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS 0 +#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK 0x1 +#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) ((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) << CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS) + +#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS 1 +#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1 +#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS) + +//CAMERA_PIXEL +inline uint32_t get_camera_pixel(volatile camera_t* reg){ + return (reg->PIXEL >> 0) & 0x7ff; +} +inline void set_camera_pixel(volatile camera_t* reg, uint16_t value){ + reg->PIXEL = (reg->PIXEL & ~(0x7ffU << 0)) | (value << 0); +} + +//CAMERA_CONTROL +inline uint32_t get_camera_control(volatile camera_t* reg){ + return (reg->CONTROL >> 0) & 0x1; +} +inline void set_camera_control(volatile camera_t* reg, uint8_t value){ + reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0); +} + +//CAMERA_STATUS +inline uint32_t get_camera_status(volatile camera_t* reg){ + return reg->STATUS; +} +inline void set_camera_status(volatile camera_t* reg, uint32_t value){ + reg->STATUS = value; +} +inline uint32_t get_camera_status_enabled(volatile camera_t* reg){ + return (reg->STATUS >> 0) & 0x1; +} +inline uint32_t get_camera_status_active(volatile camera_t* reg){ + return (reg->STATUS >> 1) & 0x1; +} +inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){ + return (reg->STATUS >> 2) & 0x1; +} + +//CAMERA_CAMERA_CLOCK_CTRL +inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg){ + return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfffff; +} +inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value){ + reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0); +} + +//CAMERA_IE +inline uint32_t get_camera_ie(volatile camera_t* reg){ + return reg->IE; +} +inline void set_camera_ie(volatile camera_t* reg, uint32_t value){ + reg->IE = value; +} +inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg){ + return (reg->IE >> 0) & 0x1; +} +inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value){ + reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); +} +inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg){ + return (reg->IE >> 1) & 0x1; +} +inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value){ + reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); +} + +//CAMERA_IP +inline uint32_t get_camera_ip(volatile camera_t* reg){ + return reg->IP; +} +inline void set_camera_ip(volatile camera_t* reg, uint32_t value){ + reg->IP = value; +} +inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg){ + return (reg->IP >> 0) & 0x1; +} +inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value){ + reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0); +} +inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg){ + return (reg->IP >> 1) & 0x1; +} +inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value){ + reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1); +} + +#endif /* _BSP_CAMERA_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/gpio.h b/include/ehrenberg/devices/gen/gpio.h new file mode 100644 index 0000000..f19b466 --- /dev/null +++ b/include/ehrenberg/devices/gen/gpio.h @@ -0,0 +1,54 @@ +/* +* Copyright (c) 2023 - 2024 MINRES Technologies GmbH +* +* SPDX-License-Identifier: Apache-2.0 +* +* Generated at 2024-05-30 18:25:57 UTC +* by peakrdl_mnrs version 1.2.5 +*/ + +#ifndef _BSP_GPIO_H +#define _BSP_GPIO_H + +#include + +typedef struct __attribute((__packed__)) { + volatile uint32_t VALUE; + volatile uint32_t WRITE; + volatile uint32_t WRITEENABLE; +}gpio_t; + +#define GPIO_VALUE_OFFS 0 +#define GPIO_VALUE_MASK 0xffffffff +#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS) + +#define GPIO_WRITE_OFFS 0 +#define GPIO_WRITE_MASK 0xffffffff +#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS) + +#define GPIO_WRITEENABLE_OFFS 0 +#define GPIO_WRITEENABLE_MASK 0xffffffff +#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS) + +//GPIO_VALUE +inline uint32_t get_gpio_value(volatile gpio_t* reg){ + return (reg->VALUE >> 0) & 0xffffffff; +} + +//GPIO_WRITE +inline uint32_t get_gpio_write(volatile gpio_t* reg){ + return (reg->WRITE >> 0) & 0xffffffff; +} +inline void set_gpio_write(volatile gpio_t* reg, uint32_t value){ + reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0); +} + +//GPIO_WRITEENABLE +inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg){ + return (reg->WRITEENABLE >> 0) & 0xffffffff; +} +inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){ + reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0); +} + +#endif /* _BSP_GPIO_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/i2s.h b/include/ehrenberg/devices/gen/i2s.h new file mode 100644 index 0000000..7c5692b --- /dev/null +++ b/include/ehrenberg/devices/gen/i2s.h @@ -0,0 +1,225 @@ +/* +* Copyright (c) 2023 - 2024 MINRES Technologies GmbH +* +* SPDX-License-Identifier: Apache-2.0 +* +* Generated at 2024-05-30 18:25:57 UTC +* by peakrdl_mnrs version 1.2.5 +*/ + +#ifndef _BSP_I2S_H +#define _BSP_I2S_H + +#include + +typedef struct __attribute((__packed__)) { + volatile uint32_t LEFT_CH; + volatile uint32_t RIGHT_CH; + volatile uint32_t CONTROL; + volatile uint32_t STATUS; + volatile uint32_t I2S_CLOCK_CTRL; + volatile uint32_t PDM_CLOCK_CTRL; + volatile uint32_t IE; + volatile uint32_t IP; +}i2s_t; + +#define I2S_LEFT_CH_OFFS 0 +#define I2S_LEFT_CH_MASK 0xffffffff +#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS) + +#define I2S_RIGHT_CH_OFFS 0 +#define I2S_RIGHT_CH_MASK 0xffffffff +#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS) + +#define I2S_CONTROL_MODE_OFFS 0 +#define I2S_CONTROL_MODE_MASK 0x3 +#define I2S_CONTROL_MODE(V) ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS) + +#define I2S_CONTROL_DISABLE_LEFT_OFFS 2 +#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1 +#define I2S_CONTROL_DISABLE_LEFT(V) ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS) + +#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3 +#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1 +#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS) + +#define I2S_CONTROL_ACTIVE_CLOCK_OFFS 4 +#define I2S_CONTROL_ACTIVE_CLOCK_MASK 0x1 +#define I2S_CONTROL_ACTIVE_CLOCK(V) ((V & I2S_CONTROL_ACTIVE_CLOCK_MASK) << I2S_CONTROL_ACTIVE_CLOCK_OFFS) + +#define I2S_CONTROL_PDM_SCALE_OFFS 5 +#define I2S_CONTROL_PDM_SCALE_MASK 0x7 +#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS) + +#define I2S_STATUS_ENABLED_OFFS 0 +#define I2S_STATUS_ENABLED_MASK 0x1 +#define I2S_STATUS_ENABLED(V) ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS) + +#define I2S_STATUS_ACTIVE_OFFS 1 +#define I2S_STATUS_ACTIVE_MASK 0x1 +#define I2S_STATUS_ACTIVE(V) ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS) + +#define I2S_STATUS_LEFT_AVAIL_OFFS 2 +#define I2S_STATUS_LEFT_AVAIL_MASK 0x1 +#define I2S_STATUS_LEFT_AVAIL(V) ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS) + +#define I2S_STATUS_RIGHT_AVAIL_OFFS 3 +#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1 +#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS) + +#define I2S_STATUS_BOTH_AVAIL_OFFS 4 +#define I2S_STATUS_BOTH_AVAIL_MASK 0x1 +#define I2S_STATUS_BOTH_AVAIL(V) ((V & I2S_STATUS_BOTH_AVAIL_MASK) << I2S_STATUS_BOTH_AVAIL_OFFS) + +#define I2S_I2S_CLOCK_CTRL_OFFS 0 +#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff +#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS) + +#define I2S_PDM_CLOCK_CTRL_OFFS 0 +#define I2S_PDM_CLOCK_CTRL_MASK 0x3ff +#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS) + +#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0 +#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1 +#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS) + +#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1 +#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1 +#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS) + +#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0 +#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1 +#define I2S_IP_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS) + +#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1 +#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1 +#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS) + +//I2S_LEFT_CH +inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){ + return (reg->LEFT_CH >> 0) & 0xffffffff; +} +inline void set_i2s_left_ch(volatile i2s_t* reg, uint32_t value){ + reg->LEFT_CH = (reg->LEFT_CH & ~(0xffffffffU << 0)) | (value << 0); +} + +//I2S_RIGHT_CH +inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){ + return (reg->RIGHT_CH >> 0) & 0xffffffff; +} +inline void set_i2s_right_ch(volatile i2s_t* reg, uint32_t value){ + reg->RIGHT_CH = (reg->RIGHT_CH & ~(0xffffffffU << 0)) | (value << 0); +} + +//I2S_CONTROL +inline uint32_t get_i2s_control(volatile i2s_t* reg){ + return reg->CONTROL; +} +inline void set_i2s_control(volatile i2s_t* reg, uint32_t value){ + reg->CONTROL = value; +} +inline uint32_t get_i2s_control_mode(volatile i2s_t* reg){ + return (reg->CONTROL >> 0) & 0x3; +} +inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value){ + reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0); +} +inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg){ + return (reg->CONTROL >> 2) & 0x1; +} +inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value){ + reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2); +} +inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){ + return (reg->CONTROL >> 3) & 0x1; +} +inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){ + reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3); +} +inline uint32_t get_i2s_control_active_clock(volatile i2s_t* reg){ + return (reg->CONTROL >> 4) & 0x1; +} +inline void set_i2s_control_active_clock(volatile i2s_t* reg, uint8_t value){ + reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4); +} +inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){ + return (reg->CONTROL >> 5) & 0x7; +} +inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){ + reg->CONTROL = (reg->CONTROL & ~(0x7U << 5)) | (value << 5); +} + +//I2S_STATUS +inline uint32_t get_i2s_status(volatile i2s_t* reg){ + return reg->STATUS; +} +inline void set_i2s_status(volatile i2s_t* reg, uint32_t value){ + reg->STATUS = value; +} +inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){ + return (reg->STATUS >> 0) & 0x1; +} +inline uint32_t get_i2s_status_active(volatile i2s_t* reg){ + return (reg->STATUS >> 1) & 0x1; +} +inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){ + return (reg->STATUS >> 2) & 0x1; +} +inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){ + return (reg->STATUS >> 3) & 0x1; +} +inline uint32_t get_i2s_status_both_avail(volatile i2s_t* reg){ + return (reg->STATUS >> 4) & 0x1; +} + +//I2S_I2S_CLOCK_CTRL +inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){ + return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff; +} +inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){ + reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0); +} + +//I2S_PDM_CLOCK_CTRL +inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){ + return (reg->PDM_CLOCK_CTRL >> 0) & 0x3ff; +} +inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint16_t value){ + reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0x3ffU << 0)) | (value << 0); +} + +//I2S_IE +inline uint32_t get_i2s_ie(volatile i2s_t* reg){ + return reg->IE; +} +inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value){ + reg->IE = value; +} +inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg){ + return (reg->IE >> 0) & 0x1; +} +inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value){ + reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); +} +inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg){ + return (reg->IE >> 1) & 0x1; +} +inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value){ + reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); +} + +//I2S_IP +inline uint32_t get_i2s_ip(volatile i2s_t* reg){ + return reg->IP; +} +inline void set_i2s_ip(volatile i2s_t* reg, uint32_t value){ + reg->IP = value; +} +inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){ + return (reg->IP >> 0) & 0x1; +} +inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg){ + return (reg->IP >> 1) & 0x1; +} + +#endif /* _BSP_I2S_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/simpledma.h b/include/ehrenberg/devices/gen/simpledma.h new file mode 100644 index 0000000..df23a4b --- /dev/null +++ b/include/ehrenberg/devices/gen/simpledma.h @@ -0,0 +1,187 @@ +/* +* Copyright (c) 2023 - 2024 MINRES Technologies GmbH +* +* SPDX-License-Identifier: Apache-2.0 +* +* Generated at 2024-05-30 18:25:57 UTC +* by peakrdl_mnrs version 1.2.5 +*/ + +#ifndef _BSP_SIMPLEDMA_H +#define _BSP_SIMPLEDMA_H + +#include + +typedef struct __attribute((__packed__)) { + volatile uint32_t CONTROL; + volatile uint32_t STATUS; + volatile uint32_t EVENT_SEL; + volatile uint32_t IE; + volatile uint32_t IP; + volatile uint32_t TRANSFER; + volatile uint32_t SRC_START_ADDR; + volatile uint32_t SRC_STRIDE; + volatile uint32_t DST_START_ADDR; + volatile uint32_t DST_STRIDE; +}simpledma_t; + +#define SIMPLEDMA_CONTROL_OFFS 0 +#define SIMPLEDMA_CONTROL_MASK 0x1 +#define SIMPLEDMA_CONTROL(V) ((V & SIMPLEDMA_CONTROL_MASK) << SIMPLEDMA_CONTROL_OFFS) + +#define SIMPLEDMA_STATUS_OFFS 0 +#define SIMPLEDMA_STATUS_MASK 0x1 +#define SIMPLEDMA_STATUS(V) ((V & SIMPLEDMA_STATUS_MASK) << SIMPLEDMA_STATUS_OFFS) + +#define SIMPLEDMA_EVENT_SEL_OFFS 0 +#define SIMPLEDMA_EVENT_SEL_MASK 0x3 +#define SIMPLEDMA_EVENT_SEL(V) ((V & SIMPLEDMA_EVENT_SEL_MASK) << SIMPLEDMA_EVENT_SEL_OFFS) + +#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_OFFS 0 +#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_MASK 0x1 +#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_OFFS) + +#define SIMPLEDMA_IE_EN_TRANSFER_DONE_OFFS 1 +#define SIMPLEDMA_IE_EN_TRANSFER_DONE_MASK 0x1 +#define SIMPLEDMA_IE_EN_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_EN_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_EN_TRANSFER_DONE_OFFS) + +#define SIMPLEDMA_IP_SEG_TRANSFER_DONE_OFFS 0 +#define SIMPLEDMA_IP_SEG_TRANSFER_DONE_MASK 0x1 +#define SIMPLEDMA_IP_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_SEG_TRANSFER_DONE_OFFS) + +#define SIMPLEDMA_IP_TRANSFER_DONE_OFFS 1 +#define SIMPLEDMA_IP_TRANSFER_DONE_MASK 0x1 +#define SIMPLEDMA_IP_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_TRANSFER_DONE_OFFS) + +#define SIMPLEDMA_TRANSFER_LENGTH_OFFS 0 +#define SIMPLEDMA_TRANSFER_LENGTH_MASK 0x3ff +#define SIMPLEDMA_TRANSFER_LENGTH(V) ((V & SIMPLEDMA_TRANSFER_LENGTH_MASK) << SIMPLEDMA_TRANSFER_LENGTH_OFFS) + +#define SIMPLEDMA_TRANSFER_COUNT_OFFS 12 +#define SIMPLEDMA_TRANSFER_COUNT_MASK 0xfffff +#define SIMPLEDMA_TRANSFER_COUNT(V) ((V & SIMPLEDMA_TRANSFER_COUNT_MASK) << SIMPLEDMA_TRANSFER_COUNT_OFFS) + +#define SIMPLEDMA_SRC_START_ADDR_OFFS 0 +#define SIMPLEDMA_SRC_START_ADDR_MASK 0xffffffff +#define SIMPLEDMA_SRC_START_ADDR(V) ((V & SIMPLEDMA_SRC_START_ADDR_MASK) << SIMPLEDMA_SRC_START_ADDR_OFFS) + +#define SIMPLEDMA_SRC_STRIDE_OFFS 0 +#define SIMPLEDMA_SRC_STRIDE_MASK 0xffffffff +#define SIMPLEDMA_SRC_STRIDE(V) ((V & SIMPLEDMA_SRC_STRIDE_MASK) << SIMPLEDMA_SRC_STRIDE_OFFS) + +#define SIMPLEDMA_DST_START_ADDR_OFFS 0 +#define SIMPLEDMA_DST_START_ADDR_MASK 0xffffffff +#define SIMPLEDMA_DST_START_ADDR(V) ((V & SIMPLEDMA_DST_START_ADDR_MASK) << SIMPLEDMA_DST_START_ADDR_OFFS) + +#define SIMPLEDMA_DST_STRIDE_OFFS 0 +#define SIMPLEDMA_DST_STRIDE_MASK 0xffffffff +#define SIMPLEDMA_DST_STRIDE(V) ((V & SIMPLEDMA_DST_STRIDE_MASK) << SIMPLEDMA_DST_STRIDE_OFFS) + +//SIMPLEDMA_CONTROL +inline uint32_t get_simpledma_control(volatile simpledma_t* reg){ + return (reg->CONTROL >> 0) & 0x1; +} +inline void set_simpledma_control(volatile simpledma_t* reg, uint8_t value){ + reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0); +} + +//SIMPLEDMA_STATUS +inline uint32_t get_simpledma_status(volatile simpledma_t* reg){ + return (reg->STATUS >> 0) & 0x1; +} + +//SIMPLEDMA_EVENT_SEL +inline uint32_t get_simpledma_event_sel(volatile simpledma_t* reg){ + return (reg->EVENT_SEL >> 0) & 0x3; +} +inline void set_simpledma_event_sel(volatile simpledma_t* reg, uint8_t value){ + reg->EVENT_SEL = (reg->EVENT_SEL & ~(0x3U << 0)) | (value << 0); +} + +//SIMPLEDMA_IE +inline uint32_t get_simpledma_ie(volatile simpledma_t* reg){ + return reg->IE; +} +inline void set_simpledma_ie(volatile simpledma_t* reg, uint32_t value){ + reg->IE = value; +} +inline uint32_t get_simpledma_ie_en_seg_transfer_done(volatile simpledma_t* reg){ + return (reg->IE >> 0) & 0x1; +} +inline void set_simpledma_ie_en_seg_transfer_done(volatile simpledma_t* reg, uint8_t value){ + reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); +} +inline uint32_t get_simpledma_ie_en_transfer_done(volatile simpledma_t* reg){ + return (reg->IE >> 1) & 0x1; +} +inline void set_simpledma_ie_en_transfer_done(volatile simpledma_t* reg, uint8_t value){ + reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); +} + +//SIMPLEDMA_IP +inline uint32_t get_simpledma_ip(volatile simpledma_t* reg){ + return reg->IP; +} +inline void set_simpledma_ip(volatile simpledma_t* reg, uint32_t value){ + reg->IP = value; +} +inline uint32_t get_simpledma_ip_seg_transfer_done(volatile simpledma_t* reg){ + return (reg->IP >> 0) & 0x1; +} +inline uint32_t get_simpledma_ip_transfer_done(volatile simpledma_t* reg){ + return (reg->IP >> 1) & 0x1; +} + +//SIMPLEDMA_TRANSFER +inline uint32_t get_simpledma_transfer(volatile simpledma_t* reg){ + return reg->TRANSFER; +} +inline void set_simpledma_transfer(volatile simpledma_t* reg, uint32_t value){ + reg->TRANSFER = value; +} +inline uint32_t get_simpledma_transfer_length(volatile simpledma_t* reg){ + return (reg->TRANSFER >> 0) & 0x3ff; +} +inline void set_simpledma_transfer_length(volatile simpledma_t* reg, uint16_t value){ + reg->TRANSFER = (reg->TRANSFER & ~(0x3ffU << 0)) | (value << 0); +} +inline uint32_t get_simpledma_transfer_count(volatile simpledma_t* reg){ + return (reg->TRANSFER >> 12) & 0xfffff; +} +inline void set_simpledma_transfer_count(volatile simpledma_t* reg, uint32_t value){ + reg->TRANSFER = (reg->TRANSFER & ~(0xfffffU << 12)) | (value << 12); +} + +//SIMPLEDMA_SRC_START_ADDR +inline uint32_t get_simpledma_src_start_addr(volatile simpledma_t* reg){ + return (reg->SRC_START_ADDR >> 0) & 0xffffffff; +} +inline void set_simpledma_src_start_addr(volatile simpledma_t* reg, uint32_t value){ + reg->SRC_START_ADDR = (reg->SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); +} + +//SIMPLEDMA_SRC_STRIDE +inline uint32_t get_simpledma_src_stride(volatile simpledma_t* reg){ + return (reg->SRC_STRIDE >> 0) & 0xffffffff; +} +inline void set_simpledma_src_stride(volatile simpledma_t* reg, uint32_t value){ + reg->SRC_STRIDE = (reg->SRC_STRIDE & ~(0xffffffffU << 0)) | (value << 0); +} + +//SIMPLEDMA_DST_START_ADDR +inline uint32_t get_simpledma_dst_start_addr(volatile simpledma_t* reg){ + return (reg->DST_START_ADDR >> 0) & 0xffffffff; +} +inline void set_simpledma_dst_start_addr(volatile simpledma_t* reg, uint32_t value){ + reg->DST_START_ADDR = (reg->DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); +} + +//SIMPLEDMA_DST_STRIDE +inline uint32_t get_simpledma_dst_stride(volatile simpledma_t* reg){ + return (reg->DST_STRIDE >> 0) & 0xffffffff; +} +inline void set_simpledma_dst_stride(volatile simpledma_t* reg, uint32_t value){ + reg->DST_STRIDE = (reg->DST_STRIDE & ~(0xffffffffU << 0)) | (value << 0); +} + +#endif /* _BSP_SIMPLEDMA_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/timercounter.h b/include/ehrenberg/devices/gen/timercounter.h new file mode 100644 index 0000000..93df614 --- /dev/null +++ b/include/ehrenberg/devices/gen/timercounter.h @@ -0,0 +1,135 @@ +/* +* Copyright (c) 2023 - 2024 MINRES Technologies GmbH +* +* SPDX-License-Identifier: Apache-2.0 +* +* Generated at 2024-05-30 18:25:57 UTC +* by peakrdl_mnrs version 1.2.5 +*/ + +#ifndef _BSP_TIMERCOUNTER_H +#define _BSP_TIMERCOUNTER_H + +#include + +typedef struct __attribute((__packed__)) { + volatile uint32_t PRESCALER; + volatile uint32_t T0_CTRL; + volatile uint32_t T0_OVERFLOW; + volatile uint32_t T0_VALUE; + volatile uint32_t T1_CTRL; + volatile uint32_t T1_OVERFLOW; + volatile uint32_t T1_VALUE; +}timercounter_t; + +#define TIMERCOUNTER_PRESCALER_OFFS 0 +#define TIMERCOUNTER_PRESCALER_MASK 0xffff +#define TIMERCOUNTER_PRESCALER(V) ((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS) + +#define TIMERCOUNTER_T0_CTRL_ENABLE_OFFS 0 +#define TIMERCOUNTER_T0_CTRL_ENABLE_MASK 0x7 +#define TIMERCOUNTER_T0_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS) + +#define TIMERCOUNTER_T0_CTRL_CLEAR_OFFS 3 +#define TIMERCOUNTER_T0_CTRL_CLEAR_MASK 0x3 +#define TIMERCOUNTER_T0_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS) + +#define TIMERCOUNTER_T0_OVERFLOW_OFFS 0 +#define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff +#define TIMERCOUNTER_T0_OVERFLOW(V) ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS) + +#define TIMERCOUNTER_T0_VALUE_OFFS 0 +#define TIMERCOUNTER_T0_VALUE_MASK 0xffffffff +#define TIMERCOUNTER_T0_VALUE(V) ((V & TIMERCOUNTER_T0_VALUE_MASK) << TIMERCOUNTER_T0_VALUE_OFFS) + +#define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0 +#define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7 +#define TIMERCOUNTER_T1_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS) + +#define TIMERCOUNTER_T1_CTRL_CLEAR_OFFS 3 +#define TIMERCOUNTER_T1_CTRL_CLEAR_MASK 0x3 +#define TIMERCOUNTER_T1_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS) + +#define TIMERCOUNTER_T1_OVERFLOW_OFFS 0 +#define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff +#define TIMERCOUNTER_T1_OVERFLOW(V) ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS) + +#define TIMERCOUNTER_T1_VALUE_OFFS 0 +#define TIMERCOUNTER_T1_VALUE_MASK 0xffffffff +#define TIMERCOUNTER_T1_VALUE(V) ((V & TIMERCOUNTER_T1_VALUE_MASK) << TIMERCOUNTER_T1_VALUE_OFFS) + +//TIMERCOUNTER_PRESCALER +inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg){ + return (reg->PRESCALER >> 0) & 0xffff; +} +inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint16_t value){ + reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0); +} + +//TIMERCOUNTER_T0_CTRL +inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg){ + return reg->T0_CTRL; +} +inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value){ + reg->T0_CTRL = value; +} +inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg){ + return (reg->T0_CTRL >> 0) & 0x7; +} +inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value){ + reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0); +} +inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg){ + return (reg->T0_CTRL >> 3) & 0x3; +} +inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value){ + reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3); +} + +//TIMERCOUNTER_T0_OVERFLOW +inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg){ + return (reg->T0_OVERFLOW >> 0) & 0xffffffff; +} +inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value){ + reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0); +} + +//TIMERCOUNTER_T0_VALUE +inline uint32_t get_timercounter_t0_value(volatile timercounter_t* reg){ + return (reg->T0_VALUE >> 0) & 0xffffffff; +} + +//TIMERCOUNTER_T1_CTRL +inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg){ + return reg->T1_CTRL; +} +inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value){ + reg->T1_CTRL = value; +} +inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg){ + return (reg->T1_CTRL >> 0) & 0x7; +} +inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value){ + reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0); +} +inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg){ + return (reg->T1_CTRL >> 3) & 0x3; +} +inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value){ + reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3); +} + +//TIMERCOUNTER_T1_OVERFLOW +inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg){ + return (reg->T1_OVERFLOW >> 0) & 0xffffffff; +} +inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value){ + reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0); +} + +//TIMERCOUNTER_T1_VALUE +inline uint32_t get_timercounter_t1_value(volatile timercounter_t* reg){ + return (reg->T1_VALUE >> 0) & 0xffffffff; +} + +#endif /* _BSP_TIMERCOUNTER_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gen/uart.h b/include/ehrenberg/devices/gen/uart.h new file mode 100644 index 0000000..3cceca1 --- /dev/null +++ b/include/ehrenberg/devices/gen/uart.h @@ -0,0 +1,223 @@ +/* +* Copyright (c) 2023 - 2024 MINRES Technologies GmbH +* +* SPDX-License-Identifier: Apache-2.0 +* +* Generated at 2024-05-30 18:25:57 UTC +* by peakrdl_mnrs version 1.2.5 +*/ + +#ifndef _BSP_UART_H +#define _BSP_UART_H + +#include + +typedef struct __attribute((__packed__)) { + volatile uint32_t RX_TX_REG; + volatile uint32_t INT_CTRL_REG; + volatile uint32_t CLK_DIVIDER_REG; + volatile uint32_t FRAME_CONFIG_REG; + volatile uint32_t STATUS_REG; +}uart_t; + +#define UART_RX_TX_REG_DATA_OFFS 0 +#define UART_RX_TX_REG_DATA_MASK 0xff +#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS) + +#define UART_RX_TX_REG_RX_AVAIL_OFFS 14 +#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1 +#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS) + +#define UART_RX_TX_REG_TX_FREE_OFFS 15 +#define UART_RX_TX_REG_TX_FREE_MASK 0x1 +#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS) + +#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0 +#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1 +#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS) + +#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1 +#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1 +#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS) + +#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2 +#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1 +#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS) + +#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8 +#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1 +#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS) + +#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9 +#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1 +#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS) + +#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10 +#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1 +#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS) + +#define UART_CLK_DIVIDER_REG_OFFS 0 +#define UART_CLK_DIVIDER_REG_MASK 0xfffff +#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS) + +#define UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS 0 +#define UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK 0x7 +#define UART_FRAME_CONFIG_REG_DATA_LENGHT(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS) + +#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3 +#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3 +#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS) + +#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5 +#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1 +#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS) + +#define UART_STATUS_REG_READ_ERROR_OFFS 0 +#define UART_STATUS_REG_READ_ERROR_MASK 0x1 +#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS) + +#define UART_STATUS_REG_STALL_OFFS 1 +#define UART_STATUS_REG_STALL_MASK 0x1 +#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS) + +#define UART_STATUS_REG_BREAK_LINE_OFFS 8 +#define UART_STATUS_REG_BREAK_LINE_MASK 0x1 +#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS) + +#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9 +#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1 +#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS) + +#define UART_STATUS_REG_SET_BREAK_OFFS 10 +#define UART_STATUS_REG_SET_BREAK_MASK 0x1 +#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS) + +#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11 +#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1 +#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS) + +//UART_RX_TX_REG +inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg){ + return reg->RX_TX_REG; +} +inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value){ + reg->RX_TX_REG = value; +} +inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){ + return (reg->RX_TX_REG >> 0) & 0xff; +} +inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){ + reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0); +} +inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){ + return (reg->RX_TX_REG >> 14) & 0x1; +} +inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){ + return (reg->RX_TX_REG >> 15) & 0x1; +} + +//UART_INT_CTRL_REG +inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){ + return reg->INT_CTRL_REG; +} +inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value){ + reg->INT_CTRL_REG = value; +} +inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg){ + return (reg->INT_CTRL_REG >> 0) & 0x1; +} +inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value){ + reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0); +} +inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg){ + return (reg->INT_CTRL_REG >> 1) & 0x1; +} +inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value){ + reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1); +} +inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg){ + return (reg->INT_CTRL_REG >> 2) & 0x1; +} +inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value){ + reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2); +} +inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){ + return (reg->INT_CTRL_REG >> 8) & 0x1; +} +inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){ + return (reg->INT_CTRL_REG >> 9) & 0x1; +} +inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){ + return (reg->INT_CTRL_REG >> 10) & 0x1; +} + +//UART_CLK_DIVIDER_REG +inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){ + return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; +} +inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){ + reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0); +} + +//UART_FRAME_CONFIG_REG +inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){ + return reg->FRAME_CONFIG_REG; +} +inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){ + reg->FRAME_CONFIG_REG = value; +} +inline uint32_t get_uart_frame_config_reg_data_lenght(volatile uart_t* reg){ + return (reg->FRAME_CONFIG_REG >> 0) & 0x7; +} +inline void set_uart_frame_config_reg_data_lenght(volatile uart_t* reg, uint8_t value){ + reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0); +} +inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){ + return (reg->FRAME_CONFIG_REG >> 3) & 0x3; +} +inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value){ + reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3); +} +inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg){ + return (reg->FRAME_CONFIG_REG >> 5) & 0x1; +} +inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value){ + reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5); +} + +//UART_STATUS_REG +inline uint32_t get_uart_status_reg(volatile uart_t* reg){ + return reg->STATUS_REG; +} +inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){ + reg->STATUS_REG = value; +} +inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){ + return (reg->STATUS_REG >> 0) & 0x1; +} +inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){ + return (reg->STATUS_REG >> 1) & 0x1; +} +inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){ + return (reg->STATUS_REG >> 8) & 0x1; +} +inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){ + return (reg->STATUS_REG >> 9) & 0x1; +} +inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){ + reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9); +} +inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){ + return (reg->STATUS_REG >> 10) & 0x1; +} +inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){ + reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10); +} +inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){ + return (reg->STATUS_REG >> 11) & 0x1; +} +inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){ + reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11); +} + +#endif /* _BSP_UART_H */ \ No newline at end of file diff --git a/include/ehrenberg/devices/gpio.h b/include/ehrenberg/devices/gpio.h index 11a50c7..511843e 100644 --- a/include/ehrenberg/devices/gpio.h +++ b/include/ehrenberg/devices/gpio.h @@ -1,14 +1,12 @@ -#ifndef _BSP_GPIO_H -#define _BSP_GPIO_H +#ifndef _DEVICES_GPIO_H +#define _DEVICES_GPIO_H #include -#include "gen/GpioModule.h" - -#define gpio_t gpiomodule_t +#include "gen/gpio.h" inline void gpio_init(gpio_t* reg) { set_gpio_write(reg, 0); set_gpio_writeEnable(reg, 0); } -#endif /* _BSP_GPIO_H */ +#endif /* _DEVICES_GPIO_H */ diff --git a/include/ehrenberg/devices/qspi.h b/include/ehrenberg/devices/qspi.h index af1ade7..51e1779 100644 --- a/include/ehrenberg/devices/qspi.h +++ b/include/ehrenberg/devices/qspi.h @@ -2,9 +2,9 @@ #define _BSP_QSPI_H #include -#include "gen/Apb3SpiModule.h" +#include "gen/apb3spi.h" -#define qspi_t apb3spimodule_t +#define qspi_t apb3spi_t typedef struct { uint32_t cpol; uint32_t cpha; diff --git a/include/ehrenberg/devices/timer.h b/include/ehrenberg/devices/timer.h index 4c77087..5bb11eb 100644 --- a/include/ehrenberg/devices/timer.h +++ b/include/ehrenberg/devices/timer.h @@ -1,21 +1,19 @@ -#ifndef _BSP_TIMER_H -#define _BSP_TIMER_H +#ifndef _DEVICES_TIMER_H +#define _DEVICES_TIMER_H #include -#include "gen/TimerModule.h" +#include "gen/timercounter.h" -#define timer_t timermodule_t - -inline void prescaler_init(timer_t* reg, uint16_t value){ - set_timer_prescaler(reg, value); +inline void prescaler_init(timercounter_t* reg, uint16_t value){ + set_timercounter_prescaler(reg, value); } -inline void timer_t0__init(apb3timer_t *reg) { - set_timer_t0_overflow(reg, 0xffffffff); +inline void timer_t0__init(timercounter_t *reg){ + set_timercounter_t0_overflow(reg, 0xffffffff); } -inline void timer_t1__init(apb3timer_t *reg) { - set_timer_t1_overflow(reg, 0xffffffff); +inline void timer_t1__init(timercounter_t *reg){ + set_timercounter_t1_overflow(reg, 0xffffffff); } -#endif /* _BSP_TIMER_H */ +#endif /* _DEVICES_TIMER_H */ diff --git a/include/ehrenberg/devices/uart.h b/include/ehrenberg/devices/uart.h index 0a2e12b..bc49b69 100644 --- a/include/ehrenberg/devices/uart.h +++ b/include/ehrenberg/devices/uart.h @@ -1,10 +1,8 @@ -#ifndef _BSP_UART_H -#define _BSP_UART_H +#ifndef _DEVICES_UART_H +#define _DEVICES_UART_H #include -#include "gen/UartModule.h" - -#define uart_t uartmodule_t +#include "gen/uart.h" static inline uint32_t uart_get_tx_free(volatile uart_t *reg){ return (reg->STATUS_REG >> 16) & 0xFF; @@ -25,4 +23,4 @@ static inline inline uint8_t uart_read(volatile uart_t *reg){ return res; } -#endif /* _BSP_UART_H */ +#endif /* _DEVICES_UART_H */