MNRS-BM-BSP/include/ehrenberg/devices/gen/simpledma.h

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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
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* Generated at 2024-06-16 13:56:44 UTC
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* by peakrdl_mnrs version 1.2.5
*/
#ifndef _BSP_SIMPLEDMA_H
#define _BSP_SIMPLEDMA_H
#include <stdint.h>
typedef struct __attribute((__packed__)) {
volatile uint32_t CONTROL;
volatile uint32_t STATUS;
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volatile uint32_t EVENT;
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volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t TRANSFER;
volatile uint32_t SRC_START_ADDR;
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volatile uint32_t SRC_ADDR_INC;
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volatile uint32_t DST_START_ADDR;
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volatile uint32_t DST_ADDR_INC;
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}simpledma_t;
#define SIMPLEDMA_CONTROL_OFFS 0
#define SIMPLEDMA_CONTROL_MASK 0x1
#define SIMPLEDMA_CONTROL(V) ((V & SIMPLEDMA_CONTROL_MASK) << SIMPLEDMA_CONTROL_OFFS)
#define SIMPLEDMA_STATUS_OFFS 0
#define SIMPLEDMA_STATUS_MASK 0x1
#define SIMPLEDMA_STATUS(V) ((V & SIMPLEDMA_STATUS_MASK) << SIMPLEDMA_STATUS_OFFS)
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#define SIMPLEDMA_EVENT_SELECT_OFFS 0
#define SIMPLEDMA_EVENT_SELECT_MASK 0x1f
#define SIMPLEDMA_EVENT_SELECT(V) ((V & SIMPLEDMA_EVENT_SELECT_MASK) << SIMPLEDMA_EVENT_SELECT_OFFS)
#define SIMPLEDMA_EVENT_COMBINE_OFFS 31
#define SIMPLEDMA_EVENT_COMBINE_MASK 0x1
#define SIMPLEDMA_EVENT_COMBINE(V) ((V & SIMPLEDMA_EVENT_COMBINE_MASK) << SIMPLEDMA_EVENT_COMBINE_OFFS)
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#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_OFFS 0
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_EN_SEG_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_IE_EN_TRANSFER_DONE_OFFS 1
#define SIMPLEDMA_IE_EN_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IE_EN_TRANSFER_DONE(V) ((V & SIMPLEDMA_IE_EN_TRANSFER_DONE_MASK) << SIMPLEDMA_IE_EN_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE_OFFS 0
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IP_SEG_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_SEG_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_SEG_TRANSFER_DONE_OFFS)
#define SIMPLEDMA_IP_TRANSFER_DONE_OFFS 1
#define SIMPLEDMA_IP_TRANSFER_DONE_MASK 0x1
#define SIMPLEDMA_IP_TRANSFER_DONE(V) ((V & SIMPLEDMA_IP_TRANSFER_DONE_MASK) << SIMPLEDMA_IP_TRANSFER_DONE_OFFS)
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#define SIMPLEDMA_TRANSFER_WIDTH_OFFS 0
#define SIMPLEDMA_TRANSFER_WIDTH_MASK 0x3
#define SIMPLEDMA_TRANSFER_WIDTH(V) ((V & SIMPLEDMA_TRANSFER_WIDTH_MASK) << SIMPLEDMA_TRANSFER_WIDTH_OFFS)
#define SIMPLEDMA_TRANSFER_SEG_LENGTH_OFFS 2
#define SIMPLEDMA_TRANSFER_SEG_LENGTH_MASK 0x3ff
#define SIMPLEDMA_TRANSFER_SEG_LENGTH(V) ((V & SIMPLEDMA_TRANSFER_SEG_LENGTH_MASK) << SIMPLEDMA_TRANSFER_SEG_LENGTH_OFFS)
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#define SIMPLEDMA_TRANSFER_SEG_COUNT_OFFS 12
#define SIMPLEDMA_TRANSFER_SEG_COUNT_MASK 0xfffff
#define SIMPLEDMA_TRANSFER_SEG_COUNT(V) ((V & SIMPLEDMA_TRANSFER_SEG_COUNT_MASK) << SIMPLEDMA_TRANSFER_SEG_COUNT_OFFS)
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#define SIMPLEDMA_SRC_START_ADDR_OFFS 0
#define SIMPLEDMA_SRC_START_ADDR_MASK 0xffffffff
#define SIMPLEDMA_SRC_START_ADDR(V) ((V & SIMPLEDMA_SRC_START_ADDR_MASK) << SIMPLEDMA_SRC_START_ADDR_OFFS)
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#define SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_OFFS 0
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STEP(V) ((V & SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_MASK) << SIMPLEDMA_SRC_ADDR_INC_SRC_STEP_OFFS)
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
#define SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE(V) ((V & SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_MASK) << SIMPLEDMA_SRC_ADDR_INC_SRC_STRIDE_OFFS)
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#define SIMPLEDMA_DST_START_ADDR_OFFS 0
#define SIMPLEDMA_DST_START_ADDR_MASK 0xffffffff
#define SIMPLEDMA_DST_START_ADDR(V) ((V & SIMPLEDMA_DST_START_ADDR_MASK) << SIMPLEDMA_DST_START_ADDR_OFFS)
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#define SIMPLEDMA_DST_ADDR_INC_DST_STEP_OFFS 0
#define SIMPLEDMA_DST_ADDR_INC_DST_STEP_MASK 0xfff
#define SIMPLEDMA_DST_ADDR_INC_DST_STEP(V) ((V & SIMPLEDMA_DST_ADDR_INC_DST_STEP_MASK) << SIMPLEDMA_DST_ADDR_INC_DST_STEP_OFFS)
#define SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_OFFS 12
#define SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define SIMPLEDMA_DST_ADDR_INC_DST_STRIDE(V) ((V & SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_MASK) << SIMPLEDMA_DST_ADDR_INC_DST_STRIDE_OFFS)
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//SIMPLEDMA_CONTROL
inline uint32_t get_simpledma_control(volatile simpledma_t* reg){
return (reg->CONTROL >> 0) & 0x1;
}
inline void set_simpledma_control(volatile simpledma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
}
//SIMPLEDMA_STATUS
inline uint32_t get_simpledma_status(volatile simpledma_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
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//SIMPLEDMA_EVENT
inline uint32_t get_simpledma_event(volatile simpledma_t* reg){
return reg->EVENT;
}
inline void set_simpledma_event(volatile simpledma_t* reg, uint32_t value){
reg->EVENT = value;
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}
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inline uint32_t get_simpledma_event_select(volatile simpledma_t* reg){
return (reg->EVENT >> 0) & 0x1f;
}
inline void set_simpledma_event_select(volatile simpledma_t* reg, uint8_t value){
reg->EVENT = (reg->EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_event_combine(volatile simpledma_t* reg){
return (reg->EVENT >> 31) & 0x1;
}
inline void set_simpledma_event_combine(volatile simpledma_t* reg, uint8_t value){
reg->EVENT = (reg->EVENT & ~(0x1U << 31)) | (value << 31);
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}
//SIMPLEDMA_IE
inline uint32_t get_simpledma_ie(volatile simpledma_t* reg){
return reg->IE;
}
inline void set_simpledma_ie(volatile simpledma_t* reg, uint32_t value){
reg->IE = value;
}
inline uint32_t get_simpledma_ie_en_seg_transfer_done(volatile simpledma_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_simpledma_ie_en_seg_transfer_done(volatile simpledma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_simpledma_ie_en_transfer_done(volatile simpledma_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_simpledma_ie_en_transfer_done(volatile simpledma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
//SIMPLEDMA_IP
inline uint32_t get_simpledma_ip(volatile simpledma_t* reg){
return reg->IP;
}
inline void set_simpledma_ip(volatile simpledma_t* reg, uint32_t value){
reg->IP = value;
}
inline uint32_t get_simpledma_ip_seg_transfer_done(volatile simpledma_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline uint32_t get_simpledma_ip_transfer_done(volatile simpledma_t* reg){
return (reg->IP >> 1) & 0x1;
}
//SIMPLEDMA_TRANSFER
inline uint32_t get_simpledma_transfer(volatile simpledma_t* reg){
return reg->TRANSFER;
}
inline void set_simpledma_transfer(volatile simpledma_t* reg, uint32_t value){
reg->TRANSFER = value;
}
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inline uint32_t get_simpledma_transfer_width(volatile simpledma_t* reg){
return (reg->TRANSFER >> 0) & 0x3;
}
inline void set_simpledma_transfer_width(volatile simpledma_t* reg, uint8_t value){
reg->TRANSFER = (reg->TRANSFER & ~(0x3U << 0)) | (value << 0);
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}
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inline uint32_t get_simpledma_transfer_seg_length(volatile simpledma_t* reg){
return (reg->TRANSFER >> 2) & 0x3ff;
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}
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inline void set_simpledma_transfer_seg_length(volatile simpledma_t* reg, uint16_t value){
reg->TRANSFER = (reg->TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_simpledma_transfer_seg_count(volatile simpledma_t* reg){
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return (reg->TRANSFER >> 12) & 0xfffff;
}
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inline void set_simpledma_transfer_seg_count(volatile simpledma_t* reg, uint32_t value){
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reg->TRANSFER = (reg->TRANSFER & ~(0xfffffU << 12)) | (value << 12);
}
//SIMPLEDMA_SRC_START_ADDR
inline uint32_t get_simpledma_src_start_addr(volatile simpledma_t* reg){
return (reg->SRC_START_ADDR >> 0) & 0xffffffff;
}
inline void set_simpledma_src_start_addr(volatile simpledma_t* reg, uint32_t value){
reg->SRC_START_ADDR = (reg->SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
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//SIMPLEDMA_SRC_ADDR_INC
inline uint32_t get_simpledma_src_addr_inc(volatile simpledma_t* reg){
return reg->SRC_ADDR_INC;
}
inline void set_simpledma_src_addr_inc(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC = value;
}
inline uint32_t get_simpledma_src_addr_inc_src_step(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_simpledma_src_addr_inc_src_step(volatile simpledma_t* reg, uint16_t value){
reg->SRC_ADDR_INC = (reg->SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_src_addr_inc_src_stride(volatile simpledma_t* reg){
return (reg->SRC_ADDR_INC >> 12) & 0xfffff;
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}
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inline void set_simpledma_src_addr_inc_src_stride(volatile simpledma_t* reg, uint32_t value){
reg->SRC_ADDR_INC = (reg->SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
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}
//SIMPLEDMA_DST_START_ADDR
inline uint32_t get_simpledma_dst_start_addr(volatile simpledma_t* reg){
return (reg->DST_START_ADDR >> 0) & 0xffffffff;
}
inline void set_simpledma_dst_start_addr(volatile simpledma_t* reg, uint32_t value){
reg->DST_START_ADDR = (reg->DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
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//SIMPLEDMA_DST_ADDR_INC
inline uint32_t get_simpledma_dst_addr_inc(volatile simpledma_t* reg){
return reg->DST_ADDR_INC;
}
inline void set_simpledma_dst_addr_inc(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC = value;
}
inline uint32_t get_simpledma_dst_addr_inc_dst_step(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_simpledma_dst_addr_inc_dst_step(volatile simpledma_t* reg, uint16_t value){
reg->DST_ADDR_INC = (reg->DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_simpledma_dst_addr_inc_dst_stride(volatile simpledma_t* reg){
return (reg->DST_ADDR_INC >> 12) & 0xfffff;
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}
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inline void set_simpledma_dst_addr_inc_dst_stride(volatile simpledma_t* reg, uint32_t value){
reg->DST_ADDR_INC = (reg->DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
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}
#endif /* _BSP_SIMPLEDMA_H */