set _WORKAREASIZE 0x2000

adapter_khz 1000

interface jlink
transport select jtag

set _WORKAREASIZE 0x1000

set _CHIPNAME rv32m1

reset_config srst_only

# OpenCores Mohor JTAG TAP ID
set _CPUTAPID  0x249511C3

jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME rv32m1 -endian little -chain-position $_TARGETNAME

# Select the TAP core we are using
tap_select mohor

# Select the debug unit core we are using. This debug unit as an option.

set ADBG_USE_HISPEED		1

# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
# on burst reads and writes to improve download speeds.
# This option must match the RTL configured option.

du_select adv [expr $ADBG_USE_HISPEED]

# Select core 0
core_select 0

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
$_TARGETNAME configure -event gdb-detach {
    resume
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_CHIPNAME.flash0 rv32m1 0 0 0 0 $_TARGETNAME # For core 0
flash bank $_CHIPNAME.flash1 rv32m1 0x01000000 0 0 0 $_TARGETNAME # For core 1

proc ri5cy_boot { } {

    # Erase all blok unsecure
    mwb 0x40023000 0x70
    mww 0x40023004 0x49000000
    mwb 0x40023000 0x80

    sleep 1000

    mwb 0x40023000 0x70
    mww 0x40023008 0xFFFF03FF
    mww 0x40023004 0x43840000
    mwb 0x40023000 0x80

    sleep 2
}

proc cm4_boot { } {

    # Erase all blok unsecure
    mwb 0x40023000 0x70
    mww 0x40023004 0x49000000
    mwb 0x40023000 0x80

    sleep 1000

    mwb 0x40023000 0x70
    mww 0x40023008 0xFFFFFFFF
    mww 0x40023004 0x43840000
    mwb 0x40023000 0x80

    sleep 2
}

proc zero_boot { } {

    # Erase all blok unsecure
    mwb 0x40023000 0x70
    mww 0x40023004 0x49000000
    mwb 0x40023000 0x80

    sleep 1000

    mwb 0x40023000 0x70
    mww 0x40023008 0xFFFF03BF
    mww 0x40023004 0x43840000
    mwb 0x40023000 0x80

    sleep 2
}

proc cm0_boot { } {

    # Erase all blok unsecure
    mwb 0x40023000 0x70
    mww 0x40023004 0x49000000
    mwb 0x40023000 0x80

    sleep 1000

    mwb 0x40023000 0x70
    mww 0x40023008 0xFFFFFFBF
    mww 0x40023004 0x43840000
    mwb 0x40023000 0x80

    sleep 2
}

# All cores are available, CM4 & RI5CY boot first
proc core0_boot { } {

    # Erase all blok unsecure
    mwb 0x40023000 0x70
    mww 0x40023004 0x49000000
    mwb 0x40023000 0x80

    sleep 1000

    mwb 0x40023000 0x70
    mww 0x40023008 0xFFFFA3FF
    mww 0x40023004 0x43840000
    mwb 0x40023000 0x80

    sleep 2
}

# All cores are available, CM0 & ZERO_RISCY boot first
proc core1_boot { } {

    # Erase all blok unsecure
    mwb 0x40023000 0x70
    mww 0x40023004 0x49000000
    mwb 0x40023000 0x80

    sleep 1000

    mwb 0x40023000 0x70
    mww 0x40023008 0xFFFFA3BF
    mww 0x40023004 0x43840000
    mwb 0x40023000 0x80

    sleep 2
}

init
