diff --git a/bare-metal-bsp/.project b/bare-metal-bsp/.project new file mode 100644 index 0000000..6aa10ed --- /dev/null +++ b/bare-metal-bsp/.project @@ -0,0 +1,27 @@ + + + bare-metal-bsp + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/bare-metal-bsp/env/tgc-vp/.gitignore b/bare-metal-bsp/env/tgc-vp/.gitignore new file mode 100644 index 0000000..cc5bb74 --- /dev/null +++ b/bare-metal-bsp/env/tgc-vp/.gitignore @@ -0,0 +1 @@ +/*.o diff --git a/bare-metal-bsp/env/tgc-vp/init.c b/bare-metal-bsp/env/tgc-vp/init.c new file mode 100644 index 0000000..690f754 --- /dev/null +++ b/bare-metal-bsp/env/tgc-vp/init.c @@ -0,0 +1,116 @@ +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +extern int main(int argc, char** argv); +extern void trap_entry(); + +static unsigned long mtime_lo(void) +{ + unsigned long ret; + __asm volatile("rdtime %0":"=r"(ret)); + return ret; +} + + +#if __riscv_xlen==32 + +static uint32_t mtime_hi(void) +{ + unsigned long ret; + __asm volatile("rdtimeh %0":"=r"(ret)); + return ret; +} + +uint64_t get_timer_value() +{ + while (1) { + uint32_t hi = mtime_hi(); + uint32_t lo = mtime_lo(); + if (hi == mtime_hi()) + return ((uint64_t)hi << 32) | lo; + } +} + +#elif __riscv_xlen==64 + +uint64_t get_timer_value() +{ + return mtime_lo(); +} + +#endif + +unsigned long get_timer_freq() +{ + return 32768; +} + +unsigned long get_cpu_freq() +{ + return 10000000; +} + +void init_pll(void){ + +} + +static void uart_init(size_t baud_rate) +{ + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif + } + else { + write(1, "trap\n", 5); + _exit(1 + mcause); + } + return epc; +} + +void _init() +{ + +#ifndef NO_INIT + init_pll(); + uart_init(115200); + printf("core freq at %d Hz\n", get_cpu_freq()); + write_csr(mtvec, &trap_entry); + if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present + write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping + write_csr(fcsr, 0); // initialize rounding mode, undefined at reset + } +#endif + +} + +void _fini() +{ +} diff --git a/bare-metal-bsp/env/tgc-vp/link.lds b/bare-metal-bsp/env/tgc-vp/link.lds new file mode 100644 index 0000000..3561a66 --- /dev/null +++ b/bare-metal-bsp/env/tgc-vp/link.lds @@ -0,0 +1,174 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 128K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init ORIGIN(flash) : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + __DATA_BEGIN__ = .; + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + __SDATA_BEGIN__ = .; + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + __BSS_END__ = .; + __global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800, MAX(__DATA_BEGIN__ + 0x800, __BSS_END__ - 0x800)); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram + + PROVIDE( tohost = 0xfffffff0 ); + PROVIDE( fromhost = 0xfffffff8 ); +} diff --git a/bare-metal-bsp/env/tgc-vp/platform.h b/bare-metal-bsp/env/tgc-vp/platform.h new file mode 100644 index 0000000..e92d254 --- /dev/null +++ b/bare-metal-bsp/env/tgc-vp/platform.h @@ -0,0 +1,127 @@ +// See LICENSE for license details. + +#ifndef _ISS_PLATFORM_H +#define _ISS_PLATFORM_H + +// Some things missing from the official encoding.h +#define MCAUSE_INT 0x80000000 +#define MCAUSE_CAUSE 0x7FFFFFFF + +#include "tgc-vp/const.h" +#include "tgc-vp/devices/aon.h" +#include "tgc-vp/devices/clint.h" +#include "tgc-vp/devices/gpio.h" +#include "tgc-vp/devices/otp.h" +#include "tgc-vp/devices/plic.h" +#include "tgc-vp/devices/prci.h" +#include "tgc-vp/devices/pwm.h" +#include "tgc-vp/devices/spi.h" +#include "tgc-vp/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define MASKROM_BASE_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) +#define OTP_MMAP_ADDR _AC(0x00020000,UL) +#define CLINT_BASE_ADDR _AC(0x02000000,UL) +#define PLIC_BASE_ADDR _AC(0x0C000000,UL) +#define AON_BASE_ADDR _AC(0x10000000,UL) +#define PRCI_BASE_ADDR _AC(0x10008000,UL) +#define OTP_BASE_ADDR _AC(0x10010000,UL) +#define GPIO_BASE_ADDR _AC(0x10012000,UL) +#define UART0_BASE_ADDR _AC(0x10013000,UL) +#define SPI0_BASE_ADDR _AC(0x10014000,UL) +#define PWM0_BASE_ADDR _AC(0x10015000,UL) +#define UART1_BASE_ADDR _AC(0x10023000,UL) +#define SPI1_BASE_ADDR _AC(0x10024000,UL) +#define PWM1_BASE_ADDR _AC(0x10025000,UL) +#define SPI2_BASE_ADDR _AC(0x10034000,UL) +#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define SPI0_MMAP_ADDR _AC(0x20000000,UL) +#define MEM_BASE_ADDR _AC(0x80000000,UL) + +// IOF masks +#define IOF0_SPI1_MASK _AC(0x000007FC,UL) +#define SPI11_NUM_SS (4) +#define IOF_SPI1_SS0 (2u) +#define IOF_SPI1_SS1 (8u) +#define IOF_SPI1_SS2 (9u) +#define IOF_SPI1_SS3 (10u) +#define IOF_SPI1_MOSI (3u) +#define IOF_SPI1_MISO (4u) +#define IOF_SPI1_SCK (5u) +#define IOF_SPI1_DQ0 (3u) +#define IOF_SPI1_DQ1 (4u) +#define IOF_SPI1_DQ2 (6u) +#define IOF_SPI1_DQ3 (7u) + +#define IOF0_SPI2_MASK _AC(0xFC000000,UL) +#define SPI2_NUM_SS (1) +#define IOF_SPI2_SS0 (26u) +#define IOF_SPI2_MOSI (27u) +#define IOF_SPI2_MISO (28u) +#define IOF_SPI2_SCK (29u) +#define IOF_SPI2_DQ0 (27u) +#define IOF_SPI2_DQ1 (28u) +#define IOF_SPI2_DQ2 (30u) +#define IOF_SPI2_DQ3 (31u) + +//#define IOF0_I2C_MASK _AC(0x00003000,UL) + +#define IOF0_UART0_MASK _AC(0x00030000, UL) +#define IOF_UART0_RX (16u) +#define IOF_UART0_TX (17u) + +#define IOF0_UART1_MASK _AC(0x03000000, UL) +#define IOF_UART1_RX (24u) +#define IOF_UART1_TX (25u) + +#define IOF1_PWM0_MASK _AC(0x0000000F, UL) +#define IOF1_PWM1_MASK _AC(0x00780000, UL) +#define IOF1_PWM2_MASK _AC(0x00003C00, UL) + +// Interrupt numbers +#define INT_RESERVED 0 +#define INT_WDOGCMP 1 +#define INT_RTCCMP 2 +#define INT_UART0_BASE 3 +#define INT_UART1_BASE 4 +#define INT_SPI0_BASE 5 +#define INT_SPI1_BASE 6 +#define INT_SPI2_BASE 7 +#define INT_GPIO_BASE 8 +#define INT_PWM0_BASE 40 +#define INT_PWM1_BASE 44 +#define INT_PWM2_BASE 48 + +// Helper functions +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) +#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) + +// Misc + +#include + +void init_pll(void); +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _ISS_PLATFORM_H */ diff --git a/bare-metal-bsp/include/tgc-vp/bits.h b/bare-metal-bsp/include/tgc-vp/bits.h new file mode 100644 index 0000000..e550f80 --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/bits.h @@ -0,0 +1,35 @@ +#ifndef _RISCV_BITS_H +#define _RISCV_BITS_H + +#define likely(x) __builtin_expect((x), 1) +#define unlikely(x) __builtin_expect((x), 0) + +#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b)) +#define ROUNDDOWN(a, b) ((a)/(b)*(b)) + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) + +#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) +#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) + +#define STR(x) XSTR(x) +#define XSTR(x) #x + +#ifdef __riscv64 +# define SLL32 sllw +# define STORE sd +# define LOAD ld +# define LWU lwu +# define LOG_REGBYTES 3 +#else +# define SLL32 sll +# define STORE sw +# define LOAD lw +# define LWU lw +# define LOG_REGBYTES 2 +#endif +#define REGBYTES (1 << LOG_REGBYTES) + +#endif diff --git a/bare-metal-bsp/include/tgc-vp/const.h b/bare-metal-bsp/include/tgc-vp/const.h new file mode 100644 index 0000000..3e0a681 --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/const.h @@ -0,0 +1,17 @@ +/* Derived from */ + +#ifndef _SIFIVE_CONST_H +#define _SIFIVE_CONST_H + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define _AC(X,Y) (X##Y) +#define _AT(T,X) ((T)(X)) +#endif /* !__ASSEMBLER__*/ + +#define _BITUL(x) (_AC(1,UL) << (x)) +#define _BITULL(x) (_AC(1,ULL) << (x)) + +#endif /* _SIFIVE_CONST_H */ diff --git a/bare-metal-bsp/include/tgc-vp/devices/aon.h b/bare-metal-bsp/include/tgc-vp/devices/aon.h new file mode 100644 index 0000000..63f1db3 --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/devices/aon.h @@ -0,0 +1,88 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_AON_H +#define _SIFIVE_AON_H + +/* Register offsets */ + +#define AON_WDOGCFG 0x000 +#define AON_WDOGCOUNT 0x008 +#define AON_WDOGS 0x010 +#define AON_WDOGFEED 0x018 +#define AON_WDOGKEY 0x01C +#define AON_WDOGCMP 0x020 + +#define AON_RTCCFG 0x040 +#define AON_RTCLO 0x048 +#define AON_RTCHI 0x04C +#define AON_RTCS 0x050 +#define AON_RTCCMP 0x060 + +#define AON_BACKUP0 0x080 +#define AON_BACKUP1 0x084 +#define AON_BACKUP2 0x088 +#define AON_BACKUP3 0x08C +#define AON_BACKUP4 0x090 +#define AON_BACKUP5 0x094 +#define AON_BACKUP6 0x098 +#define AON_BACKUP7 0x09C +#define AON_BACKUP8 0x0A0 +#define AON_BACKUP9 0x0A4 +#define AON_BACKUP10 0x0A8 +#define AON_BACKUP11 0x0AC +#define AON_BACKUP12 0x0B0 +#define AON_BACKUP13 0x0B4 +#define AON_BACKUP14 0x0B8 +#define AON_BACKUP15 0x0BC + +#define AON_PMUWAKEUPI0 0x100 +#define AON_PMUWAKEUPI1 0x104 +#define AON_PMUWAKEUPI2 0x108 +#define AON_PMUWAKEUPI3 0x10C +#define AON_PMUWAKEUPI4 0x110 +#define AON_PMUWAKEUPI5 0x114 +#define AON_PMUWAKEUPI6 0x118 +#define AON_PMUWAKEUPI7 0x11C +#define AON_PMUSLEEPI0 0x120 +#define AON_PMUSLEEPI1 0x124 +#define AON_PMUSLEEPI2 0x128 +#define AON_PMUSLEEPI3 0x12C +#define AON_PMUSLEEPI4 0x130 +#define AON_PMUSLEEPI5 0x134 +#define AON_PMUSLEEPI6 0x138 +#define AON_PMUSLEEPI7 0x13C +#define AON_PMUIE 0x140 +#define AON_PMUCAUSE 0x144 +#define AON_PMUSLEEP 0x148 +#define AON_PMUKEY 0x14C + +#define AON_LFROSC 0x070 +/* Constants */ + +#define AON_WDOGKEY_VALUE 0x51F15E +#define AON_WDOGFEED_VALUE 0xD09F00D + +#define AON_WDOGCFG_SCALE 0x0000000F +#define AON_WDOGCFG_RSTEN 0x00000100 +#define AON_WDOGCFG_ZEROCMP 0x00000200 +#define AON_WDOGCFG_ENALWAYS 0x00001000 +#define AON_WDOGCFG_ENCOREAWAKE 0x00002000 +#define AON_WDOGCFG_CMPIP 0x10000000 + +#define AON_RTCCFG_SCALE 0x0000000F +#define AON_RTCCFG_ENALWAYS 0x00001000 +#define AON_RTCCFG_CMPIP 0x10000000 + +#define AON_WAKEUPCAUSE_RESET 0x00 +#define AON_WAKEUPCAUSE_RTC 0x01 +#define AON_WAKEUPCAUSE_DWAKEUP 0x02 +#define AON_WAKEUPCAUSE_AWAKEUP 0x03 + +#define AON_RESETCAUSE_POWERON 0x0000 +#define AON_RESETCAUSE_EXTERNAL 0x0100 +#define AON_RESETCAUSE_WATCHDOG 0x0200 + +#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF +#define AON_PMUCAUSE_RESETCAUSE 0xFF00 + +#endif /* _SIFIVE_AON_H */ diff --git a/bare-metal-bsp/include/tgc-vp/devices/clint.h b/bare-metal-bsp/include/tgc-vp/devices/clint.h new file mode 100644 index 0000000..cd3e0c7 --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/devices/clint.h @@ -0,0 +1,14 @@ +// See LICENSE for license details + +#ifndef _SIFIVE_CLINT_H +#define _SIFIVE_CLINT_H + + +#define CLINT_MSIP 0x0000 +#define CLINT_MSIP_size 0x4 +#define CLINT_MTIMECMP 0x4000 +#define CLINT_MTIMECMP_size 0x8 +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIME_size 0x8 + +#endif /* _SIFIVE_CLINT_H */ diff --git a/bare-metal-bsp/include/tgc-vp/devices/gpio.h b/bare-metal-bsp/include/tgc-vp/devices/gpio.h new file mode 100644 index 0000000..f7f0acb --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/devices/gpio.h @@ -0,0 +1,24 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_GPIO_H +#define _SIFIVE_GPIO_H + +#define GPIO_INPUT_VAL (0x00) +#define GPIO_INPUT_EN (0x04) +#define GPIO_OUTPUT_EN (0x08) +#define GPIO_OUTPUT_VAL (0x0C) +#define GPIO_PULLUP_EN (0x10) +#define GPIO_DRIVE (0x14) +#define GPIO_RISE_IE (0x18) +#define GPIO_RISE_IP (0x1C) +#define GPIO_FALL_IE (0x20) +#define GPIO_FALL_IP (0x24) +#define GPIO_HIGH_IE (0x28) +#define GPIO_HIGH_IP (0x2C) +#define GPIO_LOW_IE (0x30) +#define GPIO_LOW_IP (0x34) +#define GPIO_IOF_EN (0x38) +#define GPIO_IOF_SEL (0x3C) +#define GPIO_OUTPUT_XOR (0x40) + +#endif /* _SIFIVE_GPIO_H */ diff --git a/bare-metal-bsp/include/tgc-vp/devices/otp.h b/bare-metal-bsp/include/tgc-vp/devices/otp.h new file mode 100644 index 0000000..93833e2 --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/devices/otp.h @@ -0,0 +1,23 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_OTP_H +#define _SIFIVE_OTP_H + +/* Register offsets */ + +#define OTP_LOCK 0x00 +#define OTP_CK 0x04 +#define OTP_OE 0x08 +#define OTP_SEL 0x0C +#define OTP_WE 0x10 +#define OTP_MR 0x14 +#define OTP_MRR 0x18 +#define OTP_MPP 0x1C +#define OTP_VRREN 0x20 +#define OTP_VPPEN 0x24 +#define OTP_A 0x28 +#define OTP_D 0x2C +#define OTP_Q 0x30 +#define OTP_READ_TIMINGS 0x34 + +#endif diff --git a/bare-metal-bsp/include/tgc-vp/devices/plic.h b/bare-metal-bsp/include/tgc-vp/devices/plic.h new file mode 100644 index 0000000..16ea689 --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/devices/plic.h @@ -0,0 +1,31 @@ +// See LICENSE for license details. + +#ifndef PLIC_H +#define PLIC_H + +#include + +// 32 bits per source +#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL) +#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2 +// 1 bit per source (1 address) +#define PLIC_PENDING_OFFSET _AC(0x1000,UL) +#define PLIC_PENDING_SHIFT_PER_SOURCE 0 + +//0x80 per target +#define PLIC_ENABLE_OFFSET _AC(0x2000,UL) +#define PLIC_ENABLE_SHIFT_PER_TARGET 7 + + +#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL) +#define PLIC_CLAIM_OFFSET _AC(0x200004,UL) +#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12 +#define PLIC_CLAIM_SHIFT_PER_TARGET 12 + +#define PLIC_MAX_SOURCE 1023 +#define PLIC_SOURCE_MASK 0x3FF + +#define PLIC_MAX_TARGET 15871 +#define PLIC_TARGET_MASK 0x3FFF + +#endif /* PLIC_H */ diff --git a/bare-metal-bsp/include/tgc-vp/devices/prci.h b/bare-metal-bsp/include/tgc-vp/devices/prci.h new file mode 100644 index 0000000..1a3de58 --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/devices/prci.h @@ -0,0 +1,56 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PRCI_H +#define _SIFIVE_PRCI_H + +/* Register offsets */ + +#define PRCI_HFROSCCFG (0x0000) +#define PRCI_HFXOSCCFG (0x0004) +#define PRCI_PLLCFG (0x0008) +#define PRCI_PLLDIV (0x000C) +#define PRCI_PROCMONCFG (0x00F0) + +/* Fields */ +#define ROSC_DIV(x) (((x) & 0x2F) << 0 ) +#define ROSC_TRIM(x) (((x) & 0x1F) << 16) +#define ROSC_EN(x) (((x) & 0x1 ) << 30) +#define ROSC_RDY(x) (((x) & 0x1 ) << 31) + +#define XOSC_EN(x) (((x) & 0x1) << 30) +#define XOSC_RDY(x) (((x) & 0x1) << 31) + +#define PLL_R(x) (((x) & 0x7) << 0) +// single reserved bit for F LSB. +#define PLL_F(x) (((x) & 0x3F) << 4) +#define PLL_Q(x) (((x) & 0x3) << 10) +#define PLL_SEL(x) (((x) & 0x1) << 16) +#define PLL_REFSEL(x) (((x) & 0x1) << 17) +#define PLL_BYPASS(x) (((x) & 0x1) << 18) +#define PLL_LOCK(x) (((x) & 0x1) << 31) + +#define PLL_R_default 0x1 +#define PLL_F_default 0x1F +#define PLL_Q_default 0x3 + +#define PLL_REFSEL_HFROSC 0x0 +#define PLL_REFSEL_HFXOSC 0x1 + +#define PLL_SEL_HFROSC 0x0 +#define PLL_SEL_PLL 0x1 + +#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0) +#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8) + +#define PROCMON_DIV(x) (((x) & 0x1F) << 0) +#define PROCMON_TRIM(x) (((x) & 0x1F) << 8) +#define PROCMON_EN(x) (((x) & 0x1) << 16) +#define PROCMON_SEL(x) (((x) & 0x3) << 24) +#define PROCMON_NT_EN(x) (((x) & 0x1) << 28) + +#define PROCMON_SEL_HFCLK 0 +#define PROCMON_SEL_HFXOSCIN 1 +#define PROCMON_SEL_PLLOUTDIV 2 +#define PROCMON_SEL_PROCMON 3 + +#endif // _SIFIVE_PRCI_H diff --git a/bare-metal-bsp/include/tgc-vp/devices/pwm.h b/bare-metal-bsp/include/tgc-vp/devices/pwm.h new file mode 100644 index 0000000..067889a --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/devices/pwm.h @@ -0,0 +1,37 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PWM_H +#define _SIFIVE_PWM_H + +/* Register offsets */ + +#define PWM_CFG 0x00 +#define PWM_COUNT 0x08 +#define PWM_S 0x10 +#define PWM_CMP0 0x20 +#define PWM_CMP1 0x24 +#define PWM_CMP2 0x28 +#define PWM_CMP3 0x2C + +/* Constants */ + +#define PWM_CFG_SCALE 0x0000000F +#define PWM_CFG_STICKY 0x00000100 +#define PWM_CFG_ZEROCMP 0x00000200 +#define PWM_CFG_DEGLITCH 0x00000400 +#define PWM_CFG_ENALWAYS 0x00001000 +#define PWM_CFG_ONESHOT 0x00002000 +#define PWM_CFG_CMP0CENTER 0x00010000 +#define PWM_CFG_CMP1CENTER 0x00020000 +#define PWM_CFG_CMP2CENTER 0x00040000 +#define PWM_CFG_CMP3CENTER 0x00080000 +#define PWM_CFG_CMP0GANG 0x01000000 +#define PWM_CFG_CMP1GANG 0x02000000 +#define PWM_CFG_CMP2GANG 0x04000000 +#define PWM_CFG_CMP3GANG 0x08000000 +#define PWM_CFG_CMP0IP 0x10000000 +#define PWM_CFG_CMP1IP 0x20000000 +#define PWM_CFG_CMP2IP 0x40000000 +#define PWM_CFG_CMP3IP 0x80000000 + +#endif /* _SIFIVE_PWM_H */ diff --git a/bare-metal-bsp/include/tgc-vp/devices/spi.h b/bare-metal-bsp/include/tgc-vp/devices/spi.h new file mode 100644 index 0000000..916d86b --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/devices/spi.h @@ -0,0 +1,80 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_SPI_H +#define _SIFIVE_SPI_H + +/* Register offsets */ + +#define SPI_REG_SCKDIV 0x00 +#define SPI_REG_SCKMODE 0x04 +#define SPI_REG_CSID 0x10 +#define SPI_REG_CSDEF 0x14 +#define SPI_REG_CSMODE 0x18 + +#define SPI_REG_DCSSCK 0x28 +#define SPI_REG_DSCKCS 0x2a +#define SPI_REG_DINTERCS 0x2c +#define SPI_REG_DINTERXFR 0x2e + +#define SPI_REG_FMT 0x40 +#define SPI_REG_TXFIFO 0x48 +#define SPI_REG_RXFIFO 0x4c +#define SPI_REG_TXCTRL 0x50 +#define SPI_REG_RXCTRL 0x54 + +#define SPI_REG_FCTRL 0x60 +#define SPI_REG_FFMT 0x64 + +#define SPI_REG_IE 0x70 +#define SPI_REG_IP 0x74 + +/* Fields */ + +#define SPI_SCK_POL 0x1 +#define SPI_SCK_PHA 0x2 + +#define SPI_FMT_PROTO(x) ((x) & 0x3) +#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) +#define SPI_FMT_DIR(x) (((x) & 0x1) << 3) +#define SPI_FMT_LEN(x) (((x) & 0xf) << 16) + +/* TXCTRL register */ +#define SPI_TXWM(x) ((x) & 0xffff) +/* RXCTRL register */ +#define SPI_RXWM(x) ((x) & 0xffff) + +#define SPI_IP_TXWM 0x1 +#define SPI_IP_RXWM 0x2 + +#define SPI_FCTRL_EN 0x1 + +#define SPI_INSN_CMD_EN 0x1 +#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1) +#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4) +#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8) +#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10) +#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12) +#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16) +#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24) + +#define SPI_TXFIFO_FULL (1 << 31) +#define SPI_RXFIFO_EMPTY (1 << 31) + +/* Values */ + +#define SPI_CSMODE_AUTO 0 +#define SPI_CSMODE_HOLD 2 +#define SPI_CSMODE_OFF 3 + +#define SPI_DIR_RX 0 +#define SPI_DIR_TX 1 + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +#define SPI_ENDIAN_MSB 0 +#define SPI_ENDIAN_LSB 1 + + +#endif /* _SIFIVE_SPI_H */ diff --git a/bare-metal-bsp/include/tgc-vp/devices/uart.h b/bare-metal-bsp/include/tgc-vp/devices/uart.h new file mode 100644 index 0000000..71bea6f --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/devices/uart.h @@ -0,0 +1,27 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_UART_H +#define _SIFIVE_UART_H + +/* Register offsets */ +#define UART_REG_TXFIFO 0x00 +#define UART_REG_RXFIFO 0x04 +#define UART_REG_TXCTRL 0x08 +#define UART_REG_RXCTRL 0x0c +#define UART_REG_IE 0x10 +#define UART_REG_IP 0x14 +#define UART_REG_DIV 0x18 + +/* TXCTRL register */ +#define UART_TXEN 0x1 +#define UART_TXWM(x) (((x) & 0xffff) << 16) + +/* RXCTRL register */ +#define UART_RXEN 0x1 +#define UART_RXWM(x) (((x) & 0xffff) << 16) + +/* IP register */ +#define UART_IP_TXWM 0x1 +#define UART_IP_RXWM 0x2 + +#endif /* _SIFIVE_UART_H */ diff --git a/bare-metal-bsp/include/tgc-vp/sections.h b/bare-metal-bsp/include/tgc-vp/sections.h new file mode 100644 index 0000000..848c237 --- /dev/null +++ b/bare-metal-bsp/include/tgc-vp/sections.h @@ -0,0 +1,16 @@ +#ifndef _SECTIONS_H +#define _SECTIONS_H + +extern unsigned char _rom[]; +extern unsigned char _rom_end[]; + +extern unsigned char _ram[]; +extern unsigned char _ram_end[]; + +extern unsigned char _ftext[]; +extern unsigned char _etext[]; +extern unsigned char _fbss[]; +extern unsigned char _ebss[]; +extern unsigned char _end[]; + +#endif /* _SECTIONS_H */ diff --git a/bare-metal-bsp/libwrap/sys/puts.c b/bare-metal-bsp/libwrap/sys/puts.c new file mode 100644 index 0000000..50d6437 --- /dev/null +++ b/bare-metal-bsp/libwrap/sys/puts.c @@ -0,0 +1,28 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include + +#include "platform.h" +#include "stub.h" +#include "weak_under_alias.h" + +int __wrap_puts(const char *s) +{ + while (*s != '\0') { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = *s; + + if (*s == '\n') { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = '\r'; + } + + ++s; + } + + return 0; +} +weak_under_alias(puts); diff --git a/benchmarks/dhrystone/.cproject b/benchmarks/dhrystone/.cproject index 85bd960..b1976a7 100644 --- a/benchmarks/dhrystone/.cproject +++ b/benchmarks/dhrystone/.cproject @@ -14,7 +14,7 @@ - + - + \ No newline at end of file diff --git a/benchmarks/dhrystone/.project b/benchmarks/dhrystone/.project index d2675d0..39e1517 100644 --- a/benchmarks/dhrystone/.project +++ b/benchmarks/dhrystone/.project @@ -3,7 +3,7 @@ dhrystone - bsp + bare-metal-bsp