diff --git a/raven/Makefile b/raven/Makefile index 25c627a..6729b90 100644 --- a/raven/Makefile +++ b/raven/Makefile @@ -1,13 +1,29 @@ -TARGET = hello_raven -C_SRCS += $(wildcard *.c) -CFLAGS += -g -#-fno-builtin-printf -LDFLAGS := -Wl,--wrap=scanf -Wl,--wrap=printf +TARGET = hello_raven +C_SRCS = $(wildcard src/*.c) $(BSP_BASE)/drivers/fe300prci/fe300prci_driver.c $(BSP_BASE)/drivers/plic/plic_driver.c +CXX_SRCS = $(wildcard src/*.cpp) +HEADERS = $(wildcard src/*.h) +CFLAGS = -g -fno-builtin-printf -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -I./src +CXXFLAGS = -fno-use-cxa-atexit +LDFLAGS = -Wl,--wrap=printf +LDFLAGS += -g -lstdc++ -fno-use-cxa-atexit -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -mcmodel=medany + -#BOARD = iss BOARD=freedom-e300-hifive1 -TOOL_DIR=/opt/shared/riscv/FreedomStudio/20180122/SiFive/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin +LINK_TARGET=flash +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 + +TOOL_DIR=/home/stas/Downloads/riscv64-unknown-elf-gcc-8.3.0-2020.04.0-x86_64-linux-ubuntu14/bin +#TOOL_DIR?=/opt/riscv/FreedomStudio/20180122/SiFive/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin BSP_BASE = ./bsp include $(BSP_BASE)/env/common.mk + +.PHONY: all +all: $(TARGET).dump + +$(TARGET).dump: $(TARGET) + $(TOOL_DIR)/$(TRIPLET)-objdump -d -S -C $< > $@ + + diff --git a/raven/bsp/Debug/drivers/fe300prci/subdir.mk b/raven/bsp/Debug/drivers/fe300prci/subdir.mk deleted file mode 100644 index 9a05361..0000000 --- a/raven/bsp/Debug/drivers/fe300prci/subdir.mk +++ /dev/null @@ -1,24 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -C_SRCS += \ -../drivers/fe300prci/fe300prci_driver.c - -OBJS += \ -./drivers/fe300prci/fe300prci_driver.o - -C_DEPS += \ -./drivers/fe300prci/fe300prci_driver.d - - -# Each subdirectory must supply rules for building sources it contributes -drivers/fe300prci/%.o: ../drivers/fe300prci/%.c - @echo 'Building file: $<' - @echo 'Invoking: Cross GCC Compiler' - riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" - @echo 'Finished building: $<' - @echo ' ' - - diff --git a/raven/bsp/Debug/drivers/plic/subdir.mk b/raven/bsp/Debug/drivers/plic/subdir.mk deleted file mode 100644 index be3a955..0000000 --- a/raven/bsp/Debug/drivers/plic/subdir.mk +++ /dev/null @@ -1,24 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -C_SRCS += \ -../drivers/plic/plic_driver.c - -OBJS += \ -./drivers/plic/plic_driver.o - -C_DEPS += \ -./drivers/plic/plic_driver.d - - -# Each subdirectory must supply rules for building sources it contributes -drivers/plic/%.o: ../drivers/plic/%.c - @echo 'Building file: $<' - @echo 'Invoking: Cross GCC Compiler' - riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" - @echo 'Finished building: $<' - @echo ' ' - - diff --git a/raven/bsp/Debug/env/freedom-e300-arty/subdir.mk b/raven/bsp/Debug/env/freedom-e300-arty/subdir.mk deleted file mode 100644 index c0bee22..0000000 --- a/raven/bsp/Debug/env/freedom-e300-arty/subdir.mk +++ /dev/null @@ -1,24 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -C_SRCS += \ -../env/freedom-e300-arty/init.c - -OBJS += \ -./env/freedom-e300-arty/init.o - -C_DEPS += \ -./env/freedom-e300-arty/init.d - - -# Each subdirectory must supply rules for building sources it contributes -env/freedom-e300-arty/%.o: ../env/freedom-e300-arty/%.c - @echo 'Building file: $<' - @echo 'Invoking: Cross GCC Compiler' - riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" - @echo 'Finished building: $<' - @echo ' ' - - diff --git a/raven/bsp/Debug/env/freedom-e300-hifive1/subdir.mk b/raven/bsp/Debug/env/freedom-e300-hifive1/subdir.mk deleted file mode 100644 index 16eea64..0000000 --- a/raven/bsp/Debug/env/freedom-e300-hifive1/subdir.mk +++ /dev/null @@ -1,27 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -C_SRCS += \ -../env/freedom-e300-hifive1/init.c - -O_SRCS += \ -../env/freedom-e300-hifive1/init.o - -OBJS += \ -./env/freedom-e300-hifive1/init.o - -C_DEPS += \ -./env/freedom-e300-hifive1/init.d - - -# Each subdirectory must supply rules for building sources it contributes -env/freedom-e300-hifive1/%.o: ../env/freedom-e300-hifive1/%.c - @echo 'Building file: $<' - @echo 'Invoking: Cross GCC Compiler' - riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" - @echo 'Finished building: $<' - @echo ' ' - - diff --git a/raven/bsp/Debug/env/iss/subdir.mk b/raven/bsp/Debug/env/iss/subdir.mk deleted file mode 100644 index 88f2d87..0000000 --- a/raven/bsp/Debug/env/iss/subdir.mk +++ /dev/null @@ -1,27 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -C_SRCS += \ -../env/iss/init.c - -O_SRCS += \ -../env/iss/init.o - -OBJS += \ -./env/iss/init.o - -C_DEPS += \ -./env/iss/init.d - - -# Each subdirectory must supply rules for building sources it contributes -env/iss/%.o: ../env/iss/%.c - @echo 'Building file: $<' - @echo 'Invoking: Cross GCC Compiler' - riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" - @echo 'Finished building: $<' - @echo ' ' - - diff --git a/raven/bsp/Debug/env/subdir.mk b/raven/bsp/Debug/env/subdir.mk deleted file mode 100644 index b8eaa7a..0000000 --- a/raven/bsp/Debug/env/subdir.mk +++ /dev/null @@ -1,27 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -O_SRCS += \ -../env/entry.o \ -../env/start.o - -S_UPPER_SRCS += \ -../env/entry.S \ -../env/start.S - -OBJS += \ -./env/entry.o \ -./env/start.o - - -# Each subdirectory must supply rules for building sources it contributes -env/%.o: ../env/%.S - @echo 'Building file: $<' - @echo 'Invoking: Cross GCC Assembler' - riscv32-unknown-elf-as -o "$@" "$<" - @echo 'Finished building: $<' - @echo ' ' - - diff --git a/raven/bsp/Debug/libwrap/stdlib/subdir.mk b/raven/bsp/Debug/libwrap/stdlib/subdir.mk deleted file mode 100644 index 2327c6d..0000000 --- a/raven/bsp/Debug/libwrap/stdlib/subdir.mk +++ /dev/null @@ -1,27 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -C_SRCS += \ -../libwrap/stdlib/malloc.c - -O_SRCS += \ -../libwrap/stdlib/malloc.o - -OBJS += \ -./libwrap/stdlib/malloc.o - -C_DEPS += \ -./libwrap/stdlib/malloc.d - - -# Each subdirectory must supply rules for building sources it contributes -libwrap/stdlib/%.o: ../libwrap/stdlib/%.c - @echo 'Building file: $<' - @echo 'Invoking: Cross GCC Compiler' - riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" - @echo 'Finished building: $<' - @echo ' ' - - diff --git a/raven/bsp/Debug/libwrap/sys/subdir.mk b/raven/bsp/Debug/libwrap/sys/subdir.mk deleted file mode 100644 index a93df2a..0000000 --- a/raven/bsp/Debug/libwrap/sys/subdir.mk +++ /dev/null @@ -1,98 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -C_SRCS += \ -../libwrap/sys/_exit.c \ -../libwrap/sys/close.c \ -../libwrap/sys/execve.c \ -../libwrap/sys/fork.c \ -../libwrap/sys/fstat.c \ -../libwrap/sys/getpid.c \ -../libwrap/sys/isatty.c \ -../libwrap/sys/kill.c \ -../libwrap/sys/link.c \ -../libwrap/sys/lseek.c \ -../libwrap/sys/open.c \ -../libwrap/sys/openat.c \ -../libwrap/sys/read.c \ -../libwrap/sys/sbrk.c \ -../libwrap/sys/stat.c \ -../libwrap/sys/times.c \ -../libwrap/sys/unlink.c \ -../libwrap/sys/wait.c \ -../libwrap/sys/write.c - -O_SRCS += \ -../libwrap/sys/_exit.o \ -../libwrap/sys/close.o \ -../libwrap/sys/execve.o \ -../libwrap/sys/fork.o \ -../libwrap/sys/fstat.o \ -../libwrap/sys/getpid.o \ -../libwrap/sys/isatty.o \ -../libwrap/sys/kill.o \ -../libwrap/sys/link.o \ -../libwrap/sys/lseek.o \ -../libwrap/sys/open.o \ -../libwrap/sys/read.o \ -../libwrap/sys/sbrk.o \ -../libwrap/sys/stat.o \ -../libwrap/sys/times.o \ -../libwrap/sys/unlink.o \ -../libwrap/sys/wait.o \ -../libwrap/sys/write.o - -OBJS += \ -./libwrap/sys/_exit.o \ -./libwrap/sys/close.o \ -./libwrap/sys/execve.o \ -./libwrap/sys/fork.o \ -./libwrap/sys/fstat.o \ -./libwrap/sys/getpid.o \ -./libwrap/sys/isatty.o \ -./libwrap/sys/kill.o \ -./libwrap/sys/link.o \ -./libwrap/sys/lseek.o \ -./libwrap/sys/open.o \ -./libwrap/sys/openat.o \ -./libwrap/sys/read.o \ -./libwrap/sys/sbrk.o \ -./libwrap/sys/stat.o \ -./libwrap/sys/times.o \ -./libwrap/sys/unlink.o \ -./libwrap/sys/wait.o \ -./libwrap/sys/write.o - -C_DEPS += \ -./libwrap/sys/_exit.d \ -./libwrap/sys/close.d \ -./libwrap/sys/execve.d \ -./libwrap/sys/fork.d \ -./libwrap/sys/fstat.d \ -./libwrap/sys/getpid.d \ -./libwrap/sys/isatty.d \ -./libwrap/sys/kill.d \ -./libwrap/sys/link.d \ -./libwrap/sys/lseek.d \ -./libwrap/sys/open.d \ -./libwrap/sys/openat.d \ -./libwrap/sys/read.d \ -./libwrap/sys/sbrk.d \ -./libwrap/sys/stat.d \ -./libwrap/sys/times.d \ -./libwrap/sys/unlink.d \ -./libwrap/sys/wait.d \ -./libwrap/sys/write.d - - -# Each subdirectory must supply rules for building sources it contributes -libwrap/sys/%.o: ../libwrap/sys/%.c - @echo 'Building file: $<' - @echo 'Invoking: Cross GCC Compiler' - riscv32-unknown-elf-gcc -O0 -g3 -Wall -c -fmessage-length=0 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -o "$@" "$<" - @echo 'Finished building: $<' - @echo ' ' - - diff --git a/raven/bsp/Debug/makefile b/raven/bsp/Debug/makefile deleted file mode 100644 index 34f9759..0000000 --- a/raven/bsp/Debug/makefile +++ /dev/null @@ -1,66 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - --include ../makefile.init - -RM := rm -rf - -# All of the sources participating in the build are defined here --include sources.mk --include libwrap/sys/subdir.mk --include libwrap/stdlib/subdir.mk --include libwrap/misc/subdir.mk --include env/iss/subdir.mk --include env/freedom-e300-hifive1/subdir.mk --include env/freedom-e300-arty/subdir.mk --include env/subdir.mk --include drivers/plic/subdir.mk --include drivers/fe300prci/subdir.mk --include subdir.mk --include objects.mk - -ifneq ($(MAKECMDGOALS),clean) -ifneq ($(strip $(CC_DEPS)),) --include $(CC_DEPS) -endif -ifneq ($(strip $(C++_DEPS)),) --include $(C++_DEPS) -endif -ifneq ($(strip $(C_UPPER_DEPS)),) --include $(C_UPPER_DEPS) -endif -ifneq ($(strip $(CXX_DEPS)),) --include $(CXX_DEPS) -endif -ifneq ($(strip $(C_DEPS)),) --include $(C_DEPS) -endif -ifneq ($(strip $(CPP_DEPS)),) --include $(CPP_DEPS) -endif -endif - --include ../makefile.defs - -# Add inputs and outputs from these tool invocations to the build variables - -# All Target -all: bsp - -# Tool invocations -bsp: $(OBJS) $(USER_OBJS) - @echo 'Building target: $@' - @echo 'Invoking: Cross G++ Linker' - riscv32-unknown-elf-g++ -o "bsp" $(OBJS) $(USER_OBJS) $(LIBS) - @echo 'Finished building target: $@' - @echo ' ' - -# Other Targets -clean: - -$(RM) $(CC_DEPS)$(C++_DEPS)$(EXECUTABLES)$(OBJS)$(C_UPPER_DEPS)$(CXX_DEPS)$(C_DEPS)$(CPP_DEPS) bsp - -@echo ' ' - -.PHONY: all clean dependents - --include ../makefile.targets diff --git a/raven/bsp/Debug/objects.mk b/raven/bsp/Debug/objects.mk deleted file mode 100644 index 742c2da..0000000 --- a/raven/bsp/Debug/objects.mk +++ /dev/null @@ -1,8 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -USER_OBJS := - -LIBS := - diff --git a/raven/bsp/Debug/sources.mk b/raven/bsp/Debug/sources.mk deleted file mode 100644 index bfb7eff..0000000 --- a/raven/bsp/Debug/sources.mk +++ /dev/null @@ -1,35 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -C_UPPER_SRCS := -CXX_SRCS := -C++_SRCS := -OBJ_SRCS := -CC_SRCS := -ASM_SRCS := -C_SRCS := -CPP_SRCS := -O_SRCS := -S_UPPER_SRCS := -CC_DEPS := -C++_DEPS := -EXECUTABLES := -OBJS := -C_UPPER_DEPS := -CXX_DEPS := -C_DEPS := -CPP_DEPS := - -# Every subdirectory with source files must be described here -SUBDIRS := \ -drivers/fe300prci \ -drivers/plic \ -env \ -env/freedom-e300-arty \ -env/freedom-e300-hifive1 \ -env/iss \ -libwrap/misc \ -libwrap/stdlib \ -libwrap/sys \ - diff --git a/raven/bsp/drivers/clic/clic_driver.c b/raven/bsp/drivers/clic/clic_driver.c new file mode 100644 index 0000000..0612e58 --- /dev/null +++ b/raven/bsp/drivers/clic/clic_driver.c @@ -0,0 +1,163 @@ +// See LICENSE for license details. + +#include "sifive/devices/clic.h" +#include "clic/clic_driver.h" +#include "platform.h" +#include "encoding.h" +#include + + +void volatile_memzero(uint8_t * base, unsigned int size) { + volatile uint8_t * ptr; + for (ptr = base; ptr < (base + size); ptr++){ + *ptr = 0; + } +} + +// Note that there are no assertions or bounds checking on these +// parameter values. +void clic_init ( + clic_instance_t * this_clic, + uintptr_t hart_addr, + interrupt_function_ptr_t* vect_table, + interrupt_function_ptr_t default_handler, + uint32_t num_irq, + uint32_t num_config_bits + ) +{ + this_clic->hart_addr= hart_addr; + this_clic->vect_table= vect_table; + this_clic->num_config_bits= num_config_bits; + + //initialize vector table + for(int i=0;i++;ivect_table[i] = default_handler; + } + + //set base vectors + write_csr(mtvt, vect_table); + + + //clear all interrupt enables and pending + volatile_memzero((uint8_t*)(this_clic->hart_addr+CLIC_INTIE), num_irq); + volatile_memzero((uint8_t*)(this_clic->hart_addr+CLIC_INTIP), num_irq); + + //clear nlbits and nvbits; all interrupts trap to level 15 + *(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG)=0; + +} + +void clic_install_handler (clic_instance_t * this_clic, uint32_t source, interrupt_function_ptr_t handler) { + this_clic->vect_table[source] = handler; +} + +void clic_enable_interrupt (clic_instance_t * this_clic, uint32_t source) { + *(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIE+source) = 1; +} + +void clic_disable_interrupt (clic_instance_t * this_clic, uint32_t source){ + *(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIE+source) = 0; +} + +void clic_set_pending(clic_instance_t * this_clic, uint32_t source){ + *(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIP+source) = 1; +} + +void clic_clear_pending(clic_instance_t * this_clic, uint32_t source){ + *(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTIP+source) = 0; +} + +void clic_set_intcfg (clic_instance_t * this_clic, uint32_t source, uint32_t intcfg){ + *(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTCFG+source) = intcfg; +} + +uint8_t clic_get_intcfg (clic_instance_t * this_clic, uint32_t source){ + return *(volatile uint8_t*)(this_clic->hart_addr+CLIC_INTCFG+source); +} + +void clic_set_cliccfg (clic_instance_t * this_clic, uint32_t cfg){ + *(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG) = cfg; +} + +uint8_t clic_get_cliccfg (clic_instance_t * this_clic){ + return *(volatile uint8_t*)(this_clic->hart_addr+CLIC_CFG); +} + +//sets an interrupt level based encoding of nmbits, nlbits +uint8_t clic_set_int_level( clic_instance_t * this_clic, uint32_t source, uint8_t level) { + //extract nlbits + uint8_t nlbits = clic_get_cliccfg(this_clic); + nlbits = (nlbits >>1) & 0x7; + + //shift level right to mask off unused bits + level = level>>((this_clic->num_config_bits)-nlbits); //plus this_clic->nmbits which is always 0 for now. + //shift level into correct bit position + level = level << (8-this_clic->num_config_bits) + (this_clic->num_config_bits - nlbits); + + //write to clicintcfg + uint8_t current_intcfg = clic_get_intcfg(this_clic, source); + clic_set_intcfg(this_clic, source, (current_intcfg | level)); + + return level; +} + +//gets an interrupt level based encoding of nmbits, nlbits +uint8_t clic_get_int_level( clic_instance_t * this_clic, uint32_t source) { + uint8_t level; + level = clic_get_intcfg(this_clic, source); + + //extract nlbits + uint8_t nlbits = clic_get_cliccfg(this_clic); + nlbits = (nlbits >>1) & 0x7; + + //shift level + level = level >> (8-(this_clic->num_config_bits)); + + //shift level right to mask off priority bits + level = level>>(this_clic->num_config_bits-nlbits); //this_clic->nmbits which is always 0 for now. + + return level; +} + +//sets an interrupt priority based encoding of nmbits, nlbits +uint8_t clic_set_int_priority( clic_instance_t * this_clic, uint32_t source, uint8_t priority) { + //priority bits = num_config_bits - nlbits + //extract nlbits + uint8_t nlbits = clic_get_cliccfg(this_clic); + nlbits = (nlbits >>1) & 0x7; + + uint8_t priority_bits = this_clic->num_config_bits-nlbits; + if(priority_bits = 0) { + //no bits to set + return 0; + } + //mask off unused bits + priority = priority >> (8-priority_bits); + //shift into the correct bit position + priority = priority << (8-(this_clic->num_config_bits)); + + //write to clicintcfg + uint8_t current_intcfg = clic_get_intcfg(this_clic, source); + clic_set_intcfg(this_clic, source, (current_intcfg | priority)); + return current_intcfg; +} + +//gets an interrupt priority based encoding of nmbits, nlbits +uint8_t clic_get_int_priority( clic_instance_t * this_clic, uint32_t source) { + uint8_t priority; + priority = clic_get_intcfg(this_clic, source); + + //extract nlbits + uint8_t nlbits = clic_get_cliccfg(this_clic); + nlbits = (nlbits >>1) & 0x7; + + //shift left to mask off level bits + priority = priority << nlbits; + + //shift priority + priority = priority >> (8-((this_clic->num_config_bits)+nlbits)); + + return priority; +} + + diff --git a/raven/bsp/drivers/clic/clic_driver.h b/raven/bsp/drivers/clic/clic_driver.h new file mode 100644 index 0000000..27c34c2 --- /dev/null +++ b/raven/bsp/drivers/clic/clic_driver.h @@ -0,0 +1,44 @@ +// See LICENSE file for licence details + +#ifndef PLIC_DRIVER_H +#define PLIC_DRIVER_H + + +__BEGIN_DECLS + +#include "platform.h" + +typedef void (*interrupt_function_ptr_t) (void); + +typedef struct __clic_instance_t +{ + uintptr_t hart_addr; + interrupt_function_ptr_t* vect_table; + uint32_t num_config_bits; + uint32_t num_sources; +} clic_instance_t; + +// Note that there are no assertions or bounds checking on these +// parameter values. +void clic_init (clic_instance_t * this_clic, uintptr_t hart_addr, interrupt_function_ptr_t* vect_table, interrupt_function_ptr_t default_handler, uint32_t num_irq,uint32_t num_config_bits); +void clic_install_handler (clic_instance_t * this_clic, uint32_t source, interrupt_function_ptr_t handler); +void clic_enable_interrupt (clic_instance_t * this_clic, uint32_t source); +void clic_disable_interrupt (clic_instance_t * this_clic, uint32_t source); +void clic_set_pending(clic_instance_t * this_clic, uint32_t source); +void clic_clear_pending(clic_instance_t * this_clic, uint32_t source); +void clic_set_intcfg (clic_instance_t * this_clic, uint32_t source, uint32_t intcfg); +uint8_t clic_get_intcfg (clic_instance_t * this_clic, uint32_t source); +void clic_set_cliccfg (clic_instance_t * this_clic, uint32_t cfg); +uint8_t clic_get_cliccfg (clic_instance_t * this_clic); +//sets an interrupt level based encoding of nmbits, nlbits +uint8_t clic_set_int_level( clic_instance_t * this_clic, uint32_t source, uint8_t level); +//get an interrupt level based encoding of nmbits, nlbits +uint8_t clic_get_int_level( clic_instance_t * this_clic, uint32_t source); +//sets an interrupt priority based encoding of nmbits, nlbits +uint8_t clic_set_int_priority( clic_instance_t * this_clic, uint32_t source, uint8_t priority); +//sets an interrupt priority based encoding of nmbits, nlbits +uint8_t clic_get_int_priority( clic_instance_t * this_clic, uint32_t source); + +__END_DECLS + +#endif diff --git a/raven/bsp/drivers/fe300prci/fe300prci_driver.c b/raven/bsp/drivers/fe300prci/fe300prci_driver.c index 2d9c52f..8eeaafc 100644 --- a/raven/bsp/drivers/fe300prci/fe300prci_driver.c +++ b/raven/bsp/drivers/fe300prci/fe300prci_driver.c @@ -2,7 +2,7 @@ #include "platform.h" -#ifdef PRCI_BASE_ADDR +#ifdef PRCI_CTRL_ADDR #include "fe300prci/fe300prci_driver.h" #include diff --git a/raven/bsp/drivers/plic/plic_driver.c b/raven/bsp/drivers/plic/plic_driver.c index b27d7a5..4f41bda 100644 --- a/raven/bsp/drivers/plic/plic_driver.c +++ b/raven/bsp/drivers/plic/plic_driver.c @@ -22,19 +22,20 @@ void PLIC_init ( plic_instance_t * this_plic, uintptr_t base_addr, uint32_t num_sources, - uint32_t num_priorities + uint32_t num_priorities, + uint32_t target_hartid ) { this_plic->base_addr = base_addr; this_plic->num_sources = num_sources; this_plic->num_priorities = num_priorities; + this_plic->target_hartid = target_hartid; // Disable all interrupts (don't assume that these registers are reset). - unsigned long hart_id = read_csr(mhartid); volatile_memzero((uint8_t*) (this_plic->base_addr + PLIC_ENABLE_OFFSET + - (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET)), + (this_plic->target_hartid << PLIC_ENABLE_SHIFT_PER_TARGET)), (num_sources + 8) / 8); // Set all priorities to 0 (equal priority -- don't assume that these are reset). @@ -46,7 +47,7 @@ void PLIC_init ( volatile plic_threshold* threshold = (plic_threshold*) (this_plic->base_addr + PLIC_THRESHOLD_OFFSET + - (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + (this_plic->target_hartid << PLIC_THRESHOLD_SHIFT_PER_TARGET)); *threshold = 0; @@ -55,10 +56,9 @@ void PLIC_init ( void PLIC_set_threshold (plic_instance_t * this_plic, plic_threshold threshold){ - unsigned long hart_id = read_csr(mhartid); volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr + PLIC_THRESHOLD_OFFSET + - (hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET)); + (this_plic->target_hartid << PLIC_THRESHOLD_SHIFT_PER_TARGET)); *threshold_ptr = threshold; @@ -67,10 +67,9 @@ void PLIC_set_threshold (plic_instance_t * this_plic, void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){ - unsigned long hart_id = read_csr(mhartid); volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr + PLIC_ENABLE_OFFSET + - (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (this_plic->target_hartid << PLIC_ENABLE_SHIFT_PER_TARGET) + (source >> 3)); uint8_t current = *current_ptr; current = current | ( 1 << (source & 0x7)); @@ -80,10 +79,9 @@ void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){ void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){ - unsigned long hart_id = read_csr(mhartid); volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr + PLIC_ENABLE_OFFSET + - (hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) + + (this_plic->target_hartid << PLIC_ENABLE_SHIFT_PER_TARGET) + (source >> 3)); uint8_t current = *current_ptr; current = current & ~(( 1 << (source & 0x7))); @@ -104,12 +102,10 @@ void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_pr plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){ - unsigned long hart_id = read_csr(mhartid); - volatile plic_source * claim_addr = (volatile plic_source * ) (this_plic->base_addr + PLIC_CLAIM_OFFSET + - (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + (this_plic->target_hartid << PLIC_CLAIM_SHIFT_PER_TARGET)); return *claim_addr; @@ -117,10 +113,9 @@ plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){ void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){ - unsigned long hart_id = read_csr(mhartid); volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr + PLIC_CLAIM_OFFSET + - (hart_id << PLIC_CLAIM_SHIFT_PER_TARGET)); + (this_plic->target_hartid << PLIC_CLAIM_SHIFT_PER_TARGET)); *claim_addr = source; } diff --git a/raven/bsp/drivers/plic/plic_driver.h b/raven/bsp/drivers/plic/plic_driver.h index e7d609b..f7201ee 100644 --- a/raven/bsp/drivers/plic/plic_driver.h +++ b/raven/bsp/drivers/plic/plic_driver.h @@ -14,7 +14,7 @@ typedef struct __plic_instance_t uint32_t num_sources; uint32_t num_priorities; - + uint32_t target_hartid; } plic_instance_t; typedef uint32_t plic_source; @@ -25,7 +25,8 @@ void PLIC_init ( plic_instance_t * this_plic, uintptr_t base_addr, uint32_t num_sources, - uint32_t num_priorities + uint32_t num_priorities, + uint32_t target_hartid ); void PLIC_set_threshold (plic_instance_t * this_plic, diff --git a/raven/bsp/env/common.mk b/raven/bsp/env/common.mk index 0995009..0ca2c70 100644 --- a/raven/bsp/env/common.mk +++ b/raven/bsp/env/common.mk @@ -8,18 +8,14 @@ all: $(TARGET) include $(BSP_BASE)/libwrap/libwrap.mk -BOARD ?= freedom-e300-hifive1 ENV_DIR = $(BSP_BASE)/env PLATFORM_DIR = $(ENV_DIR)/$(BOARD) -#TARGET_FLAVOR := -march=rv32imac -mabi=ilp32 -mcmodel=medany -msmall-data-limit=8 -x assembler-with-cpp -TARGET_FLAVOR := -march=rv32i -mabi=ilp32 - ASM_SRCS += $(ENV_DIR)/start.S ASM_SRCS += $(ENV_DIR)/entry.S C_SRCS += $(PLATFORM_DIR)/init.c -LINKER_SCRIPT := $(PLATFORM_DIR)/link.lds +LINKER_SCRIPT := $(PLATFORM_DIR)/$(LINK_TARGET).lds INCLUDES += -I$(BSP_BASE)/include INCLUDES += -I$(BSP_BASE)/drivers/ @@ -28,35 +24,43 @@ INCLUDES += -I$(PLATFORM_DIR) TOOL_DIR ?= $(BSP_BASE)/../toolchain/bin -CC := $(TOOL_DIR)/riscv64-unknown-elf-gcc ${TARGET_FLAVOR} -AR := $(TOOL_DIR)/riscv64-unknown-elf-ar -OBJDUMP := $(TOOL_DIR)/riscv64-unknown-elf-objdump - LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles -LDFLAGS += -L$(ENV_DIR) +LDFLAGS += -L$(ENV_DIR) --specs=nano.specs ASM_OBJS := $(ASM_SRCS:.S=.o) -C_OBJS := $(C_SRCS:.c=.o) +C_OBJS := $(C_SRCS:.c=.o) +CXX_OBJS := $(CXX_SRCS:.cpp=.o) -LINK_OBJS += $(ASM_OBJS) $(C_OBJS) +LINK_OBJS += $(ASM_OBJS) $(C_OBJS) $(CXX_OBJS) LINK_DEPS += $(LINKER_SCRIPT) CLEAN_OBJS += $(TARGET) $(LINK_OBJS) -CFLAGS += -g +CFLAGS += -march=$(RISCV_ARCH) +CFLAGS += -mabi=$(RISCV_ABI) +CFLAGS += -mcmodel=medany + +TRIPLET?=riscv64-unknown-elf +CXX=$(TOOL_DIR)/$(TRIPLET)-c++ +CC=$(TOOL_DIR)/$(TRIPLET)-gcc +LD=$(TOOL_DIR)/$(TRIPLET)-gcc +AR=$(TOOL_DIR)/$(TRIPLET)-ar + $(TARGET): $(LINK_OBJS) $(LINK_DEPS) - $(CC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS) - $(OBJDUMP) -d $(TARGET) > $(TARGET).dis - + $(LD) $(LINK_OBJS) $(LDFLAGS) $(LIBWRAP) -o $@ + $(ASM_OBJS): %.o: %.S $(HEADERS) $(CC) $(CFLAGS) $(INCLUDES) -c -o $@ $< $(C_OBJS): %.o: %.c $(HEADERS) $(CC) $(CFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $< +$(CXX_OBJS): %.o: %.cpp $(HEADERS) + $(CXX) $(CFLAGS) $(CXXFLAGS) $(INCLUDES) -include sys/cdefs.h -c -o $@ $< + .PHONY: clean clean: - rm -f $(CLEAN_OBJS) + rm -f $(CLEAN_OBJS) $(LIBWRAP) endif # _SIFIVE_MK_COMMON diff --git a/raven/bsp/env/coreip-e2-arty/flash.lds b/raven/bsp/env/coreip-e2-arty/flash.lds new file mode 100644 index 0000000..2d5eb01 --- /dev/null +++ b/raven/bsp/env/coreip-e2-arty/flash.lds @@ -0,0 +1,161 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/coreip-e2-arty/init.c b/raven/bsp/env/coreip-e2-arty/init.c new file mode 100644 index 0000000..3a4c77c --- /dev/null +++ b/raven/bsp/env/coreip-e2-arty/init.c @@ -0,0 +1,98 @@ +//See LICENSE for license details. +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +#define CPU_FREQ 32000000 +#define XSTR(x) #x +#define STR(x) XSTR(x) + +extern int main(int argc, char** argv); + +unsigned long get_cpu_freq() +{ + return CPU_FREQ; +} + +unsigned long get_timer_freq() +{ + return get_cpu_freq(); +} + +uint64_t get_timer_value() +{ +#if __riscv_xlen == 32 + while (1) { + uint32_t hi = read_csr(mcycleh); + uint32_t lo = read_csr(mcycle); + if (hi == read_csr(mcycleh)) + return ((uint64_t)hi << 32) | lo; + } +#else + return read_csr(mcycle); +#endif +} + +static void uart_init(size_t baud_rate) +{ + UART0_REG(UART_REG_DIV) = (get_cpu_freq() ) / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + +typedef void (*interrupt_function_ptr_t) (void); +interrupt_function_ptr_t localISR[CLIC_NUM_INTERRUPTS] __attribute__((aligned(64))); + + +void trap_entry(void) __attribute__((interrupt, aligned(64))); +void trap_entry(void) +{ + unsigned long mcause = read_csr(mcause); + unsigned long mepc = read_csr(mepc); + if (mcause & MCAUSE_INT) { + localISR[mcause & MCAUSE_CAUSE] (); + } else { + while(1); + } +} + +#ifdef CLIC_DIRECT +#else +void default_handler(void)__attribute__((interrupt));; +#endif +void default_handler(void) +{ + puts("default handler\n"); + while(1); +} + +void _init() +{ +#ifndef NO_INIT + uart_init(115200); + + puts("core freq at " STR(CPU_FREQ) " Hz\n"); + +//initialize vector table + int i=0; + while(iflash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/coreip-e2-arty/tim.lds b/raven/bsp/env/coreip-e2-arty/tim.lds new file mode 100644 index 0000000..7dfb36b --- /dev/null +++ b/raven/bsp/env/coreip-e2-arty/tim.lds @@ -0,0 +1,161 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K +} + +PHDRS +{ + ram PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 1K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >ram AT>ram :ram + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >ram AT>ram :ram + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >ram AT>ram :ram + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >ram AT>ram :ram + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>ram :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack : + { + . = ALIGN(8); + . += __stack_size; + PROVIDE( _sp = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/coreplexip-arty.h b/raven/bsp/env/coreplexip-arty.h new file mode 100644 index 0000000..eedcaa5 --- /dev/null +++ b/raven/bsp/env/coreplexip-arty.h @@ -0,0 +1,102 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_COREPLEXIP_ARTY_H +#define _SIFIVE_COREPLEXIP_ARTY_H + +#include + +/**************************************************************************** + * GPIO Connections + *****************************************************************************/ + +// These are the GPIO bit offsets for the directly driven +// RGB LEDs on the Freedom Exx Coreplex IP Evaluation Arty FPGA Dev Kit. +// Additional RGB LEDs are driven by the 3 PWM outputs. + +#define RED_LED_OFFSET 0 +#define GREEN_LED_OFFSET 1 +#define BLUE_LED_OFFSET 2 + +// Switch 3 is used as a GPIO input. (Switch 0 is used to set +// the reset vector, the other switches are unused). + +#define SW_3_OFFSET 3 + +// These are the buttons which are mapped as inputs. + +#define HAS_BOARD_BUTTONS + +#define BUTTON_0_OFFSET 4 +#define BUTTON_1_OFFSET 5 +#define BUTTON_2_OFFSET 6 +#define BUTTON_3_OFFSET 7 + +// These are the bit offsets for the different GPIO pins +// mapped onto the PMOD A header. + +#define JA_0_OFFSET 8 +#define JA_1_OFFSET 9 +#define JA_2_OFFSET 10 +#define JA_3_OFFSET 11 +#define JA_4_OFFSET 12 +#define JA_5_OFFSET 13 +#define JA_6_OFFSET 14 +#define JA_7_OFFSET 15 + +// The below gives a mapping between global interrupt +// sources and their number. Note that on the coreplex +// deliverable, the io_global_interrupts go directly into +// the PLIC. The evaluation image on the FPGA mimics a +// system with peripheral devices which are driving the +// global interrupt lines. +// So, on this image, in order to get an interrupt from +// e.g. pressing BUTTON_0: +// 1) Steps which are external to the delivery coreplex: +// a) The corresponding GPIO pin must be configured as in input +// b) The "interrupt on fall" bit must be set for the GPIO pin +// 2) Steps which would also need to be performed for the delivery coreplex: +// a) The corresponding global interrupt, priority, and threshold must be configured in the PLIC. +// b) The external interrupt bit must be enabled in MSTATUS +// c) Interrupts must be enabled globally in the core. + +// Any of the above GPIO pins can be used as global interrupt +// sources by adding their offset to the INT_GPIO_BASE. +// For example, the buttons are shown here: + +#define INT_DEVICE_BUTTON_0 (GPIO_INT_BASE + BUTTON_0_OFFSET) +#define INT_DEVICE_BUTTON_1 (GPIO_INT_BASE + BUTTON_1_OFFSET) +#define INT_DEVICE_BUTTON_2 (GPIO_INT_BASE + BUTTON_2_OFFSET) +#define INT_DEVICE_BUTTON_3 (GPIO_INT_BASE + BUTTON_3_OFFSET) + +// In addition, the Switches are mapped directly to +// the PLIC (without going through the GPIO Peripheral). + +#define INT_EXT_DEVICE_SW_0 (EXTERNAL_INT_BASE + 0) +#define INT_EXT_DEVICE_SW_1 (EXTERNAL_INT_BASE + 1) +#define INT_EXT_DEVICE_SW_2 (EXTERNAL_INT_BASE + 2) +#define INT_EXT_DEVICE_SW_3 (EXTERNAL_INT_BASE + 3) + +// This gives the mapping from inputs to LOCAL interrupts. + +#define LOCAL_INT_SW_0 0 +#define LOCAL_INT_SW_1 1 +#define LOCAL_INT_SW_2 2 +#define LOCAL_INT_SW_3 3 +#define LOCAL_INT_BTN_0 4 +#define LOCAL_INT_BTN_1 5 +#define LOCAL_INT_BTN_2 6 +#define LOCAL_INT_BTN_3 7 +#define LOCAL_INT_JA_0 8 +#define LOCAL_INT_JA_1 9 +#define LOCAL_INT_JA_2 10 +#define LOCAL_INT_JA_3 11 +#define LOCAL_INT_JA_4 12 +#define LOCAL_INT_JA_5 13 +#define LOCAL_INT_JA_6 14 +#define LOCAL_INT_JA_7 15 + +#define RTC_FREQ 32768 + +void write_hex(int fd, unsigned long int hex); + +#endif /* _SIFIVE_COREPLEXIP_ARTY_H */ diff --git a/raven/bsp/env/coreplexip-e31-arty/dhrystone.lds b/raven/bsp/env/coreplexip-e31-arty/dhrystone.lds new file mode 100644 index 0000000..8f6527b --- /dev/null +++ b/raven/bsp/env/coreplexip-e31-arty/dhrystone.lds @@ -0,0 +1,157 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 1K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/coreplexip-e31-arty/flash.lds b/raven/bsp/env/coreplexip-e31-arty/flash.lds new file mode 100644 index 0000000..590c5b6 --- /dev/null +++ b/raven/bsp/env/coreplexip-e31-arty/flash.lds @@ -0,0 +1,161 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/coreplexip-e31-arty/init.c b/raven/bsp/env/coreplexip-e31-arty/init.c new file mode 100644 index 0000000..1f8b679 --- /dev/null +++ b/raven/bsp/env/coreplexip-e31-arty/init.c @@ -0,0 +1,122 @@ +//See LICENSE for license details. +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +#define CPU_FREQ 65000000 +#define XSTR(x) #x +#define STR(x) XSTR(x) + +#ifndef VECT_IRQ + #define TRAP_ENTRY trap_entry +#else + #define TRAP_ENTRY vtrap_entry +#endif + +extern int main(int argc, char** argv); +extern void TRAP_ENTRY(); + +unsigned long get_cpu_freq() +{ + return CPU_FREQ; +} + +unsigned long get_timer_freq() +{ + return get_cpu_freq(); +} + +uint64_t get_timer_value() +{ +#if __riscv_xlen == 32 + while (1) { + uint32_t hi = read_csr(mcycleh); + uint32_t lo = read_csr(mcycle); + if (hi == read_csr(mcycleh)) + return ((uint64_t)hi << 32) | lo; + } +#else + return read_csr(mcycle); +#endif +} + +static void uart_init(size_t baud_rate) +{ + UART0_REG(UART_REG_DIV) = (get_cpu_freq() / 2) / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +#ifdef USE_LOCAL_ISR +typedef void (*my_interrupt_function_ptr_t) (void); +extern my_interrupt_function_ptr_t localISR[]; +#endif + +#ifndef VECT_IRQ +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) __attribute__((noinline)); +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif +#ifdef USE_LOCAL_ISR + } else if (mcause & MCAUSE_INT) { + localISR[mcause & MCAUSE_CAUSE] (); +#endif + } + else { + write(1, "Unhandled Trap:\n", 16); + _exit(1 + mcause); + } + return epc; +} +#endif + +#ifdef USE_CLIC +void trap_entry(void) __attribute__((interrupt("SiFive-CLIC-preemptible"), aligned(64))); +void trap_entry(void) +{ + unsigned long mcause = read_csr(mcause); + unsigned long mepc = read_csr(mepc); + handle_trap(mcause, mepc); +} +#endif + +void _init() +{ + #ifndef NO_INIT + uart_init(115200); + + puts("core freq at " STR(CPU_FREQ) " Hz\n"); + +#ifdef USE_CLIC + write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC)); +#else + write_csr(mtvec, ((unsigned long)&TRAP_ENTRY | MTVEC_VECTORED)); +#endif + + #endif +} + +void _fini() +{ +} diff --git a/raven/bsp/env/coreplexip-e31-arty/openocd.cfg b/raven/bsp/env/coreplexip-e31-arty/openocd.cfg new file mode 100644 index 0000000..0481a72 --- /dev/null +++ b/raven/bsp/env/coreplexip-e31-arty/openocd.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/raven/bsp/env/coreplexip-e31-arty/platform.h b/raven/bsp/env/coreplexip-e31-arty/platform.h new file mode 100644 index 0000000..6fa79ea --- /dev/null +++ b/raven/bsp/env/coreplexip-e31-arty/platform.h @@ -0,0 +1,100 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h + +#if __riscv_xlen == 32 +#define MCAUSE_INT 0x80000000UL +#define MCAUSE_CAUSE 0x000003FFUL +#else +#define MCAUSE_INT 0x8000000000000000UL +#define MCAUSE_CAUSE 0x00000000000003FFUL +#endif + +#ifdef VECT_IRQ + #define MTVEC_VECTORED 0x01 +#else + #define MTVEC_VECTORED 0x00 +#endif +#define MTVEC_CLIC 0x02 +#define IRQ_M_LOCAL 16 +#define MIP_MLIP(x) (1 << (IRQ_M_LOCAL + x)) + +#include "sifive/const.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define GPIO_CTRL_ADDR _AC(0x20002000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define PWM0_CTRL_ADDR _AC(0x20005000,UL) +#define RAM_MEM_ADDR _AC(0x80000000,UL) +#define RAM_MEM_SIZE _AC(0x10000,UL) +#define SPI0_CTRL_ADDR _AC(0x20004000,UL) +#define SPI0_MEM_ADDR _AC(0x40000000,UL) +#define SPI0_MEM_SIZE _AC(0x20000000,UL) +#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL) +#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define UART0_CTRL_ADDR _AC(0x20000000,UL) + +// IOF masks + +// Interrupt numbers +#define RESERVED_INT_BASE 0 +#define UART0_INT_BASE 1 +#define EXTERNAL_INT_BASE 2 +#define SPI0_INT_BASE 6 +#define GPIO_INT_BASE 7 +#define PWM0_INT_BASE 23 + +// Helper functions +#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i))) +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) +#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i))) +// Bulk set bits in `reg` to either 0 or 1. +// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7 +// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7 +#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); } +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define TRAPVEC_TABLE_REG(offset) _REG32(TRAPVEC_TABLE_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset) +#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset) +#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset) +#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset) +#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset) +#define TRAPVEC_TABLE_REG64(offset) _REG64(TRAPVEC_TABLE_CTRL_ADDR, offset) +#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset) + +// Misc + +#define NUM_GPIO 16 + +#define PLIC_NUM_INTERRUPTS 28 +#define PLIC_NUM_PRIORITIES 7 + +#define HAS_BOARD_BUTTONS + +#include "coreplexip-arty.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/raven/bsp/env/coreplexip-e31-arty/scratchpad.lds b/raven/bsp/env/coreplexip-e31-arty/scratchpad.lds new file mode 100644 index 0000000..7887c13 --- /dev/null +++ b/raven/bsp/env/coreplexip-e31-arty/scratchpad.lds @@ -0,0 +1,161 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + ram PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 1K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >ram AT>ram :ram + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >ram AT>ram :ram + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >ram AT>ram :ram + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >ram AT>ram :ram + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>ram :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack : + { + . = ALIGN(8); + . += __stack_size; + PROVIDE( _sp = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/coreplexip-e31-arty/settings.mk b/raven/bsp/env/coreplexip-e31-arty/settings.mk new file mode 100644 index 0000000..230fccc --- /dev/null +++ b/raven/bsp/env/coreplexip-e31-arty/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv32imac +RISCV_ABI := ilp32 diff --git a/raven/bsp/env/coreplexip-e51-arty/dhrystone.lds b/raven/bsp/env/coreplexip-e51-arty/dhrystone.lds new file mode 100644 index 0000000..8f6527b --- /dev/null +++ b/raven/bsp/env/coreplexip-e51-arty/dhrystone.lds @@ -0,0 +1,157 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 1K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/coreplexip-e51-arty/flash.lds b/raven/bsp/env/coreplexip-e51-arty/flash.lds new file mode 100644 index 0000000..590c5b6 --- /dev/null +++ b/raven/bsp/env/coreplexip-e51-arty/flash.lds @@ -0,0 +1,161 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/coreplexip-e51-arty/init.c b/raven/bsp/env/coreplexip-e51-arty/init.c new file mode 100644 index 0000000..1f8b679 --- /dev/null +++ b/raven/bsp/env/coreplexip-e51-arty/init.c @@ -0,0 +1,122 @@ +//See LICENSE for license details. +#include +#include +#include + +#include "platform.h" +#include "encoding.h" + +#define CPU_FREQ 65000000 +#define XSTR(x) #x +#define STR(x) XSTR(x) + +#ifndef VECT_IRQ + #define TRAP_ENTRY trap_entry +#else + #define TRAP_ENTRY vtrap_entry +#endif + +extern int main(int argc, char** argv); +extern void TRAP_ENTRY(); + +unsigned long get_cpu_freq() +{ + return CPU_FREQ; +} + +unsigned long get_timer_freq() +{ + return get_cpu_freq(); +} + +uint64_t get_timer_value() +{ +#if __riscv_xlen == 32 + while (1) { + uint32_t hi = read_csr(mcycleh); + uint32_t lo = read_csr(mcycle); + if (hi == read_csr(mcycleh)) + return ((uint64_t)hi << 32) | lo; + } +#else + return read_csr(mcycle); +#endif +} + +static void uart_init(size_t baud_rate) +{ + UART0_REG(UART_REG_DIV) = (get_cpu_freq() / 2) / baud_rate - 1; + UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; +} + + +#ifdef USE_PLIC +extern void handle_m_ext_interrupt(); +#endif + +#ifdef USE_M_TIME +extern void handle_m_time_interrupt(); +#endif + +#ifdef USE_LOCAL_ISR +typedef void (*my_interrupt_function_ptr_t) (void); +extern my_interrupt_function_ptr_t localISR[]; +#endif + +#ifndef VECT_IRQ +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) __attribute__((noinline)); +uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) +{ + if (0){ +#ifdef USE_PLIC + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { + handle_m_ext_interrupt(); +#endif +#ifdef USE_M_TIME + // External Machine-Level interrupt from PLIC + } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ + handle_m_time_interrupt(); +#endif +#ifdef USE_LOCAL_ISR + } else if (mcause & MCAUSE_INT) { + localISR[mcause & MCAUSE_CAUSE] (); +#endif + } + else { + write(1, "Unhandled Trap:\n", 16); + _exit(1 + mcause); + } + return epc; +} +#endif + +#ifdef USE_CLIC +void trap_entry(void) __attribute__((interrupt("SiFive-CLIC-preemptible"), aligned(64))); +void trap_entry(void) +{ + unsigned long mcause = read_csr(mcause); + unsigned long mepc = read_csr(mepc); + handle_trap(mcause, mepc); +} +#endif + +void _init() +{ + #ifndef NO_INIT + uart_init(115200); + + puts("core freq at " STR(CPU_FREQ) " Hz\n"); + +#ifdef USE_CLIC + write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC)); +#else + write_csr(mtvec, ((unsigned long)&TRAP_ENTRY | MTVEC_VECTORED)); +#endif + + #endif +} + +void _fini() +{ +} diff --git a/raven/bsp/env/coreplexip-e51-arty/openocd.cfg b/raven/bsp/env/coreplexip-e51-arty/openocd.cfg new file mode 100644 index 0000000..0481a72 --- /dev/null +++ b/raven/bsp/env/coreplexip-e51-arty/openocd.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/raven/bsp/env/coreplexip-e51-arty/platform.h b/raven/bsp/env/coreplexip-e51-arty/platform.h new file mode 100644 index 0000000..6fa79ea --- /dev/null +++ b/raven/bsp/env/coreplexip-e51-arty/platform.h @@ -0,0 +1,100 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_PLATFORM_H +#define _SIFIVE_PLATFORM_H + +// Some things missing from the official encoding.h + +#if __riscv_xlen == 32 +#define MCAUSE_INT 0x80000000UL +#define MCAUSE_CAUSE 0x000003FFUL +#else +#define MCAUSE_INT 0x8000000000000000UL +#define MCAUSE_CAUSE 0x00000000000003FFUL +#endif + +#ifdef VECT_IRQ + #define MTVEC_VECTORED 0x01 +#else + #define MTVEC_VECTORED 0x00 +#endif +#define MTVEC_CLIC 0x02 +#define IRQ_M_LOCAL 16 +#define MIP_MLIP(x) (1 << (IRQ_M_LOCAL + x)) + +#include "sifive/const.h" +#include "sifive/devices/clint.h" +#include "sifive/devices/gpio.h" +#include "sifive/devices/plic.h" +#include "sifive/devices/pwm.h" +#include "sifive/devices/spi.h" +#include "sifive/devices/uart.h" + +/**************************************************************************** + * Platform definitions + *****************************************************************************/ + +// Memory map +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define GPIO_CTRL_ADDR _AC(0x20002000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define PWM0_CTRL_ADDR _AC(0x20005000,UL) +#define RAM_MEM_ADDR _AC(0x80000000,UL) +#define RAM_MEM_SIZE _AC(0x10000,UL) +#define SPI0_CTRL_ADDR _AC(0x20004000,UL) +#define SPI0_MEM_ADDR _AC(0x40000000,UL) +#define SPI0_MEM_SIZE _AC(0x20000000,UL) +#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL) +#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define UART0_CTRL_ADDR _AC(0x20000000,UL) + +// IOF masks + +// Interrupt numbers +#define RESERVED_INT_BASE 0 +#define UART0_INT_BASE 1 +#define EXTERNAL_INT_BASE 2 +#define SPI0_INT_BASE 6 +#define GPIO_INT_BASE 7 +#define PWM0_INT_BASE 23 + +// Helper functions +#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i))) +#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i))) +#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i))) +// Bulk set bits in `reg` to either 0 or 1. +// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7 +// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7 +#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); } +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define TRAPVEC_TABLE_REG(offset) _REG32(TRAPVEC_TABLE_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset) +#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset) +#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset) +#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset) +#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset) +#define TRAPVEC_TABLE_REG64(offset) _REG64(TRAPVEC_TABLE_CTRL_ADDR, offset) +#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset) + +// Misc + +#define NUM_GPIO 16 + +#define PLIC_NUM_INTERRUPTS 28 +#define PLIC_NUM_PRIORITIES 7 + +#define HAS_BOARD_BUTTONS + +#include "coreplexip-arty.h" + +unsigned long get_cpu_freq(void); +unsigned long get_timer_freq(void); +uint64_t get_timer_value(void); + +#endif /* _SIFIVE_PLATFORM_H */ diff --git a/raven/bsp/env/coreplexip-e51-arty/scratchpad.lds b/raven/bsp/env/coreplexip-e51-arty/scratchpad.lds new file mode 100644 index 0000000..7887c13 --- /dev/null +++ b/raven/bsp/env/coreplexip-e51-arty/scratchpad.lds @@ -0,0 +1,161 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + ram PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 1K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >ram AT>ram :ram + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >ram AT>ram :ram + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >ram AT>ram :ram + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >ram AT>ram :ram + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>ram :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack : + { + . = ALIGN(8); + . += __stack_size; + PROVIDE( _sp = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram +} diff --git a/raven/bsp/env/coreplexip-e51-arty/settings.mk b/raven/bsp/env/coreplexip-e51-arty/settings.mk new file mode 100644 index 0000000..96aea84 --- /dev/null +++ b/raven/bsp/env/coreplexip-e51-arty/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv64imac +RISCV_ABI := lp64 diff --git a/raven/bsp/env/entry.S b/raven/bsp/env/entry.S index 1f5de24..261b2a4 100644 --- a/raven/bsp/env/entry.S +++ b/raven/bsp/env/entry.S @@ -8,6 +8,7 @@ .section .text.entry .align 2 + .weak trap_entry .global trap_entry trap_entry: addi sp, sp, -32*REGBYTES diff --git a/raven/bsp/env/freedom-e300-arty/link.lds b/raven/bsp/env/freedom-e300-arty/flash.lds similarity index 96% rename from raven/bsp/env/freedom-e300-arty/link.lds rename to raven/bsp/env/freedom-e300-arty/flash.lds index 90e5c8f..6b37141 100644 --- a/raven/bsp/env/freedom-e300-arty/link.lds +++ b/raven/bsp/env/freedom-e300-arty/flash.lds @@ -120,11 +120,11 @@ SECTIONS { *(.data .data.*) *(.gnu.linkonce.d.*) - } >ram AT>flash :ram_init - - .srodata : - { - PROVIDE( _gp = . + 0x800 ); + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) @@ -132,12 +132,6 @@ SECTIONS *(.srodata .srodata.*) } >ram AT>flash :ram_init - .sdata : - { - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - } >ram AT>flash :ram_init - . = ALIGN(4); PROVIDE( _edata = . ); PROVIDE( edata = . ); diff --git a/raven/bsp/env/freedom-e300-arty/platform.h b/raven/bsp/env/freedom-e300-arty/platform.h index d5d6dda..8ff7ae6 100644 --- a/raven/bsp/env/freedom-e300-arty/platform.h +++ b/raven/bsp/env/freedom-e300-arty/platform.h @@ -20,21 +20,21 @@ * Platform definitions *****************************************************************************/ -#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) -#define CLINT_BASE_ADDR _AC(0x02000000,UL) -#define PLIC_BASE_ADDR _AC(0x0C000000,UL) -#define AON_BASE_ADDR _AC(0x10000000,UL) -#define GPIO_BASE_ADDR _AC(0x10012000,UL) -#define UART0_BASE_ADDR _AC(0x10013000,UL) -#define SPI0_BASE_ADDR _AC(0x10014000,UL) -#define PWM0_BASE_ADDR _AC(0x10015000,UL) -#define UART1_BASE_ADDR _AC(0x10023000,UL) -#define SPI1_BASE_ADDR _AC(0x10024000,UL) -#define PWM1_BASE_ADDR _AC(0x10025000,UL) -#define SPI2_BASE_ADDR _AC(0x10034000,UL) -#define PWM2_BASE_ADDR _AC(0x10035000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define AON_CTRL_ADDR _AC(0x10000000,UL) +#define GPIO_CTRL_ADDR _AC(0x10012000,UL) +#define UART0_CTRL_ADDR _AC(0x10013000,UL) +#define SPI0_CTRL_ADDR _AC(0x10014000,UL) +#define PWM0_CTRL_ADDR _AC(0x10015000,UL) +#define UART1_CTRL_ADDR _AC(0x10023000,UL) +#define SPI1_CTRL_ADDR _AC(0x10024000,UL) +#define PWM1_CTRL_ADDR _AC(0x10025000,UL) +#define SPI2_CTRL_ADDR _AC(0x10034000,UL) +#define PWM2_CTRL_ADDR _AC(0x10035000,UL) #define SPI0_MMAP_ADDR _AC(0x20000000,UL) -#define MEM_BASE_ADDR _AC(0x80000000,UL) +#define MEM_CTRL_ADDR _AC(0x80000000,UL) // IOF Mappings #define IOF0_SPI1_MASK _AC(0x000007FC,UL) @@ -91,20 +91,19 @@ // Helper functions #define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) #define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) -#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) -#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) -#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) -#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) -#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) -#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) -#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) -#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) -#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) -#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) -#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) -#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) -#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) -#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) +#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset) // Misc diff --git a/raven/bsp/env/freedom-e300-arty/settings.mk b/raven/bsp/env/freedom-e300-arty/settings.mk new file mode 100644 index 0000000..230fccc --- /dev/null +++ b/raven/bsp/env/freedom-e300-arty/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv32imac +RISCV_ABI := ilp32 diff --git a/raven/bsp/env/iss/link.lds b/raven/bsp/env/freedom-e300-hifive1/dhrystone.lds similarity index 92% rename from raven/bsp/env/iss/link.lds rename to raven/bsp/env/freedom-e300-hifive1/dhrystone.lds index bc60026..cc9cd9b 100644 --- a/raven/bsp/env/iss/link.lds +++ b/raven/bsp/env/freedom-e300-hifive1/dhrystone.lds @@ -4,9 +4,8 @@ ENTRY( _start ) MEMORY { - /*flash (rxai!w) : ORIGIN = 0x00000000, LENGTH = 1M*/ flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M - ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K } PHDRS @@ -42,13 +41,6 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); - .rodata : - { - *(.rdata) - *(.rodata .rodata.*) - *(.gnu.linkonce.r.*) - } >flash AT>flash :flash - . = ALIGN(4); .preinit_array : @@ -119,13 +111,16 @@ SECTIONS .data : { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) - } >ram AT>flash :ram_init - - .srodata : - { - PROVIDE( _gp = . + 0x800 ); + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) @@ -133,12 +128,6 @@ SECTIONS *(.srodata .srodata.*) } >ram AT>flash :ram_init - .sdata : - { - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - } >ram AT>flash :ram_init - . = ALIGN(4); PROVIDE( _edata = . ); PROVIDE( edata = . ); diff --git a/raven/bsp/env/freedom-e300-hifive1/link.lds b/raven/bsp/env/freedom-e300-hifive1/flash.lds similarity index 96% rename from raven/bsp/env/freedom-e300-hifive1/link.lds rename to raven/bsp/env/freedom-e300-hifive1/flash.lds index 90e5c8f..6b37141 100644 --- a/raven/bsp/env/freedom-e300-hifive1/link.lds +++ b/raven/bsp/env/freedom-e300-hifive1/flash.lds @@ -120,11 +120,11 @@ SECTIONS { *(.data .data.*) *(.gnu.linkonce.d.*) - } >ram AT>flash :ram_init - - .srodata : - { - PROVIDE( _gp = . + 0x800 ); + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) @@ -132,12 +132,6 @@ SECTIONS *(.srodata .srodata.*) } >ram AT>flash :ram_init - .sdata : - { - *(.sdata .sdata.*) - *(.gnu.linkonce.s.*) - } >ram AT>flash :ram_init - . = ALIGN(4); PROVIDE( _edata = . ); PROVIDE( edata = . ); diff --git a/raven/bsp/env/freedom-e300-hifive1/init.c b/raven/bsp/env/freedom-e300-hifive1/init.c index de046cc..621a6e2 100644 --- a/raven/bsp/env/freedom-e300-hifive1/init.c +++ b/raven/bsp/env/freedom-e300-hifive1/init.c @@ -10,14 +10,14 @@ extern void trap_entry(); static unsigned long mtime_lo(void) { - return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); + return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME); } #ifdef __riscv32 static uint32_t mtime_hi(void) { - return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); + return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4); } uint64_t get_timer_value() diff --git a/raven/bsp/env/freedom-e300-hifive1/platform.h b/raven/bsp/env/freedom-e300-hifive1/platform.h index 63efc9e..806fcfc 100644 --- a/raven/bsp/env/freedom-e300-hifive1/platform.h +++ b/raven/bsp/env/freedom-e300-hifive1/platform.h @@ -23,25 +23,25 @@ *****************************************************************************/ // Memory map -#define MASKROM_BASE_ADDR _AC(0x00001000,UL) -#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) -#define OTP_MMAP_ADDR _AC(0x00020000,UL) -#define CLINT_BASE_ADDR _AC(0x02000000,UL) -#define PLIC_BASE_ADDR _AC(0x0C000000,UL) -#define AON_BASE_ADDR _AC(0x10000000,UL) -#define PRCI_BASE_ADDR _AC(0x10008000,UL) -#define OTP_BASE_ADDR _AC(0x10010000,UL) -#define GPIO_BASE_ADDR _AC(0x10012000,UL) -#define UART0_BASE_ADDR _AC(0x10013000,UL) -#define SPI0_BASE_ADDR _AC(0x10014000,UL) -#define PWM0_BASE_ADDR _AC(0x10015000,UL) -#define UART1_BASE_ADDR _AC(0x10023000,UL) -#define SPI1_BASE_ADDR _AC(0x10024000,UL) -#define PWM1_BASE_ADDR _AC(0x10025000,UL) -#define SPI2_BASE_ADDR _AC(0x10034000,UL) -#define PWM2_BASE_ADDR _AC(0x10035000,UL) -#define SPI0_MMAP_ADDR _AC(0x20000000,UL) -#define MEM_BASE_ADDR _AC(0x80000000,UL) +#define MASKROM_MEM_ADDR _AC(0x00001000,UL) +#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL) +#define OTP_MEM_ADDR _AC(0x00020000,UL) +#define CLINT_CTRL_ADDR _AC(0x02000000,UL) +#define PLIC_CTRL_ADDR _AC(0x0C000000,UL) +#define AON_CTRL_ADDR _AC(0x10000000,UL) +#define PRCI_CTRL_ADDR _AC(0x10008000,UL) +#define OTP_CTRL_ADDR _AC(0x10010000,UL) +#define GPIO_CTRL_ADDR _AC(0x10012000,UL) +#define UART0_CTRL_ADDR _AC(0x10013000,UL) +#define SPI0_CTRL_ADDR _AC(0x10014000,UL) +#define PWM0_CTRL_ADDR _AC(0x10015000,UL) +#define UART1_CTRL_ADDR _AC(0x10023000,UL) +#define SPI1_CTRL_ADDR _AC(0x10024000,UL) +#define PWM1_CTRL_ADDR _AC(0x10025000,UL) +#define SPI2_CTRL_ADDR _AC(0x10034000,UL) +#define PWM2_CTRL_ADDR _AC(0x10035000,UL) +#define SPI0_MEM_ADDR _AC(0x20000000,UL) +#define MEM_CTRL_ADDR _AC(0x80000000,UL) // IOF masks #define IOF0_SPI1_MASK _AC(0x000007FC,UL) @@ -100,20 +100,20 @@ // Helper functions #define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) #define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) -#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) -#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) -#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) -#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) -#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) -#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) -#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) -#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) -#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) -#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) -#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) -#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) -#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) -#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) +#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset) +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset) +#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset) +#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset) +#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset) +#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset) +#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset) +#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset) +#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset) +#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset) +#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset) +#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset) +#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset) // Misc diff --git a/raven/bsp/env/freedom-e300-hifive1/settings.mk b/raven/bsp/env/freedom-e300-hifive1/settings.mk new file mode 100644 index 0000000..230fccc --- /dev/null +++ b/raven/bsp/env/freedom-e300-hifive1/settings.mk @@ -0,0 +1,3 @@ +# Describes the CPU on this board to the rest of the SDK. +RISCV_ARCH := rv32imac +RISCV_ABI := ilp32 diff --git a/raven/bsp/env/hifive1.h b/raven/bsp/env/hifive1.h index cfd7099..0db2f0f 100644 --- a/raven/bsp/env/hifive1.h +++ b/raven/bsp/env/hifive1.h @@ -76,4 +76,6 @@ #define RTC_FREQ 32768 +void write_hex(int fd, unsigned long int hex); + #endif /* _SIFIVE_HIFIVE1_H */ diff --git a/raven/bsp/env/iss/init.c b/raven/bsp/env/iss/init.c deleted file mode 100644 index de046cc..0000000 --- a/raven/bsp/env/iss/init.c +++ /dev/null @@ -1,238 +0,0 @@ -#include -#include -#include - -#include "platform.h" -#include "encoding.h" - -extern int main(int argc, char** argv); -extern void trap_entry(); - -static unsigned long mtime_lo(void) -{ - return *(volatile unsigned long *)(CLINT_BASE_ADDR + CLINT_MTIME); -} - -#ifdef __riscv32 - -static uint32_t mtime_hi(void) -{ - return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME + 4); -} - -uint64_t get_timer_value() -{ - while (1) { - uint32_t hi = mtime_hi(); - uint32_t lo = mtime_lo(); - if (hi == mtime_hi()) - return ((uint64_t)hi << 32) | lo; - } -} - -#else /* __riscv32 */ - -uint64_t get_timer_value() -{ - return mtime_lo(); -} - -#endif - -unsigned long get_timer_freq() -{ - return 32768; -} - -static void use_hfrosc(int div, int trim) -{ - // Make sure the HFROSC is running at its default setting - PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1)); - while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ; - PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1); -} - -static void use_pll(int refsel, int bypass, int r, int f, int q) -{ - // Ensure that we aren't running off the PLL before we mess with it. - if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) { - // Make sure the HFROSC is running at its default setting - use_hfrosc(4, 16); - } - - // Set PLL Source to be HFXOSC if available. - uint32_t config_value = 0; - - config_value |= PLL_REFSEL(refsel); - - if (bypass) { - // Bypass - config_value |= PLL_BYPASS(1); - - PRCI_REG(PRCI_PLLCFG) = config_value; - - // If we don't have an HFXTAL, this doesn't really matter. - // Set our Final output divide to divide-by-1: - PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); - } else { - // In case we are executing from QSPI, - // (which is quite likely) we need to - // set the QSPI clock divider appropriately - // before boosting the clock frequency. - - // Div = f_sck/2 - SPI0_REG(SPI_REG_SCKDIV) = 8; - - // Set DIV Settings for PLL - // Both HFROSC and HFXOSC are modeled as ideal - // 16MHz sources (assuming dividers are set properly for - // HFROSC). - // (Legal values of f_REF are 6-48MHz) - - // Set DIVR to divide-by-2 to get 8MHz frequency - // (legal values of f_R are 6-12 MHz) - - config_value |= PLL_BYPASS(1); - config_value |= PLL_R(r); - - // Set DIVF to get 512Mhz frequncy - // There is an implied multiply-by-2, 16Mhz. - // So need to write 32-1 - // (legal values of f_F are 384-768 MHz) - config_value |= PLL_F(f); - - // Set DIVQ to divide-by-2 to get 256 MHz frequency - // (legal values of f_Q are 50-400Mhz) - config_value |= PLL_Q(q); - - // Set our Final output divide to divide-by-1: - PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); - - PRCI_REG(PRCI_PLLCFG) = config_value; - - // Un-Bypass the PLL. - PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1); - - // Wait for PLL Lock - // Note that the Lock signal can be glitchy. - // Need to wait 100 us - // RTC is running at 32kHz. - // So wait 4 ticks of RTC. - uint32_t now = mtime_lo(); - while (mtime_lo() - now < 4) ; - - // Now it is safe to check for PLL Lock - while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ; - } - - // Switch over to PLL Clock source - PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); -} - -static void use_default_clocks() -{ - // Turn off the LFROSC - AON_REG(AON_LFROSC) &= ~ROSC_EN(1); - - // Use HFROSC - use_hfrosc(4, 16); -} - -static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n) -{ - unsigned long start_mtime, delta_mtime; - unsigned long mtime_freq = get_timer_freq(); - - // Don't start measuruing until we see an mtime tick - unsigned long tmp = mtime_lo(); - do { - start_mtime = mtime_lo(); - } while (start_mtime == tmp); - - unsigned long start_mcycle = read_csr(mcycle); - - do { - delta_mtime = mtime_lo() - start_mtime; - } while (delta_mtime < n); - - unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle; - - return (delta_mcycle / delta_mtime) * mtime_freq - + ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime; -} - -unsigned long get_cpu_freq() -{ - static uint32_t cpu_freq; - - if (!cpu_freq) { - // warm up I$ - measure_cpu_freq(1); - // measure for real - cpu_freq = measure_cpu_freq(10); - } - - return cpu_freq; -} - -static void uart_init(size_t baud_rate) -{ - GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; - GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; - UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1; - UART0_REG(UART_REG_TXCTRL) |= UART_TXEN; -} - - - -#ifdef USE_PLIC -extern void handle_m_ext_interrupt(); -#endif - -#ifdef USE_M_TIME -extern void handle_m_time_interrupt(); -#endif - -uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) -{ - if (0){ -#ifdef USE_PLIC - // External Machine-Level interrupt from PLIC - } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) { - handle_m_ext_interrupt(); -#endif -#ifdef USE_M_TIME - // External Machine-Level interrupt from PLIC - } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){ - handle_m_time_interrupt(); -#endif - } - else { - write(1, "trap\n", 5); - _exit(1 + mcause); - } - return epc; -} - -void _init() -{ - - #ifndef NO_INIT - use_default_clocks(); - use_pll(0, 0, 1, 31, 1); - uart_init(115200); - - printf("core freq at %d Hz\n", get_cpu_freq()); - - write_csr(mtvec, &trap_entry); - if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present - write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping - write_csr(fcsr, 0); // initialize rounding mode, undefined at reset - } - #endif - -} - -void _fini() -{ -} diff --git a/raven/bsp/env/iss/openocd.cfg b/raven/bsp/env/iss/openocd.cfg deleted file mode 100644 index b531e9c..0000000 --- a/raven/bsp/env/iss/openocd.cfg +++ /dev/null @@ -1,34 +0,0 @@ -adapter_khz 10000 - -interface ftdi -ftdi_device_desc "Dual RS232-HS" -ftdi_vid_pid 0x0403 0x6010 - -ftdi_layout_init 0x0008 0x001b -ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 - -#Reset Stretcher logic on FE310 is ~1 second long -#This doesn't apply if you use -# ftdi_set_signal, but still good to document -#adapter_nsrst_delay 1500 - -set _CHIPNAME riscv -jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME riscv -chain-position $_TARGETNAME -$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 - -flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME -init -#reset -- This type of reset is not implemented yet -if {[ info exists pulse_srst]} { - ftdi_set_signal nSRST 0 - ftdi_set_signal nSRST z - #Wait for the reset stretcher - #It will work without this, but - #will incur lots of delays for later commands. - sleep 1500 -} -halt -#flash protect 0 64 last off diff --git a/raven/bsp/env/iss/platform.h b/raven/bsp/env/iss/platform.h deleted file mode 100644 index 63efc9e..0000000 --- a/raven/bsp/env/iss/platform.h +++ /dev/null @@ -1,133 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_PLATFORM_H -#define _SIFIVE_PLATFORM_H - -// Some things missing from the official encoding.h -#define MCAUSE_INT 0x80000000 -#define MCAUSE_CAUSE 0x7FFFFFFF - -#include "sifive/const.h" -#include "sifive/devices/aon.h" -#include "sifive/devices/clint.h" -#include "sifive/devices/gpio.h" -#include "sifive/devices/otp.h" -#include "sifive/devices/plic.h" -#include "sifive/devices/prci.h" -#include "sifive/devices/pwm.h" -#include "sifive/devices/spi.h" -#include "sifive/devices/uart.h" - -/**************************************************************************** - * Platform definitions - *****************************************************************************/ - -// Memory map -#define MASKROM_BASE_ADDR _AC(0x00001000,UL) -#define TRAPVEC_TABLE_BASE_ADDR _AC(0x00001010,UL) -#define OTP_MMAP_ADDR _AC(0x00020000,UL) -#define CLINT_BASE_ADDR _AC(0x02000000,UL) -#define PLIC_BASE_ADDR _AC(0x0C000000,UL) -#define AON_BASE_ADDR _AC(0x10000000,UL) -#define PRCI_BASE_ADDR _AC(0x10008000,UL) -#define OTP_BASE_ADDR _AC(0x10010000,UL) -#define GPIO_BASE_ADDR _AC(0x10012000,UL) -#define UART0_BASE_ADDR _AC(0x10013000,UL) -#define SPI0_BASE_ADDR _AC(0x10014000,UL) -#define PWM0_BASE_ADDR _AC(0x10015000,UL) -#define UART1_BASE_ADDR _AC(0x10023000,UL) -#define SPI1_BASE_ADDR _AC(0x10024000,UL) -#define PWM1_BASE_ADDR _AC(0x10025000,UL) -#define SPI2_BASE_ADDR _AC(0x10034000,UL) -#define PWM2_BASE_ADDR _AC(0x10035000,UL) -#define SPI0_MMAP_ADDR _AC(0x20000000,UL) -#define MEM_BASE_ADDR _AC(0x80000000,UL) - -// IOF masks -#define IOF0_SPI1_MASK _AC(0x000007FC,UL) -#define SPI11_NUM_SS (4) -#define IOF_SPI1_SS0 (2u) -#define IOF_SPI1_SS1 (8u) -#define IOF_SPI1_SS2 (9u) -#define IOF_SPI1_SS3 (10u) -#define IOF_SPI1_MOSI (3u) -#define IOF_SPI1_MISO (4u) -#define IOF_SPI1_SCK (5u) -#define IOF_SPI1_DQ0 (3u) -#define IOF_SPI1_DQ1 (4u) -#define IOF_SPI1_DQ2 (6u) -#define IOF_SPI1_DQ3 (7u) - -#define IOF0_SPI2_MASK _AC(0xFC000000,UL) -#define SPI2_NUM_SS (1) -#define IOF_SPI2_SS0 (26u) -#define IOF_SPI2_MOSI (27u) -#define IOF_SPI2_MISO (28u) -#define IOF_SPI2_SCK (29u) -#define IOF_SPI2_DQ0 (27u) -#define IOF_SPI2_DQ1 (28u) -#define IOF_SPI2_DQ2 (30u) -#define IOF_SPI2_DQ3 (31u) - -//#define IOF0_I2C_MASK _AC(0x00003000,UL) - -#define IOF0_UART0_MASK _AC(0x00030000, UL) -#define IOF_UART0_RX (16u) -#define IOF_UART0_TX (17u) - -#define IOF0_UART1_MASK _AC(0x03000000, UL) -#define IOF_UART1_RX (24u) -#define IOF_UART1_TX (25u) - -#define IOF1_PWM0_MASK _AC(0x0000000F, UL) -#define IOF1_PWM1_MASK _AC(0x00780000, UL) -#define IOF1_PWM2_MASK _AC(0x00003C00, UL) - -// Interrupt numbers -#define INT_RESERVED 0 -#define INT_WDOGCMP 1 -#define INT_RTCCMP 2 -#define INT_UART0_BASE 3 -#define INT_UART1_BASE 4 -#define INT_SPI0_BASE 5 -#define INT_SPI1_BASE 6 -#define INT_SPI2_BASE 7 -#define INT_GPIO_BASE 8 -#define INT_PWM0_BASE 40 -#define INT_PWM1_BASE 44 -#define INT_PWM2_BASE 48 - -// Helper functions -#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) -#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) -#define AON_REG(offset) _REG32(AON_BASE_ADDR, offset) -#define CLINT_REG(offset) _REG32(CLINT_BASE_ADDR, offset) -#define GPIO_REG(offset) _REG32(GPIO_BASE_ADDR, offset) -#define OTP_REG(offset) _REG32(OTP_BASE_ADDR, offset) -#define PLIC_REG(offset) _REG32(PLIC_BASE_ADDR, offset) -#define PRCI_REG(offset) _REG32(PRCI_BASE_ADDR, offset) -#define PWM0_REG(offset) _REG32(PWM0_BASE_ADDR, offset) -#define PWM1_REG(offset) _REG32(PWM1_BASE_ADDR, offset) -#define PWM2_REG(offset) _REG32(PWM2_BASE_ADDR, offset) -#define SPI0_REG(offset) _REG32(SPI0_BASE_ADDR, offset) -#define SPI1_REG(offset) _REG32(SPI1_BASE_ADDR, offset) -#define SPI2_REG(offset) _REG32(SPI2_BASE_ADDR, offset) -#define UART0_REG(offset) _REG32(UART0_BASE_ADDR, offset) -#define UART1_REG(offset) _REG32(UART1_BASE_ADDR, offset) - -// Misc - -#include - -#define NUM_GPIO 32 - -#define PLIC_NUM_INTERRUPTS 52 -#define PLIC_NUM_PRIORITIES 7 - -#include "hifive1.h" - -unsigned long get_cpu_freq(void); -unsigned long get_timer_freq(void); -uint64_t get_timer_value(void); - -#endif /* _SIFIVE_PLATFORM_H */ diff --git a/raven/bsp/env/start.S b/raven/bsp/env/start.S index b526411..4e9f665 100644 --- a/raven/bsp/env/start.S +++ b/raven/bsp/env/start.S @@ -1,13 +1,27 @@ // See LICENSE for license details. +#include + +/* This is defined in sifive/platform.h, but that can't be included from + * assembly. */ +#define CLINT_CTRL_ADDR 0x02000000 .section .init .globl _start .type _start,@function _start: - la gp, _gp + .cfi_startproc + .cfi_undefined ra +.option push +.option norelax + la gp, __global_pointer$ +.option pop la sp, _sp +#if defined(ENABLE_SMP) + smp_pause(t0, t1) +#endif + /* Load data section */ la a0, _data_lma la a1, _data @@ -47,8 +61,51 @@ _start: 1: #endif +#if defined(ENABLE_SMP) + smp_resume(t0, t1) + + csrr a0, mhartid + bnez a0, 2f +#endif + + auipc ra, 0 + addi sp, sp, -16 +#if __riscv_xlen == 32 + sw ra, 8(sp) +#else + sd ra, 8(sp) +#endif + /* argc = argv = 0 */ li a0, 0 li a1, 0 call main tail exit +1: + j 1b + +#if defined(ENABLE_SMP) +2: + la t0, trap_entry + csrw mtvec, t0 + + csrr a0, mhartid + la t1, _sp + slli t0, a0, 10 + sub sp, t1, t0 + + auipc ra, 0 + addi sp, sp, -16 +#if __riscv_xlen == 32 + sw ra, 8(sp) +#else + sd ra, 8(sp) +#endif + + call secondary_main + tail exit + +1: + j 1b +#endif + .cfi_endproc diff --git a/raven/bsp/env/ventry.S b/raven/bsp/env/ventry.S new file mode 100644 index 0000000..5c82c48 --- /dev/null +++ b/raven/bsp/env/ventry.S @@ -0,0 +1,288 @@ +// See LICENSE for license details + +#ifndef VENTRY_S +#define VENTRY_S + +#include "encoding.h" +#include "sifive/bits.h" + +#only save caller registers +.macro TRAP_ENTRY + addi sp, sp, -16*REGBYTES + + STORE x1, 0*REGBYTES(sp) + STORE x5, 1*REGBYTES(sp) + STORE x6, 2*REGBYTES(sp) + STORE x7, 3*REGBYTES(sp) + STORE x10, 4*REGBYTES(sp) + STORE x11, 5*REGBYTES(sp) + STORE x12, 6*REGBYTES(sp) + STORE x13, 7*REGBYTES(sp) + STORE x14, 8*REGBYTES(sp) + STORE x15, 9*REGBYTES(sp) + STORE x16, 10*REGBYTES(sp) + STORE x17, 11*REGBYTES(sp) + STORE x28, 12*REGBYTES(sp) + STORE x29, 13*REGBYTES(sp) + STORE x30, 14*REGBYTES(sp) + STORE x31, 15*REGBYTES(sp) +.endm + +#restore caller registers +.macro TRAP_EXIT +# Remain in M-mode after mret + li t0, MSTATUS_MPP + csrs mstatus, t0 + + LOAD x1, 0*REGBYTES(sp) + LOAD x5, 1*REGBYTES(sp) + LOAD x6, 2*REGBYTES(sp) + LOAD x7, 3*REGBYTES(sp) + LOAD x10, 4*REGBYTES(sp) + LOAD x11, 5*REGBYTES(sp) + LOAD x12, 6*REGBYTES(sp) + LOAD x13, 7*REGBYTES(sp) + LOAD x14, 8*REGBYTES(sp) + LOAD x15, 9*REGBYTES(sp) + LOAD x16, 10*REGBYTES(sp) + LOAD x17, 11*REGBYTES(sp) + LOAD x28, 12*REGBYTES(sp) + LOAD x29, 13*REGBYTES(sp) + LOAD x30, 14*REGBYTES(sp) + LOAD x31, 15*REGBYTES(sp) + + addi sp, sp, 16*REGBYTES + mret +.endm + + + +#Vector table for E31/E51 + + .section .text.entry + .align 8 + .global vtrap_entry +vtrap_entry: + j sync_trap + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j vmsi_Handler + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j vmti_Handler + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j vmei_Handler + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j vlip_Handler0 + .align 2 + j vlip_Handler1 + .align 2 + j vlip_Handler2 + .align 2 + j vlip_Handler3 + .align 2 + j vlip_Handler4 + .align 2 + j vlip_Handler5 + .align 2 + j vlip_Handler6 + .align 2 + j vlip_Handler7 + .align 2 + j vlip_Handler8 + .align 2 + j vlip_Handler9 + .align 2 + j vlip_Handler10 + .align 2 + j vlip_Handler11 + .align 2 + j vlip_Handler12 + .align 2 + j vlip_Handler13 + .align 2 + j vlip_Handler14 + .align 2 + j vlip_Handler15 + +#synchronous trap +sync_trap: + TRAP_ENTRY + jal handle_sync_trap + TRAP_EXIT + +#Machine Software Interrupt +vmsi_Handler: + TRAP_ENTRY + jal reserved + TRAP_EXIT + +#Machine Timer Interrupt +vmti_Handler: + TRAP_ENTRY + jal handle_m_time_interrupt + TRAP_EXIT + +#Machine External Interrupt +vmei_Handler: + TRAP_ENTRY + jal handle_m_external_interrupt + TRAP_EXIT + +#LIP0 +vlip_Handler0: + TRAP_ENTRY + jal handle_local_interrupt0 + TRAP_EXIT + +#LIP1 +vlip_Handler1: + TRAP_ENTRY + jal handle_local_interrupt1 + TRAP_EXIT + +#LIP2 +vlip_Handler2: + TRAP_ENTRY + jal handle_local_interrupt2 + TRAP_EXIT + +#LIP3 +vlip_Handler3: + TRAP_ENTRY + jal handle_local_interrupt3 + TRAP_EXIT + +#LIP4 +vlip_Handler4: + TRAP_ENTRY + jal handle_local_interrupt4 + TRAP_EXIT + +#LIP5 +vlip_Handler5: + TRAP_ENTRY + jal handle_local_interrupt5 + TRAP_EXIT + +#LIP6 +vlip_Handler6: + TRAP_ENTRY + jal handle_local_interrupt6 + TRAP_EXIT + +#LIP7 +vlip_Handler7: + TRAP_ENTRY + jal handle_local_interrupt7 + TRAP_EXIT + +#LIP8 +vlip_Handler8: + TRAP_ENTRY + jal handle_local_interrupt8 + TRAP_EXIT + +#LIP9 +vlip_Handler9: + TRAP_ENTRY + jal handle_local_interrupt9 + TRAP_EXIT + +#LIP10 +vlip_Handler10: + TRAP_ENTRY + jal handle_local_interrupt10 + TRAP_EXIT + +#LIP11 +vlip_Handler11: + TRAP_ENTRY + jal handle_local_interrupt11 + TRAP_EXIT + +#LIP12 +vlip_Handler12: + TRAP_ENTRY + jal handle_local_interrupt12 + TRAP_EXIT + +#LIP13 +vlip_Handler13: + TRAP_ENTRY + jal handle_local_interrupt13 + TRAP_EXIT + +#LIP14 +vlip_Handler14: + TRAP_ENTRY + jal handle_local_interrupt14 + TRAP_EXIT + +#LIP15 +vlip_Handler15: + TRAP_ENTRY + jal handle_local_interrupt15 + TRAP_EXIT + +#unimplemented ISRs trap here +.weak reserved +reserved: +.weak handle_local_interrupt0 +handle_local_interrupt0: +.weak handle_local_interrupt1 +handle_local_interrupt1: +.weak handle_local_interrupt2 +handle_local_interrupt2: +.weak handle_local_interrupt3 +handle_local_interrupt3: +.weak handle_local_interrupt4 +handle_local_interrupt4: +.weak handle_local_interrupt5 +handle_local_interrupt5: +.weak handle_local_interrupt6 +handle_local_interrupt6: +.weak handle_local_interrupt7 +handle_local_interrupt7: +.weak handle_local_interrupt8 +handle_local_interrupt8: +.weak handle_local_interrupt9 +handle_local_interrupt9: +.weak handle_local_interrupt10 +handle_local_interrupt10: +.weak handle_local_interrupt11 +handle_local_interrupt11: +.weak handle_local_interrupt12 +handle_local_interrupt12: +.weak handle_local_interrupt13 +handle_local_interrupt13: +.weak handle_local_interrupt14 +handle_local_interrupt14: +.weak handle_local_interrupt15 +handle_local_interrupt15: +1: + j 1b + +#endif diff --git a/raven/bsp/include/sifive/bits.h b/raven/bsp/include/sifive/bits.h index e550f80..bfe656f 100644 --- a/raven/bsp/include/sifive/bits.h +++ b/raven/bsp/include/sifive/bits.h @@ -1,3 +1,4 @@ +// See LICENSE for license details. #ifndef _RISCV_BITS_H #define _RISCV_BITS_H @@ -17,7 +18,7 @@ #define STR(x) XSTR(x) #define XSTR(x) #x -#ifdef __riscv64 +#if __riscv_xlen == 64 # define SLL32 sllw # define STORE sd # define LOAD ld diff --git a/raven/bsp/include/sifive/const.h b/raven/bsp/include/sifive/const.h index 3e0a681..8dcffbb 100644 --- a/raven/bsp/include/sifive/const.h +++ b/raven/bsp/include/sifive/const.h @@ -1,3 +1,4 @@ +// See LICENSE for license details. /* Derived from */ #ifndef _SIFIVE_CONST_H diff --git a/raven/bsp/include/sifive/devices/clic.h b/raven/bsp/include/sifive/devices/clic.h new file mode 100644 index 0000000..e8dc2df --- /dev/null +++ b/raven/bsp/include/sifive/devices/clic.h @@ -0,0 +1,30 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_CLIC_H +#define _SIFIVE_CLIC_H + +#define CLIC_HART0 0x00800000 +#define CLIC_MSIP 0x0000 +#define CLIC_MSIP_size 0x4 +#define CLIC_MTIMECMP 0x4000 +#define CLIC_MTIMECMP_size 0x8 +#define CLIC_MTIME 0xBFF8 +#define CLIC_MTIME_size 0x8 + +#define CLIC_INTIP 0x000 +#define CLIC_INTIE 0x400 +#define CLIC_INTCFG 0x800 +#define CLIC_CFG 0xc00 + +// These interrupt IDs are consistent across old and new mtvec modes +#define SSIPID 1 +#define MSIPID 3 +#define STIPID 5 +#define MTIPID 7 +#define SEIPID 9 +#define MEIPID 11 +#define CSIPID 12 +#define LOCALINTIDBASE 16 + + +#endif /* _SIFIVE_CLIC_H */ diff --git a/raven/bsp/include/sifive/devices/spi.h b/raven/bsp/include/sifive/devices/spi.h index 916d86b..80ef345 100644 --- a/raven/bsp/include/sifive/devices/spi.h +++ b/raven/bsp/include/sifive/devices/spi.h @@ -30,8 +30,8 @@ /* Fields */ -#define SPI_SCK_POL 0x1 -#define SPI_SCK_PHA 0x2 +#define SPI_SCK_PHA 0x1 +#define SPI_SCK_POL 0x2 #define SPI_FMT_PROTO(x) ((x) & 0x3) #define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2) diff --git a/raven/bsp/include/sifive/sections.h b/raven/bsp/include/sifive/sections.h index 848c237..6e1f051 100644 --- a/raven/bsp/include/sifive/sections.h +++ b/raven/bsp/include/sifive/sections.h @@ -1,3 +1,4 @@ +// See LICENSE for license details. #ifndef _SECTIONS_H #define _SECTIONS_H diff --git a/raven/bsp/include/sifive/smp.h b/raven/bsp/include/sifive/smp.h new file mode 100644 index 0000000..8e34388 --- /dev/null +++ b/raven/bsp/include/sifive/smp.h @@ -0,0 +1,65 @@ +#ifndef SIFIVE_SMP +#define SIFIVE_SMP + +// The maximum number of HARTs this code supports +#ifndef MAX_HARTS +#define MAX_HARTS 32 +#endif +#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4) + +// The hart that non-SMP tests should run on +#ifndef NONSMP_HART +#define NONSMP_HART 0 +#endif + +/* If your test cannot handle multiple-threads, use this: + * smp_disable(reg1) + */ +#define smp_disable(reg1, reg2) \ + csrr reg1, mhartid ;\ + li reg2, NONSMP_HART ;\ + beq reg1, reg2, hart0_entry ;\ +42: ;\ + wfi ;\ + j 42b ;\ +hart0_entry: + +/* If your test needs to temporarily block multiple-threads, do this: + * smp_pause(reg1, reg2) + * ... single-threaded work ... + * smp_resume(reg1, reg2) + * ... multi-threaded work ... + */ + +#define smp_pause(reg1, reg2) \ + li reg2, 0x8 ;\ + csrw mie, reg2 ;\ + csrr reg2, mhartid ;\ + bnez reg2, 42f + +#define smp_resume(reg1, reg2) \ + li reg1, CLINT_CTRL_ADDR ;\ +41: ;\ + li reg2, 1 ;\ + sw reg2, 0(reg1) ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b ;\ +42: ;\ + wfi ;\ + csrr reg2, mip ;\ + andi reg2, reg2, 0x8 ;\ + beqz reg2, 42b ;\ + li reg1, CLINT_CTRL_ADDR ;\ + csrr reg2, mhartid ;\ + slli reg2, reg2, 2 ;\ + add reg2, reg2, reg1 ;\ + sw zero, 0(reg2) ;\ +41: ;\ + lw reg2, 0(reg1) ;\ + bnez reg2, 41b ;\ + addi reg1, reg1, 4 ;\ + li reg2, CLINT_END_HART_IPI ;\ + blt reg1, reg2, 41b + +#endif diff --git a/raven/bsp/libwrap/libwrap.mk b/raven/bsp/libwrap/libwrap.mk index add3285..71bba3d 100644 --- a/raven/bsp/libwrap/libwrap.mk +++ b/raven/bsp/libwrap/libwrap.mk @@ -25,7 +25,9 @@ LIBWRAP_SRCS := \ sys/isatty.c \ sys/times.c \ sys/sbrk.c \ - sys/_exit.c + sys/_exit.c \ + sys/puts.c \ + misc/write_hex.c LIBWRAP_SRCS := $(foreach f,$(LIBWRAP_SRCS),$(LIBWRAP_DIR)/$(f)) LIBWRAP_OBJS := $(LIBWRAP_SRCS:.c=.o) @@ -33,13 +35,14 @@ LIBWRAP_OBJS := $(LIBWRAP_SRCS:.c=.o) LIBWRAP_SYMS := malloc free \ open lseek read write fstat stat close link unlink \ execve fork getpid kill wait \ - isatty times sbrk _exit + isatty times sbrk _exit puts LIBWRAP := libwrap.a LINK_DEPS += $(LIBWRAP) LDFLAGS += $(foreach s,$(LIBWRAP_SYMS),-Wl,--wrap=$(s)) +LDFLAGS += $(foreach s,$(LIBWRAP_SYMS),-Wl,--wrap=_$(s)) LDFLAGS += -L. -Wl,--start-group -lwrap -lc -Wl,--end-group CLEAN_OBJS += $(LIBWRAP_OBJS) diff --git a/raven/bsp/libwrap/misc/write_hex.c b/raven/bsp/libwrap/misc/write_hex.c new file mode 100644 index 0000000..a35ad7a --- /dev/null +++ b/raven/bsp/libwrap/misc/write_hex.c @@ -0,0 +1,19 @@ +/* See LICENSE of license details. */ + +#include +#include +#include "platform.h" + +void write_hex(int fd, unsigned long int hex) +{ + uint8_t ii; + uint8_t jj; + char towrite; + write(fd , "0x", 2); + for (ii = sizeof(unsigned long int) * 2 ; ii > 0; ii--) { + jj = ii - 1; + uint8_t digit = ((hex & (0xF << (jj*4))) >> (jj*4)); + towrite = digit < 0xA ? ('0' + digit) : ('A' + (digit - 0xA)); + write(fd, &towrite, 1); + } +} diff --git a/raven/bsp/libwrap/sys/_exit.c b/raven/bsp/libwrap/sys/_exit.c index ceb0b82..011464f 100644 --- a/raven/bsp/libwrap/sys/_exit.c +++ b/raven/bsp/libwrap/sys/_exit.c @@ -2,15 +2,16 @@ #include #include "platform.h" +#include "weak_under_alias.h" -void __wrap__exit(int code) +void __wrap_exit(int code) { -//volatile uint32_t* leds = (uint32_t*) (GPIO_BASE_ADDR + GPIO_OUT_OFFSET); const char message[] = "\nProgam has exited with code:"; -//*leds = (~(code)); write(STDERR_FILENO, message, sizeof(message) - 1); + write_hex(STDERR_FILENO, code); write(STDERR_FILENO, "\n", 1); for (;;); } +weak_under_alias(exit); diff --git a/raven/bsp/libwrap/sys/close.c b/raven/bsp/libwrap/sys/close.c index e4f8e14..199fe51 100644 --- a/raven/bsp/libwrap/sys/close.c +++ b/raven/bsp/libwrap/sys/close.c @@ -2,8 +2,10 @@ #include #include "stub.h" +#include "weak_under_alias.h" int __wrap_close(int fd) { return _stub(EBADF); } +weak_under_alias(close); diff --git a/raven/bsp/libwrap/sys/execve.c b/raven/bsp/libwrap/sys/execve.c index 6178a01..f7be25a 100644 --- a/raven/bsp/libwrap/sys/execve.c +++ b/raven/bsp/libwrap/sys/execve.c @@ -2,8 +2,10 @@ #include #include "stub.h" +#include "weak_under_alias.h" int __wrap_execve(const char* name, char* const argv[], char* const env[]) { return _stub(ENOMEM); } +weak_under_alias(execve); diff --git a/raven/bsp/libwrap/sys/fstat.c b/raven/bsp/libwrap/sys/fstat.c index 6ea3e6a..ff82bf9 100644 --- a/raven/bsp/libwrap/sys/fstat.c +++ b/raven/bsp/libwrap/sys/fstat.c @@ -4,6 +4,7 @@ #include #include #include "stub.h" +#include "weak_under_alias.h" int __wrap_fstat(int fd, struct stat* st) { @@ -14,3 +15,4 @@ int __wrap_fstat(int fd, struct stat* st) return _stub(EBADF); } +weak_under_alias(fstat); diff --git a/raven/bsp/libwrap/sys/getpid.c b/raven/bsp/libwrap/sys/getpid.c index 5aa510b..195fbec 100644 --- a/raven/bsp/libwrap/sys/getpid.c +++ b/raven/bsp/libwrap/sys/getpid.c @@ -1,6 +1,8 @@ /* See LICENSE of license details. */ +#include "weak_under_alias.h" int __wrap_getpid(void) { return 1; } +weak_under_alias(getpid); diff --git a/raven/bsp/libwrap/sys/isatty.c b/raven/bsp/libwrap/sys/isatty.c index 55eab0a..7bb82ab 100644 --- a/raven/bsp/libwrap/sys/isatty.c +++ b/raven/bsp/libwrap/sys/isatty.c @@ -1,6 +1,7 @@ /* See LICENSE of license details. */ #include +#include "weak_under_alias.h" int __wrap_isatty(int fd) { @@ -9,3 +10,4 @@ int __wrap_isatty(int fd) return 0; } +weak_under_alias(isatty); diff --git a/raven/bsp/libwrap/sys/kill.c b/raven/bsp/libwrap/sys/kill.c index 9c56632..18b9bd4 100644 --- a/raven/bsp/libwrap/sys/kill.c +++ b/raven/bsp/libwrap/sys/kill.c @@ -2,8 +2,10 @@ #include #include "stub.h" +#include "weak_under_alias.h" int __wrap_kill(int pid, int sig) { return _stub(EINVAL); } +weak_under_alias(kill); diff --git a/raven/bsp/libwrap/sys/link.c b/raven/bsp/libwrap/sys/link.c index 9340cad..0cad551 100644 --- a/raven/bsp/libwrap/sys/link.c +++ b/raven/bsp/libwrap/sys/link.c @@ -2,8 +2,10 @@ #include #include "stub.h" +#include "weak_under_alias.h" int __wrap_link(const char *old_name, const char *new_name) { return _stub(EMLINK); } +weak_under_alias(link); diff --git a/raven/bsp/libwrap/sys/lseek.c b/raven/bsp/libwrap/sys/lseek.c index 46f58fa..4131449 100644 --- a/raven/bsp/libwrap/sys/lseek.c +++ b/raven/bsp/libwrap/sys/lseek.c @@ -4,6 +4,7 @@ #include #include #include "stub.h" +#include "weak_under_alias.h" off_t __wrap_lseek(int fd, off_t ptr, int dir) { @@ -12,3 +13,4 @@ off_t __wrap_lseek(int fd, off_t ptr, int dir) return _stub(EBADF); } +weak_under_alias(lseek); diff --git a/raven/bsp/libwrap/sys/open.c b/raven/bsp/libwrap/sys/open.c index d1871f9..c61415a 100644 --- a/raven/bsp/libwrap/sys/open.c +++ b/raven/bsp/libwrap/sys/open.c @@ -2,8 +2,10 @@ #include #include "stub.h" +#include "weak_under_alias.h" int __wrap_open(const char* name, int flags, int mode) { return _stub(ENOENT); } +weak_under_alias(open); diff --git a/raven/bsp/libwrap/sys/openat.c b/raven/bsp/libwrap/sys/openat.c index 7f1c945..227c956 100644 --- a/raven/bsp/libwrap/sys/openat.c +++ b/raven/bsp/libwrap/sys/openat.c @@ -2,8 +2,10 @@ #include #include "stub.h" +#include "weak_under_alias.h" int __wrap_openat(int dirfd, const char* name, int flags, int mode) { return _stub(ENOENT); } +weak_under_alias(openat); diff --git a/raven/bsp/libwrap/sys/puts.c b/raven/bsp/libwrap/sys/puts.c new file mode 100644 index 0000000..50d6437 --- /dev/null +++ b/raven/bsp/libwrap/sys/puts.c @@ -0,0 +1,28 @@ +/* See LICENSE of license details. */ + +#include +#include +#include +#include + +#include "platform.h" +#include "stub.h" +#include "weak_under_alias.h" + +int __wrap_puts(const char *s) +{ + while (*s != '\0') { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = *s; + + if (*s == '\n') { + while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ; + UART0_REG(UART_REG_TXFIFO) = '\r'; + } + + ++s; + } + + return 0; +} +weak_under_alias(puts); diff --git a/raven/bsp/libwrap/sys/read.c b/raven/bsp/libwrap/sys/read.c index 4e57f08..3226cdb 100644 --- a/raven/bsp/libwrap/sys/read.c +++ b/raven/bsp/libwrap/sys/read.c @@ -7,12 +7,13 @@ #include "platform.h" #include "stub.h" +#include "weak_under_alias.h" ssize_t __wrap_read(int fd, void* ptr, size_t len) { uint8_t * current = (uint8_t *)ptr; - volatile uint32_t * uart_rx = (uint32_t *)(UART0_BASE_ADDR + UART_REG_RXFIFO); - volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_BASE_ADDR + UART_REG_RXCTRL + 2); + volatile uint32_t * uart_rx = (uint32_t *)(UART0_CTRL_ADDR + UART_REG_RXFIFO); + volatile uint8_t * uart_rx_cnt = (uint8_t *)(UART0_CTRL_ADDR + UART_REG_RXCTRL + 2); ssize_t result = 0; @@ -28,3 +29,4 @@ ssize_t __wrap_read(int fd, void* ptr, size_t len) return _stub(EBADF); } +weak_under_alias(read); diff --git a/raven/bsp/libwrap/sys/sbrk.c b/raven/bsp/libwrap/sys/sbrk.c index 6e6b36a..12170b4 100644 --- a/raven/bsp/libwrap/sys/sbrk.c +++ b/raven/bsp/libwrap/sys/sbrk.c @@ -1,6 +1,7 @@ /* See LICENSE of license details. */ #include +#include "weak_under_alias.h" void *__wrap_sbrk(ptrdiff_t incr) { @@ -14,3 +15,4 @@ void *__wrap_sbrk(ptrdiff_t incr) curbrk += incr; return curbrk - incr; } +weak_under_alias(sbrk); diff --git a/raven/bsp/libwrap/sys/stat.c b/raven/bsp/libwrap/sys/stat.c index 1ccc2f4..1576ca1 100644 --- a/raven/bsp/libwrap/sys/stat.c +++ b/raven/bsp/libwrap/sys/stat.c @@ -3,8 +3,10 @@ #include #include #include "stub.h" +#include "weak_under_alias.h" int __wrap_stat(const char* file, struct stat* st) { return _stub(EACCES); } +weak_under_alias(stat); diff --git a/raven/bsp/libwrap/sys/times.c b/raven/bsp/libwrap/sys/times.c index 26a9566..55969a7 100644 --- a/raven/bsp/libwrap/sys/times.c +++ b/raven/bsp/libwrap/sys/times.c @@ -3,8 +3,10 @@ #include #include #include "stub.h" +#include "weak_under_alias.h" clock_t __wrap_times(struct tms* buf) { return _stub(EACCES); } +weak_under_alias(times); diff --git a/raven/bsp/libwrap/sys/unlink.c b/raven/bsp/libwrap/sys/unlink.c index b62b1ba..09f4da7 100644 --- a/raven/bsp/libwrap/sys/unlink.c +++ b/raven/bsp/libwrap/sys/unlink.c @@ -2,8 +2,10 @@ #include #include "stub.h" +#include "weak_under_alias.h" int __wrap_unlink(const char* name) { return _stub(ENOENT); } +weak_under_alias(unlink); diff --git a/raven/bsp/libwrap/sys/weak_under_alias.h b/raven/bsp/libwrap/sys/weak_under_alias.h new file mode 100644 index 0000000..7629353 --- /dev/null +++ b/raven/bsp/libwrap/sys/weak_under_alias.h @@ -0,0 +1,7 @@ +#ifndef _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H +#define _BSP_LIBWRAP_WEAK_UNDER_ALIAS_H + +#define weak_under_alias(name) \ + extern __typeof (__wrap_##name) __wrap__##name __attribute__ ((weak, alias ("__wrap_"#name))) + +#endif diff --git a/raven/bsp/libwrap/sys/write.c b/raven/bsp/libwrap/sys/write.c index d00eb17..b1e9a7e 100644 --- a/raven/bsp/libwrap/sys/write.c +++ b/raven/bsp/libwrap/sys/write.c @@ -7,6 +7,7 @@ #include "platform.h" #include "stub.h" +#include "weak_under_alias.h" ssize_t __wrap_write(int fd, const void* ptr, size_t len) { @@ -27,3 +28,4 @@ ssize_t __wrap_write(int fd, const void* ptr, size_t len) return _stub(EBADF); } +weak_under_alias(write); diff --git a/raven/hello_raven b/raven/hello_raven index d68e0dd..7f2c204 100755 Binary files a/raven/hello_raven and b/raven/hello_raven differ diff --git a/raven/hello_raven.c b/raven/hello_raven.c deleted file mode 100644 index 93dd1fc..0000000 --- a/raven/hello_raven.c +++ /dev/null @@ -1,55 +0,0 @@ -#include -#include -#include - -#include "platform.h" -#include "encoding.h" - -#define IOF_ENABLE_TERMINAL (0x30000) -int factorial(int i){ - - volatile int result = 1; - for (int ii = 1; ii <= i; ii++) { - result = result * ii; - } - return result; - -} - - - -int main() -{ - GPIO_REG(GPIO_IOF_EN) |= IOF_ENABLE_TERMINAL; // enable GPIO connection to the terminal - - int hartid = read_csr(0xf14); // CSR_MHARTID - int target_mem_base = 0x90000000; - int local_mem_base = 0x80000000; - - if (hartid == 0) { - int val_a = 5; - int val_b = 0xA; - *(int *)target_mem_base = val_a; - *(int *)(target_mem_base+4) = val_b; - printf("HW thread ID %d: write value A=0x%x and value B=0x%x to thread 1\n", hartid, val_a, val_b); - } - - - int result = factorial (10); - printf("HW thread ID %d: spend some time calculating factorial of 10=0x%x\n", hartid, result); - - if (hartid == 1) { - int val_a = *(int *)local_mem_base; - int val_b = *(int *)(local_mem_base+4); - int sum = val_a + val_b; - if (sum == 0xF) - printf("HW thread ID %d: sum of A+B=0x%x\n", hartid, sum); - else { - printf("HW thread ID %d: sum of A+B is not 0x%x. Test FAILED!!!\n", hartid, sum); - return 1; - } - } - - printf("End of execution"); - return 0; -} diff --git a/raven/hello_raven.dis b/raven/hello_raven.dis deleted file mode 100644 index c5d1bca..0000000 --- a/raven/hello_raven.dis +++ /dev/null @@ -1,2156 +0,0 @@ - -hello_raven: file format elf32-littleriscv - - -Disassembly of section .init: - -20400000 <_start>: -20400000: 5fc01197 auipc gp,0x5fc01 -20400004: c2818193 addi gp,gp,-984 # 80000c28 <_gp> -20400008: 5fc04117 auipc sp,0x5fc04 -2040000c: ff810113 addi sp,sp,-8 # 80004000 <_sp> -20400010: 00002517 auipc a0,0x2 -20400014: 40450513 addi a0,a0,1028 # 20402414 <__fini_array_end> -20400018: 5fc00597 auipc a1,0x5fc00 -2040001c: fe858593 addi a1,a1,-24 # 80000000 <_data> -20400020: 5fc00617 auipc a2,0x5fc00 -20400024: 41060613 addi a2,a2,1040 # 80000430 <__bss_start> -20400028: 00c5fc63 bgeu a1,a2,20400040 <_start+0x40> -2040002c: 00052283 lw t0,0(a0) -20400030: 0055a023 sw t0,0(a1) -20400034: 00450513 addi a0,a0,4 -20400038: 00458593 addi a1,a1,4 -2040003c: fec5e8e3 bltu a1,a2,2040002c <_start+0x2c> -20400040: 5fc00517 auipc a0,0x5fc00 -20400044: 3f050513 addi a0,a0,1008 # 80000430 <__bss_start> -20400048: 5fc00597 auipc a1,0x5fc00 -2040004c: 3f058593 addi a1,a1,1008 # 80000438 <_end> -20400050: 00b57863 bgeu a0,a1,20400060 <_start+0x60> -20400054: 00052023 sw zero,0(a0) -20400058: 00450513 addi a0,a0,4 -2040005c: feb56ce3 bltu a0,a1,20400054 <_start+0x54> -20400060: 00001517 auipc a0,0x1 -20400064: 4c450513 addi a0,a0,1220 # 20401524 <__libc_fini_array> -20400068: 470010ef jal ra,204014d8 -2040006c: 518010ef jal ra,20401584 <__libc_init_array> -20400070: 00000513 li a0,0 -20400074: 00000593 li a1,0 -20400078: 321000ef jal ra,20400b98
-2040007c: 4700106f j 204014ec - -Disassembly of section .text: - -20400080 : -20400080: dfc00797 auipc a5,0xdfc00 -20400084: f8078793 addi a5,a5,-128 # 0 <__stack_size-0x800> -20400088: 00078863 beqz a5,20400098 -2040008c: 00001517 auipc a0,0x1 -20400090: 49850513 addi a0,a0,1176 # 20401524 <__libc_fini_array> -20400094: 4440106f j 204014d8 -20400098: 00008067 ret - -2040009c : -2040009c: f8010113 addi sp,sp,-128 -204000a0: 00112223 sw ra,4(sp) -204000a4: 00212423 sw sp,8(sp) -204000a8: 00312623 sw gp,12(sp) -204000ac: 00412823 sw tp,16(sp) -204000b0: 00512a23 sw t0,20(sp) -204000b4: 00612c23 sw t1,24(sp) -204000b8: 00712e23 sw t2,28(sp) -204000bc: 02812023 sw s0,32(sp) -204000c0: 02912223 sw s1,36(sp) -204000c4: 02a12423 sw a0,40(sp) -204000c8: 02b12623 sw a1,44(sp) -204000cc: 02c12823 sw a2,48(sp) -204000d0: 02d12a23 sw a3,52(sp) -204000d4: 02e12c23 sw a4,56(sp) -204000d8: 02f12e23 sw a5,60(sp) -204000dc: 05012023 sw a6,64(sp) -204000e0: 05112223 sw a7,68(sp) -204000e4: 05212423 sw s2,72(sp) -204000e8: 05312623 sw s3,76(sp) -204000ec: 05412823 sw s4,80(sp) -204000f0: 05512a23 sw s5,84(sp) -204000f4: 05612c23 sw s6,88(sp) -204000f8: 05712e23 sw s7,92(sp) -204000fc: 07812023 sw s8,96(sp) -20400100: 07912223 sw s9,100(sp) -20400104: 07a12423 sw s10,104(sp) -20400108: 07b12623 sw s11,108(sp) -2040010c: 07c12823 sw t3,112(sp) -20400110: 07d12a23 sw t4,116(sp) -20400114: 07e12c23 sw t5,120(sp) -20400118: 07f12e23 sw t6,124(sp) -2040011c: 34202573 csrr a0,mcause -20400120: 341025f3 csrr a1,mepc -20400124: 00010613 mv a2,sp -20400128: 100010ef jal ra,20401228 -2040012c: 34151073 csrw mepc,a0 -20400130: 000022b7 lui t0,0x2 -20400134: 80028293 addi t0,t0,-2048 # 1800 <__stack_size+0x1000> -20400138: 3002a073 csrs mstatus,t0 -2040013c: 00412083 lw ra,4(sp) -20400140: 00812103 lw sp,8(sp) -20400144: 00c12183 lw gp,12(sp) -20400148: 01012203 lw tp,16(sp) -2040014c: 01412283 lw t0,20(sp) -20400150: 01812303 lw t1,24(sp) -20400154: 01c12383 lw t2,28(sp) -20400158: 02012403 lw s0,32(sp) -2040015c: 02412483 lw s1,36(sp) -20400160: 02812503 lw a0,40(sp) -20400164: 02c12583 lw a1,44(sp) -20400168: 03012603 lw a2,48(sp) -2040016c: 03412683 lw a3,52(sp) -20400170: 03812703 lw a4,56(sp) -20400174: 03c12783 lw a5,60(sp) -20400178: 04012803 lw a6,64(sp) -2040017c: 04412883 lw a7,68(sp) -20400180: 04812903 lw s2,72(sp) -20400184: 04c12983 lw s3,76(sp) -20400188: 05012a03 lw s4,80(sp) -2040018c: 05412a83 lw s5,84(sp) -20400190: 05812b03 lw s6,88(sp) -20400194: 05c12b83 lw s7,92(sp) -20400198: 06012c03 lw s8,96(sp) -2040019c: 06412c83 lw s9,100(sp) -204001a0: 06812d03 lw s10,104(sp) -204001a4: 06c12d83 lw s11,108(sp) -204001a8: 07012e03 lw t3,112(sp) -204001ac: 07412e83 lw t4,116(sp) -204001b0: 07812f03 lw t5,120(sp) -204001b4: 07c12f83 lw t6,124(sp) -204001b8: 08010113 addi sp,sp,128 -204001bc: 30200073 mret -204001c0: 0000006f j 204001c0 - -204001c4 : -204001c4: fe010113 addi sp,sp,-32 -204001c8: 00112e23 sw ra,28(sp) -204001cc: 00812c23 sw s0,24(sp) -204001d0: 02010413 addi s0,sp,32 -204001d4: fea42623 sw a0,-20(s0) -204001d8: fec40793 addi a5,s0,-20 -204001dc: 00100613 li a2,1 -204001e0: 00078593 mv a1,a5 -204001e4: 00100513 li a0,1 -204001e8: 14c010ef jal ra,20401334 <__wrap_write> -204001ec: 00050713 mv a4,a0 -204001f0: 00100793 li a5,1 -204001f4: 00f71663 bne a4,a5,20400200 -204001f8: fec42783 lw a5,-20(s0) -204001fc: 0080006f j 20400204 -20400200: fff00793 li a5,-1 -20400204: 00078513 mv a0,a5 -20400208: 01c12083 lw ra,28(sp) -2040020c: 01812403 lw s0,24(sp) -20400210: 02010113 addi sp,sp,32 -20400214: 00008067 ret - -20400218 : -20400218: fd010113 addi sp,sp,-48 -2040021c: 02812623 sw s0,44(sp) -20400220: 03010413 addi s0,sp,48 -20400224: fca42e23 sw a0,-36(s0) -20400228: fcb42c23 sw a1,-40(s0) -2040022c: fd842783 lw a5,-40(s0) -20400230: fef42623 sw a5,-20(s0) -20400234: fec42783 lw a5,-20(s0) -20400238: 0007a783 lw a5,0(a5) -2040023c: fdc42703 lw a4,-36(s0) -20400240: 0ff77713 andi a4,a4,255 -20400244: 00e78023 sb a4,0(a5) -20400248: fec42783 lw a5,-20(s0) -2040024c: 0007a783 lw a5,0(a5) -20400250: 00178713 addi a4,a5,1 -20400254: fec42783 lw a5,-20(s0) -20400258: 00e7a023 sw a4,0(a5) -2040025c: 00000013 nop -20400260: 02c12403 lw s0,44(sp) -20400264: 03010113 addi sp,sp,48 -20400268: 00008067 ret - -2040026c : -2040026c: fe010113 addi sp,sp,-32 -20400270: 00812e23 sw s0,28(sp) -20400274: 02010413 addi s0,sp,32 -20400278: fea42623 sw a0,-20(s0) -2040027c: feb42423 sw a1,-24(s0) -20400280: fe842783 lw a5,-24(s0) -20400284: 02078063 beqz a5,204002a4 -20400288: fec42783 lw a5,-20(s0) -2040028c: 0007a783 lw a5,0(a5) -20400290: 00478693 addi a3,a5,4 -20400294: fec42703 lw a4,-20(s0) -20400298: 00d72023 sw a3,0(a4) -2040029c: 0007a783 lw a5,0(a5) -204002a0: 01c0006f j 204002bc -204002a4: fec42783 lw a5,-20(s0) -204002a8: 0007a783 lw a5,0(a5) -204002ac: 00478693 addi a3,a5,4 -204002b0: fec42703 lw a4,-20(s0) -204002b4: 00d72023 sw a3,0(a4) -204002b8: 0007a783 lw a5,0(a5) -204002bc: 00078513 mv a0,a5 -204002c0: 01c12403 lw s0,28(sp) -204002c4: 02010113 addi sp,sp,32 -204002c8: 00008067 ret - -204002cc : -204002cc: fe010113 addi sp,sp,-32 -204002d0: 00812e23 sw s0,28(sp) -204002d4: 02010413 addi s0,sp,32 -204002d8: fea42623 sw a0,-20(s0) -204002dc: feb42423 sw a1,-24(s0) -204002e0: fe842783 lw a5,-24(s0) -204002e4: 02078063 beqz a5,20400304 -204002e8: fec42783 lw a5,-20(s0) -204002ec: 0007a783 lw a5,0(a5) -204002f0: 00478693 addi a3,a5,4 -204002f4: fec42703 lw a4,-20(s0) -204002f8: 00d72023 sw a3,0(a4) -204002fc: 0007a783 lw a5,0(a5) -20400300: 01c0006f j 2040031c -20400304: fec42783 lw a5,-20(s0) -20400308: 0007a783 lw a5,0(a5) -2040030c: 00478693 addi a3,a5,4 -20400310: fec42703 lw a4,-20(s0) -20400314: 00d72023 sw a3,0(a4) -20400318: 0007a783 lw a5,0(a5) -2040031c: 00078513 mv a0,a5 -20400320: 01c12403 lw s0,28(sp) -20400324: 02010113 addi sp,sp,32 -20400328: 00008067 ret - -2040032c : -2040032c: f4010113 addi sp,sp,-192 -20400330: 0a112e23 sw ra,188(sp) -20400334: 0a812c23 sw s0,184(sp) -20400338: 0a912a23 sw s1,180(sp) -2040033c: 0c010413 addi s0,sp,192 -20400340: f4a42e23 sw a0,-164(s0) -20400344: f4b42c23 sw a1,-168(s0) -20400348: f4c42a23 sw a2,-172(s0) -2040034c: f4d42823 sw a3,-176(s0) -20400350: f4e42623 sw a4,-180(s0) -20400354: f4f42423 sw a5,-184(s0) -20400358: fe042623 sw zero,-20(s0) -2040035c: fec42483 lw s1,-20(s0) -20400360: 00148793 addi a5,s1,1 -20400364: fef42623 sw a5,-20(s0) -20400368: f5442783 lw a5,-172(s0) -2040036c: f5042583 lw a1,-176(s0) -20400370: 00078513 mv a0,a5 -20400374: 409010ef jal ra,20401f7c <__umodsi3> -20400378: 00050793 mv a5,a0 -2040037c: 00078713 mv a4,a5 -20400380: 00249793 slli a5,s1,0x2 -20400384: ff040693 addi a3,s0,-16 -20400388: 00f687b3 add a5,a3,a5 -2040038c: f6e7ae23 sw a4,-132(a5) -20400390: f5442703 lw a4,-172(s0) -20400394: f5042783 lw a5,-176(s0) -20400398: 00f76e63 bltu a4,a5,204003b4 -2040039c: f5042583 lw a1,-176(s0) -204003a0: f5442503 lw a0,-172(s0) -204003a4: 391010ef jal ra,20401f34 <__udivsi3> -204003a8: 00050793 mv a5,a0 -204003ac: f4f42a23 sw a5,-172(s0) -204003b0: fadff06f j 2040035c -204003b4: 00000013 nop -204003b8: 0140006f j 204003cc -204003bc: f5c42783 lw a5,-164(s0) -204003c0: f5842583 lw a1,-168(s0) -204003c4: f4842503 lw a0,-184(s0) -204003c8: 000780e7 jalr a5 -204003cc: f4c42783 lw a5,-180(s0) -204003d0: fff78713 addi a4,a5,-1 -204003d4: f4e42623 sw a4,-180(s0) -204003d8: fec42703 lw a4,-20(s0) -204003dc: fef740e3 blt a4,a5,204003bc -204003e0: 0540006f j 20400434 -204003e4: fec42783 lw a5,-20(s0) -204003e8: 00279793 slli a5,a5,0x2 -204003ec: ff040713 addi a4,s0,-16 -204003f0: 00f707b3 add a5,a4,a5 -204003f4: f7c7a703 lw a4,-132(a5) -204003f8: fec42783 lw a5,-20(s0) -204003fc: 00279793 slli a5,a5,0x2 -20400400: ff040693 addi a3,s0,-16 -20400404: 00f687b3 add a5,a3,a5 -20400408: f7c7a683 lw a3,-132(a5) -2040040c: 00900793 li a5,9 -20400410: 00d7f663 bgeu a5,a3,2040041c -20400414: 05700793 li a5,87 -20400418: 0080006f j 20400420 -2040041c: 03000793 li a5,48 -20400420: 00e787b3 add a5,a5,a4 -20400424: f5c42703 lw a4,-164(s0) -20400428: f5842583 lw a1,-168(s0) -2040042c: 00078513 mv a0,a5 -20400430: 000700e7 jalr a4 -20400434: fec42783 lw a5,-20(s0) -20400438: fff78713 addi a4,a5,-1 -2040043c: fee42623 sw a4,-20(s0) -20400440: faf042e3 bgtz a5,204003e4 -20400444: 00000013 nop -20400448: 0bc12083 lw ra,188(sp) -2040044c: 0b812403 lw s0,184(sp) -20400450: 0b412483 lw s1,180(sp) -20400454: 0c010113 addi sp,sp,192 -20400458: 00008067 ret - -2040045c : -2040045c: f9010113 addi sp,sp,-112 -20400460: 06112623 sw ra,108(sp) -20400464: 06812423 sw s0,104(sp) -20400468: 07212223 sw s2,100(sp) -2040046c: 07312023 sw s3,96(sp) -20400470: 07010413 addi s0,sp,112 -20400474: faa42623 sw a0,-84(s0) -20400478: fab42423 sw a1,-88(s0) -2040047c: fac42023 sw a2,-96(s0) -20400480: fad42223 sw a3,-92(s0) -20400484: f8e42e23 sw a4,-100(s0) -20400488: f8f42c23 sw a5,-104(s0) -2040048c: fa042783 lw a5,-96(s0) -20400490: fa442803 lw a6,-92(s0) -20400494: fcf42c23 sw a5,-40(s0) -20400498: fd042e23 sw a6,-36(s0) -2040049c: fd842783 lw a5,-40(s0) -204004a0: fdc42803 lw a6,-36(s0) -204004a4: 00080793 mv a5,a6 -204004a8: 0207da63 bgez a5,204004dc -204004ac: fac42783 lw a5,-84(s0) -204004b0: fa842583 lw a1,-88(s0) -204004b4: 02d00513 li a0,45 -204004b8: 000780e7 jalr a5 -204004bc: fd842783 lw a5,-40(s0) -204004c0: fdc42803 lw a6,-36(s0) -204004c4: fff7f913 andi s2,a5,-1 -204004c8: 80000737 lui a4,0x80000 -204004cc: fff74713 not a4,a4 -204004d0: 00e879b3 and s3,a6,a4 -204004d4: fd242c23 sw s2,-40(s0) -204004d8: fd342e23 sw s3,-36(s0) -204004dc: fe042623 sw zero,-20(s0) -204004e0: 0400006f j 20400520 -204004e4: fd842783 lw a5,-40(s0) -204004e8: fdc42803 lw a6,-36(s0) -204004ec: 20402737 lui a4,0x20402 -204004f0: 19072603 lw a2,400(a4) # 20402190 <__clzsi2+0x1b0> -204004f4: 19472683 lw a3,404(a4) -204004f8: 00078513 mv a0,a5 -204004fc: 00080593 mv a1,a6 -20400500: 31c010ef jal ra,2040181c <__muldf3> -20400504: 00050793 mv a5,a0 -20400508: 00058813 mv a6,a1 -2040050c: fcf42c23 sw a5,-40(s0) -20400510: fd042e23 sw a6,-36(s0) -20400514: fec42783 lw a5,-20(s0) -20400518: 00178793 addi a5,a5,1 -2040051c: fef42623 sw a5,-20(s0) -20400520: fec42703 lw a4,-20(s0) -20400524: f9842783 lw a5,-104(s0) -20400528: faf74ee3 blt a4,a5,204004e4 -2040052c: fb840793 addi a5,s0,-72 -20400530: faf42a23 sw a5,-76(s0) -20400534: fd842783 lw a5,-40(s0) -20400538: fdc42803 lw a6,-36(s0) -2040053c: 00078513 mv a0,a5 -20400540: 00080593 mv a1,a6 -20400544: 149010ef jal ra,20401e8c <__fixunsdfsi> -20400548: 00050613 mv a2,a0 -2040054c: fb440593 addi a1,s0,-76 -20400550: 00000793 li a5,0 -20400554: 00000713 li a4,0 -20400558: 00a00693 li a3,10 -2040055c: 20400537 lui a0,0x20400 -20400560: 21850513 addi a0,a0,536 # 20400218 -20400564: dc9ff0ef jal ra,2040032c -20400568: f9842783 lw a5,-104(s0) -2040056c: 06f05863 blez a5,204005dc -20400570: fe042423 sw zero,-24(s0) -20400574: 0380006f j 204005ac -20400578: fb442703 lw a4,-76(s0) -2040057c: fe842783 lw a5,-24(s0) -20400580: fff7c793 not a5,a5 -20400584: 00f70733 add a4,a4,a5 -20400588: fb442783 lw a5,-76(s0) -2040058c: fe842683 lw a3,-24(s0) -20400590: 40d006b3 neg a3,a3 -20400594: 00d787b3 add a5,a5,a3 -20400598: 00074703 lbu a4,0(a4) -2040059c: 00e78023 sb a4,0(a5) -204005a0: fe842783 lw a5,-24(s0) -204005a4: 00178793 addi a5,a5,1 -204005a8: fef42423 sw a5,-24(s0) -204005ac: fe842703 lw a4,-24(s0) -204005b0: f9842783 lw a5,-104(s0) -204005b4: fcf742e3 blt a4,a5,20400578 -204005b8: fb442783 lw a5,-76(s0) -204005bc: f9842703 lw a4,-104(s0) -204005c0: 40e00733 neg a4,a4 -204005c4: 00e787b3 add a5,a5,a4 -204005c8: 02e00713 li a4,46 -204005cc: 00e78023 sb a4,0(a5) -204005d0: fb442783 lw a5,-76(s0) -204005d4: 00178793 addi a5,a5,1 -204005d8: faf42a23 sw a5,-76(s0) -204005dc: fb840793 addi a5,s0,-72 -204005e0: fef42223 sw a5,-28(s0) -204005e4: 0280006f j 2040060c -204005e8: fe442783 lw a5,-28(s0) -204005ec: 0007c783 lbu a5,0(a5) -204005f0: fac42703 lw a4,-84(s0) -204005f4: fa842583 lw a1,-88(s0) -204005f8: 00078513 mv a0,a5 -204005fc: 000700e7 jalr a4 -20400600: fe442783 lw a5,-28(s0) -20400604: 00178793 addi a5,a5,1 -20400608: fef42223 sw a5,-28(s0) -2040060c: fb442783 lw a5,-76(s0) -20400610: fe442703 lw a4,-28(s0) -20400614: fcf76ae3 bltu a4,a5,204005e8 -20400618: 00000013 nop -2040061c: 06c12083 lw ra,108(sp) -20400620: 06812403 lw s0,104(sp) -20400624: 06412903 lw s2,100(sp) -20400628: 06012983 lw s3,96(sp) -2040062c: 07010113 addi sp,sp,112 -20400630: 00008067 ret - -20400634 : -20400634: fc010113 addi sp,sp,-64 -20400638: 02112e23 sw ra,60(sp) -2040063c: 02812c23 sw s0,56(sp) -20400640: 02912a23 sw s1,52(sp) -20400644: 03212823 sw s2,48(sp) -20400648: 04010413 addi s0,sp,64 -2040064c: fca42623 sw a0,-52(s0) -20400650: fcb42423 sw a1,-56(s0) -20400654: fcc42223 sw a2,-60(s0) -20400658: fcd42023 sw a3,-64(s0) -2040065c: 0240006f j 20400680 -20400660: 3a048863 beqz s1,20400a10 -20400664: fc442783 lw a5,-60(s0) -20400668: 00178793 addi a5,a5,1 -2040066c: fcf42223 sw a5,-60(s0) -20400670: fcc42783 lw a5,-52(s0) -20400674: fc842583 lw a1,-56(s0) -20400678: 00048513 mv a0,s1 -2040067c: 000780e7 jalr a5 -20400680: fc442783 lw a5,-60(s0) -20400684: 0007c783 lbu a5,0(a5) -20400688: 00078493 mv s1,a5 -2040068c: 02500793 li a5,37 -20400690: fcf498e3 bne s1,a5,20400660 -20400694: fc442783 lw a5,-60(s0) -20400698: 00178793 addi a5,a5,1 -2040069c: fcf42223 sw a5,-60(s0) -204006a0: fc442783 lw a5,-60(s0) -204006a4: fcf42a23 sw a5,-44(s0) -204006a8: 02000793 li a5,32 -204006ac: fcf40da3 sb a5,-37(s0) -204006b0: fff00793 li a5,-1 -204006b4: fef42023 sw a5,-32(s0) -204006b8: fff00793 li a5,-1 -204006bc: fcf42e23 sw a5,-36(s0) -204006c0: fe042223 sw zero,-28(s0) -204006c4: fc042823 sw zero,-48(s0) -204006c8: fc442783 lw a5,-60(s0) -204006cc: 00178713 addi a4,a5,1 -204006d0: fce42223 sw a4,-60(s0) -204006d4: 0007c783 lbu a5,0(a5) -204006d8: 00078493 mv s1,a5 -204006dc: fdd48793 addi a5,s1,-35 -204006e0: 05500713 li a4,85 -204006e4: 30f76663 bltu a4,a5,204009f0 -204006e8: 00279713 slli a4,a5,0x2 -204006ec: 204027b7 lui a5,0x20402 -204006f0: 03878793 addi a5,a5,56 # 20402038 <__clzsi2+0x58> -204006f4: 00f707b3 add a5,a4,a5 -204006f8: 0007a783 lw a5,0(a5) -204006fc: 00078067 jr a5 -20400700: 02d00793 li a5,45 -20400704: fcf40da3 sb a5,-37(s0) -20400708: fc1ff06f j 204006c8 -2040070c: 03000793 li a5,48 -20400710: fcf40da3 sb a5,-37(s0) -20400714: fb5ff06f j 204006c8 -20400718: fc042e23 sw zero,-36(s0) -2040071c: fdc42703 lw a4,-36(s0) -20400720: 00070793 mv a5,a4 -20400724: 00279793 slli a5,a5,0x2 -20400728: 00e787b3 add a5,a5,a4 -2040072c: 00179793 slli a5,a5,0x1 -20400730: 00f487b3 add a5,s1,a5 -20400734: fd078793 addi a5,a5,-48 -20400738: fcf42e23 sw a5,-36(s0) -2040073c: fc442783 lw a5,-60(s0) -20400740: 0007c783 lbu a5,0(a5) -20400744: 00078493 mv s1,a5 -20400748: 02f00793 li a5,47 -2040074c: 0497d863 bge a5,s1,2040079c -20400750: 03900793 li a5,57 -20400754: 0497c463 blt a5,s1,2040079c -20400758: fc442783 lw a5,-60(s0) -2040075c: 00178793 addi a5,a5,1 -20400760: fcf42223 sw a5,-60(s0) -20400764: fb9ff06f j 2040071c -20400768: fc042783 lw a5,-64(s0) -2040076c: 00478713 addi a4,a5,4 -20400770: fce42023 sw a4,-64(s0) -20400774: 0007a783 lw a5,0(a5) -20400778: fcf42e23 sw a5,-36(s0) -2040077c: 0240006f j 204007a0 -20400780: fe042783 lw a5,-32(s0) -20400784: f407d2e3 bgez a5,204006c8 -20400788: fe042023 sw zero,-32(s0) -2040078c: f3dff06f j 204006c8 -20400790: 00100793 li a5,1 -20400794: fcf42823 sw a5,-48(s0) -20400798: f31ff06f j 204006c8 -2040079c: 00000013 nop -204007a0: fe042783 lw a5,-32(s0) -204007a4: f207d2e3 bgez a5,204006c8 -204007a8: fdc42783 lw a5,-36(s0) -204007ac: fef42023 sw a5,-32(s0) -204007b0: fff00793 li a5,-1 -204007b4: fcf42e23 sw a5,-36(s0) -204007b8: f11ff06f j 204006c8 -204007bc: fe442783 lw a5,-28(s0) -204007c0: 22079663 bnez a5,204009ec -204007c4: f05ff06f j 204006c8 -204007c8: fc042783 lw a5,-64(s0) -204007cc: 00478713 addi a4,a5,4 -204007d0: fce42023 sw a4,-64(s0) -204007d4: 0007a783 lw a5,0(a5) -204007d8: fcc42703 lw a4,-52(s0) -204007dc: fc842583 lw a1,-56(s0) -204007e0: 00078513 mv a0,a5 -204007e4: 000700e7 jalr a4 -204007e8: 2240006f j 20400a0c -204007ec: fc042783 lw a5,-64(s0) -204007f0: 00778793 addi a5,a5,7 -204007f4: ff87f793 andi a5,a5,-8 -204007f8: 00878713 addi a4,a5,8 -204007fc: fce42023 sw a4,-64(s0) -20400800: 0007a603 lw a2,0(a5) -20400804: 0047a683 lw a3,4(a5) -20400808: fdc42783 lw a5,-36(s0) -2040080c: fe042703 lw a4,-32(s0) -20400810: fc842583 lw a1,-56(s0) -20400814: fcc42503 lw a0,-52(s0) -20400818: c45ff0ef jal ra,2040045c -2040081c: 1f00006f j 20400a0c -20400820: fc042783 lw a5,-64(s0) -20400824: 00478713 addi a4,a5,4 -20400828: fce42023 sw a4,-64(s0) -2040082c: 0007a903 lw s2,0(a5) -20400830: 00091663 bnez s2,2040083c -20400834: 204027b7 lui a5,0x20402 -20400838: 03078913 addi s2,a5,48 # 20402030 <__clzsi2+0x50> -2040083c: fe042783 lw a5,-32(s0) -20400840: 08f05063 blez a5,204008c0 -20400844: fdb44703 lbu a4,-37(s0) -20400848: 02d00793 li a5,45 -2040084c: 06f70a63 beq a4,a5,204008c0 -20400850: fdc42783 lw a5,-36(s0) -20400854: 00078593 mv a1,a5 -20400858: 00090513 mv a0,s2 -2040085c: 5bd000ef jal ra,20401618 -20400860: 00050713 mv a4,a0 -20400864: fe042783 lw a5,-32(s0) -20400868: 40e787b3 sub a5,a5,a4 -2040086c: fef42023 sw a5,-32(s0) -20400870: 0240006f j 20400894 -20400874: fdb44783 lbu a5,-37(s0) -20400878: fcc42703 lw a4,-52(s0) -2040087c: fc842583 lw a1,-56(s0) -20400880: 00078513 mv a0,a5 -20400884: 000700e7 jalr a4 -20400888: fe042783 lw a5,-32(s0) -2040088c: fff78793 addi a5,a5,-1 -20400890: fef42023 sw a5,-32(s0) -20400894: fe042783 lw a5,-32(s0) -20400898: fcf04ee3 bgtz a5,20400874 -2040089c: 0240006f j 204008c0 -204008a0: fcc42783 lw a5,-52(s0) -204008a4: fc842583 lw a1,-56(s0) -204008a8: 00048513 mv a0,s1 -204008ac: 000780e7 jalr a5 -204008b0: 00190913 addi s2,s2,1 -204008b4: fe042783 lw a5,-32(s0) -204008b8: fff78793 addi a5,a5,-1 -204008bc: fef42023 sw a5,-32(s0) -204008c0: 00094783 lbu a5,0(s2) -204008c4: 00078493 mv s1,a5 -204008c8: 04048063 beqz s1,20400908 -204008cc: fdc42783 lw a5,-36(s0) -204008d0: fc07c8e3 bltz a5,204008a0 -204008d4: fdc42783 lw a5,-36(s0) -204008d8: fff78793 addi a5,a5,-1 -204008dc: fcf42e23 sw a5,-36(s0) -204008e0: fdc42783 lw a5,-36(s0) -204008e4: fa07dee3 bgez a5,204008a0 -204008e8: 0200006f j 20400908 -204008ec: fcc42783 lw a5,-52(s0) -204008f0: fc842583 lw a1,-56(s0) -204008f4: 02000513 li a0,32 -204008f8: 000780e7 jalr a5 -204008fc: fe042783 lw a5,-32(s0) -20400900: fff78793 addi a5,a5,-1 -20400904: fef42023 sw a5,-32(s0) -20400908: fe042783 lw a5,-32(s0) -2040090c: fef040e3 bgtz a5,204008ec -20400910: 0fc0006f j 20400a0c -20400914: fc040793 addi a5,s0,-64 -20400918: fe442583 lw a1,-28(s0) -2040091c: 00078513 mv a0,a5 -20400920: 9adff0ef jal ra,204002cc -20400924: 00050793 mv a5,a0 -20400928: fef42623 sw a5,-20(s0) -2040092c: fec42783 lw a5,-20(s0) -20400930: 0207d063 bgez a5,20400950 -20400934: fcc42783 lw a5,-52(s0) -20400938: fc842583 lw a1,-56(s0) -2040093c: 02d00513 li a0,45 -20400940: 000780e7 jalr a5 -20400944: fec42783 lw a5,-20(s0) -20400948: 40f007b3 neg a5,a5 -2040094c: fef42623 sw a5,-20(s0) -20400950: 00a00793 li a5,10 -20400954: fef42423 sw a5,-24(s0) -20400958: 0600006f j 204009b8 -2040095c: 00a00793 li a5,10 -20400960: fef42423 sw a5,-24(s0) -20400964: 0400006f j 204009a4 -20400968: 00800793 li a5,8 -2040096c: fef42423 sw a5,-24(s0) -20400970: 0340006f j 204009a4 -20400974: 00100793 li a5,1 -20400978: fef42223 sw a5,-28(s0) -2040097c: fcc42783 lw a5,-52(s0) -20400980: fc842583 lw a1,-56(s0) -20400984: 03000513 li a0,48 -20400988: 000780e7 jalr a5 -2040098c: fcc42783 lw a5,-52(s0) -20400990: fc842583 lw a1,-56(s0) -20400994: 07800513 li a0,120 -20400998: 000780e7 jalr a5 -2040099c: 01000793 li a5,16 -204009a0: fef42423 sw a5,-24(s0) -204009a4: fc040793 addi a5,s0,-64 -204009a8: fe442583 lw a1,-28(s0) -204009ac: 00078513 mv a0,a5 -204009b0: 8bdff0ef jal ra,2040026c -204009b4: fea42623 sw a0,-20(s0) -204009b8: fe842683 lw a3,-24(s0) -204009bc: fdb44783 lbu a5,-37(s0) -204009c0: fe042703 lw a4,-32(s0) -204009c4: fec42603 lw a2,-20(s0) -204009c8: fc842583 lw a1,-56(s0) -204009cc: fcc42503 lw a0,-52(s0) -204009d0: 95dff0ef jal ra,2040032c -204009d4: 0380006f j 20400a0c -204009d8: fcc42783 lw a5,-52(s0) -204009dc: fc842583 lw a1,-56(s0) -204009e0: 00048513 mv a0,s1 -204009e4: 000780e7 jalr a5 -204009e8: 0240006f j 20400a0c -204009ec: 00000013 nop -204009f0: fcc42783 lw a5,-52(s0) -204009f4: fc842583 lw a1,-56(s0) -204009f8: 02500513 li a0,37 -204009fc: 000780e7 jalr a5 -20400a00: fd442783 lw a5,-44(s0) -20400a04: fcf42223 sw a5,-60(s0) -20400a08: 00000013 nop -20400a0c: c75ff06f j 20400680 -20400a10: 00000013 nop -20400a14: 03c12083 lw ra,60(sp) -20400a18: 03812403 lw s0,56(sp) -20400a1c: 03412483 lw s1,52(sp) -20400a20: 03012903 lw s2,48(sp) -20400a24: 04010113 addi sp,sp,64 -20400a28: 00008067 ret - -20400a2c <__wrap_printf>: -20400a2c: fb010113 addi sp,sp,-80 -20400a30: 02112623 sw ra,44(sp) -20400a34: 02812423 sw s0,40(sp) -20400a38: 03010413 addi s0,sp,48 -20400a3c: fca42e23 sw a0,-36(s0) -20400a40: 00b42223 sw a1,4(s0) -20400a44: 00c42423 sw a2,8(s0) -20400a48: 00d42623 sw a3,12(s0) -20400a4c: 00e42823 sw a4,16(s0) -20400a50: 00f42a23 sw a5,20(s0) -20400a54: 01042c23 sw a6,24(s0) -20400a58: 01142e23 sw a7,28(s0) -20400a5c: 02040793 addi a5,s0,32 -20400a60: fe478793 addi a5,a5,-28 -20400a64: fef42623 sw a5,-20(s0) -20400a68: fec42783 lw a5,-20(s0) -20400a6c: 00078693 mv a3,a5 -20400a70: fdc42603 lw a2,-36(s0) -20400a74: 00000593 li a1,0 -20400a78: 204007b7 lui a5,0x20400 -20400a7c: 1c478513 addi a0,a5,452 # 204001c4 -20400a80: bb5ff0ef jal ra,20400634 -20400a84: 00000793 li a5,0 -20400a88: 00078513 mv a0,a5 -20400a8c: 02c12083 lw ra,44(sp) -20400a90: 02812403 lw s0,40(sp) -20400a94: 05010113 addi sp,sp,80 -20400a98: 00008067 ret - -20400a9c <__wrap_sprintf>: -20400a9c: fb010113 addi sp,sp,-80 -20400aa0: 02112623 sw ra,44(sp) -20400aa4: 02812423 sw s0,40(sp) -20400aa8: 03010413 addi s0,sp,48 -20400aac: fca42e23 sw a0,-36(s0) -20400ab0: fcb42c23 sw a1,-40(s0) -20400ab4: 00c42423 sw a2,8(s0) -20400ab8: 00d42623 sw a3,12(s0) -20400abc: 00e42823 sw a4,16(s0) -20400ac0: 00f42a23 sw a5,20(s0) -20400ac4: 01042c23 sw a6,24(s0) -20400ac8: 01142e23 sw a7,28(s0) -20400acc: fdc42783 lw a5,-36(s0) -20400ad0: fef42623 sw a5,-20(s0) -20400ad4: 02040793 addi a5,s0,32 -20400ad8: fe878793 addi a5,a5,-24 -20400adc: fef42423 sw a5,-24(s0) -20400ae0: fe842703 lw a4,-24(s0) -20400ae4: fdc40793 addi a5,s0,-36 -20400ae8: 00070693 mv a3,a4 -20400aec: fd842603 lw a2,-40(s0) -20400af0: 00078593 mv a1,a5 -20400af4: 204007b7 lui a5,0x20400 -20400af8: 21878513 addi a0,a5,536 # 20400218 -20400afc: b39ff0ef jal ra,20400634 -20400b00: fdc42783 lw a5,-36(s0) -20400b04: 00078023 sb zero,0(a5) -20400b08: fdc42703 lw a4,-36(s0) -20400b0c: fec42783 lw a5,-20(s0) -20400b10: 40f707b3 sub a5,a4,a5 -20400b14: 00078513 mv a0,a5 -20400b18: 02c12083 lw ra,44(sp) -20400b1c: 02812403 lw s0,40(sp) -20400b20: 05010113 addi sp,sp,80 -20400b24: 00008067 ret - -20400b28 : -20400b28: fd010113 addi sp,sp,-48 -20400b2c: 02112623 sw ra,44(sp) -20400b30: 02812423 sw s0,40(sp) -20400b34: 03010413 addi s0,sp,48 -20400b38: fca42e23 sw a0,-36(s0) -20400b3c: 00100793 li a5,1 -20400b40: fef42423 sw a5,-24(s0) -20400b44: 00100793 li a5,1 -20400b48: fef42623 sw a5,-20(s0) -20400b4c: 0280006f j 20400b74 -20400b50: fe842783 lw a5,-24(s0) -20400b54: fec42583 lw a1,-20(s0) -20400b58: 00078513 mv a0,a5 -20400b5c: 3ac010ef jal ra,20401f08 <__mulsi3> -20400b60: 00050793 mv a5,a0 -20400b64: fef42423 sw a5,-24(s0) -20400b68: fec42783 lw a5,-20(s0) -20400b6c: 00178793 addi a5,a5,1 -20400b70: fef42623 sw a5,-20(s0) -20400b74: fec42703 lw a4,-20(s0) -20400b78: fdc42783 lw a5,-36(s0) -20400b7c: fce7dae3 bge a5,a4,20400b50 -20400b80: fe842783 lw a5,-24(s0) -20400b84: 00078513 mv a0,a5 -20400b88: 02c12083 lw ra,44(sp) -20400b8c: 02812403 lw s0,40(sp) -20400b90: 03010113 addi sp,sp,48 -20400b94: 00008067 ret - -20400b98
: -20400b98: fc010113 addi sp,sp,-64 -20400b9c: 02112e23 sw ra,60(sp) -20400ba0: 02812c23 sw s0,56(sp) -20400ba4: 04010413 addi s0,sp,64 -20400ba8: 100127b7 lui a5,0x10012 -20400bac: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> -20400bb0: 0007a683 lw a3,0(a5) -20400bb4: 100127b7 lui a5,0x10012 -20400bb8: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> -20400bbc: 00030737 lui a4,0x30 -20400bc0: 00e6e733 or a4,a3,a4 -20400bc4: 00e7a023 sw a4,0(a5) -20400bc8: f14027f3 csrr a5,mhartid -20400bcc: fef42623 sw a5,-20(s0) -20400bd0: fec42783 lw a5,-20(s0) -20400bd4: fef42423 sw a5,-24(s0) -20400bd8: 900007b7 lui a5,0x90000 -20400bdc: fef42223 sw a5,-28(s0) -20400be0: 800007b7 lui a5,0x80000 -20400be4: fef42023 sw a5,-32(s0) -20400be8: fe842783 lw a5,-24(s0) -20400bec: 04079663 bnez a5,20400c38 -20400bf0: 00500793 li a5,5 -20400bf4: fcf42e23 sw a5,-36(s0) -20400bf8: 00a00793 li a5,10 -20400bfc: fcf42c23 sw a5,-40(s0) -20400c00: fe442783 lw a5,-28(s0) -20400c04: fdc42703 lw a4,-36(s0) -20400c08: 00e7a023 sw a4,0(a5) # 80000000 <_sp+0xffffc000> -20400c0c: fe442783 lw a5,-28(s0) -20400c10: 00478793 addi a5,a5,4 -20400c14: 00078713 mv a4,a5 -20400c18: fd842783 lw a5,-40(s0) -20400c1c: 00f72023 sw a5,0(a4) # 30000 <__stack_size+0x2f800> -20400c20: fd842683 lw a3,-40(s0) -20400c24: fdc42603 lw a2,-36(s0) -20400c28: fe842583 lw a1,-24(s0) -20400c2c: 204027b7 lui a5,0x20402 -20400c30: 19878513 addi a0,a5,408 # 20402198 <__clzsi2+0x1b8> -20400c34: df9ff0ef jal ra,20400a2c <__wrap_printf> -20400c38: 00a00513 li a0,10 -20400c3c: eedff0ef jal ra,20400b28 -20400c40: fca42a23 sw a0,-44(s0) -20400c44: fd442603 lw a2,-44(s0) -20400c48: fe842583 lw a1,-24(s0) -20400c4c: 204027b7 lui a5,0x20402 -20400c50: 1dc78513 addi a0,a5,476 # 204021dc <__clzsi2+0x1fc> -20400c54: dd9ff0ef jal ra,20400a2c <__wrap_printf> -20400c58: fe842703 lw a4,-24(s0) -20400c5c: 00100793 li a5,1 -20400c60: 06f71863 bne a4,a5,20400cd0 -20400c64: fe042783 lw a5,-32(s0) -20400c68: 0007a783 lw a5,0(a5) -20400c6c: fcf42823 sw a5,-48(s0) -20400c70: fe042783 lw a5,-32(s0) -20400c74: 00478793 addi a5,a5,4 -20400c78: 0007a783 lw a5,0(a5) -20400c7c: fcf42623 sw a5,-52(s0) -20400c80: fd042703 lw a4,-48(s0) -20400c84: fcc42783 lw a5,-52(s0) -20400c88: 00f707b3 add a5,a4,a5 -20400c8c: fcf42423 sw a5,-56(s0) -20400c90: fc842703 lw a4,-56(s0) -20400c94: 00f00793 li a5,15 -20400c98: 00f71e63 bne a4,a5,20400cb4 -20400c9c: fc842603 lw a2,-56(s0) -20400ca0: fe842583 lw a1,-24(s0) -20400ca4: 204027b7 lui a5,0x20402 -20400ca8: 22078513 addi a0,a5,544 # 20402220 <__clzsi2+0x240> -20400cac: d81ff0ef jal ra,20400a2c <__wrap_printf> -20400cb0: 0200006f j 20400cd0 -20400cb4: fc842603 lw a2,-56(s0) -20400cb8: fe842583 lw a1,-24(s0) -20400cbc: 204027b7 lui a5,0x20402 -20400cc0: 24478513 addi a0,a5,580 # 20402244 <__clzsi2+0x264> -20400cc4: d69ff0ef jal ra,20400a2c <__wrap_printf> -20400cc8: 00100793 li a5,1 -20400ccc: 0140006f j 20400ce0 -20400cd0: 204027b7 lui a5,0x20402 -20400cd4: 28078513 addi a0,a5,640 # 20402280 <__clzsi2+0x2a0> -20400cd8: d55ff0ef jal ra,20400a2c <__wrap_printf> -20400cdc: 00000793 li a5,0 -20400ce0: 00078513 mv a0,a5 -20400ce4: 03c12083 lw ra,60(sp) -20400ce8: 03812403 lw s0,56(sp) -20400cec: 04010113 addi sp,sp,64 -20400cf0: 00008067 ret - -20400cf4 : -20400cf4: ff010113 addi sp,sp,-16 -20400cf8: 00812623 sw s0,12(sp) -20400cfc: 01010413 addi s0,sp,16 -20400d00: 0200c7b7 lui a5,0x200c -20400d04: ff878793 addi a5,a5,-8 # 200bff8 <__stack_size+0x200b7f8> -20400d08: 0007a783 lw a5,0(a5) -20400d0c: 00078513 mv a0,a5 -20400d10: 00c12403 lw s0,12(sp) -20400d14: 01010113 addi sp,sp,16 -20400d18: 00008067 ret - -20400d1c : -20400d1c: ff010113 addi sp,sp,-16 -20400d20: 00112623 sw ra,12(sp) -20400d24: 00812423 sw s0,8(sp) -20400d28: 01212223 sw s2,4(sp) -20400d2c: 01312023 sw s3,0(sp) -20400d30: 01010413 addi s0,sp,16 -20400d34: fc1ff0ef jal ra,20400cf4 -20400d38: 00050793 mv a5,a0 -20400d3c: 00078913 mv s2,a5 -20400d40: 00000993 li s3,0 -20400d44: 00090793 mv a5,s2 -20400d48: 00098813 mv a6,s3 -20400d4c: 00078513 mv a0,a5 -20400d50: 00080593 mv a1,a6 -20400d54: 00c12083 lw ra,12(sp) -20400d58: 00812403 lw s0,8(sp) -20400d5c: 00412903 lw s2,4(sp) -20400d60: 00012983 lw s3,0(sp) -20400d64: 01010113 addi sp,sp,16 -20400d68: 00008067 ret - -20400d6c : -20400d6c: ff010113 addi sp,sp,-16 -20400d70: 00812623 sw s0,12(sp) -20400d74: 01010413 addi s0,sp,16 -20400d78: 000087b7 lui a5,0x8 -20400d7c: 00078513 mv a0,a5 -20400d80: 00c12403 lw s0,12(sp) -20400d84: 01010113 addi sp,sp,16 -20400d88: 00008067 ret - -20400d8c : -20400d8c: fe010113 addi sp,sp,-32 -20400d90: 00812e23 sw s0,28(sp) -20400d94: 02010413 addi s0,sp,32 -20400d98: fea42623 sw a0,-20(s0) -20400d9c: feb42423 sw a1,-24(s0) -20400da0: fec42783 lw a5,-20(s0) -20400da4: 02f7f713 andi a4,a5,47 -20400da8: fe842783 lw a5,-24(s0) -20400dac: 01079693 slli a3,a5,0x10 -20400db0: 001f07b7 lui a5,0x1f0 -20400db4: 00f6f7b3 and a5,a3,a5 -20400db8: 00f76733 or a4,a4,a5 -20400dbc: 400007b7 lui a5,0x40000 -20400dc0: 00f76733 or a4,a4,a5 -20400dc4: 100087b7 lui a5,0x10008 -20400dc8: 00e7a023 sw a4,0(a5) # 10008000 <__stack_size+0x10007800> -20400dcc: 00000013 nop -20400dd0: 100087b7 lui a5,0x10008 -20400dd4: 0007a783 lw a5,0(a5) # 10008000 <__stack_size+0x10007800> -20400dd8: fe07dce3 bgez a5,20400dd0 -20400ddc: 100087b7 lui a5,0x10008 -20400de0: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> -20400de4: 0007a683 lw a3,0(a5) -20400de8: 100087b7 lui a5,0x10008 -20400dec: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> -20400df0: ffff0737 lui a4,0xffff0 -20400df4: fff70713 addi a4,a4,-1 # fffeffff <_sp+0x7ffebfff> -20400df8: 00e6f733 and a4,a3,a4 -20400dfc: 00e7a023 sw a4,0(a5) -20400e00: 00000013 nop -20400e04: 01c12403 lw s0,28(sp) -20400e08: 02010113 addi sp,sp,32 -20400e0c: 00008067 ret - -20400e10 : -20400e10: fc010113 addi sp,sp,-64 -20400e14: 02112e23 sw ra,60(sp) -20400e18: 02812c23 sw s0,56(sp) -20400e1c: 04010413 addi s0,sp,64 -20400e20: fca42e23 sw a0,-36(s0) -20400e24: fcb42c23 sw a1,-40(s0) -20400e28: fcc42a23 sw a2,-44(s0) -20400e2c: fcd42823 sw a3,-48(s0) -20400e30: fce42623 sw a4,-52(s0) -20400e34: 100087b7 lui a5,0x10008 -20400e38: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> -20400e3c: 0007a703 lw a4,0(a5) -20400e40: 000107b7 lui a5,0x10 -20400e44: 00f777b3 and a5,a4,a5 -20400e48: 00078863 beqz a5,20400e58 -20400e4c: 01000593 li a1,16 -20400e50: 00400513 li a0,4 -20400e54: f39ff0ef jal ra,20400d8c -20400e58: fe042623 sw zero,-20(s0) -20400e5c: fdc42783 lw a5,-36(s0) -20400e60: 01179793 slli a5,a5,0x11 -20400e64: 00078713 mv a4,a5 -20400e68: 000207b7 lui a5,0x20 -20400e6c: 00f777b3 and a5,a4,a5 -20400e70: fec42703 lw a4,-20(s0) -20400e74: 00f767b3 or a5,a4,a5 -20400e78: fef42623 sw a5,-20(s0) -20400e7c: fd842783 lw a5,-40(s0) -20400e80: 02078c63 beqz a5,20400eb8 -20400e84: fec42703 lw a4,-20(s0) -20400e88: 000407b7 lui a5,0x40 -20400e8c: 00f767b3 or a5,a4,a5 -20400e90: fef42623 sw a5,-20(s0) -20400e94: 100087b7 lui a5,0x10008 -20400e98: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> -20400e9c: fec42703 lw a4,-20(s0) -20400ea0: 00e7a023 sw a4,0(a5) -20400ea4: 100087b7 lui a5,0x10008 -20400ea8: 00c78793 addi a5,a5,12 # 1000800c <__stack_size+0x1000780c> -20400eac: 10000713 li a4,256 -20400eb0: 00e7a023 sw a4,0(a5) -20400eb4: 0ec0006f j 20400fa0 -20400eb8: 100147b7 lui a5,0x10014 -20400ebc: 00800713 li a4,8 -20400ec0: 00e7a023 sw a4,0(a5) # 10014000 <__stack_size+0x10013800> -20400ec4: fec42703 lw a4,-20(s0) -20400ec8: 000407b7 lui a5,0x40 -20400ecc: 00f767b3 or a5,a4,a5 -20400ed0: fef42623 sw a5,-20(s0) -20400ed4: fd442783 lw a5,-44(s0) -20400ed8: 0077f793 andi a5,a5,7 -20400edc: fec42703 lw a4,-20(s0) -20400ee0: 00f767b3 or a5,a4,a5 -20400ee4: fef42623 sw a5,-20(s0) -20400ee8: fd042783 lw a5,-48(s0) -20400eec: 00479793 slli a5,a5,0x4 -20400ef0: 3f07f793 andi a5,a5,1008 -20400ef4: fec42703 lw a4,-20(s0) -20400ef8: 00f767b3 or a5,a4,a5 -20400efc: fef42623 sw a5,-20(s0) -20400f00: fcc42783 lw a5,-52(s0) -20400f04: 00a79793 slli a5,a5,0xa -20400f08: 00078713 mv a4,a5 -20400f0c: 000017b7 lui a5,0x1 -20400f10: c0078793 addi a5,a5,-1024 # c00 <__stack_size+0x400> -20400f14: 00f777b3 and a5,a4,a5 -20400f18: fec42703 lw a4,-20(s0) -20400f1c: 00f767b3 or a5,a4,a5 -20400f20: fef42623 sw a5,-20(s0) -20400f24: 100087b7 lui a5,0x10008 -20400f28: 00c78793 addi a5,a5,12 # 1000800c <__stack_size+0x1000780c> -20400f2c: 10000713 li a4,256 -20400f30: 00e7a023 sw a4,0(a5) -20400f34: 100087b7 lui a5,0x10008 -20400f38: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> -20400f3c: fec42703 lw a4,-20(s0) -20400f40: 00e7a023 sw a4,0(a5) -20400f44: 100087b7 lui a5,0x10008 -20400f48: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> -20400f4c: 0007a683 lw a3,0(a5) -20400f50: 100087b7 lui a5,0x10008 -20400f54: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> -20400f58: fffc0737 lui a4,0xfffc0 -20400f5c: fff70713 addi a4,a4,-1 # fffbffff <_sp+0x7ffbbfff> -20400f60: 00e6f733 and a4,a3,a4 -20400f64: 00e7a023 sw a4,0(a5) -20400f68: d8dff0ef jal ra,20400cf4 -20400f6c: fea42423 sw a0,-24(s0) -20400f70: 00000013 nop -20400f74: d81ff0ef jal ra,20400cf4 -20400f78: 00050713 mv a4,a0 -20400f7c: fe842783 lw a5,-24(s0) -20400f80: 40f70733 sub a4,a4,a5 -20400f84: 00300793 li a5,3 -20400f88: fee7f6e3 bgeu a5,a4,20400f74 -20400f8c: 00000013 nop -20400f90: 100087b7 lui a5,0x10008 -20400f94: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> -20400f98: 0007a783 lw a5,0(a5) -20400f9c: fe07dae3 bgez a5,20400f90 -20400fa0: 100087b7 lui a5,0x10008 -20400fa4: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> -20400fa8: 0007a683 lw a3,0(a5) -20400fac: 100087b7 lui a5,0x10008 -20400fb0: 00878793 addi a5,a5,8 # 10008008 <__stack_size+0x10007808> -20400fb4: 00010737 lui a4,0x10 -20400fb8: 00e6e733 or a4,a3,a4 -20400fbc: 00e7a023 sw a4,0(a5) -20400fc0: 00000013 nop -20400fc4: 03c12083 lw ra,60(sp) -20400fc8: 03812403 lw s0,56(sp) -20400fcc: 04010113 addi sp,sp,64 -20400fd0: 00008067 ret - -20400fd4 : -20400fd4: ff010113 addi sp,sp,-16 -20400fd8: 00112623 sw ra,12(sp) -20400fdc: 00812423 sw s0,8(sp) -20400fe0: 01010413 addi s0,sp,16 -20400fe4: 100007b7 lui a5,0x10000 -20400fe8: 07078793 addi a5,a5,112 # 10000070 <__stack_size+0xffff870> -20400fec: 0007a683 lw a3,0(a5) -20400ff0: 100007b7 lui a5,0x10000 -20400ff4: 07078793 addi a5,a5,112 # 10000070 <__stack_size+0xffff870> -20400ff8: c0000737 lui a4,0xc0000 -20400ffc: fff70713 addi a4,a4,-1 # bfffffff <_sp+0x3fffbfff> -20401000: 00e6f733 and a4,a3,a4 -20401004: 00e7a023 sw a4,0(a5) -20401008: 01000593 li a1,16 -2040100c: 00400513 li a0,4 -20401010: d7dff0ef jal ra,20400d8c -20401014: 00000013 nop -20401018: 00c12083 lw ra,12(sp) -2040101c: 00812403 lw s0,8(sp) -20401020: 01010113 addi sp,sp,16 -20401024: 00008067 ret - -20401028 : -20401028: fc010113 addi sp,sp,-64 -2040102c: 02112e23 sw ra,60(sp) -20401030: 02812c23 sw s0,56(sp) -20401034: 02912a23 sw s1,52(sp) -20401038: 04010413 addi s0,sp,64 -2040103c: fca42623 sw a0,-52(s0) -20401040: d2dff0ef jal ra,20400d6c -20401044: fea42623 sw a0,-20(s0) -20401048: cadff0ef jal ra,20400cf4 -2040104c: fea42423 sw a0,-24(s0) -20401050: ca5ff0ef jal ra,20400cf4 -20401054: fea42223 sw a0,-28(s0) -20401058: fe442703 lw a4,-28(s0) -2040105c: fe842783 lw a5,-24(s0) -20401060: fef708e3 beq a4,a5,20401050 -20401064: b00027f3 csrr a5,mcycle -20401068: fef42023 sw a5,-32(s0) -2040106c: fe042783 lw a5,-32(s0) -20401070: fcf42e23 sw a5,-36(s0) -20401074: c81ff0ef jal ra,20400cf4 -20401078: 00050713 mv a4,a0 -2040107c: fe442783 lw a5,-28(s0) -20401080: 40f707b3 sub a5,a4,a5 -20401084: fcf42c23 sw a5,-40(s0) -20401088: fd842703 lw a4,-40(s0) -2040108c: fcc42783 lw a5,-52(s0) -20401090: fef762e3 bltu a4,a5,20401074 -20401094: b00027f3 csrr a5,mcycle -20401098: fcf42a23 sw a5,-44(s0) -2040109c: fd442703 lw a4,-44(s0) -204010a0: fdc42783 lw a5,-36(s0) -204010a4: 40f707b3 sub a5,a4,a5 -204010a8: fcf42823 sw a5,-48(s0) -204010ac: fd842583 lw a1,-40(s0) -204010b0: fd042503 lw a0,-48(s0) -204010b4: 681000ef jal ra,20401f34 <__udivsi3> -204010b8: 00050793 mv a5,a0 -204010bc: fec42583 lw a1,-20(s0) -204010c0: 00078513 mv a0,a5 -204010c4: 645000ef jal ra,20401f08 <__mulsi3> -204010c8: 00050793 mv a5,a0 -204010cc: 00078493 mv s1,a5 -204010d0: fd042783 lw a5,-48(s0) -204010d4: fd842583 lw a1,-40(s0) -204010d8: 00078513 mv a0,a5 -204010dc: 6a1000ef jal ra,20401f7c <__umodsi3> -204010e0: 00050793 mv a5,a0 -204010e4: fec42583 lw a1,-20(s0) -204010e8: 00078513 mv a0,a5 -204010ec: 61d000ef jal ra,20401f08 <__mulsi3> -204010f0: 00050793 mv a5,a0 -204010f4: fd842583 lw a1,-40(s0) -204010f8: 00078513 mv a0,a5 -204010fc: 639000ef jal ra,20401f34 <__udivsi3> -20401100: 00050793 mv a5,a0 -20401104: 00f487b3 add a5,s1,a5 -20401108: 00078513 mv a0,a5 -2040110c: 03c12083 lw ra,60(sp) -20401110: 03812403 lw s0,56(sp) -20401114: 03412483 lw s1,52(sp) -20401118: 04010113 addi sp,sp,64 -2040111c: 00008067 ret - -20401120 : -20401120: ff010113 addi sp,sp,-16 -20401124: 00112623 sw ra,12(sp) -20401128: 00812423 sw s0,8(sp) -2040112c: 01010413 addi s0,sp,16 -20401130: 800007b7 lui a5,0x80000 -20401134: 4307a783 lw a5,1072(a5) # 80000430 <_sp+0xffffc430> -20401138: 02079063 bnez a5,20401158 -2040113c: 00100513 li a0,1 -20401140: ee9ff0ef jal ra,20401028 -20401144: 00a00513 li a0,10 -20401148: ee1ff0ef jal ra,20401028 -2040114c: 00050713 mv a4,a0 -20401150: 800007b7 lui a5,0x80000 -20401154: 42e7a823 sw a4,1072(a5) # 80000430 <_sp+0xffffc430> -20401158: 800007b7 lui a5,0x80000 -2040115c: 4307a783 lw a5,1072(a5) # 80000430 <_sp+0xffffc430> -20401160: 00078513 mv a0,a5 -20401164: 00c12083 lw ra,12(sp) -20401168: 00812403 lw s0,8(sp) -2040116c: 01010113 addi sp,sp,16 -20401170: 00008067 ret - -20401174 : -20401174: fe010113 addi sp,sp,-32 -20401178: 00112e23 sw ra,28(sp) -2040117c: 00812c23 sw s0,24(sp) -20401180: 02010413 addi s0,sp,32 -20401184: fea42623 sw a0,-20(s0) -20401188: 100127b7 lui a5,0x10012 -2040118c: 03c78793 addi a5,a5,60 # 1001203c <__stack_size+0x1001183c> -20401190: 0007a683 lw a3,0(a5) -20401194: 100127b7 lui a5,0x10012 -20401198: 03c78793 addi a5,a5,60 # 1001203c <__stack_size+0x1001183c> -2040119c: fffd0737 lui a4,0xfffd0 -204011a0: fff70713 addi a4,a4,-1 # fffcffff <_sp+0x7ffcbfff> -204011a4: 00e6f733 and a4,a3,a4 -204011a8: 00e7a023 sw a4,0(a5) -204011ac: 100127b7 lui a5,0x10012 -204011b0: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> -204011b4: 0007a683 lw a3,0(a5) -204011b8: 100127b7 lui a5,0x10012 -204011bc: 03878793 addi a5,a5,56 # 10012038 <__stack_size+0x10011838> -204011c0: 00030737 lui a4,0x30 -204011c4: 00e6e733 or a4,a3,a4 -204011c8: 00e7a023 sw a4,0(a5) -204011cc: f55ff0ef jal ra,20401120 -204011d0: 00050793 mv a5,a0 -204011d4: fec42583 lw a1,-20(s0) -204011d8: 00078513 mv a0,a5 -204011dc: 559000ef jal ra,20401f34 <__udivsi3> -204011e0: 00050793 mv a5,a0 -204011e4: 00078713 mv a4,a5 -204011e8: 100137b7 lui a5,0x10013 -204011ec: 01878793 addi a5,a5,24 # 10013018 <__stack_size+0x10012818> -204011f0: fff70713 addi a4,a4,-1 # 2ffff <__stack_size+0x2f7ff> -204011f4: 00e7a023 sw a4,0(a5) -204011f8: 100137b7 lui a5,0x10013 -204011fc: 00878793 addi a5,a5,8 # 10013008 <__stack_size+0x10012808> -20401200: 0007a703 lw a4,0(a5) -20401204: 100137b7 lui a5,0x10013 -20401208: 00878793 addi a5,a5,8 # 10013008 <__stack_size+0x10012808> -2040120c: 00176713 ori a4,a4,1 -20401210: 00e7a023 sw a4,0(a5) -20401214: 00000013 nop -20401218: 01c12083 lw ra,28(sp) -2040121c: 01812403 lw s0,24(sp) -20401220: 02010113 addi sp,sp,32 -20401224: 00008067 ret - -20401228 : -20401228: fe010113 addi sp,sp,-32 -2040122c: 00112e23 sw ra,28(sp) -20401230: 00812c23 sw s0,24(sp) -20401234: 02010413 addi s0,sp,32 -20401238: fea42623 sw a0,-20(s0) -2040123c: feb42423 sw a1,-24(s0) -20401240: 00500613 li a2,5 -20401244: 204027b7 lui a5,0x20402 -20401248: 29478593 addi a1,a5,660 # 20402294 <__clzsi2+0x2b4> -2040124c: 00100513 li a0,1 -20401250: 0e4000ef jal ra,20401334 <__wrap_write> -20401254: fec42783 lw a5,-20(s0) -20401258: 00178793 addi a5,a5,1 -2040125c: 00078513 mv a0,a5 -20401260: 1f0000ef jal ra,20401450 <__wrap__exit> - -20401264 <_init>: -20401264: fe010113 addi sp,sp,-32 -20401268: 00112e23 sw ra,28(sp) -2040126c: 00812c23 sw s0,24(sp) -20401270: 02010413 addi s0,sp,32 -20401274: d61ff0ef jal ra,20400fd4 -20401278: 00100713 li a4,1 -2040127c: 01f00693 li a3,31 -20401280: 00100613 li a2,1 -20401284: 00000593 li a1,0 -20401288: 00000513 li a0,0 -2040128c: b85ff0ef jal ra,20400e10 -20401290: 0001c7b7 lui a5,0x1c -20401294: 20078513 addi a0,a5,512 # 1c200 <__stack_size+0x1ba00> -20401298: eddff0ef jal ra,20401174 -2040129c: e85ff0ef jal ra,20401120 -204012a0: 00050793 mv a5,a0 -204012a4: 00078593 mv a1,a5 -204012a8: 204027b7 lui a5,0x20402 -204012ac: 29c78513 addi a0,a5,668 # 2040229c <__clzsi2+0x2bc> -204012b0: f7cff0ef jal ra,20400a2c <__wrap_printf> -204012b4: 204007b7 lui a5,0x20400 -204012b8: 09c78793 addi a5,a5,156 # 2040009c -204012bc: 30579073 csrw mtvec,a5 -204012c0: 301027f3 csrr a5,misa -204012c4: fef42623 sw a5,-20(s0) -204012c8: fec42783 lw a5,-20(s0) -204012cc: 0207f793 andi a5,a5,32 -204012d0: 00078863 beqz a5,204012e0 <_init+0x7c> -204012d4: 000067b7 lui a5,0x6 -204012d8: 30079073 csrw mstatus,a5 -204012dc: 00305073 csrwi fcsr,0 -204012e0: 00000013 nop -204012e4: 01c12083 lw ra,28(sp) -204012e8: 01812403 lw s0,24(sp) -204012ec: 02010113 addi sp,sp,32 -204012f0: 00008067 ret - -204012f4 <_fini>: -204012f4: ff010113 addi sp,sp,-16 -204012f8: 00812623 sw s0,12(sp) -204012fc: 01010413 addi s0,sp,16 -20401300: 00000013 nop -20401304: 00c12403 lw s0,12(sp) -20401308: 01010113 addi sp,sp,16 -2040130c: 00008067 ret - -20401310 <_stub>: -20401310: fe010113 addi sp,sp,-32 -20401314: 00812e23 sw s0,28(sp) -20401318: 02010413 addi s0,sp,32 -2040131c: fea42623 sw a0,-20(s0) -20401320: fff00793 li a5,-1 -20401324: 00078513 mv a0,a5 -20401328: 01c12403 lw s0,28(sp) -2040132c: 02010113 addi sp,sp,32 -20401330: 00008067 ret - -20401334 <__wrap_write>: -20401334: fd010113 addi sp,sp,-48 -20401338: 02112623 sw ra,44(sp) -2040133c: 02812423 sw s0,40(sp) -20401340: 03010413 addi s0,sp,48 -20401344: fca42e23 sw a0,-36(s0) -20401348: fcb42c23 sw a1,-40(s0) -2040134c: fcc42a23 sw a2,-44(s0) -20401350: fd842783 lw a5,-40(s0) -20401354: fef42423 sw a5,-24(s0) -20401358: fdc42503 lw a0,-36(s0) -2040135c: 0b0000ef jal ra,2040140c <__wrap_isatty> -20401360: 00050793 mv a5,a0 -20401364: 08078463 beqz a5,204013ec <__wrap_write+0xb8> -20401368: fe042623 sw zero,-20(s0) -2040136c: 06c0006f j 204013d8 <__wrap_write+0xa4> -20401370: 00000013 nop -20401374: 100137b7 lui a5,0x10013 -20401378: 0007a783 lw a5,0(a5) # 10013000 <__stack_size+0x10012800> -2040137c: fe07cce3 bltz a5,20401374 <__wrap_write+0x40> -20401380: fe842703 lw a4,-24(s0) -20401384: fec42783 lw a5,-20(s0) -20401388: 00f707b3 add a5,a4,a5 -2040138c: 0007c703 lbu a4,0(a5) -20401390: 100137b7 lui a5,0x10013 -20401394: 00e7a023 sw a4,0(a5) # 10013000 <__stack_size+0x10012800> -20401398: fe842703 lw a4,-24(s0) -2040139c: fec42783 lw a5,-20(s0) -204013a0: 00f707b3 add a5,a4,a5 -204013a4: 0007c703 lbu a4,0(a5) -204013a8: 00a00793 li a5,10 -204013ac: 02f71063 bne a4,a5,204013cc <__wrap_write+0x98> -204013b0: 00000013 nop -204013b4: 100137b7 lui a5,0x10013 -204013b8: 0007a783 lw a5,0(a5) # 10013000 <__stack_size+0x10012800> -204013bc: fe07cce3 bltz a5,204013b4 <__wrap_write+0x80> -204013c0: 100137b7 lui a5,0x10013 -204013c4: 00d00713 li a4,13 -204013c8: 00e7a023 sw a4,0(a5) # 10013000 <__stack_size+0x10012800> -204013cc: fec42783 lw a5,-20(s0) -204013d0: 00178793 addi a5,a5,1 -204013d4: fef42623 sw a5,-20(s0) -204013d8: fec42703 lw a4,-20(s0) -204013dc: fd442783 lw a5,-44(s0) -204013e0: f8f768e3 bltu a4,a5,20401370 <__wrap_write+0x3c> -204013e4: fd442783 lw a5,-44(s0) -204013e8: 0100006f j 204013f8 <__wrap_write+0xc4> -204013ec: 00900513 li a0,9 -204013f0: f21ff0ef jal ra,20401310 <_stub> -204013f4: 00050793 mv a5,a0 -204013f8: 00078513 mv a0,a5 -204013fc: 02c12083 lw ra,44(sp) -20401400: 02812403 lw s0,40(sp) -20401404: 03010113 addi sp,sp,48 -20401408: 00008067 ret - -2040140c <__wrap_isatty>: -2040140c: fe010113 addi sp,sp,-32 -20401410: 00812e23 sw s0,28(sp) -20401414: 02010413 addi s0,sp,32 -20401418: fea42623 sw a0,-20(s0) -2040141c: fec42703 lw a4,-20(s0) -20401420: 00100793 li a5,1 -20401424: 00f70863 beq a4,a5,20401434 <__wrap_isatty+0x28> -20401428: fec42703 lw a4,-20(s0) -2040142c: 00200793 li a5,2 -20401430: 00f71663 bne a4,a5,2040143c <__wrap_isatty+0x30> -20401434: 00100793 li a5,1 -20401438: 0080006f j 20401440 <__wrap_isatty+0x34> -2040143c: 00000793 li a5,0 -20401440: 00078513 mv a0,a5 -20401444: 01c12403 lw s0,28(sp) -20401448: 02010113 addi sp,sp,32 -2040144c: 00008067 ret - -20401450 <__wrap__exit>: -20401450: fc010113 addi sp,sp,-64 -20401454: 02112e23 sw ra,60(sp) -20401458: 02812c23 sw s0,56(sp) -2040145c: 04010413 addi s0,sp,64 -20401460: fca42623 sw a0,-52(s0) -20401464: 204027b7 lui a5,0x20402 -20401468: 2b478793 addi a5,a5,692 # 204022b4 <__clzsi2+0x2d4> -2040146c: 0007a883 lw a7,0(a5) -20401470: 0047a803 lw a6,4(a5) -20401474: 0087a503 lw a0,8(a5) -20401478: 00c7a583 lw a1,12(a5) -2040147c: 0107a603 lw a2,16(a5) -20401480: 0147a683 lw a3,20(a5) -20401484: 0187a703 lw a4,24(a5) -20401488: fd142823 sw a7,-48(s0) -2040148c: fd042a23 sw a6,-44(s0) -20401490: fca42c23 sw a0,-40(s0) -20401494: fcb42e23 sw a1,-36(s0) -20401498: fec42023 sw a2,-32(s0) -2040149c: fed42223 sw a3,-28(s0) -204014a0: fee42423 sw a4,-24(s0) -204014a4: 01c7d783 lhu a5,28(a5) -204014a8: fef41623 sh a5,-20(s0) -204014ac: fd040793 addi a5,s0,-48 -204014b0: 01d00613 li a2,29 -204014b4: 00078593 mv a1,a5 -204014b8: 00200513 li a0,2 -204014bc: e79ff0ef jal ra,20401334 <__wrap_write> -204014c0: 00100613 li a2,1 -204014c4: 204027b7 lui a5,0x20402 -204014c8: 2b078593 addi a1,a5,688 # 204022b0 <__clzsi2+0x2d0> -204014cc: 00200513 li a0,2 -204014d0: e65ff0ef jal ra,20401334 <__wrap_write> -204014d4: 0000006f j 204014d4 <__wrap__exit+0x84> - -204014d8 : -204014d8: 00050593 mv a1,a0 -204014dc: 00000693 li a3,0 -204014e0: 00000613 li a2,0 -204014e4: 00000513 li a0,0 -204014e8: 1740006f j 2040165c <__register_exitproc> - -204014ec : -204014ec: ff010113 addi sp,sp,-16 -204014f0: 00000593 li a1,0 -204014f4: 00812423 sw s0,8(sp) -204014f8: 00112623 sw ra,12(sp) -204014fc: 00050413 mv s0,a0 -20401500: 1fc000ef jal ra,204016fc <__call_exitprocs> -20401504: 5fbff797 auipc a5,0x5fbff -20401508: f2478793 addi a5,a5,-220 # 80000428 <_global_impure_ptr> -2040150c: 0007a503 lw a0,0(a5) -20401510: 03c52783 lw a5,60(a0) -20401514: 00078463 beqz a5,2040151c -20401518: 000780e7 jalr a5 -2040151c: 00040513 mv a0,s0 -20401520: f31ff0ef jal ra,20401450 <__wrap__exit> - -20401524 <__libc_fini_array>: -20401524: ff010113 addi sp,sp,-16 -20401528: 00812423 sw s0,8(sp) -2040152c: 00001797 auipc a5,0x1 -20401530: ee878793 addi a5,a5,-280 # 20402414 <__fini_array_end> -20401534: 00001417 auipc s0,0x1 -20401538: ee040413 addi s0,s0,-288 # 20402414 <__fini_array_end> -2040153c: 40f40433 sub s0,s0,a5 -20401540: 00112623 sw ra,12(sp) -20401544: 00912223 sw s1,4(sp) -20401548: 40245413 srai s0,s0,0x2 -2040154c: 02040263 beqz s0,20401570 <__libc_fini_array+0x4c> -20401550: 00241493 slli s1,s0,0x2 -20401554: ffc48493 addi s1,s1,-4 -20401558: 00f484b3 add s1,s1,a5 -2040155c: 0004a783 lw a5,0(s1) -20401560: fff40413 addi s0,s0,-1 -20401564: ffc48493 addi s1,s1,-4 -20401568: 000780e7 jalr a5 -2040156c: fe0418e3 bnez s0,2040155c <__libc_fini_array+0x38> -20401570: 00c12083 lw ra,12(sp) -20401574: 00812403 lw s0,8(sp) -20401578: 00412483 lw s1,4(sp) -2040157c: 01010113 addi sp,sp,16 -20401580: 00008067 ret - -20401584 <__libc_init_array>: -20401584: ff010113 addi sp,sp,-16 -20401588: 00812423 sw s0,8(sp) -2040158c: 01212023 sw s2,0(sp) -20401590: 00001417 auipc s0,0x1 -20401594: e8040413 addi s0,s0,-384 # 20402410 <__init_array_start> -20401598: 00001917 auipc s2,0x1 -2040159c: e7890913 addi s2,s2,-392 # 20402410 <__init_array_start> -204015a0: 40890933 sub s2,s2,s0 -204015a4: 00112623 sw ra,12(sp) -204015a8: 00912223 sw s1,4(sp) -204015ac: 40295913 srai s2,s2,0x2 -204015b0: 00090e63 beqz s2,204015cc <__libc_init_array+0x48> -204015b4: 00000493 li s1,0 -204015b8: 00042783 lw a5,0(s0) -204015bc: 00148493 addi s1,s1,1 -204015c0: 00440413 addi s0,s0,4 -204015c4: 000780e7 jalr a5 -204015c8: fe9918e3 bne s2,s1,204015b8 <__libc_init_array+0x34> -204015cc: 00001417 auipc s0,0x1 -204015d0: e4440413 addi s0,s0,-444 # 20402410 <__init_array_start> -204015d4: 00001917 auipc s2,0x1 -204015d8: e4090913 addi s2,s2,-448 # 20402414 <__fini_array_end> -204015dc: 40890933 sub s2,s2,s0 -204015e0: 40295913 srai s2,s2,0x2 -204015e4: 00090e63 beqz s2,20401600 <__libc_init_array+0x7c> -204015e8: 00000493 li s1,0 -204015ec: 00042783 lw a5,0(s0) -204015f0: 00148493 addi s1,s1,1 -204015f4: 00440413 addi s0,s0,4 -204015f8: 000780e7 jalr a5 -204015fc: fe9918e3 bne s2,s1,204015ec <__libc_init_array+0x68> -20401600: 00c12083 lw ra,12(sp) -20401604: 00812403 lw s0,8(sp) -20401608: 00412483 lw s1,4(sp) -2040160c: 00012903 lw s2,0(sp) -20401610: 01010113 addi sp,sp,16 -20401614: 00008067 ret - -20401618 : -20401618: 02058463 beqz a1,20401640 -2040161c: 00054783 lbu a5,0(a0) -20401620: 02078a63 beqz a5,20401654 -20401624: 00b506b3 add a3,a0,a1 -20401628: 00050793 mv a5,a0 -2040162c: 00c0006f j 20401638 -20401630: 0007c703 lbu a4,0(a5) -20401634: 00070a63 beqz a4,20401648 -20401638: 00178793 addi a5,a5,1 -2040163c: fed79ae3 bne a5,a3,20401630 -20401640: 00058513 mv a0,a1 -20401644: 00008067 ret -20401648: 40a785b3 sub a1,a5,a0 -2040164c: 00058513 mv a0,a1 -20401650: 00008067 ret -20401654: 00000593 li a1,0 -20401658: fe9ff06f j 20401640 - -2040165c <__register_exitproc>: -2040165c: 5fbff797 auipc a5,0x5fbff -20401660: dcc78793 addi a5,a5,-564 # 80000428 <_global_impure_ptr> -20401664: 0007a703 lw a4,0(a5) -20401668: 14872783 lw a5,328(a4) -2040166c: 04078c63 beqz a5,204016c4 <__register_exitproc+0x68> -20401670: 0047a703 lw a4,4(a5) -20401674: 01f00813 li a6,31 -20401678: 06e84e63 blt a6,a4,204016f4 <__register_exitproc+0x98> -2040167c: 00271813 slli a6,a4,0x2 -20401680: 02050663 beqz a0,204016ac <__register_exitproc+0x50> -20401684: 01078333 add t1,a5,a6 -20401688: 08c32423 sw a2,136(t1) -2040168c: 1887a883 lw a7,392(a5) -20401690: 00100613 li a2,1 -20401694: 00e61633 sll a2,a2,a4 -20401698: 00c8e8b3 or a7,a7,a2 -2040169c: 1917a423 sw a7,392(a5) -204016a0: 10d32423 sw a3,264(t1) -204016a4: 00200693 li a3,2 -204016a8: 02d50463 beq a0,a3,204016d0 <__register_exitproc+0x74> -204016ac: 00170713 addi a4,a4,1 -204016b0: 00e7a223 sw a4,4(a5) -204016b4: 010787b3 add a5,a5,a6 -204016b8: 00b7a423 sw a1,8(a5) -204016bc: 00000513 li a0,0 -204016c0: 00008067 ret -204016c4: 14c70793 addi a5,a4,332 -204016c8: 14f72423 sw a5,328(a4) -204016cc: fa5ff06f j 20401670 <__register_exitproc+0x14> -204016d0: 18c7a683 lw a3,396(a5) -204016d4: 00170713 addi a4,a4,1 -204016d8: 00e7a223 sw a4,4(a5) -204016dc: 00c6e633 or a2,a3,a2 -204016e0: 18c7a623 sw a2,396(a5) -204016e4: 010787b3 add a5,a5,a6 -204016e8: 00b7a423 sw a1,8(a5) -204016ec: 00000513 li a0,0 -204016f0: 00008067 ret -204016f4: fff00513 li a0,-1 -204016f8: 00008067 ret - -204016fc <__call_exitprocs>: -204016fc: fd010113 addi sp,sp,-48 -20401700: 5fbff797 auipc a5,0x5fbff -20401704: d2878793 addi a5,a5,-728 # 80000428 <_global_impure_ptr> -20401708: 01812423 sw s8,8(sp) -2040170c: 0007ac03 lw s8,0(a5) -20401710: 01312e23 sw s3,28(sp) -20401714: 01412c23 sw s4,24(sp) -20401718: 01512a23 sw s5,20(sp) -2040171c: 01612823 sw s6,16(sp) -20401720: 02112623 sw ra,44(sp) -20401724: 02812423 sw s0,40(sp) -20401728: 02912223 sw s1,36(sp) -2040172c: 03212023 sw s2,32(sp) -20401730: 01712623 sw s7,12(sp) -20401734: 00050a93 mv s5,a0 -20401738: 00058b13 mv s6,a1 -2040173c: 00100a13 li s4,1 -20401740: fff00993 li s3,-1 -20401744: 148c2903 lw s2,328(s8) -20401748: 02090863 beqz s2,20401778 <__call_exitprocs+0x7c> -2040174c: 00492483 lw s1,4(s2) -20401750: fff48413 addi s0,s1,-1 -20401754: 02044263 bltz s0,20401778 <__call_exitprocs+0x7c> -20401758: 00249493 slli s1,s1,0x2 -2040175c: 009904b3 add s1,s2,s1 -20401760: 040b0463 beqz s6,204017a8 <__call_exitprocs+0xac> -20401764: 1044a783 lw a5,260(s1) -20401768: 05678063 beq a5,s6,204017a8 <__call_exitprocs+0xac> -2040176c: fff40413 addi s0,s0,-1 -20401770: ffc48493 addi s1,s1,-4 -20401774: ff3416e3 bne s0,s3,20401760 <__call_exitprocs+0x64> -20401778: 02c12083 lw ra,44(sp) -2040177c: 02812403 lw s0,40(sp) -20401780: 02412483 lw s1,36(sp) -20401784: 02012903 lw s2,32(sp) -20401788: 01c12983 lw s3,28(sp) -2040178c: 01812a03 lw s4,24(sp) -20401790: 01412a83 lw s5,20(sp) -20401794: 01012b03 lw s6,16(sp) -20401798: 00c12b83 lw s7,12(sp) -2040179c: 00812c03 lw s8,8(sp) -204017a0: 03010113 addi sp,sp,48 -204017a4: 00008067 ret -204017a8: 00492783 lw a5,4(s2) -204017ac: 0044a683 lw a3,4(s1) -204017b0: fff78793 addi a5,a5,-1 -204017b4: 04878a63 beq a5,s0,20401808 <__call_exitprocs+0x10c> -204017b8: 0004a223 sw zero,4(s1) -204017bc: fa0688e3 beqz a3,2040176c <__call_exitprocs+0x70> -204017c0: 18892783 lw a5,392(s2) -204017c4: 008a1733 sll a4,s4,s0 -204017c8: 00492b83 lw s7,4(s2) -204017cc: 00f777b3 and a5,a4,a5 -204017d0: 00079e63 bnez a5,204017ec <__call_exitprocs+0xf0> -204017d4: 000680e7 jalr a3 -204017d8: 00492783 lw a5,4(s2) -204017dc: f77794e3 bne a5,s7,20401744 <__call_exitprocs+0x48> -204017e0: 148c2783 lw a5,328(s8) -204017e4: f92784e3 beq a5,s2,2040176c <__call_exitprocs+0x70> -204017e8: f5dff06f j 20401744 <__call_exitprocs+0x48> -204017ec: 18c92783 lw a5,396(s2) -204017f0: 0844a583 lw a1,132(s1) -204017f4: 00f77733 and a4,a4,a5 -204017f8: 00071c63 bnez a4,20401810 <__call_exitprocs+0x114> -204017fc: 000a8513 mv a0,s5 -20401800: 000680e7 jalr a3 -20401804: fd5ff06f j 204017d8 <__call_exitprocs+0xdc> -20401808: 00892223 sw s0,4(s2) -2040180c: fb1ff06f j 204017bc <__call_exitprocs+0xc0> -20401810: 00058513 mv a0,a1 -20401814: 000680e7 jalr a3 -20401818: fc1ff06f j 204017d8 <__call_exitprocs+0xdc> - -2040181c <__muldf3>: -2040181c: fd010113 addi sp,sp,-48 -20401820: 01312e23 sw s3,28(sp) -20401824: 0145d993 srli s3,a1,0x14 -20401828: 02812423 sw s0,40(sp) -2040182c: 02912223 sw s1,36(sp) -20401830: 01412c23 sw s4,24(sp) -20401834: 01512a23 sw s5,20(sp) -20401838: 01612823 sw s6,16(sp) -2040183c: 00c59493 slli s1,a1,0xc -20401840: 02112623 sw ra,44(sp) -20401844: 03212023 sw s2,32(sp) -20401848: 01712623 sw s7,12(sp) -2040184c: 7ff9f993 andi s3,s3,2047 -20401850: 00050413 mv s0,a0 -20401854: 00060b13 mv s6,a2 -20401858: 00068a93 mv s5,a3 -2040185c: 00c4d493 srli s1,s1,0xc -20401860: 01f5da13 srli s4,a1,0x1f -20401864: 0a098463 beqz s3,2040190c <__muldf3+0xf0> -20401868: 7ff00793 li a5,2047 -2040186c: 10f98263 beq s3,a5,20401970 <__muldf3+0x154> -20401870: 01d55793 srli a5,a0,0x1d -20401874: 00349493 slli s1,s1,0x3 -20401878: 0097e4b3 or s1,a5,s1 -2040187c: 008007b7 lui a5,0x800 -20401880: 00f4e4b3 or s1,s1,a5 -20401884: 00351913 slli s2,a0,0x3 -20401888: c0198993 addi s3,s3,-1023 -2040188c: 00000b93 li s7,0 -20401890: 014ad513 srli a0,s5,0x14 -20401894: 00ca9413 slli s0,s5,0xc -20401898: 7ff57513 andi a0,a0,2047 -2040189c: 00c45413 srli s0,s0,0xc -204018a0: 01fada93 srli s5,s5,0x1f -204018a4: 10050263 beqz a0,204019a8 <__muldf3+0x18c> -204018a8: 7ff00793 li a5,2047 -204018ac: 16f50263 beq a0,a5,20401a10 <__muldf3+0x1f4> -204018b0: 01db5793 srli a5,s6,0x1d -204018b4: 00341413 slli s0,s0,0x3 -204018b8: 0087e433 or s0,a5,s0 -204018bc: 008007b7 lui a5,0x800 -204018c0: 00f46433 or s0,s0,a5 -204018c4: c0150513 addi a0,a0,-1023 -204018c8: 003b1793 slli a5,s6,0x3 -204018cc: 00000713 li a4,0 -204018d0: 002b9693 slli a3,s7,0x2 -204018d4: 00e6e6b3 or a3,a3,a4 -204018d8: 00a989b3 add s3,s3,a0 -204018dc: fff68693 addi a3,a3,-1 -204018e0: 00e00613 li a2,14 -204018e4: 015a4833 xor a6,s4,s5 -204018e8: 00198893 addi a7,s3,1 -204018ec: 14d66e63 bltu a2,a3,20401a48 <__muldf3+0x22c> -204018f0: 00001617 auipc a2,0x1 -204018f4: 9e460613 addi a2,a2,-1564 # 204022d4 <__clzsi2+0x2f4> -204018f8: 00269693 slli a3,a3,0x2 -204018fc: 00c686b3 add a3,a3,a2 -20401900: 0006a683 lw a3,0(a3) -20401904: 00c686b3 add a3,a3,a2 -20401908: 00068067 jr a3 -2040190c: 00a4e933 or s2,s1,a0 -20401910: 06090c63 beqz s2,20401988 <__muldf3+0x16c> -20401914: 04048063 beqz s1,20401954 <__muldf3+0x138> -20401918: 00048513 mv a0,s1 -2040191c: 6c4000ef jal ra,20401fe0 <__clzsi2> -20401920: ff550713 addi a4,a0,-11 -20401924: 01c00793 li a5,28 -20401928: 02e7cc63 blt a5,a4,20401960 <__muldf3+0x144> -2040192c: 01d00793 li a5,29 -20401930: ff850913 addi s2,a0,-8 -20401934: 40e787b3 sub a5,a5,a4 -20401938: 012494b3 sll s1,s1,s2 -2040193c: 00f457b3 srl a5,s0,a5 -20401940: 0097e4b3 or s1,a5,s1 -20401944: 01241933 sll s2,s0,s2 -20401948: c0d00993 li s3,-1011 -2040194c: 40a989b3 sub s3,s3,a0 -20401950: f3dff06f j 2040188c <__muldf3+0x70> -20401954: 68c000ef jal ra,20401fe0 <__clzsi2> -20401958: 02050513 addi a0,a0,32 -2040195c: fc5ff06f j 20401920 <__muldf3+0x104> -20401960: fd850493 addi s1,a0,-40 -20401964: 009414b3 sll s1,s0,s1 -20401968: 00000913 li s2,0 -2040196c: fddff06f j 20401948 <__muldf3+0x12c> -20401970: 00a4e933 or s2,s1,a0 -20401974: 02090263 beqz s2,20401998 <__muldf3+0x17c> -20401978: 00050913 mv s2,a0 -2040197c: 7ff00993 li s3,2047 -20401980: 00300b93 li s7,3 -20401984: f0dff06f j 20401890 <__muldf3+0x74> -20401988: 00000493 li s1,0 -2040198c: 00000993 li s3,0 -20401990: 00100b93 li s7,1 -20401994: efdff06f j 20401890 <__muldf3+0x74> -20401998: 00000493 li s1,0 -2040199c: 7ff00993 li s3,2047 -204019a0: 00200b93 li s7,2 -204019a4: eedff06f j 20401890 <__muldf3+0x74> -204019a8: 016467b3 or a5,s0,s6 -204019ac: 06078e63 beqz a5,20401a28 <__muldf3+0x20c> -204019b0: 04040063 beqz s0,204019f0 <__muldf3+0x1d4> -204019b4: 00040513 mv a0,s0 -204019b8: 628000ef jal ra,20401fe0 <__clzsi2> -204019bc: ff550693 addi a3,a0,-11 -204019c0: 01c00793 li a5,28 -204019c4: 02d7ce63 blt a5,a3,20401a00 <__muldf3+0x1e4> -204019c8: 01d00713 li a4,29 -204019cc: ff850793 addi a5,a0,-8 -204019d0: 40d70733 sub a4,a4,a3 -204019d4: 00f41433 sll s0,s0,a5 -204019d8: 00eb5733 srl a4,s6,a4 -204019dc: 00876433 or s0,a4,s0 -204019e0: 00fb17b3 sll a5,s6,a5 -204019e4: c0d00713 li a4,-1011 -204019e8: 40a70533 sub a0,a4,a0 -204019ec: ee1ff06f j 204018cc <__muldf3+0xb0> -204019f0: 000b0513 mv a0,s6 -204019f4: 5ec000ef jal ra,20401fe0 <__clzsi2> -204019f8: 02050513 addi a0,a0,32 -204019fc: fc1ff06f j 204019bc <__muldf3+0x1a0> -20401a00: fd850413 addi s0,a0,-40 -20401a04: 008b1433 sll s0,s6,s0 -20401a08: 00000793 li a5,0 -20401a0c: fd9ff06f j 204019e4 <__muldf3+0x1c8> -20401a10: 016467b3 or a5,s0,s6 -20401a14: 02078263 beqz a5,20401a38 <__muldf3+0x21c> -20401a18: 000b0793 mv a5,s6 -20401a1c: 7ff00513 li a0,2047 -20401a20: 00300713 li a4,3 -20401a24: eadff06f j 204018d0 <__muldf3+0xb4> -20401a28: 00000413 li s0,0 -20401a2c: 00000513 li a0,0 -20401a30: 00100713 li a4,1 -20401a34: e9dff06f j 204018d0 <__muldf3+0xb4> -20401a38: 00000413 li s0,0 -20401a3c: 7ff00513 li a0,2047 -20401a40: 00200713 li a4,2 -20401a44: e8dff06f j 204018d0 <__muldf3+0xb4> -20401a48: 000102b7 lui t0,0x10 -20401a4c: fff28313 addi t1,t0,-1 # ffff <__stack_size+0xf7ff> -20401a50: 01095f13 srli t5,s2,0x10 -20401a54: 0107df93 srli t6,a5,0x10 -20401a58: 00697933 and s2,s2,t1 -20401a5c: 0067f7b3 and a5,a5,t1 -20401a60: 00090513 mv a0,s2 -20401a64: 00078593 mv a1,a5 -20401a68: 4a0000ef jal ra,20401f08 <__mulsi3> -20401a6c: 00050e93 mv t4,a0 -20401a70: 000f8593 mv a1,t6 -20401a74: 00090513 mv a0,s2 -20401a78: 490000ef jal ra,20401f08 <__mulsi3> -20401a7c: 00050e13 mv t3,a0 -20401a80: 00078593 mv a1,a5 -20401a84: 000f0513 mv a0,t5 -20401a88: 480000ef jal ra,20401f08 <__mulsi3> -20401a8c: 00050a13 mv s4,a0 -20401a90: 000f8593 mv a1,t6 -20401a94: 000f0513 mv a0,t5 -20401a98: 470000ef jal ra,20401f08 <__mulsi3> -20401a9c: 010ed713 srli a4,t4,0x10 -20401aa0: 014e0e33 add t3,t3,s4 -20401aa4: 01c70733 add a4,a4,t3 -20401aa8: 00050393 mv t2,a0 -20401aac: 01477463 bgeu a4,s4,20401ab4 <__muldf3+0x298> -20401ab0: 005503b3 add t2,a0,t0 -20401ab4: 00677e33 and t3,a4,t1 -20401ab8: 006efeb3 and t4,t4,t1 -20401abc: 01045a13 srli s4,s0,0x10 -20401ac0: 010e1e13 slli t3,t3,0x10 -20401ac4: 00647433 and s0,s0,t1 -20401ac8: 01075293 srli t0,a4,0x10 -20401acc: 01de0e33 add t3,t3,t4 -20401ad0: 00090513 mv a0,s2 -20401ad4: 00040593 mv a1,s0 -20401ad8: 430000ef jal ra,20401f08 <__mulsi3> -20401adc: 00050e93 mv t4,a0 -20401ae0: 000a0593 mv a1,s4 -20401ae4: 00090513 mv a0,s2 -20401ae8: 420000ef jal ra,20401f08 <__mulsi3> -20401aec: 00050713 mv a4,a0 -20401af0: 00040593 mv a1,s0 -20401af4: 000f0513 mv a0,t5 -20401af8: 410000ef jal ra,20401f08 <__mulsi3> -20401afc: 00050313 mv t1,a0 -20401b00: 000a0593 mv a1,s4 -20401b04: 000f0513 mv a0,t5 -20401b08: 400000ef jal ra,20401f08 <__mulsi3> -20401b0c: 010ed693 srli a3,t4,0x10 -20401b10: 00670733 add a4,a4,t1 -20401b14: 00e686b3 add a3,a3,a4 -20401b18: 0066f663 bgeu a3,t1,20401b24 <__muldf3+0x308> -20401b1c: 00010737 lui a4,0x10 -20401b20: 00e50533 add a0,a0,a4 -20401b24: 00010ab7 lui s5,0x10 -20401b28: fffa8613 addi a2,s5,-1 # ffff <__stack_size+0xf7ff> -20401b2c: 0106d713 srli a4,a3,0x10 -20401b30: 00c6f6b3 and a3,a3,a2 -20401b34: 01069693 slli a3,a3,0x10 -20401b38: 00cefeb3 and t4,t4,a2 -20401b3c: 00a70f33 add t5,a4,a0 -20401b40: 01d68eb3 add t4,a3,t4 -20401b44: 0104d713 srli a4,s1,0x10 -20401b48: 00c4f4b3 and s1,s1,a2 -20401b4c: 01d282b3 add t0,t0,t4 -20401b50: 00048513 mv a0,s1 -20401b54: 00078593 mv a1,a5 -20401b58: 3b0000ef jal ra,20401f08 <__mulsi3> -20401b5c: 00050913 mv s2,a0 -20401b60: 000f8593 mv a1,t6 -20401b64: 00048513 mv a0,s1 -20401b68: 3a0000ef jal ra,20401f08 <__mulsi3> -20401b6c: 00050313 mv t1,a0 -20401b70: 00078593 mv a1,a5 -20401b74: 00070513 mv a0,a4 -20401b78: 390000ef jal ra,20401f08 <__mulsi3> -20401b7c: 00050b13 mv s6,a0 -20401b80: 000f8593 mv a1,t6 -20401b84: 00070513 mv a0,a4 -20401b88: 380000ef jal ra,20401f08 <__mulsi3> -20401b8c: 01095793 srli a5,s2,0x10 -20401b90: 01630333 add t1,t1,s6 -20401b94: 006787b3 add a5,a5,t1 -20401b98: 0167f463 bgeu a5,s6,20401ba0 <__muldf3+0x384> -20401b9c: 01550533 add a0,a0,s5 -20401ba0: 00010ab7 lui s5,0x10 -20401ba4: fffa8693 addi a3,s5,-1 # ffff <__stack_size+0xf7ff> -20401ba8: 00d7f333 and t1,a5,a3 -20401bac: 0107d613 srli a2,a5,0x10 -20401bb0: 00d97933 and s2,s2,a3 -20401bb4: 01031313 slli t1,t1,0x10 -20401bb8: 00a60fb3 add t6,a2,a0 -20401bbc: 01230333 add t1,t1,s2 -20401bc0: 00048513 mv a0,s1 -20401bc4: 00040593 mv a1,s0 -20401bc8: 340000ef jal ra,20401f08 <__mulsi3> -20401bcc: 00050793 mv a5,a0 -20401bd0: 000a0593 mv a1,s4 -20401bd4: 00048513 mv a0,s1 -20401bd8: 330000ef jal ra,20401f08 <__mulsi3> -20401bdc: 00050493 mv s1,a0 -20401be0: 00040593 mv a1,s0 -20401be4: 00070513 mv a0,a4 -20401be8: 320000ef jal ra,20401f08 <__mulsi3> -20401bec: 00050913 mv s2,a0 -20401bf0: 000a0593 mv a1,s4 -20401bf4: 00070513 mv a0,a4 -20401bf8: 310000ef jal ra,20401f08 <__mulsi3> -20401bfc: 0107d693 srli a3,a5,0x10 -20401c00: 012484b3 add s1,s1,s2 -20401c04: 009686b3 add a3,a3,s1 -20401c08: 0126f463 bgeu a3,s2,20401c10 <__muldf3+0x3f4> -20401c0c: 01550533 add a0,a0,s5 -20401c10: 00010637 lui a2,0x10 -20401c14: fff60613 addi a2,a2,-1 # ffff <__stack_size+0xf7ff> -20401c18: 00c6f733 and a4,a3,a2 -20401c1c: 00c7f7b3 and a5,a5,a2 -20401c20: 01071713 slli a4,a4,0x10 -20401c24: 007282b3 add t0,t0,t2 -20401c28: 00f70733 add a4,a4,a5 -20401c2c: 01d2beb3 sltu t4,t0,t4 -20401c30: 01e70733 add a4,a4,t5 -20401c34: 01d70433 add s0,a4,t4 -20401c38: 006282b3 add t0,t0,t1 -20401c3c: 01f40633 add a2,s0,t6 -20401c40: 0062b333 sltu t1,t0,t1 -20401c44: 006605b3 add a1,a2,t1 -20401c48: 01e73733 sltu a4,a4,t5 -20401c4c: 01d43433 sltu s0,s0,t4 -20401c50: 00876433 or s0,a4,s0 -20401c54: 0106d693 srli a3,a3,0x10 -20401c58: 01f63633 sltu a2,a2,t6 -20401c5c: 0065b333 sltu t1,a1,t1 -20401c60: 00d40433 add s0,s0,a3 -20401c64: 00666333 or t1,a2,t1 -20401c68: 00640433 add s0,s0,t1 -20401c6c: 00929793 slli a5,t0,0x9 -20401c70: 00a40433 add s0,s0,a0 -20401c74: 01c7e7b3 or a5,a5,t3 -20401c78: 00941413 slli s0,s0,0x9 -20401c7c: 0175d513 srli a0,a1,0x17 -20401c80: 00f037b3 snez a5,a5 -20401c84: 0172de13 srli t3,t0,0x17 -20401c88: 00959713 slli a4,a1,0x9 -20401c8c: 00a46433 or s0,s0,a0 -20401c90: 01c7e7b3 or a5,a5,t3 -20401c94: 00e7e7b3 or a5,a5,a4 -20401c98: 00741713 slli a4,s0,0x7 -20401c9c: 10075263 bgez a4,20401da0 <__muldf3+0x584> -20401ca0: 0017d713 srli a4,a5,0x1 -20401ca4: 0017f793 andi a5,a5,1 -20401ca8: 00f767b3 or a5,a4,a5 -20401cac: 01f41713 slli a4,s0,0x1f -20401cb0: 00e7e7b3 or a5,a5,a4 -20401cb4: 00145413 srli s0,s0,0x1 -20401cb8: 3ff88693 addi a3,a7,1023 -20401cbc: 0ed05663 blez a3,20401da8 <__muldf3+0x58c> -20401cc0: 0077f713 andi a4,a5,7 -20401cc4: 02070063 beqz a4,20401ce4 <__muldf3+0x4c8> -20401cc8: 00f7f713 andi a4,a5,15 -20401ccc: 00400613 li a2,4 -20401cd0: 00c70a63 beq a4,a2,20401ce4 <__muldf3+0x4c8> -20401cd4: 00478713 addi a4,a5,4 # 800004 <__stack_size+0x7ff804> -20401cd8: 00f737b3 sltu a5,a4,a5 -20401cdc: 00f40433 add s0,s0,a5 -20401ce0: 00070793 mv a5,a4 -20401ce4: 00741713 slli a4,s0,0x7 -20401ce8: 00075a63 bgez a4,20401cfc <__muldf3+0x4e0> -20401cec: ff000737 lui a4,0xff000 -20401cf0: fff70713 addi a4,a4,-1 # feffffff <_sp+0x7effbfff> -20401cf4: 00e47433 and s0,s0,a4 -20401cf8: 40088693 addi a3,a7,1024 -20401cfc: 7fe00713 li a4,2046 -20401d00: 16d74663 blt a4,a3,20401e6c <__muldf3+0x650> -20401d04: 0037d713 srli a4,a5,0x3 -20401d08: 01d41793 slli a5,s0,0x1d -20401d0c: 00e7e7b3 or a5,a5,a4 -20401d10: 00345413 srli s0,s0,0x3 -20401d14: 00c41413 slli s0,s0,0xc -20401d18: 7ff6f713 andi a4,a3,2047 -20401d1c: 01471713 slli a4,a4,0x14 -20401d20: 00c45413 srli s0,s0,0xc -20401d24: 00e46433 or s0,s0,a4 -20401d28: 01f81813 slli a6,a6,0x1f -20401d2c: 01046733 or a4,s0,a6 -20401d30: 02c12083 lw ra,44(sp) -20401d34: 02812403 lw s0,40(sp) -20401d38: 02412483 lw s1,36(sp) -20401d3c: 02012903 lw s2,32(sp) -20401d40: 01c12983 lw s3,28(sp) -20401d44: 01812a03 lw s4,24(sp) -20401d48: 01412a83 lw s5,20(sp) -20401d4c: 01012b03 lw s6,16(sp) -20401d50: 00c12b83 lw s7,12(sp) -20401d54: 00078513 mv a0,a5 -20401d58: 00070593 mv a1,a4 -20401d5c: 03010113 addi sp,sp,48 -20401d60: 00008067 ret -20401d64: 000a0813 mv a6,s4 -20401d68: 00048413 mv s0,s1 -20401d6c: 00090793 mv a5,s2 -20401d70: 000b8713 mv a4,s7 -20401d74: 00200693 li a3,2 -20401d78: 0ed70a63 beq a4,a3,20401e6c <__muldf3+0x650> -20401d7c: 00300693 li a3,3 -20401d80: 0cd70c63 beq a4,a3,20401e58 <__muldf3+0x63c> -20401d84: 00100693 li a3,1 -20401d88: f2d718e3 bne a4,a3,20401cb8 <__muldf3+0x49c> -20401d8c: 00000413 li s0,0 -20401d90: 00000793 li a5,0 -20401d94: 0880006f j 20401e1c <__muldf3+0x600> -20401d98: 000a8813 mv a6,s5 -20401d9c: fd9ff06f j 20401d74 <__muldf3+0x558> -20401da0: 00098893 mv a7,s3 -20401da4: f15ff06f j 20401cb8 <__muldf3+0x49c> -20401da8: 00100613 li a2,1 -20401dac: 40d60633 sub a2,a2,a3 -20401db0: 03800713 li a4,56 -20401db4: fcc74ce3 blt a4,a2,20401d8c <__muldf3+0x570> -20401db8: 01f00713 li a4,31 -20401dbc: 06c74463 blt a4,a2,20401e24 <__muldf3+0x608> -20401dc0: 41e88893 addi a7,a7,1054 -20401dc4: 01141733 sll a4,s0,a7 -20401dc8: 00c7d6b3 srl a3,a5,a2 -20401dcc: 011797b3 sll a5,a5,a7 -20401dd0: 00d76733 or a4,a4,a3 -20401dd4: 00f037b3 snez a5,a5 -20401dd8: 00f767b3 or a5,a4,a5 -20401ddc: 00c45433 srl s0,s0,a2 -20401de0: 0077f713 andi a4,a5,7 -20401de4: 02070063 beqz a4,20401e04 <__muldf3+0x5e8> -20401de8: 00f7f713 andi a4,a5,15 -20401dec: 00400693 li a3,4 -20401df0: 00d70a63 beq a4,a3,20401e04 <__muldf3+0x5e8> -20401df4: 00478713 addi a4,a5,4 -20401df8: 00f737b3 sltu a5,a4,a5 -20401dfc: 00f40433 add s0,s0,a5 -20401e00: 00070793 mv a5,a4 -20401e04: 00841713 slli a4,s0,0x8 -20401e08: 06074a63 bltz a4,20401e7c <__muldf3+0x660> -20401e0c: 01d41713 slli a4,s0,0x1d -20401e10: 0037d793 srli a5,a5,0x3 -20401e14: 00f767b3 or a5,a4,a5 -20401e18: 00345413 srli s0,s0,0x3 -20401e1c: 00000693 li a3,0 -20401e20: ef5ff06f j 20401d14 <__muldf3+0x4f8> -20401e24: fe100713 li a4,-31 -20401e28: 40d70733 sub a4,a4,a3 -20401e2c: 02000593 li a1,32 -20401e30: 00e45733 srl a4,s0,a4 -20401e34: 00000693 li a3,0 -20401e38: 00b60663 beq a2,a1,20401e44 <__muldf3+0x628> -20401e3c: 43e88893 addi a7,a7,1086 -20401e40: 011416b3 sll a3,s0,a7 -20401e44: 00f6e7b3 or a5,a3,a5 -20401e48: 00f037b3 snez a5,a5 -20401e4c: 00f767b3 or a5,a4,a5 -20401e50: 00000413 li s0,0 -20401e54: f8dff06f j 20401de0 <__muldf3+0x5c4> -20401e58: 00080437 lui s0,0x80 -20401e5c: 00000793 li a5,0 -20401e60: 7ff00693 li a3,2047 -20401e64: 00000813 li a6,0 -20401e68: eadff06f j 20401d14 <__muldf3+0x4f8> -20401e6c: 00000413 li s0,0 -20401e70: 00000793 li a5,0 -20401e74: 7ff00693 li a3,2047 -20401e78: e9dff06f j 20401d14 <__muldf3+0x4f8> -20401e7c: 00000413 li s0,0 -20401e80: 00000793 li a5,0 -20401e84: 00100693 li a3,1 -20401e88: e8dff06f j 20401d14 <__muldf3+0x4f8> - -20401e8c <__fixunsdfsi>: -20401e8c: 0145d713 srli a4,a1,0x14 -20401e90: 001006b7 lui a3,0x100 -20401e94: 00050613 mv a2,a0 -20401e98: fff68793 addi a5,a3,-1 # fffff <__stack_size+0xff7ff> -20401e9c: 7ff77713 andi a4,a4,2047 -20401ea0: 3fe00513 li a0,1022 -20401ea4: 00b7f7b3 and a5,a5,a1 -20401ea8: 01f5d593 srli a1,a1,0x1f -20401eac: 04e55a63 bge a0,a4,20401f00 <__fixunsdfsi+0x74> -20401eb0: 00000513 li a0,0 -20401eb4: 00059863 bnez a1,20401ec4 <__fixunsdfsi+0x38> -20401eb8: 41e00593 li a1,1054 -20401ebc: fff00513 li a0,-1 -20401ec0: 00e5d463 bge a1,a4,20401ec8 <__fixunsdfsi+0x3c> -20401ec4: 00008067 ret -20401ec8: 00d7e7b3 or a5,a5,a3 -20401ecc: 43300693 li a3,1075 -20401ed0: 40e686b3 sub a3,a3,a4 -20401ed4: 01f00593 li a1,31 -20401ed8: 00d5cc63 blt a1,a3,20401ef0 <__fixunsdfsi+0x64> -20401edc: bed70713 addi a4,a4,-1043 -20401ee0: 00e797b3 sll a5,a5,a4 -20401ee4: 00d65533 srl a0,a2,a3 -20401ee8: 00a7e533 or a0,a5,a0 -20401eec: 00008067 ret -20401ef0: 41300513 li a0,1043 -20401ef4: 40e50533 sub a0,a0,a4 -20401ef8: 00a7d533 srl a0,a5,a0 -20401efc: 00008067 ret -20401f00: 00000513 li a0,0 -20401f04: 00008067 ret - -20401f08 <__mulsi3>: -20401f08: 00050613 mv a2,a0 -20401f0c: 00000513 li a0,0 -20401f10: 0015f693 andi a3,a1,1 -20401f14: 00068463 beqz a3,20401f1c <__mulsi3+0x14> -20401f18: 00c50533 add a0,a0,a2 -20401f1c: 0015d593 srli a1,a1,0x1 -20401f20: 00161613 slli a2,a2,0x1 -20401f24: fe0596e3 bnez a1,20401f10 <__mulsi3+0x8> -20401f28: 00008067 ret - -20401f2c <__divsi3>: -20401f2c: 06054063 bltz a0,20401f8c <__umodsi3+0x10> -20401f30: 0605c663 bltz a1,20401f9c <__umodsi3+0x20> - -20401f34 <__udivsi3>: -20401f34: 00058613 mv a2,a1 -20401f38: 00050593 mv a1,a0 -20401f3c: fff00513 li a0,-1 -20401f40: 02060c63 beqz a2,20401f78 <__udivsi3+0x44> -20401f44: 00100693 li a3,1 -20401f48: 00b67a63 bgeu a2,a1,20401f5c <__udivsi3+0x28> -20401f4c: 00c05863 blez a2,20401f5c <__udivsi3+0x28> -20401f50: 00161613 slli a2,a2,0x1 -20401f54: 00169693 slli a3,a3,0x1 -20401f58: feb66ae3 bltu a2,a1,20401f4c <__udivsi3+0x18> -20401f5c: 00000513 li a0,0 -20401f60: 00c5e663 bltu a1,a2,20401f6c <__udivsi3+0x38> -20401f64: 40c585b3 sub a1,a1,a2 -20401f68: 00d56533 or a0,a0,a3 -20401f6c: 0016d693 srli a3,a3,0x1 -20401f70: 00165613 srli a2,a2,0x1 -20401f74: fe0696e3 bnez a3,20401f60 <__udivsi3+0x2c> -20401f78: 00008067 ret - -20401f7c <__umodsi3>: -20401f7c: 00008293 mv t0,ra -20401f80: fb5ff0ef jal ra,20401f34 <__udivsi3> -20401f84: 00058513 mv a0,a1 -20401f88: 00028067 jr t0 -20401f8c: 40a00533 neg a0,a0 -20401f90: 0005d863 bgez a1,20401fa0 <__umodsi3+0x24> -20401f94: 40b005b3 neg a1,a1 -20401f98: f9dff06f j 20401f34 <__udivsi3> -20401f9c: 40b005b3 neg a1,a1 -20401fa0: 00008293 mv t0,ra -20401fa4: f91ff0ef jal ra,20401f34 <__udivsi3> -20401fa8: 40a00533 neg a0,a0 -20401fac: 00028067 jr t0 - -20401fb0 <__modsi3>: -20401fb0: 00008293 mv t0,ra -20401fb4: 0005ca63 bltz a1,20401fc8 <__modsi3+0x18> -20401fb8: 00054c63 bltz a0,20401fd0 <__modsi3+0x20> -20401fbc: f79ff0ef jal ra,20401f34 <__udivsi3> -20401fc0: 00058513 mv a0,a1 -20401fc4: 00028067 jr t0 -20401fc8: 40b005b3 neg a1,a1 -20401fcc: fe0558e3 bgez a0,20401fbc <__modsi3+0xc> -20401fd0: 40a00533 neg a0,a0 -20401fd4: f61ff0ef jal ra,20401f34 <__udivsi3> -20401fd8: 40b00533 neg a0,a1 -20401fdc: 00028067 jr t0 - -20401fe0 <__clzsi2>: -20401fe0: 000107b7 lui a5,0x10 -20401fe4: 02f57a63 bgeu a0,a5,20402018 <__clzsi2+0x38> -20401fe8: 0ff00793 li a5,255 -20401fec: 00a7b7b3 sltu a5,a5,a0 -20401ff0: 00379793 slli a5,a5,0x3 -20401ff4: 02000713 li a4,32 -20401ff8: 40f70733 sub a4,a4,a5 -20401ffc: 00f557b3 srl a5,a0,a5 -20402000: 00000517 auipc a0,0x0 -20402004: 31050513 addi a0,a0,784 # 20402310 <__clz_tab> -20402008: 00f507b3 add a5,a0,a5 -2040200c: 0007c503 lbu a0,0(a5) # 10000 <__stack_size+0xf800> -20402010: 40a70533 sub a0,a4,a0 -20402014: 00008067 ret -20402018: 01000737 lui a4,0x1000 -2040201c: 01000793 li a5,16 -20402020: fce56ae3 bltu a0,a4,20401ff4 <__clzsi2+0x14> -20402024: 01800793 li a5,24 -20402028: fcdff06f j 20401ff4 <__clzsi2+0x14> diff --git a/raven/src/bsp.h b/raven/src/bsp.h new file mode 100644 index 0000000..f04f4f4 --- /dev/null +++ b/raven/src/bsp.h @@ -0,0 +1,22 @@ +/* + * bsp.h + * + * Created on: 30.07.2018 + * Author: eyck + */ + +#ifndef BSP_H_ +#define BSP_H_ + +#ifdef __cplusplus +extern "C" { +#endif +#include +#include +#include +extern void trap_entry(); +#ifdef __cplusplus +} +#endif + +#endif /* BSP_H_ */ diff --git a/raven/src/delay.c b/raven/src/delay.c new file mode 100644 index 0000000..24070b4 --- /dev/null +++ b/raven/src/delay.c @@ -0,0 +1,123 @@ +/* + * delay.c + * + * Created on: 30.07.2018 + * Author: eyck + */ + +#include "delay.h" + +#define rdmcycle(x) { \ + uint32_t lo, hi, hi2; \ + __asm__ __volatile__ ("1:\n\t" \ + "csrr %0, mcycleh\n\t" \ + "csrr %1, mcycle\n\t" \ + "csrr %2, mcycleh\n\t" \ + "bne %0, %2, 1b\n\t" \ + : "=r" (hi), "=r" (lo), "=r" (hi2)) ; \ + *(x) = lo | ((uint64_t) hi << 32); \ + } + +typedef struct { + uint32_t n; + uint32_t mult; + uint32_t shift; +} int_inverse ; + +int_inverse f_cpu_1000_inv; +int_inverse f_cpu_1000000_inv; + +uint32_t F_CPU=1000000; + +void calc_inv(uint32_t n, int_inverse * res){ + uint32_t one = ~0; + uint32_t d = one/n; + uint32_t r = one%n + 1; + if (r >= n) ++d; + if (d == 0) --d; + uint32_t shift = 0; + while ((d & 0x80000000) == 0){ + d <<= 1; + ++shift; + } + res->n = n; + res->mult = d; + res->shift = shift; +} + +uint32_t divide32_using_inverse(uint32_t n, int_inverse *inv){ + uint32_t d = (uint32_t)(((uint64_t)n * inv->mult) >> 32); + d >>= inv->shift; + if (n - d*inv->n >= inv->n) ++d; + return d; +} + +// Almost full-range 64/32 divide. +// If divisor-1 has i bits, then the answer is exact for n of up to 64-i bits +// e.g. for divisors up to a million, n can have up to 45 bits +// On RV32IM with divide32_using_inverse inlines this uses 5 multiplies, +// 33 instructions, zero branches, 3 loads, 0 stores. +uint64_t divide64_using_inverse(uint64_t n, int_inverse *inv){ + uint32_t preshift = (31 - inv->shift) & 31; + uint64_t d = (uint64_t)divide32_using_inverse(n >> preshift, inv) << preshift; + uint32_t r = n - d * inv->n; + d += divide32_using_inverse(r, inv); + return d; +} + + +uint32_t millis(){ + uint64_t x; + rdmcycle(&x); + x = divide64_using_inverse(x, &f_cpu_1000_inv); + return((uint32_t) (x & 0xFFFFFFFF)); +} + +uint32_t micros(void){ + uint64_t x; + rdmcycle(&x); + // For Power-of-two MHz F_CPU, + // this compiles into a simple shift, + // and is faster than the general solution. +#if F_CPU==16000000 + x = x / (F_CPU / 1000000); +#else +#if F_CPU==256000000 + x = x / (F_CPU / 1000000); +#else + x = divide64_using_inverse(x, &f_cpu_1000000_inv); +#endif +#endif + return((uint32_t) (x & 0xFFFFFFFF)); +} + + +void delayMS(uint32_t dwMs){ + uint64_t current, later; + rdmcycle(¤t); + later = current + dwMs * (F_CPU/1000); + if (later > current){ // usual case + while (later > current) + rdmcycle(¤t); + } else { // wrap. Though this is unlikely to be hit w/ 64-bit mcycle + while (later < current) + rdmcycle(¤t); + while (current < later) + rdmcycle(¤t); + } +} + +void delayUS(uint32_t dwUs){ + uint64_t current, later; + rdmcycle(¤t); + later = current + dwUs * (F_CPU/1000000); + if (later > current){ // usual case + while (later > current) + rdmcycle(¤t); + } else {// wrap. Though this is unlikely to be hit w/ 64-bit mcycle + while (later < current) + rdmcycle(¤t); + while (current < later) + rdmcycle(¤t); + } +} diff --git a/raven/src/delay.h b/raven/src/delay.h new file mode 100644 index 0000000..36ce098 --- /dev/null +++ b/raven/src/delay.h @@ -0,0 +1,25 @@ +/* + * delay.h + * + * Created on: 30.07.2018 + * Author: eyck + */ + +#ifndef DELAY_H_ +#define DELAY_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +extern uint32_t F_CPU; + +void delayMS(uint32_t dwMs); +void delayUS(uint32_t dwUs); + +#ifdef __cplusplus +} +#endif + +#endif /* DELAY_H_ */ diff --git a/raven/src/hello_raven.cpp b/raven/src/hello_raven.cpp new file mode 100644 index 0000000..60f558e --- /dev/null +++ b/raven/src/hello_raven.cpp @@ -0,0 +1,148 @@ +#include "hello_raven.h" +#include "delay.h" +#include "bsp.h" +#include "plic/plic_driver.h" + +#include +#include + +#include "hifive1_io.h" + + + +#define IOF_ENABLE_TERMINAL (0x30000) + + +typedef void (*function_ptr_t) (void); +//! Instance data for the PLIC. +plic_instance_t g_plic; +std::array g_ext_interrupt_handlers; + + +char * end = (char *)0x80001000; // TODO: end supposed to be a RAM section according to the linker file falsh.lds, but for some reason it's not initialized + +/*! \brief external interrupt handler + * + * routes the peripheral interrupts to the the respective handler + * + */ +extern "C" void handle_m_ext_interrupt() { + plic_source int_num = PLIC_claim_interrupt(&g_plic); + if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS)) + g_ext_interrupt_handlers[int_num](); + else + exit(1 + (uintptr_t) int_num); + PLIC_complete_interrupt(&g_plic, int_num); +} +/*! \brief mtime interval interrupt + * + */ +extern "C" void handle_m_time_interrupt(){ + clear_csr(mie, MIP_MTIP); + // Reset the timer for 3s in the future. + // This also clears the existing timer interrupt. + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); + uint64_t now = *mtime; + uint64_t then = now + RTC_FREQ; + *mtimecmp = then; + // Re-enable the timer interrupt. + set_csr(mie, MIP_MTIP); +} +/*! \brief dummy interrupt handler + * + */ +void no_interrupt_handler (void) {}; +/*! \brief configure the per-interrupt handler + * + */ +void configure_irq(size_t irq_num, function_ptr_t handler, unsigned char prio=1) { + g_ext_interrupt_handlers[irq_num] = handler; + // Priority must be set > 0 to trigger the interrupt. + PLIC_set_priority(&g_plic, irq_num, prio); + // Have to enable the interrupt both at the GPIO level, and at the PLIC level. + PLIC_enable_interrupt(&g_plic, irq_num); +} + +static void msi_interrupt_handler(){ + int * local_mem_base = (int *) end; + int hartid = read_csr(mhartid); + + int val_a = *local_mem_base; + int val_b = *(local_mem_base+1); + int sum = val_a + val_b; + *(local_mem_base+100) = sum; + if (sum == 0xF) + printf("HW thread ID %d: sum of A+B=0x%x\n", hartid, sum); + else { + printf("HW thread ID %d: sum of A+B is not 0x%x. Test FAILED!!!\n", hartid, sum); + } +} + +/*!\brief initializes platform + * + */ +void platform_init(){ + // configure clocks + PRCI_use_hfxosc(1); // is equivalent to + qspi1::sckdiv_reg() = 8; + + F_CPU=PRCI_measure_mcycle_freq(20, RTC_FREQ); + printf("core freq at %d Hz\n", F_CPU); + // initialie interupt & trap handling + write_csr(mtvec, &trap_entry); + + PLIC_init(&g_plic, PLIC_CTRL_ADDR, PLIC_NUM_INTERRUPTS, PLIC_NUM_PRIORITIES, 0); + // Disable the machine & timer interrupts until setup is done. + clear_csr(mie, MIP_MEIP); + clear_csr(mie, MIP_MTIP); + for (auto& h:g_ext_interrupt_handlers) h=no_interrupt_handler; + configure_irq(1, msi_interrupt_handler); + // Set the machine timer to go off in 1 second. + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); + uint64_t now = *mtime; + uint64_t then = now + RTC_FREQ; + *mtimecmp = then; + // Enable the Machine-External bit in MIE + set_csr(mie, MIP_MEIP); + // Enable the Machine-Timer bit in MIE + set_csr(mie, MIP_MTIP); + // Enable interrupts in general. + set_csr(mstatus, MSTATUS_MIE); +} + +/*! \brief main function + * + */ +int main() { + volatile int * target_mem_base = (int *)(end + 0x10000000); + int * local_mem_base = (int *) end; + int * plic_b_pending = (int *)(0xA0000000+PLIC_PENDING_OFFSET); + + int * local_sync_bit = (int *)(local_mem_base + 10); + int * target_sync_bit = (int *)(target_mem_base + 10); + + int hartid = read_csr(mhartid); + + *local_sync_bit = 0; + GPIO_REG(GPIO_IOF_EN) |= IOF_ENABLE_TERMINAL; // enable GPIO connection to the terminal + platform_init(); + // Enable the Machine-External bit in MIE + set_csr(mie, MIP_MEIP); + + if (hartid == 0) { + int val_a = 5; + int val_b = 0xA; + *target_mem_base = val_a; + *(target_mem_base+1) = val_b; + *(plic_b_pending) = 2; + printf("HW thread ID %d: write value A=0x%x and value B=0x%x to thread 1\n", hartid, val_a, val_b); + } + + *local_sync_bit++; + while (*target_sync_bit < *local_sync_bit); + + printf("End of execution"); + return 0; +} diff --git a/raven/src/hello_raven.h b/raven/src/hello_raven.h new file mode 100644 index 0000000..ec287f6 --- /dev/null +++ b/raven/src/hello_raven.h @@ -0,0 +1,7 @@ +#ifndef HELLO_RAVEN_H_ +#define HELLO_RAVEN_H_ + +extern "C" void handle_m_ext_interrupt(); +extern "C" void handle_m_time_interrupt(); + +#endif /* HELLO_RAVEN_H_ */ diff --git a/raven/src/hifive1_io.cpp b/raven/src/hifive1_io.cpp new file mode 100644 index 0000000..2822762 --- /dev/null +++ b/raven/src/hifive1_io.cpp @@ -0,0 +1,16 @@ +/* + * peripherals.c + * + * Created on: 10.09.2018 + * Author: eyck + */ + +#include "hifive1_io.h" + +template<> volatile bool qspi0::spi_active=false; +template<> volatile bool qspi1::spi_active=false; +template<> volatile bool qspi2::spi_active=false; +template<> volatile bool pwm0::pwm_active=false; +template<> volatile bool pwm1::pwm_active=false; +template<> volatile bool pwm2::pwm_active=false; + diff --git a/raven/src/hifive1_io.h b/raven/src/hifive1_io.h new file mode 100644 index 0000000..9dc4325 --- /dev/null +++ b/raven/src/hifive1_io.h @@ -0,0 +1,26 @@ +/* + * peripherals.h + * + * Created on: 29.07.2018 + * Author: eyck + */ + +#ifndef HIFIVE1_IO_H_ +#define HIFIVE1_IO_H_ + +#include "io/gpio.h" +#include "io/spi.h" +#include "io/pwm.h" +#include "io/uart.h" + +using gpio0=gpio_regs<0x10012000>; +using uart0=uart_regs<0x10013000>; +using uart1=uart_regs<0x10023000>; +using qspi0=spi_regs<0x10014000>; +using qspi1=spi_regs<0x10024000>; +using qspi2=spi_regs<0x10034000>; +using pwm0 =pwm_regs<0x10015000>; +using pwm1 =pwm_regs<0x10025000>; +using pwm2 =pwm_regs<0x10035000>; + +#endif /* HIFIVE1_IO_H_ */ diff --git a/raven/src/io/gpio.h b/raven/src/io/gpio.h new file mode 100644 index 0000000..466f2d2 --- /dev/null +++ b/raven/src/io/gpio.h @@ -0,0 +1,89 @@ +/* + * gpio.h + * + * Created on: 29.07.2018 + * Author: eyck + */ + +#ifndef GPIO_H_ +#define GPIO_H_ + +#include +#include + +template +class gpio_regs { +public: + static inline uint32_t& value_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_INPUT_VAL); + } + + static inline uint32_t& input_en_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_INPUT_EN); + } + + static inline uint32_t& output_en_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_OUTPUT_EN); + } + + static inline uint32_t& port_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_OUTPUT_VAL); + } + + static inline uint32_t& pue_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_PULLUP_EN); + } + + static inline uint32_t& ds_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_DRIVE); + } + + static inline uint32_t& rise_ie_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_RISE_IE); + } + + static inline uint32_t& rise_ip_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_RISE_IP); + } + + static inline uint32_t& fall_ie_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_FALL_IE); + } + + static inline uint32_t& fall_ip_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_FALL_IP); + } + + static inline uint32_t& high_ie_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_HIGH_IE); + } + + static inline uint32_t& high_ip_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_HIGH_IP); + } + + static inline uint32_t& low_ie_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_LOW_IE); + } + + static inline uint32_t& low_ip_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_LOW_IP); + } + + static inline uint32_t& iof_en_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_IOF_EN); + } + + static inline uint32_t& iof_sel_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_IOF_SEL); + } + + static inline uint32_t& out_xor_reg(){ + return *reinterpret_cast(BASE_ADDR+GPIO_OUTPUT_XOR); + } + +}; + + + +#endif /* GPIO_H_ */ diff --git a/raven/src/io/pwm.h b/raven/src/io/pwm.h new file mode 100644 index 0000000..2aab61b --- /dev/null +++ b/raven/src/io/pwm.h @@ -0,0 +1,122 @@ +/* + * pwm.h + * + * Created on: 29.07.2018 + * Author: eyck + */ + +#ifndef PWM_H_ +#define PWM_H_ + +#include +#include "util/bit_field.h" +#include +#include + +template +class pwm_regs { +public: + BEGIN_BF_DECL(pwmcfg_t, uint32_t); + BF_FIELD(scale, 0, 4); + BF_FIELD(sticky, 8, 1); + BF_FIELD(zerocmp, 9, 1); + BF_FIELD(deglitch, 10, 1); + BF_FIELD(enalways, 12, 1); + BF_FIELD(enoneshot, 13, 1); + BF_FIELD(cmp0center, 16, 1); + BF_FIELD(cmp1center, 17, 1); + BF_FIELD(cmp2center, 18, 1); + BF_FIELD(cmp3center, 19, 1); + BF_FIELD(cmp0gang, 24, 1); + BF_FIELD(cmp1gang, 25, 1); + BF_FIELD(cmp2gang, 26, 1); + BF_FIELD(cmp3gang, 27, 1); + BF_FIELD(cmp0ip, 28, 1); + BF_FIELD(cmp1ip, 29, 1); + BF_FIELD(cmp2ip, 30, 1); + BF_FIELD(cmp3ip, 31, 1); + END_BF_DECL(); + + BEGIN_BF_DECL(pwms_t, uint32_t); + BF_FIELD(s, 0, 16); + END_BF_DECL() r_pwms; + + BEGIN_BF_DECL(pwmcmp0_t, uint32_t); + BF_FIELD(cmp0, 0, 16); + END_BF_DECL() r_pwmcmp0; + + BEGIN_BF_DECL(pwmcmp1_t, uint32_t); + BF_FIELD(cmp0, 0, 16); + END_BF_DECL() r_pwmcmp1; + + BEGIN_BF_DECL(pwmcmp2_t, uint32_t); + BF_FIELD(cmp0, 0, 16); + END_BF_DECL() r_pwmcmp2; + + BEGIN_BF_DECL(pwmcmp3_t, uint32_t); + BF_FIELD(cmp0, 0, 16); + END_BF_DECL() r_pwmcmp3; + + static inline pwmcfg_t& cfg_reg(){ + return *reinterpret_cast(BASE_ADDR+PWM_CFG); + } + + static inline uint32_t& count_reg(){ + return *reinterpret_cast(BASE_ADDR+PWM_COUNT); + } + + static inline pwms_t& s_reg(){ + return *reinterpret_cast(BASE_ADDR+PWM_S); + } + + static inline pwmcmp0_t& cmp0_reg(){ + return *reinterpret_cast(BASE_ADDR+PWM_CMP0); + } + + static inline pwmcmp1_t& cmp1_reg(){ + return *reinterpret_cast(BASE_ADDR+PWM_CMP1); + } + + static inline pwmcmp2_t& cmp2_reg(){ + return *reinterpret_cast(BASE_ADDR+PWM_CMP2); + } + + static inline pwmcmp3_t& cmp3_reg(){ + return *reinterpret_cast(BASE_ADDR+PWM_CMP3); + } + + static inline bool oneshot_delay(long delay_us){ + auto scaling_factor=0; + while(delay_us/(1< std::numeric_limits::max()){ + scaling_factor++; + } + cfg_reg()=0; + count_reg()=0; + cfg_reg().scale=4+scaling_factor; // divide by 16 so we get 1us per pwm clock + cmp0_reg().cmp0 = delay_us/(1< +#include "util/bit_field.h" +#include +#include + +template +class spi_regs { +public: + // storage declarations + BEGIN_BF_DECL(sckdiv_t, uint32_t); + BF_FIELD(div, 0, 12); + END_BF_DECL(); + + BEGIN_BF_DECL(sckmode_t, uint32_t); + BF_FIELD(pha, 0, 1); + BF_FIELD(pol, 1, 1); + END_BF_DECL(); + + uint32_t r_csid; + + uint32_t r_csdef; + + BEGIN_BF_DECL(csmode_t, uint32_t); + BF_FIELD(mode, 0, 2); + END_BF_DECL(); + + BEGIN_BF_DECL(delay0_t, uint32_t); + BF_FIELD(cssck, 0, 8); + BF_FIELD(sckcs, 16, 8); + END_BF_DECL(); + + BEGIN_BF_DECL(delay1_t, uint32_t); + BF_FIELD(intercs, 0, 16); + BF_FIELD(interxfr, 16, 8); + END_BF_DECL(); + + BEGIN_BF_DECL(fmt_t, uint32_t); + BF_FIELD(proto, 0, 2); + BF_FIELD(endian, 2, 1); + BF_FIELD(dir, 3, 1); + BF_FIELD(len, 16, 4); + END_BF_DECL(); + + BEGIN_BF_DECL(txdata_t, uint32_t); + BF_FIELD(data, 0, 8); + BF_FIELD(full, 31, 1); + END_BF_DECL() r_txdata; + + BEGIN_BF_DECL(rxdata_t, uint32_t); + BF_FIELD(data, 0, 8); + BF_FIELD(empty, 31, 1); + END_BF_DECL(); + + BEGIN_BF_DECL(txmark_t, uint32_t); + BF_FIELD(txmark, 0, 3); + END_BF_DECL(); + + BEGIN_BF_DECL(rxmark_t, uint32_t); + BF_FIELD(rxmark, 0, 3); + END_BF_DECL(); + + BEGIN_BF_DECL(fctrl_t, uint32_t); + BF_FIELD(en, 0, 1); + END_BF_DECL(); + + BEGIN_BF_DECL(ffmt_t, uint32_t); + BF_FIELD(cmd_en, 0, 1); + BF_FIELD(addr_len, 1, 2); + BF_FIELD(pad_cnt, 3, 4); + BF_FIELD(cmd_proto, 7, 2); + BF_FIELD(addr_proto, 9, 2); + BF_FIELD(data_proto, 11, 2); + BF_FIELD(cmd_code, 16, 8); + BF_FIELD(pad_code, 24, 8); + END_BF_DECL(); + + BEGIN_BF_DECL(ie_t, uint32_t); + BF_FIELD(txwm, 0, 1); + BF_FIELD(rxwm, 1, 1); + END_BF_DECL(); + + BEGIN_BF_DECL(ip_t, uint32_t); + BF_FIELD(txwm, 0, 1); + BF_FIELD(rxwm, 1, 1); + END_BF_DECL(); + + static inline sckdiv_t& sckdiv_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_SCKDIV); + } + + static inline sckmode_t& sckmode_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_SCKMODE); + } + + static inline uint32_t& csid_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_CSID); + } + + static inline uint32_t& csdef_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_CSDEF); + } + + static inline csmode_t& csmode_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_CSMODE); + } + + static inline delay0_t& dcssck_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_DCSSCK); + } + + static inline uint32_t& dsckcs_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_DSCKCS); + } + + static inline delay1_t& dintercs_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_DINTERCS); + } + + static inline uint32_t& dinterxfr_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_DINTERXFR); + } + + static inline fmt_t& fmt_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_FMT); + } + + static inline txdata_t& txfifo_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_TXFIFO); + } + + static inline rxdata_t& rxfifo_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_RXFIFO); + } + + static inline txmark_t& txctrl_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_TXCTRL); + } + + static inline rxmark_t& rxctrl_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_RXCTRL); + } + + static inline fctrl_t& fctrl_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_FCTRL); + } + + static inline ffmt_t& ffmt_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_FFMT); + } + + static inline ie_t& ie_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_IE); + } + + static inline ip_t& ip_reg(){ + return *reinterpret_cast(BASE_ADDR+SPI_REG_IP); + } + + template + static bool transfer(std::array& bytes){ + csmode_reg().mode=2; // HOLD mode + rxctrl_reg().rxmark=bytes.size()-1; // trigger irq if more than 2 bytes are received; + ie_reg().rxwm=1; + // write data bytes + for(size_t i=0; i +#include "util/bit_field.h" +#include + +template +class uart_regs { +public: + BEGIN_BF_DECL(txdata_t, uint32_t); + BF_FIELD(data, 0, 8); + BF_FIELD(full, 31, 1); + END_BF_DECL() ; + + BEGIN_BF_DECL(rxdata_t, uint32_t); + BF_FIELD(data, 0, 8); + BF_FIELD(empty, 31, 1); + END_BF_DECL(); + + BEGIN_BF_DECL(txctrl_t, uint32_t); + BF_FIELD(txen, 0, 1); + BF_FIELD(nstop, 1, 1); + BF_FIELD(txcnt, 16, 3); + END_BF_DECL(); + + BEGIN_BF_DECL(rxctrl_t, uint32_t); + BF_FIELD(rxen, 0, 1); + BF_FIELD(rxcnt, 16, 3); + END_BF_DECL(); + + BEGIN_BF_DECL(ie_t, uint32_t); + BF_FIELD(txwm, 0, 1); + BF_FIELD(rxwm, 1, 1); + END_BF_DECL(); + + BEGIN_BF_DECL(ip_t, uint32_t); + BF_FIELD(txwm, 0, 1); + BF_FIELD(rxwm, 1, 1); + END_BF_DECL(); + + BEGIN_BF_DECL(div_t, uint32_t); + BF_FIELD(div, 0, 16); + END_BF_DECL(); + + static inline txdata_t& txdata_reg(){ + return *reinterpret_cast(BASE_ADDR+UART_REG_TXFIFO); + } + + static inline rxdata_t& rxdata_reg(){ + return *reinterpret_cast(BASE_ADDR+UART_REG_RXFIFO); + } + + static inline txctrl_t& txctrl_reg(){ + return *reinterpret_cast(BASE_ADDR+UART_REG_TXCTRL); + } + + static inline rxctrl_t& rxctrl_reg(){ + return *reinterpret_cast(BASE_ADDR+UART_REG_RXCTRL); + } + + static inline ie_t& ie_reg(){ + return *reinterpret_cast(BASE_ADDR+UART_REG_IE); + } + + static inline ip_t& ip_reg(){ + return *reinterpret_cast(BASE_ADDR+UART_REG_IP); + } + + static inline div_t& div_reg(){ + return *reinterpret_cast(BASE_ADDR+UART_REG_DIV); + } + +}; + +#endif /* SPI_H_ */ diff --git a/raven/src/util/bit_field.h b/raven/src/util/bit_field.h new file mode 100644 index 0000000..d4aff48 --- /dev/null +++ b/raven/src/util/bit_field.h @@ -0,0 +1,179 @@ +/*--------------------------------------------------------- +Copyright (c) 2015 Jeff Preshing + +This software is provided 'as-is', without any express or implied +warranty. In no event will the authors be held liable for any damages +arising from the use of this software. + +Permission is granted to anyone to use this software for any purpose, +including commercial applications, and to alter it and redistribute it +freely, subject to the following restrictions: + +1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgement in the product documentation would be + appreciated but is not required. +2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. +3. This notice may not be removed or altered from any source distribution. +---------------------------------------------------------*/ + +#ifndef BIT_FIELD_H_ +#define BIT_FIELD_H_ + +#ifndef __CPP11OM_BITFIELD_H__ +#define __CPP11OM_BITFIELD_H__ + +#include + +//--------------------------------------------------------- +// BitFieldMember<>: Used internally by ADD_BITFIELD_MEMBER macro. +// All members are public to simplify compliance with sections 9.0.7 and +// 9.5.1 of the C++11 standard, thereby avoiding undefined behavior. +//--------------------------------------------------------- +template struct BitFieldMember { + T value; + + static_assert(Offset + Bits <= (int)sizeof(T) * 8, "Member exceeds bitfield boundaries"); + static_assert(Bits < (int)sizeof(T) * 8, "Can't fill entire bitfield with one member"); + + static const T Maximum = (T(1) << Bits) - 1; + static const T Mask = Maximum << Offset; + T maximum() const { return Maximum; } + T one() const { return T(1) << Offset; } + + operator T() const { return (value >> Offset) & Maximum; } + + BitFieldMember &operator=(T v) { + assert(v <= Maximum); // v must fit inside the bitfield member + value = (value & ~Mask) | (v << Offset); + return *this; + } + + BitFieldMember &operator+=(T v) { + assert(T(*this) + v <= Maximum); // result must fit inside the bitfield member + value += v << Offset; + return *this; + } + + BitFieldMember &operator-=(T v) { + assert(T(*this) >= v); // result must not underflow + value -= v << Offset; + return *this; + } + + BitFieldMember &operator++() { return *this += 1; } + BitFieldMember operator++(int) { // postfix form + BitFieldMember tmp(*this); + operator++(); + return tmp; + } + BitFieldMember &operator--() { return *this -= 1; } + BitFieldMember operator--(int) { // postfix form + BitFieldMember tmp(*this); + operator--(); + return tmp; + } +}; + +//--------------------------------------------------------- +// BitFieldArray<>: Used internally by ADD_BITFIELD_ARRAY macro. +// All members are public to simplify compliance with sections 9.0.7 and +// 9.5.1 of the C++11 standard, thereby avoiding undefined behavior. +//--------------------------------------------------------- +template class BitFieldArray { +public: + T value; + + static_assert(BaseOffset + BitsPerItem * NumItems <= (int)sizeof(T) * 8, "Array exceeds bitfield boundaries"); + static_assert(BitsPerItem < (int)sizeof(T) * 8, "Can't fill entire bitfield with one array element"); + + static const T Maximum = (T(1) << BitsPerItem) - 1; + T maximum() const { return Maximum; } + int numItems() const { return NumItems; } + + class Element { + private: + T &value; + int offset; + + public: + Element(T &value, int offset) + : value(value) + , offset(offset) {} + T mask() const { return Maximum << offset; } + + operator T() const { return (value >> offset) & Maximum; } + + Element &operator=(T v) { + assert(v <= Maximum); // v must fit inside the bitfield member + value = (value & ~mask()) | (v << offset); + return *this; + } + + Element &operator+=(T v) { + assert(T(*this) + v <= Maximum); // result must fit inside the bitfield member + value += v << offset; + return *this; + } + + Element &operator-=(T v) { + assert(T(*this) >= v); // result must not underflow + value -= v << offset; + return *this; + } + + Element &operator++() { return *this += 1; } + Element operator++(int) { // postfix form + Element tmp(*this); + operator++(); + return tmp; + } + Element &operator--() { return *this -= 1; } + Element operator--(int) { // postfix form + Element tmp(*this); + operator--(); + return tmp; + } + }; + + Element operator[](int i) { + assert(i >= 0 && i < NumItems); // array index must be in range + return Element(value, BaseOffset + BitsPerItem * i); + } + + const Element operator[](int i) const { + assert(i >= 0 && i < NumItems); // array index must be in range + return Element(value, BaseOffset + BitsPerItem * i); + } +}; + +//--------------------------------------------------------- +// Bitfield definition macros. +// All members are public to simplify compliance with sections 9.0.7 and +// 9.5.1 of the C++11 standard, thereby avoiding undefined behavior. +//--------------------------------------------------------- +#define BEGIN_BF_DECL(typeName, T) \ + union typeName { \ + struct Wrapper { \ + T value; \ + }; \ + Wrapper flat; \ + typeName(T v = 0) { flat.value = v; } \ + typeName &operator=(T v) { \ + flat.value = v; \ + return *this; \ + } \ + operator T &() { return flat.value; } \ + operator T() const { return flat.value; } \ + using StorageType = T; + +#define BF_FIELD(memberName, offset, bits) BitFieldMember memberName; + +#define BF_ARRAY(memberName, offset, bits, numItems) BitFieldArray memberName; + +#define END_BF_DECL() } + +#endif // __CPP11OM_BITFIELD_H__ + +#endif /* BIT_FIELD_H_ */ diff --git a/raven/wrap_printf.c b/raven/src/wrap_printf.c similarity index 99% rename from raven/wrap_printf.c rename to raven/src/wrap_printf.c index 025d231..af23b1a 100644 --- a/raven/wrap_printf.c +++ b/raven/src/wrap_printf.c @@ -11,7 +11,7 @@ #undef putchar int putchar(int ch) { - return write(1, &ch, 1) == 1 ? ch : -1; + return write(STDOUT_FILENO, &ch, 1) == 1 ? ch : -1; } static void sprintf_putch(int ch, void** data) diff --git a/raven/toolchain-rv32.cmake b/raven/toolchain-rv32.cmake new file mode 100644 index 0000000..bd5ee3b --- /dev/null +++ b/raven/toolchain-rv32.cmake @@ -0,0 +1,33 @@ +set(CMAKE_SYSTEM_NAME Linux) +set(CMAKE_SYSTEM_VERSION 1) +set(CMAKE_SYSTEM_PROCESSOR riscv) + +set(TOOLCHAIN_DIR /opt/riscv/tools) +set(ARCHITECTURE riscv64-unknown-elf) + +set(CMAKE_C_COMPILER ${ARCHITECTURE}-gcc +set(CMAKE_CXX_COMPILER ${ARCHITECTURE}-g++ +set(RISCV_LINUX_SYSROOT /opt/riscv/tools CACHE PATH "RISC-V cross compilation system root") # search path for the cross compile toolchain + +set(CMAKE_CXX_FLAGS "" CACHE STRING "c++ flags") +set(CMAKE_C_FLAGS "" CACHE STRING "c flags") +set(CMAKE_SHARED_LINKER_FLAGS "" CACHE STRING "shared linker flags") +set(CMAKE_MODULE_LINKER_FLAGS "" CACHE STRING "module linker flags") +set(CMAKE_EXE_LINKER_FLAGS "" CACHE STRING "executable linker flags") + +set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=rv32imac -mabi=ilp32") +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -march=rv32imac -mabi=ilp32") +#set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS}") +#set(CMAKE_MODULE_LINKER_FLAGS "${CMAKE_MODULE_LINKER_FLAGS}") +set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -march=rv32imac -mabi=ilp32") + +set(COMPILER_IS_RV32 "1") #flags for the CMakeList.txt +#add_definitions(-D_ARM_TEGRA3) # C/C++ preprocessor macro, which will be used in many many files + +set(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_DIR}/${ARCHITECTURE}) + +include_directories(${TOOLCHAIN_DIR}/${ARCHITECTURE}/include) + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) \ No newline at end of file