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core_complex.h 5.2KB

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  1. /*******************************************************************************
  2. * Copyright (C) 2017, 2018 MINRES Technologies GmbH
  3. * All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are met:
  7. *
  8. * 1. Redistributions of source code must retain the above copyright notice,
  9. * this list of conditions and the following disclaimer.
  10. *
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. *
  15. * 3. Neither the name of the copyright holder nor the names of its contributors
  16. * may be used to endorse or promote products derived from this software
  17. * without specific prior written permission.
  18. *
  19. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29. * POSSIBILITY OF SUCH DAMAGE.
  30. *
  31. *******************************************************************************/
  32. #ifndef _SYSC_SIFIVE_FE310_H_
  33. #define _SYSC_SIFIVE_FE310_H_
  34. #include "scc/initiator_mixin.h"
  35. #include "scc/traceable.h"
  36. #include "scc/utilities.h"
  37. #include "scv4tlm/tlm_rec_initiator_socket.h"
  38. #include <cci_configuration>
  39. #include <tlm>
  40. #include <tlm_utils/tlm_quantumkeeper.h>
  41. #include <util/range_lut.h>
  42. class scv_tr_db;
  43. class scv_tr_stream;
  44. struct _scv_tr_generator_default_data;
  45. template <class T_begin, class T_end> class scv_tr_generator;
  46. namespace iss {
  47. class vm_if;
  48. namespace arch {
  49. template <typename BASE> class riscv_hart_msu_vp;
  50. }
  51. namespace debugger {
  52. class target_adapter_if;
  53. }
  54. }
  55. namespace sysc {
  56. class tlm_dmi_ext : public tlm::tlm_dmi {
  57. public:
  58. bool operator==(const tlm_dmi_ext &o) const {
  59. return this->get_granted_access() == o.get_granted_access() &&
  60. this->get_start_address() == o.get_start_address() && this->get_end_address() == o.get_end_address();
  61. }
  62. bool operator!=(const tlm_dmi_ext &o) const { return !operator==(o); }
  63. };
  64. namespace SiFive {
  65. class core_wrapper;
  66. class core_complex : public sc_core::sc_module, public scc::traceable {
  67. public:
  68. SC_HAS_PROCESS(core_complex);// NOLINT
  69. scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator;
  70. sc_core::sc_in<sc_core::sc_time> clk_i;
  71. sc_core::sc_in<bool> rst_i;
  72. sc_core::sc_in<bool> global_irq_i;
  73. sc_core::sc_in<bool> timer_irq_i;
  74. sc_core::sc_in<bool> sw_irq_i;
  75. sc_core::sc_vector<sc_core::sc_in<bool>> local_irq_i;
  76. cci::cci_param<std::string> elf_file;
  77. cci::cci_param<bool> enable_disass;
  78. cci::cci_param<uint64_t> reset_address;
  79. cci::cci_param<unsigned short> gdb_server_port;
  80. cci::cci_param<bool> dump_ir;
  81. core_complex(sc_core::sc_module_name name);
  82. ~core_complex();
  83. inline void sync(uint64_t cycle) {
  84. auto time = curr_clk * (cycle - last_sync_cycle);
  85. quantum_keeper.inc(time);
  86. if (quantum_keeper.need_sync()) {
  87. wait(quantum_keeper.get_local_time());
  88. quantum_keeper.reset();
  89. }
  90. last_sync_cycle = cycle;
  91. }
  92. bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
  93. bool write_mem(uint64_t addr, unsigned length, const uint8_t *const data);
  94. bool read_mem_dbg(uint64_t addr, unsigned length, uint8_t *const data);
  95. bool write_mem_dbg(uint64_t addr, unsigned length, const uint8_t *const data);
  96. void trace(sc_core::sc_trace_file *trf) const override;
  97. void disass_output(uint64_t pc, const std::string instr);
  98. protected:
  99. void before_end_of_elaboration();
  100. void start_of_simulation();
  101. void run();
  102. void clk_cb();
  103. void rst_cb();
  104. void sw_irq_cb();
  105. void timer_irq_cb();
  106. void global_irq_cb();
  107. uint64_t last_sync_cycle = 0;
  108. util::range_lut<tlm_dmi_ext> read_lut, write_lut;
  109. tlm_utils::tlm_quantumkeeper quantum_keeper;
  110. std::vector<uint8_t> write_buf;
  111. std::unique_ptr<core_wrapper> cpu;
  112. std::unique_ptr<iss::vm_if> vm;
  113. sc_core::sc_time curr_clk;
  114. iss::debugger::target_adapter_if *tgt_adapter;
  115. #ifdef WITH_SCV
  116. //! transaction recording database
  117. scv_tr_db *m_db;
  118. //! blocking transaction recording stream handle
  119. scv_tr_stream *stream_handle;
  120. //! transaction generator handle for blocking transactions
  121. scv_tr_generator<_scv_tr_generator_default_data, _scv_tr_generator_default_data> *instr_tr_handle;
  122. scv_tr_generator<uint64_t, _scv_tr_generator_default_data> *fetch_tr_handle;
  123. scv_tr_handle tr_handle;
  124. #endif
  125. };
  126. } /* namespace SiFive */
  127. } /* namespace sysc */
  128. #endif /* _SYSC_SIFIVE_FE310_H_ */