////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
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//    this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution.
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//    may be used to endorse or promote products derived from this software
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// Created on: Tue Sep 05 18:57:24 CEST 2017
//             *      rv64ia.cpp Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////

#include "util/ities.h"
#include <util/logging.h>

#include <elfio/elfio.hpp>
#include <iss/arch/rv64ia.h>

#ifdef __cplusplus
extern "C" {
#endif
#include <ihex.h>
#ifdef __cplusplus
}
#endif
#include <cstdio>
#include <cstring>
#include <fstream>

using namespace iss::arch;

rv64ia::rv64ia() { reg.icount = 0; reg.machine_state = 0x3;}

rv64ia::~rv64ia(){}

void rv64ia::reset(uint64_t address) {
    for (size_t i = 0; i < traits<rv64ia>::NUM_REGS; ++i)
        set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t), 0));
    reg.PC = address;
    reg.NEXT_PC = reg.PC;
    reg.trap_state = 0;
    reg.machine_state = 0x3;
}

uint8_t *rv64ia::get_regs_base_ptr() { return reinterpret_cast<uint8_t *>(&reg); }

rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t &pc) {
    return phys_addr_t(pc); // change logical address to physical address
}