/******************************************************************************* * Copyright (C) 2021 MINRES Technologies GmbH * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * 3. Neither the name of the copyright holder nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * *******************************************************************************/ #include "../fp_functions.h" #include #include #include #include #include #include #include #include #include #include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif #include #include #include namespace iss { namespace interp { namespace tgc_c { using namespace iss::arch; using namespace iss::debugger; using namespace std::placeholders; template class vm_impl : public iss::interp::vm_base { public: using traits = arch::traits; using super = typename iss::interp::vm_base; using virt_addr_t = typename super::virt_addr_t; using phys_addr_t = typename super::phys_addr_t; using code_word_t = typename super::code_word_t; using addr_t = typename super::addr_t; using reg_t = typename traits::reg_t; using mem_type_e = typename traits::mem_type_e; vm_impl(); vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } target_adapter_if *accquire_target_adapter(server_if *srv) override { debugger_if::dbg_enabled = true; if (super::tgt_adapter == nullptr) super::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); return super::tgt_adapter; } protected: using this_class = vm_impl; using compile_ret_t = virt_addr_t; using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr); inline const char *name(size_t index){return traits::reg_aliases.at(index);} typename arch::traits::opcode_e decode_inst_id(code_word_t instr); virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override; // some compile time constants // enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 }; enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 }; enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 }; enum { LUT_SIZE = 1 << util::bit_count(static_cast(EXTR_MASK32)), LUT_SIZE_C = 1 << util::bit_count(static_cast(EXTR_MASK16)) }; std::array lut; std::array lut_00, lut_01, lut_10; std::array lut_11; struct instruction_pattern { uint32_t value; uint32_t mask; typename arch::traits::opcode_e id; }; std::array, 4> qlut; inline void raise(uint16_t trap_id, uint16_t cause){ auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id; this->template get_reg(traits::TRAP_STATE) = trap_val; this->template get_reg(traits::NEXT_PC) = std::numeric_limits::max(); } inline void leave(unsigned lvl){ this->core.leave_trap(lvl); } inline void wait(unsigned type){ this->core.wait_until(type); } using yield_t = boost::coroutines2::coroutine::push_type; using coro_t = boost::coroutines2::coroutine::pull_type; std::vector spawn_blocks; template T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;} inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){ auto ret = super::template read_mem(space, addr); if(this->template get_reg(traits::TRAP_STATE)) throw 0; return ret; } inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){ auto ret = super::template read_mem(space, addr); if(this->template get_reg(traits::TRAP_STATE)) throw 0; return ret; } inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){ auto ret = super::template read_mem(space, addr); if(this->template get_reg(traits::TRAP_STATE)) throw 0; return ret; } inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){ auto ret = super::template read_mem(space, addr); if(this->template get_reg(traits::TRAP_STATE)) throw 0; return ret; } inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){ super::write_mem(space, addr, data); if(this->template get_reg(traits::TRAP_STATE)) throw 0; } inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){ super::write_mem(space, addr, data); if(this->template get_reg(traits::TRAP_STATE)) throw 0; } inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){ super::write_mem(space, addr, data); if(this->template get_reg(traits::TRAP_STATE)) throw 0; } inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){ super::write_mem(space, addr, data); if(this->template get_reg(traits::TRAP_STATE)) throw 0; } template::type> inline S sext(U from) { auto mask = (1ULL<::opcode_e op; }; const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits::opcode_e::LUI}, {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits::opcode_e::AUIPC}, {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, arch::traits::opcode_e::JAL}, {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::JALR}, {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BEQ}, {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BNE}, {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLT}, {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGE}, {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLTU}, {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGEU}, {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LB}, {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LH}, {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LW}, {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LBU}, {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LHU}, {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SB}, {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SH}, {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SW}, {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ADDI}, {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTI}, {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTIU}, {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::XORI}, {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ORI}, {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ANDI}, {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLLI}, {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRLI}, {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRAI}, {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::ADD}, {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SUB}, {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLL}, {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLT}, {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLTU}, {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::XOR}, {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRL}, {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRA}, {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::OR}, {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::AND}, {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE}, {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::ECALL}, {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::EBREAK}, {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::URET}, {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::SRET}, {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::MRET}, {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::WFI}, {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::DRET}, {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRW}, {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRS}, {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRC}, {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRWI}, {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRSI}, {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRCI}, {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE_I}, {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MUL}, {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULH}, {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULHSU}, {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULHU}, {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::DIV}, {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::DIVU}, {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REM}, {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REMU}, {16, 0b0000000000000000, 0b1110000000000011, arch::traits::opcode_e::CADDI4SPN}, {16, 0b0100000000000000, 0b1110000000000011, arch::traits::opcode_e::CLW}, {16, 0b1100000000000000, 0b1110000000000011, arch::traits::opcode_e::CSW}, {16, 0b0000000000000001, 0b1110000000000011, arch::traits::opcode_e::CADDI}, {16, 0b0000000000000001, 0b1110111110000011, arch::traits::opcode_e::CNOP}, {16, 0b0010000000000001, 0b1110000000000011, arch::traits::opcode_e::CJAL}, {16, 0b0100000000000001, 0b1110000000000011, arch::traits::opcode_e::CLI}, {16, 0b0110000000000001, 0b1110000000000011, arch::traits::opcode_e::CLUI}, {16, 0b0110000100000001, 0b1110111110000011, arch::traits::opcode_e::CADDI16SP}, {16, 0b0110000000000001, 0b1111000001111111, arch::traits::opcode_e::__reserved_clui}, {16, 0b1000000000000001, 0b1111110000000011, arch::traits::opcode_e::CSRLI}, {16, 0b1000010000000001, 0b1111110000000011, arch::traits::opcode_e::CSRAI}, {16, 0b1000100000000001, 0b1110110000000011, arch::traits::opcode_e::CANDI}, {16, 0b1000110000000001, 0b1111110001100011, arch::traits::opcode_e::CSUB}, {16, 0b1000110000100001, 0b1111110001100011, arch::traits::opcode_e::CXOR}, {16, 0b1000110001000001, 0b1111110001100011, arch::traits::opcode_e::COR}, {16, 0b1000110001100001, 0b1111110001100011, arch::traits::opcode_e::CAND}, {16, 0b1010000000000001, 0b1110000000000011, arch::traits::opcode_e::CJ}, {16, 0b1100000000000001, 0b1110000000000011, arch::traits::opcode_e::CBEQZ}, {16, 0b1110000000000001, 0b1110000000000011, arch::traits::opcode_e::CBNEZ}, {16, 0b0000000000000010, 0b1111000000000011, arch::traits::opcode_e::CSLLI}, {16, 0b0100000000000010, 0b1110000000000011, arch::traits::opcode_e::CLWSP}, {16, 0b1000000000000010, 0b1111000000000011, arch::traits::opcode_e::CMV}, {16, 0b1000000000000010, 0b1111000001111111, arch::traits::opcode_e::CJR}, {16, 0b1000000000000010, 0b1111111111111111, arch::traits::opcode_e::__reserved_cmv}, {16, 0b1001000000000010, 0b1111000000000011, arch::traits::opcode_e::CADD}, {16, 0b1001000000000010, 0b1111000001111111, arch::traits::opcode_e::CJALR}, {16, 0b1001000000000010, 0b1111111111111111, arch::traits::opcode_e::CEBREAK}, {16, 0b1100000000000010, 0b1110000000000011, arch::traits::opcode_e::CSWSP}, {16, 0b0000000000000000, 0b1111111111111111, arch::traits::opcode_e::DII}, }}; //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK; iss::status fetch_ins(virt_addr_t pc, uint8_t * data){ auto phys_pc = this->core.v2p(pc); //if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary // if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err; // if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction // if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err; //} else { if (this->core.read(phys_pc, 4, data) != iss::Ok) return iss::Err; //} return iss::Ok; } }; template void debug_fn(CODE_WORD insn) { volatile CODE_WORD x = insn; insn = 2 * x; } template vm_impl::vm_impl() { this(new ARCH()); } // according to // https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation #ifdef __GCC__ constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); } #elif __cplusplus < 201402L constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); } constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; } #else constexpr size_t bit_count(uint32_t u) { size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); return ((uCount + (uCount >> 3)) & 030707070707) % 63; } #endif template vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) : vm_base(core, core_id, cluster_id) { unsigned id=0; for (auto instr : instr_descr) { auto quadrant = instr.value & 0x3; qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op}); } for(auto& lut: qlut){ std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){ return bit_count(a.mask) > bit_count(b.mask); }); } } inline bool is_count_limit_enabled(finish_cond_e cond){ return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT; } inline bool is_jump_to_self_enabled(finish_cond_e cond){ return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF; } template typename arch::traits::opcode_e vm_impl::decode_inst_id(code_word_t instr){ for(auto& e: qlut[instr&0x3]){ if(!((instr&e.mask) ^ e.value )) return e.id; } return arch::traits::opcode_e::MAX_OPCODE; } template typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){ // we fetch at max 4 byte, alignment is 2 code_word_t instr = 0; auto *const data = (uint8_t *)&instr; auto pc=start; auto* PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::PC]); auto* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); auto* trap_state = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::TRAP_STATE]); auto* icount = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::ICOUNT]); auto* instret = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::INSTRET]); while(!this->core.should_stop() && !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){ if(fetch_ins(pc, data)!=iss::Ok){ this->do_sync(POST_SYNC, std::numeric_limits::max()); pc.val = super::core.enter_trap(std::numeric_limits::max(), pc.val, 0); } else { if (is_jump_to_self_enabled(cond) && (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' auto inst_id = decode_inst_id(instr); // pre execution stuff if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast(inst_id)); switch(inst_id){ case arch::traits::opcode_e::LUI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint32_t imm = ((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = (int32_t)imm; } catch(...){} } break; case arch::traits::opcode_e::AUIPC: { uint8_t rd = ((bit_sub<7,5>(instr))); uint32_t imm = ((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *PC + (int32_t)imm; } catch(...){} } break; case arch::traits::opcode_e::JAL: { uint8_t rd = ((bit_sub<7,5>(instr))); uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(imm % traits::INSTR_ALIGNMENT) { raise( 0, 0); } else { if(rd != 0) *(X+rd) = *PC + 4; pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm); } } } catch(...){} } break; case arch::traits::opcode_e::JALR: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { int32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 1; if(new_pc % traits::INSTR_ALIGNMENT) { raise( 0, 0); } else { if(rd != 0) *(X+rd) = *PC + 4; pc_assign(*NEXT_PC) = new_pc & ~ 0x1; } } } catch(...){} } break; case arch::traits::opcode_e::BEQ: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(*(X+rs1) == *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) { raise( 0, 0); } else { pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); } } } catch(...){} } break; case arch::traits::opcode_e::BNE: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(*(X+rs1) != *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) { raise( 0, 0); } else { pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); } } } catch(...){} } break; case arch::traits::opcode_e::BLT: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) { raise( 0, 0); } else { pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); } } } catch(...){} } break; case arch::traits::opcode_e::BGE: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) { raise( 0, 0); } else { pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); } } } catch(...){} } break; case arch::traits::opcode_e::BLTU: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(*(X+rs1) < *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) { raise( 0, 0); } else { pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); } } } catch(...){} } break; case arch::traits::opcode_e::BGEU: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(*(X+rs1) >= *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) { raise( 0, 0); } else { pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); } } } catch(...){} } break; case arch::traits::opcode_e::LB: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { int8_t res = (int8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm)); if(rd != 0) *(X+rd) = res; } } catch(...){} } break; case arch::traits::opcode_e::LH: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm); int16_t res = (int16_t)readSpace2(traits::MEM, load_address); if(rd != 0) *(X+rd) = res; } } catch(...){} } break; case arch::traits::opcode_e::LW: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm); int32_t res = (int32_t)readSpace4(traits::MEM, load_address); if(rd != 0) *(X+rd) = (uint32_t)res; } } catch(...){} } break; case arch::traits::opcode_e::LBU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint8_t res = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm)); if(rd != 0) *(X+rd) = res; } } catch(...){} } break; case arch::traits::opcode_e::LHU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm); uint16_t res = (uint16_t)readSpace2(traits::MEM, load_address); if(rd != 0) *(X+rd) = res; } } catch(...){} } break; case arch::traits::opcode_e::SB: { uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { writeSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm), (int8_t)*(X+rs2)); } catch(...){} } break; case arch::traits::opcode_e::SH: { uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm); writeSpace2(traits::MEM, store_address, (int16_t)*(X+rs2)); } } catch(...){} } break; case arch::traits::opcode_e::SW: { uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm); writeSpace4(traits::MEM, store_address, *(X+rs2)); } } catch(...){} } break; case arch::traits::opcode_e::ADDI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm); } catch(...){} } break; case arch::traits::opcode_e::SLTI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int16_t)sext<12>(imm)? 1 : 0; } catch(...){} } break; case arch::traits::opcode_e::SLTIU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0; } catch(...){} } break; case arch::traits::opcode_e::XORI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs1) ^ (int16_t)sext<12>(imm); } catch(...){} } break; case arch::traits::opcode_e::ORI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs1) | (int16_t)sext<12>(imm); } catch(...){} } break; case arch::traits::opcode_e::ANDI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs1) & (int16_t)sext<12>(imm); } catch(...){} } break; case arch::traits::opcode_e::SLLI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(shamt > 31) { raise( 0, 0); } else { if(rd != 0) *(X+rd) = *(X+rs1) << shamt; } } catch(...){} } break; case arch::traits::opcode_e::SRLI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(shamt > 31) { raise( 0, 0); } else { if(rd != 0) *(X+rd) = *(X+rs1) >> shamt; } } catch(...){} } break; case arch::traits::opcode_e::SRAI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(shamt > 31) { raise( 0, 0); } else { if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) >> shamt; } } catch(...){} } break; case arch::traits::opcode_e::ADD: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs1) + *(X+rs2); } catch(...){} } break; case arch::traits::opcode_e::SUB: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs1) - *(X+rs2); } catch(...){} } break; case arch::traits::opcode_e::SLL: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1)); } catch(...){} } break; case arch::traits::opcode_e::SLT: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0; } catch(...){} } break; case arch::traits::opcode_e::SLTU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = (uint32_t)*(X+rs1) < (uint32_t)*(X+rs2)? 1 : 0; } catch(...){} } break; case arch::traits::opcode_e::XOR: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs1) ^ *(X+rs2); } catch(...){} } break; case arch::traits::opcode_e::SRL: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); } catch(...){} } break; case arch::traits::opcode_e::SRA: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); } catch(...){} } break; case arch::traits::opcode_e::OR: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs1) | *(X+rs2); } catch(...){} } break; case arch::traits::opcode_e::AND: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs1) & *(X+rs2); } catch(...){} } break; case arch::traits::opcode_e::FENCE: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t succ = ((bit_sub<20,4>(instr))); uint8_t pred = ((bit_sub<24,4>(instr))); uint8_t fm = ((bit_sub<28,4>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); this->core.disass_output(pc.val, mnemonic); } // used registers// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { writeSpace1(traits::FENCE, traits::fence, pred << 4 | succ); } catch(...){} } break; case arch::traits::opcode_e::ECALL: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "ecall"); } // used registers// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { raise( 0, 11); } catch(...){} } break; case arch::traits::opcode_e::EBREAK: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "ebreak"); } // used registers// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { raise( 0, 3); } catch(...){} } break; case arch::traits::opcode_e::URET: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "uret"); } // used registers// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { leave( 0); } catch(...){} } break; case arch::traits::opcode_e::SRET: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "sret"); } // used registers// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { leave( 1); } catch(...){} } break; case arch::traits::opcode_e::MRET: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "mret"); } // used registers// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { leave( 3); } catch(...){} } break; case arch::traits::opcode_e::WFI: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "wfi"); } // used registers// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { wait( 1); } catch(...){} } break; case arch::traits::opcode_e::DRET: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "dret"); } // used registers auto* PRIV = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::PRIV]); auto* DPC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::DPC]); // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(*PRIV < 4) raise( 0, 2); else { pc_assign(*NEXT_PC) = *DPC; *PRIV &= 0x3; } } } catch(...){} } break; case arch::traits::opcode_e::CSRRW: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint32_t xrs1 = *(X+rs1); if(rd != 0) { uint32_t xrd = readSpace4(traits::CSR, csr); writeSpace4(traits::CSR, csr, xrs1); *(X+rd) = xrd; } else { writeSpace4(traits::CSR, csr, xrs1); } } } catch(...){} } break; case arch::traits::opcode_e::CSRRS: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint32_t xrd = readSpace4(traits::CSR, csr); uint32_t xrs1 = *(X+rs1); if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd | xrs1); if(rd != 0) *(X+rd) = xrd; } } catch(...){} } break; case arch::traits::opcode_e::CSRRC: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint32_t xrd = readSpace4(traits::CSR, csr); uint32_t xrs1 = *(X+rs1); if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd & ~ xrs1); if(rd != 0) *(X+rd) = xrd; } } catch(...){} } break; case arch::traits::opcode_e::CSRRWI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint32_t xrd = readSpace4(traits::CSR, csr); writeSpace4(traits::CSR, csr, (uint32_t)zimm); if(rd != 0) *(X+rd) = xrd; } } catch(...){} } break; case arch::traits::opcode_e::CSRRSI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint32_t xrd = readSpace4(traits::CSR, csr); if(zimm != 0) writeSpace4(traits::CSR, csr, xrd | (uint32_t)zimm); if(rd != 0) *(X+rd) = xrd; } } catch(...){} } break; case arch::traits::opcode_e::CSRRCI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { uint32_t xrd = readSpace4(traits::CSR, csr); if(zimm != 0) writeSpace4(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); if(rd != 0) *(X+rd) = xrd; } } catch(...){} } break; case arch::traits::opcode_e::FENCE_I: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { writeSpace2(traits::FENCE, traits::fencei, imm); } catch(...){} } break; case arch::traits::opcode_e::MUL: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(rd != 0) { int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2); *(X+rd) = (uint32_t)res; } } } catch(...){} } break; case arch::traits::opcode_e::MULH: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(rd != 0) { int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2); *(X+rd) = (uint32_t)(res >> traits::XLEN); } } } catch(...){} } break; case arch::traits::opcode_e::MULHSU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(rd != 0) { int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2); *(X+rd) = (uint32_t)(res >> traits::XLEN); } } } catch(...){} } break; case arch::traits::opcode_e::MULHU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(rd != 0) { uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2); *(X+rd) = (uint32_t)(res >> traits::XLEN); } } } catch(...){} } break; case arch::traits::opcode_e::DIV: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(rd != 0) { if(*(X+rs2) != 0) { uint32_t MMIN = 1 << (traits::XLEN - 1); if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) = MMIN; else *(X+rd) = (int32_t)*(X+rs1) / (int32_t)*(X+rs2); } else *(X+rd) = - 1; } } } catch(...){} } break; case arch::traits::opcode_e::DIVU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(rd != 0) { if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) / *(X+rs2); else *(X+rd) = - 1; } } } catch(...){} } break; case arch::traits::opcode_e::REM: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(rd != 0) { if(*(X+rs2) != 0) { uint32_t MMIN = 1 << (traits::XLEN - 1); if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) = 0; else *(X+rd) = (int32_t)*(X+rs1) % (int32_t)*(X+rs2); } else *(X+rd) = *(X+rs1); } } } catch(...){} } break; case arch::traits::opcode_e::REMU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction try { { if(rd != 0) { if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) % *(X+rs2); else *(X+rd) = *(X+rs1); } } } catch(...){} } break; case arch::traits::opcode_e::CADDI4SPN: { uint8_t rd = ((bit_sub<2,3>(instr))); uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { if(imm) *(X+rd + 8) = *(X+2) + imm; else raise( 0, 2); } catch(...){} } break; case arch::traits::opcode_e::CLW: { uint8_t rd = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "clw"), fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { uint32_t load_address = *(X+rs1 + 8) + uimm; *(X+rd + 8) = (int32_t)readSpace4(traits::MEM, load_address); } } catch(...){} } break; case arch::traits::opcode_e::CSW: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "csw"), fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { uint32_t load_address = *(X+rs1 + 8) + uimm; writeSpace4(traits::MEM, load_address, *(X+rs2 + 8)); } } catch(...){} } break; case arch::traits::opcode_e::CADDI: { uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "caddi"), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { *(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm); } catch(...){} } break; case arch::traits::opcode_e::CNOP: { uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "cnop"); } // used registers// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { } } catch(...){} } break; case arch::traits::opcode_e::CJAL: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cjal"), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { *(X+1) = *PC + 2; pc_assign(*NEXT_PC) = *PC + (int16_t)sext<12>(imm); } } catch(...){} } break; case arch::traits::opcode_e::CLI: { uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "cli"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { if(rd != 0) *(X+rd) = (uint32_t)(int32_t)sext<6>(imm); } } catch(...){} } break; case arch::traits::opcode_e::CLUI: { uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "clui"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { if(imm == 0) raise( 0, 2); if(rd != 0) *(X+rd) = (int32_t)sext<18>(imm); } } catch(...){} } break; case arch::traits::opcode_e::CADDI16SP: { uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "caddi16sp"), fmt::arg("nzimm", nzimm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { if(nzimm) *(X+2) = *(X+2) + (int16_t)sext<10>(nzimm); else raise( 0, 2); } catch(...){} } break; case arch::traits::opcode_e::__reserved_clui: { uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "__reserved_clui"); } // used registers// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { raise( 0, 2); } catch(...){} } break; case arch::traits::opcode_e::CSRLI: { uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrli"), fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { uint32_t rs1_idx = rs1 + 8; *(X+rs1_idx) = *(X+rs1_idx) >> shamt; } } catch(...){} } break; case arch::traits::opcode_e::CSRAI: { uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrai"), fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { if(shamt) { uint32_t rs1_idx = rs1 + 8; *(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >> shamt; } else if(traits::XLEN == 128) { uint32_t rs1_idx = rs1 + 8; *(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >> 64; } } catch(...){} } break; case arch::traits::opcode_e::CANDI: { uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "candi"), fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { uint32_t rs1_idx = rs1 + 8; *(X+rs1_idx) = *(X+rs1_idx) & (int8_t)sext<6>(imm); } } catch(...){} } break; case arch::traits::opcode_e::CSUB: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "csub"), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { uint32_t rd_idx = rd + 8; *(X+rd_idx) = *(X+rd_idx) - *(X+rs2 + 8); } } catch(...){} } break; case arch::traits::opcode_e::CXOR: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cxor"), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { uint32_t rd_idx = rd + 8; *(X+rd_idx) = *(X+rd_idx) ^ *(X+rs2 + 8); } } catch(...){} } break; case arch::traits::opcode_e::COR: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cor"), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { uint32_t rd_idx = rd + 8; *(X+rd_idx) = *(X+rd_idx) | *(X+rs2 + 8); } } catch(...){} } break; case arch::traits::opcode_e::CAND: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cand"), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { uint32_t rd_idx = rd + 8; *(X+rd_idx) = *(X+rd_idx) & *(X+rs2 + 8); } } catch(...){} } break; case arch::traits::opcode_e::CJ: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cj"), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { pc_assign(*NEXT_PC) = *PC + (int16_t)sext<12>(imm); } catch(...){} } break; case arch::traits::opcode_e::CBEQZ: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbeqz"), fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { if(*(X+rs1 + 8) == 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm); } catch(...){} } break; case arch::traits::opcode_e::CBNEZ: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbnez"), fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { if(*(X+rs1 + 8) != 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm); } catch(...){} } break; case arch::traits::opcode_e::CSLLI: { uint8_t nzuimm = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "cslli"), fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { if(nzuimm) *(X+rs1) = *(X+rs1) << nzuimm; } catch(...){} } break; case arch::traits::opcode_e::CLWSP: { uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "clwsp"), fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { if(rd) { uint32_t offs = *(X+2) + uimm; *(X+rd) = (int32_t)readSpace4(traits::MEM, offs); } else raise( 0, 2); } catch(...){} } break; case arch::traits::opcode_e::CMV: { uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cmv"), fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rs2); } catch(...){} } break; case arch::traits::opcode_e::CJR: { uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjr"), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { if(rs1) pc_assign(*NEXT_PC) = *(X+rs1) & ~ 0x1; else raise( 0, 2); } catch(...){} } break; case arch::traits::opcode_e::__reserved_cmv: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "__reserved_cmv"); } // used registers// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { raise( 0, 2); } catch(...){} } break; case arch::traits::opcode_e::CADD: { uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cadd"), fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { if(rd != 0) *(X+rd) = *(X+rd) + *(X+rs2); } catch(...){} } break; case arch::traits::opcode_e::CJALR: { uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjalr"), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { int32_t new_pc = *(X+rs1); *(X+1) = *PC + 2; pc_assign(*NEXT_PC) = new_pc & ~ 0x1; } } catch(...){} } break; case arch::traits::opcode_e::CEBREAK: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "cebreak"); } // used registers// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { raise( 0, 3); } catch(...){} } break; case arch::traits::opcode_e::CSWSP: { uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "cswsp"), fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); this->core.disass_output(pc.val, mnemonic); } // used registers auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { { uint32_t offs = *(X+2) + uimm; writeSpace4(traits::MEM, offs, (uint32_t)*(X+rs2)); } } catch(...){} } break; case arch::traits::opcode_e::DII: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "dii"); } // used registers// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction try { raise( 0, 2); } catch(...){} } break; default: { *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2); raise(0, 2); } } // post execution stuff process_spawn_blocks(); if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast(inst_id)); // trap check if(*trap_state!=0){ super::core.enter_trap(*trap_state, pc.val, instr); } else { (*icount)++; (*instret)++; } (*reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::CYCLE]))++; pc.val=*NEXT_PC; this->core.reg.PC = this->core.reg.NEXT_PC; this->core.reg.trap_state = this->core.reg.pending_trap; } } return pc; } } template <> std::unique_ptr create(arch::tgc_c *core, unsigned short port, bool dump) { auto ret = new tgc_c::vm_impl(*core, dump); if (port != 0) debugger::server::run_server(ret, port); return std::unique_ptr(ret); } } // namespace interp } // namespace iss