From feaff8c4a5c837c0b5408e16a1a78f700bb8579f Mon Sep 17 00:00:00 2001
From: Eyck-Alexander Jentzsch <alex@minres.com>
Date: Thu, 13 Feb 2025 21:05:49 +0100
Subject: [PATCH] adds support for narrowing shifts

---
 gen_input/templates/interp/CORENAME.cpp.gtl | 26 +++++++++++++++++++++
 src/vm/vector_functions.hpp                 | 16 +++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl
index ee3585b..ad1a96b 100644
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -331,6 +331,32 @@ if(vector != null) {%>
                 throw new std::runtime_error("Unsupported sew bit value");
         }
     }
+    void vector_vector_vw(uint8_t* V, uint8_t funct, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, uint8_t vs1, uint8_t sew_val){
+        switch(sew_val){
+            case 0b000:
+                return softvector::vector_vector_op<${vlen}, uint8_t, uint16_t, uint8_t>(V, funct, vl, vstart, vtype, vm, vd, vs2, vs1 );
+            case 0b001:
+                return softvector::vector_vector_op<${vlen}, uint16_t, uint32_t, uint16_t>(V, funct, vl, vstart, vtype, vm, vd, vs2, vs1 );
+            case 0b010:
+                return softvector::vector_vector_op<${vlen}, uint32_t, uint64_t, uint32_t>(V, funct, vl, vstart, vtype, vm, vd, vs2, vs1 );
+            case 0b011: // would require 128 bits vs2 value
+            default:
+                throw new std::runtime_error("Unsupported sew bit value");
+        }
+    }
+    void vector_imm_vw(uint8_t* V, uint8_t funct, uint64_t vl, uint64_t vstart, softvector::vtype_t vtype, bool vm, uint8_t vd, uint8_t vs2, int64_t imm, uint8_t sew_val){
+        switch(sew_val){
+            case 0b000:
+                return softvector::vector_imm_op<${vlen}, uint8_t,  uint16_t, uint8_t>(V, funct, vl, vstart, vtype, vm, vd, vs2, imm);
+            case 0b001:
+                return softvector::vector_imm_op<${vlen}, uint16_t, uint32_t, uint16_t>(V, funct, vl, vstart, vtype, vm, vd, vs2, imm);
+            case 0b010:
+                return softvector::vector_imm_op<${vlen}, uint32_t, uint64_t, uint32_t>(V, funct, vl, vstart, vtype, vm, vd, vs2, imm);
+            case 0b011: // would require 128 bits vs2 value
+            default:
+                throw new std::runtime_error("Unsupported sew bit value");
+        }
+    }
 
 <%}%>
     uint64_t fetch_count{0};
diff --git a/src/vm/vector_functions.hpp b/src/vm/vector_functions.hpp
index f312d89..ecc3e1c 100644
--- a/src/vm/vector_functions.hpp
+++ b/src/vm/vector_functions.hpp
@@ -65,6 +65,12 @@ template <unsigned VLEN> vmask_view read_vmask(uint8_t* V, uint16_t elem_count,
     assert(mask_start + elem_count / 8 <= V + VLEN * RFS / 8);
     return {mask_start, elem_count};
 }
+
+template <typename elem_t> constexpr elem_t shift_mask() {
+    static_assert(std::numeric_limits<elem_t>::is_integer, "shift_mask only supports integer types");
+    return std::numeric_limits<elem_t>::digits - 1;
+}
+
 template <typename dest_elem_t, typename src2_elem_t = dest_elem_t, typename src1_elem_t = dest_elem_t>
 std::function<dest_elem_t(src2_elem_t, src1_elem_t)> get_funct(unsigned funct) {
     switch(funct) {
@@ -85,6 +91,16 @@ std::function<dest_elem_t(src2_elem_t, src1_elem_t)> get_funct(unsigned funct) {
         return [](src2_elem_t vs2, src1_elem_t vs1) { return vs1 | vs2; };
     case 0b001011: // VXOR
         return [](src2_elem_t vs2, src1_elem_t vs1) { return vs1 ^ vs2; };
+    case 0b100101: // VSLL
+        return [](src2_elem_t vs2, src1_elem_t vs1) { return vs2 << (vs1 & shift_mask<src2_elem_t>()); };
+    case 0b101000: // VSRL
+    case 0b101100: // VNSRL
+        return [](src2_elem_t vs2, src1_elem_t vs1) { return vs2 >> (vs1 & shift_mask<src2_elem_t>()); };
+    case 0b101001: // VSRA
+    case 0b101101: // VNSRA
+        return [](src2_elem_t vs2, src1_elem_t vs1) {
+            return static_cast<typename std::make_signed_t<src2_elem_t>>(vs2) >> (vs1 & shift_mask<src2_elem_t>());
+        };
     case 0b110001: // VWADD
     case 0b110101: // VWADD.W
         return [](src2_elem_t vs2, src1_elem_t vs1) {