From fe2d5cb2f99c5e4cb1609db627c3a68435f0b40a Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Wed, 10 Jan 2024 11:47:12 +0100 Subject: [PATCH] adds semihosting to all backends --- gen_input/templates/asmjit/CORENAME.cpp.gtl | 8 +- gen_input/templates/interp/CORENAME.cpp.gtl | 4 +- gen_input/templates/llvm/CORENAME.cpp.gtl | 8 +- gen_input/templates/tcc/CORENAME.cpp.gtl | 12 +- src/iss/arch/tgc5c.h | 1 + src/vm/asmjit/vm_tgc5c.cpp | 20 +- src/vm/llvm/vm_tgc5c.cpp | 5244 ++++++++++--------- src/vm/tcc/vm_tgc5c.cpp | 3841 +++++++------- 8 files changed, 4961 insertions(+), 4177 deletions(-) diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 4dfc294..863628c 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -263,9 +263,9 @@ std::unique_ptr create(arch::${coreD namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); - auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); @@ -273,9 +273,9 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 099b638..e8062c8 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -363,7 +363,7 @@ std::unique_ptr create(arch::${coreD namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -373,7 +373,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/gen_input/templates/llvm/CORENAME.cpp.gtl b/gen_input/templates/llvm/CORENAME.cpp.gtl index da04ae1..d31802f 100644 --- a/gen_input/templates/llvm/CORENAME.cpp.gtl +++ b/gen_input/templates/llvm/CORENAME.cpp.gtl @@ -365,9 +365,9 @@ std::unique_ptr create(arch::${coreD namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); - auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); @@ -375,9 +375,9 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); diff --git a/gen_input/templates/tcc/CORENAME.cpp.gtl b/gen_input/templates/tcc/CORENAME.cpp.gtl index 252df3d..5ac57ae 100644 --- a/gen_input/templates/tcc/CORENAME.cpp.gtl +++ b/gen_input/templates/tcc/CORENAME.cpp.gtl @@ -329,16 +329,24 @@ std::unique_ptr create(arch::${coreD namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }) }; diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 36254f7..7285edd 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -201,6 +201,7 @@ struct tgc5c: public arch_if { inline uint32_t get_last_branch() { return reg.last_branch; } + #pragma pack(push, 1) struct TGC5C_regs { uint32_t X0 = 0; diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index c9656ae..497cc1e 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -3752,16 +3752,24 @@ std::unique_ptr create(arch::tgc5c *core, unsigned short por namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("tgc5c|m_p|asmjit", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("tgc5c|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); - auto* vm = new asmjit::tgc5c::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); + auto vm = new asmjit::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto* vm = new asmjit::tgc5c::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); + auto vm = new asmjit::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }) }; diff --git a/src/vm/llvm/vm_tgc5c.cpp b/src/vm/llvm/vm_tgc5c.cpp index 94fe033..5447fa1 100644 --- a/src/vm/llvm/vm_tgc5c.cpp +++ b/src/vm/llvm/vm_tgc5c.cpp @@ -29,7 +29,7 @@ * POSSIBILITY OF SUCH DAMAGE. * *******************************************************************************/ - +// clang-format off #include #include #include @@ -48,7 +48,7 @@ namespace iss { namespace llvm { namespace fp_impl { -void add_fp_functions_2_module(::llvm::Module*, unsigned, unsigned); +void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned); } namespace tgc5c { @@ -67,13 +67,13 @@ public: vm_impl(); - vm_impl(ARCH& core, unsigned core_id = 0, unsigned cluster_id = 0); + vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } - target_adapter_if* accquire_target_adapter(server_if* srv) override { + target_adapter_if *accquire_target_adapter(server_if *srv) override { debugger_if::dbg_enabled = true; - if(vm_base::tgt_adapter == nullptr) + if (vm_base::tgt_adapter == nullptr) vm_base::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); return vm_base::tgt_adapter; } @@ -81,9 +81,9 @@ public: protected: using vm_base::get_reg_ptr; - inline const char* name(size_t index) { return traits::reg_aliases.at(index); } + inline const char *name(size_t index){return traits::reg_aliases.at(index);} - template inline ConstantInt* size(T type) { + template inline ConstantInt *size(T type) { return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits())); } @@ -92,13 +92,13 @@ protected: iss::llvm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE, traits::XLEN); } - inline Value* gen_choose(Value* cond, Value* trueVal, Value* falseVal, unsigned size) { + inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) { return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size)); } - std::tuple gen_single_inst_behavior(virt_addr_t&, unsigned int&, BasicBlock*) override; + std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override; - void gen_leave_behavior(BasicBlock* leave_blk) override; + void gen_leave_behavior(BasicBlock *leave_blk) override; void gen_raise_trap(uint16_t trap_id, uint16_t cause); @@ -106,28 +106,32 @@ protected: void gen_wait(unsigned type); - void gen_trap_behavior(BasicBlock*) override; + void gen_trap_behavior(BasicBlock *) override; - void gen_trap_check(BasicBlock* bb); + void gen_trap_check(BasicBlock *bb); - inline Value* gen_reg_load(unsigned i, unsigned level = 0) { + inline Value *gen_reg_load(unsigned i, unsigned level = 0) { return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false); } inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) { - Value* next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), this->get_type(traits::XLEN)); + Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), + this->get_type(traits::XLEN)); this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true); } // some compile time constants using this_class = vm_impl; - using compile_func = std::tuple (this_class::*)(virt_addr_t& pc, code_word_t instr, BasicBlock* bb); - template ::type> inline S sext(U from) { - auto mask = (1ULL << W) - 1; - auto sign_mask = 1ULL << (W - 1); + using compile_func = std::tuple (this_class::*)(virt_addr_t &pc, + code_word_t instr, + BasicBlock *bb); + template::type> + inline S sext(U from) { + auto mask = (1ULL< instrs; std::vector children; uint32_t submask = std::numeric_limits::max(); uint32_t value; - decoding_tree_node(uint32_t value) - : value(value) {} + decoding_tree_node(uint32_t value) : value(value){} }; - decoding_tree_node* root{nullptr}; + decoding_tree_node* root {nullptr}; const std::array instr_descr = {{ - /* entries are: size, valid value, valid mask, function ptr */ + /* entries are: size, valid value, valid mask, function ptr */ /* instruction LUI, encoding '0b00000000000000000000000000110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, /* instruction AUIPC, encoding '0b00000000000000000000000000010111' */ @@ -327,3649 +330,4101 @@ private: /* instruction DII, encoding '0b0000000000000000' */ {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, }}; - + /* instruction definitions */ /* instruction 0: LUI */ - std::tuple __lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LUI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 0); + std::tuple __lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LUI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,0); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = ((bit_sub<12, 20>(instr) << 12)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)((int32_t)imm)), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)((int32_t)imm)), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 0); + this->gen_sync(POST_SYNC, 0); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 1: AUIPC */ - std::tuple __auipc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("AUIPC_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 1); + std::tuple __auipc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("AUIPC_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,1); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = ((bit_sub<12, 20>(instr) << 12)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + (int32_t)imm)), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)(PC+(int32_t)imm)), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 1); + this->gen_sync(POST_SYNC, 1); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 2: JAL */ - std::tuple __jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("JAL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 2); + std::tuple __jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("JAL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,2); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = - ((bit_sub<12, 8>(instr) << 12) | (bit_sub<20, 1>(instr) << 11) | (bit_sub<21, 10>(instr) << 1) | (bit_sub<31, 1>(instr) << 20)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 4)), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)(PC+ 4)), + get_reg_ptr(rd + traits::X0), false); } - auto PC_val_v = (uint32_t)(PC + (int32_t)sext<21>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + auto PC_val_v = (uint32_t)(PC+(int32_t)sext<21>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 2); + this->gen_sync(POST_SYNC, 2); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 3: JALR */ - std::tuple __jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("JALR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 3); + std::tuple __jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("JALR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,3); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto addr_mask = this->gen_const(32, (uint32_t)-2); - auto new_pc = this->gen_ext( - (this->builder.CreateAnd((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - this->gen_ext(addr_mask, 64, false))), + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto addr_mask =this->gen_const(32,(uint32_t)- 2); + auto new_pc =this->gen_ext( + (this->builder.CreateAnd( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + this->gen_ext(addr_mask, 64,false)) + ), 32, true); auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext(this->builder.CreateURem(new_pc, this->gen_const(32, static_cast(traits::INSTR_ALIGNMENT))), 1), - bb_then, bb_else); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateURem( + new_pc, + this->gen_const(32,static_cast(traits::INSTR_ALIGNMENT))) + , 1), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); - { this->gen_raise_trap(0, 0); } + { + this->gen_raise_trap(0, 0); + } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_else); { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 4)), get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)(PC+ 4)), + get_reg_ptr(rd + traits::X0), false); } auto PC_val_v = new_pc; - this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 3); + this->gen_sync(POST_SYNC, 3); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 4: BEQ */ - std::tuple __beq(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BEQ_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 4); + std::tuple __beq(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BEQ_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,4); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 4); + this->gen_sync(POST_SYNC, 4); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 5: BNE */ - std::tuple __bne(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BNE_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 5); + std::tuple __bne(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BNE_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,5); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 5); + this->gen_sync(POST_SYNC, 5); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 6: BLT */ - std::tuple __blt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BLT_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 6); + std::tuple __blt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BLT_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,6); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SLT, - this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), + 32, false), + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 6); + this->gen_sync(POST_SYNC, 6); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 7: BGE */ - std::tuple __bge(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BGE_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 7); + std::tuple __bge(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BGE_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,7); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SGE, - this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SGE, + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), + 32, false), + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 7); + this->gen_sync(POST_SYNC, 7); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 8: BLTU */ - std::tuple __bltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BLTU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 8); + std::tuple __bltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BLTU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,8); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_ULT, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 8); + this->gen_sync(POST_SYNC, 8); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 9: BGEU */ - std::tuple __bgeu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BGEU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 9); + std::tuple __bgeu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BGEU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,9); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_UGE, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_UGE, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 9); + this->gen_sync(POST_SYNC, 9); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 10: LB */ - std::tuple __lb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LB_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 10); + std::tuple __lb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,10); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto load_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - auto res = this->gen_ext(this->gen_read_mem(traits::MEM, load_address, 1), 8, false); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto load_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + auto res =this->gen_ext( + this->gen_read_mem(traits::MEM, load_address, 1), + 8, false); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 10); + this->gen_sync(POST_SYNC, 10); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 11: LH */ - std::tuple __lh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LH_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 11); + std::tuple __lh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LH_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,11); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto load_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - auto res = this->gen_ext(this->gen_read_mem(traits::MEM, load_address, 2), 16, false); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto load_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + auto res =this->gen_ext( + this->gen_read_mem(traits::MEM, load_address, 2), + 16, false); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 11); + this->gen_sync(POST_SYNC, 11); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 12: LW */ - std::tuple __lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LW_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 12); + std::tuple __lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,12); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto load_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - auto res = this->gen_ext(this->gen_read_mem(traits::MEM, load_address, 4), 32, false); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto load_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + auto res =this->gen_ext( + this->gen_read_mem(traits::MEM, load_address, 4), + 32, false); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 12); + this->gen_sync(POST_SYNC, 12); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 13: LBU */ - std::tuple __lbu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LBU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 13); + std::tuple __lbu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LBU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,13); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto load_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - auto res = this->gen_read_mem(traits::MEM, load_address, 1); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, false), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto load_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + auto res =this->gen_read_mem(traits::MEM, load_address, 1); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 13); + this->gen_sync(POST_SYNC, 13); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 14: LHU */ - std::tuple __lhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LHU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 14); + std::tuple __lhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LHU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,14); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto load_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - auto res = this->gen_read_mem(traits::MEM, load_address, 2); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, false), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto load_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + auto res =this->gen_read_mem(traits::MEM, load_address, 2); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 14); + this->gen_sync(POST_SYNC, 14); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 15: SB */ - std::tuple __sb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SB_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 15); + std::tuple __sb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,15); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto store_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - this->gen_write_mem(traits::MEM, store_address, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 8, false)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto store_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + this->gen_write_mem(traits::MEM, + store_address, + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 8, false)); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 15); + this->gen_sync(POST_SYNC, 15); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 16: SH */ - std::tuple __sh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SH_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 16); + std::tuple __sh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SH_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,16); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto store_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - this->gen_write_mem(traits::MEM, store_address, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 16, false)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto store_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + this->gen_write_mem(traits::MEM, + store_address, + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 16, false)); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 16); + this->gen_sync(POST_SYNC, 16); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 17: SW */ - std::tuple __sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SW_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 17); + std::tuple __sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,17); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto store_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - this->gen_write_mem(traits::MEM, store_address, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto store_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + this->gen_write_mem(traits::MEM, + store_address, + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false)); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 17); + this->gen_sync(POST_SYNC, 17); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 18: ADDI */ - std::tuple __addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("ADDI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 18); + std::tuple __addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("ADDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,18); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 18); + this->gen_sync(POST_SYNC, 18); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 19: SLTI */ - std::tuple __slti(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLTI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 19); + std::tuple __slti(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLTI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,19); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext(this->gen_choose((this->builder.CreateICmp( - ICmpInst::ICMP_SLT, this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 32, true))), - this->gen_const(8, 1), this->gen_const(8, 0), 1), - 32), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->gen_choose((this->builder.CreateICmp(ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 32,true)) + ), + this->gen_const(8, 1), + this->gen_const(8, 0), + 1), 32), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 19); + this->gen_sync(POST_SYNC, 19); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 20: SLTIU */ - std::tuple __sltiu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLTIU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 20); + std::tuple __sltiu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLTIU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,20); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext(this->gen_choose((this->builder.CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm))))), - this->gen_const(8, 1), this->gen_const(8, 0), 1), - 32), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->gen_choose((this->builder.CreateICmp(ICmpInst::ICMP_ULT, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm)))) + ), + this->gen_const(8, 1), + this->gen_const(8, 0), + 1), 32), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 20); + this->gen_sync(POST_SYNC, 20); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 21: XORI */ - std::tuple __xori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("XORI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 21); + std::tuple __xori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("XORI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,21); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->builder.CreateXor(this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm)))), - get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->builder.CreateXor( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm)))) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 21); + this->gen_sync(POST_SYNC, 21); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 22: ORI */ - std::tuple __ori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("ORI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 22); + std::tuple __ori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("ORI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,22); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->builder.CreateOr(this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm)))), - get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->builder.CreateOr( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm)))) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 22); + this->gen_sync(POST_SYNC, 22); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 23: ANDI */ - std::tuple __andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("ANDI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 23); + std::tuple __andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("ANDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,23); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->builder.CreateAnd(this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm)))), - get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->builder.CreateAnd( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm)))) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 23); + this->gen_sync(POST_SYNC, 23); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 24: SLLI */ - std::tuple __slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLLI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 24); + std::tuple __slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,24); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->builder.CreateShl(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_ext(this->gen_const(8, shamt), 32, false)), - get_reg_ptr(rd + traits::X0), false); + this->builder.CreateShl( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_ext(this->gen_const(8,shamt), 32,false)) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 24); + this->gen_sync(POST_SYNC, 24); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 25: SRLI */ - std::tuple __srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SRLI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 25); + std::tuple __srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SRLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,25); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->builder.CreateLShr(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_ext(this->gen_const(8, shamt), 32, false)), - get_reg_ptr(rd + traits::X0), false); + this->builder.CreateLShr( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_ext(this->gen_const(8,shamt), 32,false)) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 25); + this->gen_sync(POST_SYNC, 25); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 26: SRAI */ - std::tuple __srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SRAI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 26); + std::tuple __srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SRAI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,26); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAShr(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_ext(this->gen_const(8, shamt), 32, false))), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateAShr( + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + this->gen_ext(this->gen_const(8,shamt), 32,false)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 26); + this->gen_sync(POST_SYNC, 26); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 27: ADD */ - std::tuple __add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("ADD_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 27); + std::tuple __add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("ADD_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,27); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false))), - 32, false), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false)) + ), + 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 27); + this->gen_sync(POST_SYNC, 27); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 28: SUB */ - std::tuple __sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SUB_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 28); + std::tuple __sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SUB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,28); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateSub(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false))), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateSub( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 28); + this->gen_sync(POST_SYNC, 28); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 29: SLL */ - std::tuple __sll(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 29); + std::tuple __sll(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,29); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext( - this->builder.CreateShl(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - (this->builder.CreateAnd(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), - this->gen_const(64, (static_cast(traits::XLEN) - 1))))), - 32, false), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->builder.CreateShl( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + (this->builder.CreateAnd( + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false), + this->gen_const(64,(static_cast(traits::XLEN)- 1))) + )) + , 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 29); + this->gen_sync(POST_SYNC, 29); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 30: SLT */ - std::tuple __slt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLT_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 30); + std::tuple __slt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLT_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,30); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext(this->gen_choose(this->builder.CreateICmp( - ICmpInst::ICMP_SLT, this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), - this->gen_const(8, 1), this->gen_const(8, 0), 1), - 32), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->gen_choose(this->builder.CreateICmp(ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), 32,true)) + , + this->gen_const(8, 1), + this->gen_const(8, 0), + 1), 32), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 30); + this->gen_sync(POST_SYNC, 30); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 31: SLTU */ - std::tuple __sltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLTU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 31); + std::tuple __sltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLTU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,31); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext(this->gen_choose(this->builder.CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0)), - this->gen_const(8, 1), this->gen_const(8, 0), 1), - 32), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->gen_choose(this->builder.CreateICmp(ICmpInst::ICMP_ULT, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , + this->gen_const(8, 1), + this->gen_const(8, 0), + 1), 32), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 31); + this->gen_sync(POST_SYNC, 31); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 32: XOR */ - std::tuple __xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("XOR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 32); + std::tuple __xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("XOR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,32); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->builder.CreateXor(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)), - get_reg_ptr(rd + traits::X0), false); + this->builder.CreateXor( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 32); + this->gen_sync(POST_SYNC, 32); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 33: SRL */ - std::tuple __srl(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SRL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 33); + std::tuple __srl(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SRL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,33); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext( - this->builder.CreateLShr(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - (this->builder.CreateAnd(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), - this->gen_const(64, (static_cast(traits::XLEN) - 1))))), - 32, false), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->builder.CreateLShr( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + (this->builder.CreateAnd( + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false), + this->gen_const(64,(static_cast(traits::XLEN)- 1))) + )) + , 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 33); + this->gen_sync(POST_SYNC, 33); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 34: SRA */ - std::tuple __sra(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SRA_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 34); + std::tuple __sra(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SRA_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,34); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext( - (this->gen_ext(this->builder.CreateAShr( - this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true), - (this->builder.CreateAnd(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), - this->gen_const(64, (static_cast(traits::XLEN) - 1))))), - 32, true)), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->gen_ext(this->builder.CreateAShr( + this->gen_ext(this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), 64,true), + (this->builder.CreateAnd( + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false), + this->gen_const(64,(static_cast(traits::XLEN)- 1))) + )) + , 32, true)), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 34); + this->gen_sync(POST_SYNC, 34); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 35: OR */ - std::tuple __or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("OR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 35); + std::tuple __or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("OR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,35); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->builder.CreateOr(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)), - get_reg_ptr(rd + traits::X0), false); + this->builder.CreateOr( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 35); + this->gen_sync(POST_SYNC, 35); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 36: AND */ - std::tuple __and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("AND_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 36); + std::tuple __and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("AND_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,36); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->builder.CreateAnd(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)), - get_reg_ptr(rd + traits::X0), false); + this->builder.CreateAnd( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 36); + this->gen_sync(POST_SYNC, 36); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 37: FENCE */ - std::tuple __fence(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("FENCE_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 37); + std::tuple __fence(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("FENCE_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,37); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t succ = ((bit_sub<20, 4>(instr))); - uint8_t pred = ((bit_sub<24, 4>(instr))); - uint8_t fm = ((bit_sub<28, 4>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); + uint8_t fm = ((bit_sub<28,4>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), fmt::arg("pred", pred), - fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), + fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_write_mem(traits::FENCE, static_cast(traits::fence), this->gen_const(8, (uint8_t)pred << 4 | succ)); + this->gen_write_mem(traits::FENCE, + static_cast(traits::fence), + this->gen_const(8,(uint8_t)pred<< 4|succ)); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 37); + this->gen_sync(POST_SYNC, 37); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 38: ECALL */ - std::tuple __ecall(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("ECALL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 38); + std::tuple __ecall(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("ECALL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,38); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_raise_trap(0, 11); + this->gen_raise_trap(0, 11); bb = this->leave_blk; - auto returnValue = std::make_tuple(TRAP, nullptr); - + auto returnValue = std::make_tuple(TRAP,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 38); + this->gen_sync(POST_SYNC, 38); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 39: EBREAK */ - std::tuple __ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("EBREAK_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 39); + std::tuple __ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("EBREAK_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,39); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_raise_trap(0, 3); + this->gen_raise_trap(0, 3); bb = this->leave_blk; - auto returnValue = std::make_tuple(TRAP, nullptr); - + auto returnValue = std::make_tuple(TRAP,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 39); + this->gen_sync(POST_SYNC, 39); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 40: MRET */ - std::tuple __mret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("MRET_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 40); + std::tuple __mret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("MRET_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,40); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); this->gen_leave_trap(3); bb = this->leave_blk; - auto returnValue = std::make_tuple(TRAP, nullptr); - + auto returnValue = std::make_tuple(TRAP,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 40); + this->gen_sync(POST_SYNC, 40); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 41: WFI */ - std::tuple __wfi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("WFI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 41); + std::tuple __wfi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("WFI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,41); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); this->gen_wait(1); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 41); + this->gen_sync(POST_SYNC, 41); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 42: CSRRW */ - std::tuple __csrrw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRW_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 42); + std::tuple __csrrw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,42); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrs1 = this->gen_reg_load(rs1 + traits::X0, 0); - if(rd != 0) { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - this->gen_write_mem(traits::CSR, csr, xrs1); - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); - } else { - this->gen_write_mem(traits::CSR, csr, xrs1); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0); + if(rd!= 0){ auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + this->gen_write_mem(traits::CSR, + csr, + xrs1); + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); + } + else{ + this->gen_write_mem(traits::CSR, + csr, + xrs1); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 42); + this->gen_sync(POST_SYNC, 42); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 43: CSRRS */ - std::tuple __csrrs(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRS_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 43); + std::tuple __csrrs(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRS_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,43); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - auto xrs1 = this->gen_reg_load(rs1 + traits::X0, 0); - if(rs1 != 0) { - this->gen_write_mem(traits::CSR, csr, this->builder.CreateOr(xrd, xrs1)); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0); + if(rs1!= 0) { + this->gen_write_mem(traits::CSR, + csr, + this->builder.CreateOr( + xrd, + xrs1) + ); } - if(rd != 0) { - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 43); + this->gen_sync(POST_SYNC, 43); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 44: CSRRC */ - std::tuple __csrrc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRC_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 44); + std::tuple __csrrc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRC_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,44); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - auto xrs1 = this->gen_reg_load(rs1 + traits::X0, 0); - if(rs1 != 0) { - this->gen_write_mem(traits::CSR, csr, this->builder.CreateAnd(xrd, this->builder.CreateNeg(xrs1))); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0); + if(rs1!= 0) { + this->gen_write_mem(traits::CSR, + csr, + this->builder.CreateAnd( + xrd, + this->builder.CreateNeg(xrs1)) + ); } - if(rd != 0) { - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 44); + this->gen_sync(POST_SYNC, 44); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 45: CSRRWI */ - std::tuple __csrrwi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRWI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 45); + std::tuple __csrrwi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRWI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,45); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - this->gen_write_mem(traits::CSR, csr, this->gen_const(32, (uint32_t)zimm)); - if(rd != 0) { - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + this->gen_write_mem(traits::CSR, + csr, + this->gen_const(32,(uint32_t)zimm)); + if(rd!= 0) { + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 45); + this->gen_sync(POST_SYNC, 45); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 46: CSRRSI */ - std::tuple __csrrsi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRSI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 46); + std::tuple __csrrsi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRSI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,46); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - if(zimm != 0) { - this->gen_write_mem(traits::CSR, csr, this->builder.CreateOr(xrd, this->gen_const(32, (uint32_t)zimm))); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + if(zimm!= 0) { + this->gen_write_mem(traits::CSR, + csr, + this->builder.CreateOr( + xrd, + this->gen_const(32,(uint32_t)zimm)) + ); } - if(rd != 0) { - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 46); + this->gen_sync(POST_SYNC, 46); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 47: CSRRCI */ - std::tuple __csrrci(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRCI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 47); + std::tuple __csrrci(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRCI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,47); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - if(zimm != 0) { - this->gen_write_mem(traits::CSR, csr, this->builder.CreateAnd(xrd, this->gen_const(32, ~((uint32_t)zimm)))); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + if(zimm!= 0) { + this->gen_write_mem(traits::CSR, + csr, + this->builder.CreateAnd( + xrd, + this->gen_const(32,~ ((uint32_t)zimm))) + ); } - if(rd != 0) { - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 47); + this->gen_sync(POST_SYNC, 47); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 48: FENCE_I */ - std::tuple __fence_i(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("FENCE_I_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 48); + std::tuple __fence_i(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("FENCE_I_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,48); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), fmt::arg("rs1", name(rs1)), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), + fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_write_mem(traits::FENCE, static_cast(traits::fencei), this->gen_const(16, imm)); + this->gen_write_mem(traits::FENCE, + static_cast(traits::fencei), + this->gen_const(16,imm)); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 48); + this->gen_sync(POST_SYNC, 48); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 49: MUL */ - std::tuple __mul(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("MUL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 49); + std::tuple __mul(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("MUL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,49); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto res = this->gen_ext( + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto res =this->gen_ext( (this->builder.CreateMul( - this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true), 128, true), - this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, true), 64, true), 128, true))), + this->gen_ext(this->gen_ext( + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + 64, true), 128,true), + this->gen_ext(this->gen_ext( + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), 32,true), + 64, true), 128,true)) + ), 64, true); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false); + if(rd!=0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 49); + this->gen_sync(POST_SYNC, 49); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 50: MULH */ - std::tuple __mulh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("MULH_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 50); + std::tuple __mulh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("MULH_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,50); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto res = this->gen_ext( + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto res =this->gen_ext( (this->builder.CreateMul( - this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true), 128, true), - this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, true), 64, true), 128, true))), + this->gen_ext(this->gen_ext( + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + 64, true), 128,true), + this->gen_ext(this->gen_ext( + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), 32,true), + 64, true), 128,true)) + ), 64, true); - if(rd != 0) { + if(rd!=0) { this->builder.CreateStore( - this->gen_ext( - (this->builder.CreateAShr(res, this->gen_ext(this->gen_const(32, static_cast(traits::XLEN)), 64, false))), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateAShr( + res, + this->gen_ext(this->gen_const(32,static_cast(traits::XLEN)), 64,false)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 50); + this->gen_sync(POST_SYNC, 50); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 51: MULHSU */ - std::tuple __mulhsu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("MULHSU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 51); + std::tuple __mulhsu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("MULHSU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,51); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto res = this->gen_ext( + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto res =this->gen_ext( (this->builder.CreateMul( - this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true), 128, true), - this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), 128, false))), + this->gen_ext(this->gen_ext( + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + 64, true), 128,true), + this->gen_ext(this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 64, false), 128,false)) + ), 64, true); - if(rd != 0) { + if(rd!=0) { this->builder.CreateStore( - this->gen_ext( - (this->builder.CreateAShr(res, this->gen_ext(this->gen_const(32, static_cast(traits::XLEN)), 64, false))), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateAShr( + res, + this->gen_ext(this->gen_const(32,static_cast(traits::XLEN)), 64,false)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 51); + this->gen_sync(POST_SYNC, 51); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 52: MULHU */ - std::tuple __mulhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("MULHU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 52); + std::tuple __mulhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("MULHU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,52); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto res = this->gen_ext( - (this->builder.CreateMul(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), 128, false), - this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), 128, false))), + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto res =this->gen_ext( + (this->builder.CreateMul( + this->gen_ext(this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), + 64, false), 128,false), + this->gen_ext(this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 64, false), 128,false)) + ), 64, false); - if(rd != 0) { + if(rd!=0) { this->builder.CreateStore( - this->gen_ext( - (this->builder.CreateLShr(res, this->gen_ext(this->gen_const(32, static_cast(traits::XLEN)), 64, false))), - 32, false), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateLShr( + res, + this->gen_ext(this->gen_const(32,static_cast(traits::XLEN)), 64,false)) + ), + 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 52); + this->gen_sync(POST_SYNC, 52); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 53: DIV */ - std::tuple __div(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("DIV_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 53); + std::tuple __div(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("DIV_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,53); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto dividend = this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false); - auto divisor = this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false); - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto dividend =this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), + 32, false); + auto divisor =this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false); + if(rd!= 0){ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); + auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); + auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + divisor, + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_else); + this->builder.SetInsertPoint(bb_then); + { + auto MMIN =this->gen_const(32,((uint32_t)1)<<(static_cast(traits::XLEN)-1)); auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, divisor, this->gen_ext(this->gen_const(8, 0), 32, false)), 1), - bb_then, bb_else); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateAnd( + this->builder.CreateICmp(ICmpInst::ICMP_EQ, + this->gen_reg_load(rs1+ traits::X0, 0), + MMIN) + , + this->builder.CreateICmp(ICmpInst::ICMP_EQ, + divisor, + this->gen_ext(this->gen_const(8,- 1), 32,true)) + ) + , 1), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); { - auto MMIN = this->gen_const(32, ((uint32_t)1) << (static_cast(traits::XLEN) - 1)); - auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); - auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext( - this->builder.CreateAnd( - this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + traits::X0, 0), MMIN), - this->builder.CreateICmp(ICmpInst::ICMP_EQ, divisor, this->gen_ext(this->gen_const(8, -1), 32, true))), - 1), - bb_then, bb_else); - this->builder.SetInsertPoint(bb_then); - { this->builder.CreateStore(MMIN, get_reg_ptr(rd + traits::X0), false); } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_else); - { - this->builder.CreateStore( - this->gen_ext((this->builder.CreateSDiv(this->gen_ext(dividend, 64, true), this->gen_ext(divisor, 64, true))), - 32, true), - get_reg_ptr(rd + traits::X0), false); - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_merge); - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_else); - { this->builder.CreateStore(this->gen_const(32, (uint32_t)-1), get_reg_ptr(rd + traits::X0), false); } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_merge); - } - } - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 53); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 54: DIVU */ - std::tuple __divu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("DIVU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 54); - uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); - auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2 + traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32, false)), - 1), - bb_then, bb_else); - this->builder.SetInsertPoint(bb_then); - { - if(rd != 0) { - this->builder.CreateStore(this->gen_ext((this->builder.CreateUDiv(this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0))), - 32, false), - get_reg_ptr(rd + traits::X0), false); - } - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_else); - { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)-1), get_reg_ptr(rd + traits::X0), false); - } - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_merge); - } - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 54); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 55: REM */ - std::tuple __rem(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("REM_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 55); - uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); - auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2 + traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32, false)), - 1), - bb_then, bb_else); - this->builder.SetInsertPoint(bb_then); - { - auto MMIN = this->gen_const(32, (uint32_t)1 << (static_cast(traits::XLEN) - 1)); - auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); - auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext( - this->builder.CreateAnd(this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + traits::X0, 0), MMIN), - this->builder.CreateICmp(ICmpInst::ICMP_EQ, - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false), - this->gen_ext(this->gen_const(8, -1), 32, true))), - 1), - bb_then, bb_else); - this->builder.SetInsertPoint(bb_then); - { - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(this->gen_const(8, 0), 32), get_reg_ptr(rd + traits::X0), false); - } - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_else); - { - if(rd != 0) { - this->builder.CreateStore( - this->gen_ext((this->builder.CreateSRem(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false))), - 32, true), - get_reg_ptr(rd + traits::X0), false); - } - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_merge); - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_else); - { - if(rd != 0) { - this->builder.CreateStore(this->gen_reg_load(rs1 + traits::X0, 0), get_reg_ptr(rd + traits::X0), false); - } - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_merge); - } - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 55); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 56: REMU */ - std::tuple __remu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("REMU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 56); - uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); - auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2 + traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32, false)), - 1), - bb_then, bb_else); - this->builder.SetInsertPoint(bb_then); - { - if(rd != 0) { this->builder.CreateStore( - this->builder.CreateURem(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)), - get_reg_ptr(rd + traits::X0), false); + MMIN, + get_reg_ptr(rd + traits::X0), false); } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_else); + { + this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateSDiv( + this->gen_ext(dividend, 64,true), + this->gen_ext(divisor, 64,true)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_merge); } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_else); { - if(rd != 0) { - this->builder.CreateStore(this->gen_reg_load(rs1 + traits::X0, 0), get_reg_ptr(rd + traits::X0), false); - } + this->builder.CreateStore( + this->gen_const(32,(uint32_t)- 1), + get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); + } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 56); + this->gen_sync(POST_SYNC, 53); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - - /* instruction 57: C__ADDI4SPN */ - std::tuple __c__addi4spn(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__ADDI4SPN_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 57); + + /* instruction 54: DIVU */ + std::tuple __divu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("DIVU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,54); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<2, 3>(instr))); - uint16_t imm = - ((bit_sub<5, 1>(instr) << 3) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<7, 4>(instr) << 6) | (bit_sub<11, 2>(instr) << 4)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"), fmt::arg("rd", name(8 + rd)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); + auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); + auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + this->gen_reg_load(rs2+ traits::X0, 0), + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_else); + this->builder.SetInsertPoint(bb_then); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateUDiv( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + ), + 32, false), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_else); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)- 1), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_merge); + } + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 54); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 55: REM */ + std::tuple __rem(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("REM_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,55); + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); + auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); + auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + this->gen_reg_load(rs2+ traits::X0, 0), + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_else); + this->builder.SetInsertPoint(bb_then); + { + auto MMIN =this->gen_const(32,(uint32_t)1<<(static_cast(traits::XLEN)-1)); + auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); + auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); + auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateAnd( + this->builder.CreateICmp(ICmpInst::ICMP_EQ, + this->gen_reg_load(rs1+ traits::X0, 0), + MMIN) + , + this->builder.CreateICmp(ICmpInst::ICMP_EQ, + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false), + this->gen_ext(this->gen_const(8,- 1), 32,true)) + ) + , 1), bb_then, bb_else); + this->builder.SetInsertPoint(bb_then); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_ext(this->gen_const(8, 0), 32), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_else); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateSRem( + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), + 32, false), + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_merge); + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_else); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_reg_load(rs1+ traits::X0, 0), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_merge); + } + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 55); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 56: REMU */ + std::tuple __remu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("REMU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,56); + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); + auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); + auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + this->gen_reg_load(rs2+ traits::X0, 0), + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_else); + this->builder.SetInsertPoint(bb_then); + { + if(rd!=0) { + this->builder.CreateStore( + this->builder.CreateURem( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_else); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_reg_load(rs1+ traits::X0, 0), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_merge); + } + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 56); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 57: C__ADDI4SPN */ + std::tuple __c__addi4spn(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__ADDI4SPN_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,57); + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<2,3>(instr))); + uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"), + fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm)); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); if(imm) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, imm), 64, false))), - 32, false), - get_reg_ptr(rd + 8 + traits::X0), false); - } else { - this->gen_raise_trap(0, 2); + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,imm), 64,false)) + ), + 32, false), + get_reg_ptr(rd+ 8 + traits::X0), false); + } + else{ + this->gen_raise_trap(0, 2); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 57); + this->gen_sync(POST_SYNC, 57); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 58: C__LW */ - std::tuple __c__lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__LW_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 58); + std::tuple __c__lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__LW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,58); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<2, 3>(instr))); - uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"), - fmt::arg("rd", name(8 + rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(8, uimm), 64, false))), - 32, false); - this->builder.CreateStore(this->gen_ext(this->gen_ext(this->gen_read_mem(traits::MEM, offs, 4), 32, false), 32, true), - get_reg_ptr(rd + 8 + traits::X0), false); + auto offs =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ 8+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(8,uimm), 64,false)) + ), + 32, false); + this->builder.CreateStore( + this->gen_ext( + this->gen_ext( + this->gen_read_mem(traits::MEM, offs, 4), + 32, false), + 32, true), + get_reg_ptr(rd+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 58); + this->gen_sync(POST_SYNC, 58); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 59: C__SW */ - std::tuple __c__sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SW_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 59); + std::tuple __c__sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,59); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"), - fmt::arg("rs2", name(8 + rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(8, uimm), 64, false))), - 32, false); - this->gen_write_mem(traits::MEM, offs, this->gen_ext(this->gen_reg_load(rs2 + 8 + traits::X0, 0), 32, false)); + auto offs =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ 8+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(8,uimm), 64,false)) + ), + 32, false); + this->gen_write_mem(traits::MEM, + offs, + this->gen_ext( + this->gen_reg_load(rs2+ 8+ traits::X0, 0), + 32, false)); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 59); + this->gen_sync(POST_SYNC, 59); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 60: C__ADDI */ - std::tuple __c__addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__ADDI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 60); + std::tuple __c__addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__ADDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,60); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"), fmt::arg("rs1", name(rs1)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rs1 != 0) { + if(rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rs1!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(8, (int8_t)sext<6>(imm)), 64, true))), - 32, true), - get_reg_ptr(rs1 + traits::X0), false); + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(8,(int8_t)sext<6>(imm)), 64,true)) + ), + 32, true), + get_reg_ptr(rs1 + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 60); + this->gen_sync(POST_SYNC, 60); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 61: C__NOP */ - std::tuple __c__nop(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__NOP_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 61); + std::tuple __c__nop(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__NOP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,61); uint64_t PC = pc.val; - uint8_t nzimm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - if(this->disass_enabled) { + uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 61); + this->gen_sync(POST_SYNC, 61); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 62: C__JAL */ - std::tuple __c__jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__JAL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 62); + std::tuple __c__jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__JAL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,62); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) | - (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11)); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"), + fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 2)), get_reg_ptr(1 + traits::X0), false); - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<12>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + this->builder.CreateStore( + this->gen_const(32,(uint32_t)(PC+ 2)), + get_reg_ptr(1 + traits::X0), false); + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 62); + this->gen_sync(POST_SYNC, 62); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 63: C__LI */ - std::tuple __c__li(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__LI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 63); + std::tuple __c__li(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__LI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,63); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)((int8_t)sext<6>(imm))), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)((int8_t)sext<6>(imm))), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 63); + this->gen_sync(POST_SYNC, 63); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 64: C__LUI */ - std::tuple __c__lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__LUI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 64); + std::tuple __c__lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__LUI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,64); uint64_t PC = pc.val; - uint32_t imm = ((bit_sub<2, 5>(instr) << 12) | (bit_sub<12, 1>(instr) << 17)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(imm == 0 || rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + if(imm== 0||rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); } - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)((int32_t)sext<18>(imm))), get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)((int32_t)sext<18>(imm))), + get_reg_ptr(rd + traits::X0), false); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 64); + this->gen_sync(POST_SYNC, 64); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 65: C__ADDI16SP */ - std::tuple __c__addi16sp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__ADDI16SP_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 65); + std::tuple __c__addi16sp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__ADDI16SP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,65); uint64_t PC = pc.val; - uint16_t nzimm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 7) | (bit_sub<5, 1>(instr) << 6) | - (bit_sub<6, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 9)); - if(this->disass_enabled) { + uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"), fmt::arg("nzimm", nzimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"), + fmt::arg("nzimm", nzimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); if(nzimm) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<10>(nzimm)), 64, true))), - 32, true), - get_reg_ptr(2 + traits::X0), false); - } else { - this->gen_raise_trap(0, 2); + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<10>(nzimm)), 64,true)) + ), + 32, true), + get_reg_ptr(2 + traits::X0), false); + } + else{ + this->gen_raise_trap(0, 2); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 65); + this->gen_sync(POST_SYNC, 65); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 66: __reserved_clui */ - std::tuple ____reserved_clui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("__reserved_clui_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 66); + std::tuple ____reserved_clui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("__reserved_clui_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,66); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 66); + this->gen_sync(POST_SYNC, 66); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 67: C__SRLI */ - std::tuple __c__srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SRLI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 67); + std::tuple __c__srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SRLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,67); uint64_t PC = pc.val; - uint8_t shamt = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("shamt", shamt)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->builder.CreateLShr(this->gen_reg_load(rs1 + 8 + traits::X0, 0), this->gen_ext(this->gen_const(8, shamt), 32, false)), - get_reg_ptr(rs1 + 8 + traits::X0), false); + this->builder.CreateLShr( + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_ext(this->gen_const(8,shamt), 32,false)) + , + get_reg_ptr(rs1+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 67); + this->gen_sync(POST_SYNC, 67); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 68: C__SRAI */ - std::tuple __c__srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SRAI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 68); + std::tuple __c__srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SRAI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,68); uint64_t PC = pc.val; - uint8_t shamt = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("shamt", shamt)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(shamt) { - this->builder.CreateStore( - this->gen_ext((this->builder.CreateAShr((this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 32, false)), - this->gen_ext(this->gen_const(8, shamt), 32, false))), - 32, true), - get_reg_ptr(rs1 + 8 + traits::X0), false); - } else { - if(static_cast(traits::XLEN) == 128) { - this->builder.CreateStore( - this->gen_ext((this->builder.CreateAShr((this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 32, false)), - this->gen_ext(this->gen_const(8, 64), 32, false))), - 32, true), - get_reg_ptr(rs1 + 8 + traits::X0), false); + if(shamt){ this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateAShr( + (this->gen_ext( + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + 32, false)), + this->gen_ext(this->gen_const(8,shamt), 32,false)) + ), + 32, true), + get_reg_ptr(rs1+ 8 + traits::X0), false); + } + else{ + if(static_cast(traits::XLEN)== 128){ this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateAShr( + (this->gen_ext( + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + 32, false)), + this->gen_ext(this->gen_const(8, 64), 32,false)) + ), + 32, true), + get_reg_ptr(rs1+ 8 + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 68); + this->gen_sync(POST_SYNC, 68); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 69: C__ANDI */ - std::tuple __c__andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__ANDI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 69); + std::tuple __c__andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__ANDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,69); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->gen_ext((this->builder.CreateAnd(this->gen_reg_load(rs1 + 8 + traits::X0, 0), - this->gen_ext(this->gen_const(8, (int8_t)sext<6>(imm)), 32, true))), - 32, true), - get_reg_ptr(rs1 + 8 + traits::X0), false); + this->gen_ext( + (this->builder.CreateAnd( + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_ext(this->gen_const(8,(int8_t)sext<6>(imm)), 32,true)) + ), + 32, true), + get_reg_ptr(rs1+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 69); + this->gen_sync(POST_SYNC, 69); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 70: C__SUB */ - std::tuple __c__sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SUB_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 70); + std::tuple __c__sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SUB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,70); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->gen_ext((this->builder.CreateSub(this->gen_ext(this->gen_reg_load(rd + 8 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_reg_load(rs2 + 8 + traits::X0, 0), 64, false))), - 32, true), - get_reg_ptr(rd + 8 + traits::X0), false); + this->gen_ext( + (this->builder.CreateSub( + this->gen_ext(this->gen_reg_load(rd+ 8+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_reg_load(rs2+ 8+ traits::X0, 0), 64,false)) + ), + 32, true), + get_reg_ptr(rd+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 70); + this->gen_sync(POST_SYNC, 70); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 71: C__XOR */ - std::tuple __c__xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__XOR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 71); + std::tuple __c__xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__XOR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,71); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->builder.CreateXor(this->gen_reg_load(rd + 8 + traits::X0, 0), this->gen_reg_load(rs2 + 8 + traits::X0, 0)), - get_reg_ptr(rd + 8 + traits::X0), false); + this->builder.CreateXor( + this->gen_reg_load(rd+ 8+ traits::X0, 0), + this->gen_reg_load(rs2+ 8+ traits::X0, 0)) + , + get_reg_ptr(rd+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 71); + this->gen_sync(POST_SYNC, 71); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 72: C__OR */ - std::tuple __c__or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__OR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 72); + std::tuple __c__or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__OR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,72); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->builder.CreateOr(this->gen_reg_load(rd + 8 + traits::X0, 0), this->gen_reg_load(rs2 + 8 + traits::X0, 0)), - get_reg_ptr(rd + 8 + traits::X0), false); + this->builder.CreateOr( + this->gen_reg_load(rd+ 8+ traits::X0, 0), + this->gen_reg_load(rs2+ 8+ traits::X0, 0)) + , + get_reg_ptr(rd+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 72); + this->gen_sync(POST_SYNC, 72); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 73: C__AND */ - std::tuple __c__and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__AND_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 73); + std::tuple __c__and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__AND_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,73); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->builder.CreateAnd(this->gen_reg_load(rd + 8 + traits::X0, 0), this->gen_reg_load(rs2 + 8 + traits::X0, 0)), - get_reg_ptr(rd + 8 + traits::X0), false); + this->builder.CreateAnd( + this->gen_reg_load(rd+ 8+ traits::X0, 0), + this->gen_reg_load(rs2+ 8+ traits::X0, 0)) + , + get_reg_ptr(rd+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 73); + this->gen_sync(POST_SYNC, 73); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 74: C__J */ - std::tuple __c__j(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__J_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 74); + std::tuple __c__j(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__J_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,74); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) | - (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11)); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"), + fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<12>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 74); + this->gen_sync(POST_SYNC, 74); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 75: C__BEQZ */ - std::tuple __c__beqz(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__BEQZ_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 75); + std::tuple __c__beqz(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__BEQZ_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,75); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) | - (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + 8 + traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32, false)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<9>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 75); + this->gen_sync(POST_SYNC, 75); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 76: C__BNEZ */ - std::tuple __c__bnez(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__BNEZ_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 76); + std::tuple __c__bnez(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__BNEZ_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,76); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) | - (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs1 + 8 + traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32, false)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<9>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 76); + this->gen_sync(POST_SYNC, 76); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 77: C__SLLI */ - std::tuple __c__slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SLLI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 77); + std::tuple __c__slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SLLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,77); uint64_t PC = pc.val; - uint8_t nzuimm = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t nzuimm = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"), fmt::arg("rs1", name(rs1)), - fmt::arg("nzuimm", nzuimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rs1 != 0) { + if(rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rs1!= 0) { this->builder.CreateStore( - this->builder.CreateShl(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_ext(this->gen_const(8, nzuimm), 32, false)), - get_reg_ptr(rs1 + traits::X0), false); + this->builder.CreateShl( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_ext(this->gen_const(8,nzuimm), 32,false)) + , + get_reg_ptr(rs1 + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 77); + this->gen_sync(POST_SYNC, 77); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 78: C__LWSP */ - std::tuple __c__lwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__LWSP_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 78); + std::tuple __c__lwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__LWSP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,78); uint64_t PC = pc.val; - uint8_t uimm = ((bit_sub<2, 2>(instr) << 6) | (bit_sub<4, 3>(instr) << 2) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"), fmt::arg("rd", name(rd)), - fmt::arg("uimm", uimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rd == 0) { - this->gen_raise_trap(0, 2); - } else { - auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(8, uimm), 64, false))), - 32, false); - this->builder.CreateStore(this->gen_ext(this->gen_ext(this->gen_read_mem(traits::MEM, offs, 4), 32, false), 32, true), - get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rd== 0) { + this->gen_raise_trap(0, 2); + } + else{ + auto offs =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(8,uimm), 64,false)) + ), + 32, false); + this->builder.CreateStore( + this->gen_ext( + this->gen_ext( + this->gen_read_mem(traits::MEM, offs, 4), + 32, false), + 32, true), + get_reg_ptr(rd + traits::X0), false); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 78); + this->gen_sync(POST_SYNC, 78); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 79: C__MV */ - std::tuple __c__mv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__MV_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 79); + std::tuple __c__mv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__MV_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,79); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"), fmt::arg("rd", name(rd)), - fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->gen_reg_load(rs2 + traits::X0, 0), get_reg_ptr(rd + traits::X0), false); - } + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); } - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 79); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 80: C__JR */ - std::tuple __c__jr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__JR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 80); - uint64_t PC = pc.val; - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"), fmt::arg("rs1", name(rs1))); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rs1 && rs1 < static_cast(traits::RFS)) { - auto addr_mask = this->gen_const(32, (uint32_t)-2); - auto PC_val_v = - this->builder.CreateAnd(this->gen_reg_load(rs1 % static_cast(traits::RFS) + traits::X0, 0), addr_mask); - this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); - } else { - this->gen_raise_trap(0, 2); - } - bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 80); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 81: __reserved_cmv */ - std::tuple ____reserved_cmv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("__reserved_cmv_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 81); - uint64_t PC = pc.val; - if(this->disass_enabled) { - /* generate console output when executing the command */ - // This disass is not yet implemented - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; - this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_raise_trap(0, 2); - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 81); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 82: C__ADD */ - std::tuple __c__add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__ADD_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 82); - uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"), fmt::arg("rd", name(rd)), - fmt::arg("rs2", name(rs2))); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rd + traits::X0, 0), 64, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false))), - 32, false), - get_reg_ptr(rd + traits::X0), false); + this->gen_reg_load(rs2+ traits::X0, 0), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 82); + this->gen_sync(POST_SYNC, 79); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - - /* instruction 83: C__JALR */ - std::tuple __c__jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__JALR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 83); + + /* instruction 80: C__JR */ + std::tuple __c__jr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__JR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,80); uint64_t PC = pc.val; - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"), + fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs1 >= static_cast(traits::RFS)) { + if(rs1&&rs1(traits::RFS)) { + auto PC_val_v = this->builder.CreateAnd( + this->gen_reg_load(rs1%static_cast(traits::RFS)+ traits::X0, 0), + this->gen_ext(this->gen_const(8,~ 0x1), 32,false)) + ; + this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); + } + else{ this->gen_raise_trap(0, 2); - } else { - auto addr_mask = this->gen_const(32, (uint32_t)-2); - auto new_pc = this->gen_reg_load(rs1 + traits::X0, 0); - this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 2)), get_reg_ptr(1 + traits::X0), false); - auto PC_val_v = this->builder.CreateAnd(new_pc, addr_mask); - this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 83); + this->gen_sync(POST_SYNC, 80); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - - /* instruction 84: C__EBREAK */ - std::tuple __c__ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__EBREAK_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 84); + + /* instruction 81: __reserved_cmv */ + std::tuple ____reserved_cmv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("__reserved_cmv_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,81); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; - this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_raise_trap(0, 3); - bb = this->leave_blk; - auto returnValue = std::make_tuple(TRAP, nullptr); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 84); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 85: C__SWSP */ - std::tuple __c__swsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SWSP_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 85); - uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t uimm = ((bit_sub<7, 2>(instr) << 6) | (bit_sub<9, 4>(instr) << 2)); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"), fmt::arg("rs2", name(rs2)), - fmt::arg("uimm", uimm)); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(8, uimm), 64, false))), - 32, false); - this->gen_write_mem(traits::MEM, offs, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false)); - } - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 85); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 86: DII */ - std::tuple __dii(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("DII_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 86); - uint64_t PC = pc.val; - if(this->disass_enabled) { - /* generate console output when executing the command */ - // This disass is not yet implemented - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->gen_raise_trap(0, 2); - bb = this->leave_blk; - auto returnValue = std::make_tuple(TRAP, nullptr); - + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 86); + this->gen_sync(POST_SYNC, 81); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + + /* instruction 82: C__ADD */ + std::tuple __c__add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__ADD_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,82); + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rd+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false)) + ), + 32, false), + get_reg_ptr(rd + traits::X0), false); + } + } + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 82); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 83: C__JALR */ + std::tuple __c__jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__JALR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,83); + uint64_t PC = pc.val; + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"), + fmt::arg("rs1", name(rs1))); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto new_pc =this->gen_reg_load(rs1+ traits::X0, 0); + this->builder.CreateStore( + this->gen_const(32,(uint32_t)(PC+ 2)), + get_reg_ptr(1 + traits::X0), false); + auto PC_val_v = this->builder.CreateAnd( + new_pc, + this->gen_ext(this->gen_const(8,~ 0x1), 32,false)) + ; + this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); + } + bb = this->leave_blk; + auto returnValue = std::make_tuple(BRANCH,nullptr); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 83); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 84: C__EBREAK */ + std::tuple __c__ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__EBREAK_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,84); + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate console output when executing the command */ + //This disass is not yet implemented + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; + this->gen_set_pc(pc, traits::NEXT_PC); + this->gen_raise_trap(0, 3); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 84); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 85: C__SWSP */ + std::tuple __c__swsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SWSP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,85); + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto offs =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(8,uimm), 64,false)) + ), + 32, false); + this->gen_write_mem(traits::MEM, + offs, + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false)); + } + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 85); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 86: DII */ + std::tuple __dii(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("DII_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,86); + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate console output when executing the command */ + //This disass is not yet implemented + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; + this->gen_set_pc(pc, traits::NEXT_PC); + this->gen_raise_trap(0, 2); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 86); + this->builder.CreateBr(bb); + return returnValue; + } + /**************************************************************************** * end opcode definitions ****************************************************************************/ - std::tuple illegal_intruction(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - this->gen_sync(iss::PRE_SYNC, instr_descr.size()); + std::tuple illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) { + this->gen_sync(iss::PRE_SYNC, instr_descr.size()); this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true), - get_reg_ptr(traits::PC), true); + get_reg_ptr(traits::PC), true); this->builder.CreateStore( this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits::ICOUNT), get_reg_ptr(traits::ICOUNT), true), - this->gen_const(64U, 1)), + this->gen_const(64U, 1)), get_reg_ptr(traits::ICOUNT), true); pc = pc + ((instr & 3) == 3 ? 4 : 2); - this->gen_raise_trap(0, 2); // illegal instruction trap - this->gen_sync(iss::POST_SYNC, instr_descr.size()); + this->gen_raise_trap(0, 2); // illegal instruction trap + this->gen_sync(iss::POST_SYNC, instr_descr.size()); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); - } - // decoding functionality + } + //decoding functionality - void populate_decoding_tree(decoding_tree_node* root) { - // create submask - for(auto instr : root->instrs) { + void populate_decoding_tree(decoding_tree_node* root){ + //create submask + for(auto instr: root->instrs){ root->submask &= instr.mask; } - // put each instr according to submask&encoding into children - for(auto instr : root->instrs) { + //put each instr according to submask&encoding into children + for(auto instr: root->instrs){ bool foundMatch = false; - for(auto child : root->children) { - // use value as identifying trait - if(child->value == (instr.value & root->submask)) { + for(auto child: root->children){ + //use value as identifying trait + if(child->value == (instr.value&root->submask)){ child->instrs.push_back(instr); foundMatch = true; } } - if(!foundMatch) { - decoding_tree_node* child = new decoding_tree_node(instr.value & root->submask); + if(!foundMatch){ + decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask); child->instrs.push_back(instr); root->children.push_back(child); } } root->instrs.clear(); - // call populate_decoding_tree for all children - if(root->children.size() > 1) - for(auto child : root->children) { - populate_decoding_tree(child); + //call populate_decoding_tree for all children + if(root->children.size() >1) + for(auto child: root->children){ + populate_decoding_tree(child); } - else { - // sort instrs by value of the mask, this works bc we want to have the least restrictive one last - std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), - [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { return instr1.mask > instr2.mask; }); + else{ + //sort instrs by value of the mask, this works bc we want to have the least restrictive one last + std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { + return instr1.mask > instr2.mask; + }); } } - compile_func decode_instr(decoding_tree_node* node, code_word_t word) { - if(!node->children.size()) { - if(node->instrs.size() == 1) - return node->instrs[0].op; - for(auto instr : node->instrs) { - if((instr.mask & word) == instr.value) - return instr.op; + compile_func decode_instr(decoding_tree_node* node, code_word_t word){ + if(!node->children.size()){ + if(node->instrs.size() == 1) return node->instrs[0].op; + for(auto instr : node->instrs){ + if((instr.mask&word) == instr.value) return instr.op; } - } else { - for(auto child : node->children) { - if(child->value == (node->submask & word)) { + } + else{ + for(auto child : node->children){ + if (child->value == (node->submask&word)){ return decode_instr(child, word); - } - } + } + } } return nullptr; } @@ -3983,125 +4438,132 @@ template void debug_fn(CODE_WORD instr) { template vm_impl::vm_impl() { this(new ARCH()); } template -vm_impl::vm_impl(ARCH& core, unsigned core_id, unsigned cluster_id) +vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) : vm_base(core, core_id, cluster_id) { root = new decoding_tree_node(std::numeric_limits::max()); - for(auto instr : instr_descr) { + for(auto instr:instr_descr){ root->instrs.push_back(instr); } populate_decoding_tree(root); } template -std::tuple vm_impl::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, - BasicBlock* this_block) { +std::tuple +vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) { // we fetch at max 4 byte, alignment is 2 - enum { TRAP_ID = 1 << 16 }; + enum {TRAP_ID=1<<16}; code_word_t instr = 0; // const typename traits::addr_t upper_bits = ~traits::PGMASK; phys_addr_t paddr(pc); - auto* const data = (uint8_t*)&instr; + auto *const data = (uint8_t *)&instr; if(this->core.has_mmu()) paddr = this->core.virt2phys(pc); - // TODO: re-add page handling - // if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary - // auto res = this->core.read(paddr, 2, data); - // if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); - // if ((instr & 0x3) == 0x3) { // this is a 32bit instruction - // res = this->core.read(this->core.v2p(pc + 2), 2, data + 2); - // } - // } else { - auto res = this->core.read(paddr, 4, data); - if(res != iss::Ok) - throw trap_access(TRAP_ID, pc.val); - // } - if(instr == 0x0000006f || (instr & 0xffff) == 0xa001) - throw simulation_stopped(0); // 'J 0' or 'C.J 0' + //TODO: re-add page handling +// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary +// auto res = this->core.read(paddr, 2, data); +// if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); +// if ((instr & 0x3) == 0x3) { // this is a 32bit instruction +// res = this->core.read(this->core.v2p(pc + 2), 2, data + 2); +// } +// } else { + auto res = this->core.read(paddr, 4, data); + if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); +// } + if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0' // curr pc on stack ++inst_cnt; auto f = decode_instr(root, instr); - if(f == nullptr) { + if (f == nullptr) { f = &this_class::illegal_intruction; } return (this->*f)(pc, instr, this_block); } -template void vm_impl::gen_leave_behavior(BasicBlock* leave_blk) { +template void vm_impl::gen_leave_behavior(BasicBlock *leave_blk) { this->builder.SetInsertPoint(leave_blk); - this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false)); + this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false)); } template void vm_impl::gen_raise_trap(uint16_t trap_id, uint16_t cause) { - auto* TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id); + auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id); this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } template void vm_impl::gen_leave_trap(unsigned lvl) { - std::vector args{this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl))}; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) }; this->builder.CreateCall(this->mod->getFunction("leave_trap"), args); - auto* PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8); + auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } template void vm_impl::gen_wait(unsigned type) { - std::vector args{this->core_ptr, ConstantInt::get(getContext(), APInt(64, type))}; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) }; this->builder.CreateCall(this->mod->getFunction("wait"), args); } -template void vm_impl::gen_trap_behavior(BasicBlock* trap_blk) { +template void vm_impl::gen_trap_behavior(BasicBlock *trap_blk) { this->builder.SetInsertPoint(trap_blk); - this->gen_sync(POST_SYNC, -1); // TODO get right InstrId - auto* trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); - this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); - std::vector args{this->core_ptr, this->adj_to64(trap_state_val), - this->adj_to64(this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), false))}; + this->gen_sync(POST_SYNC, -1); //TODO get right InstrId + auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); + this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), + get_reg_ptr(traits::LAST_BRANCH), false); + std::vector args{this->core_ptr, this->adj_to64(trap_state_val), + this->adj_to64(this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), false))}; this->builder.CreateCall(this->mod->getFunction("enter_trap"), args); - auto* trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false); + auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateRet(trap_addr_val); } -template inline void vm_impl::gen_trap_check(BasicBlock* bb) { +template inline void vm_impl::gen_trap_check(BasicBlock *bb) { auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb); - auto* v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); - this->gen_cond_branch( - this->builder.CreateICmp(ICmpInst::ICMP_EQ, v, ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))), - target_bb, this->trap_blk, 1); + auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_EQ, v, + ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))), + target_bb, this->trap_blk, 1); this->builder.SetInsertPoint(target_bb); } } // namespace tgc5c -template <> std::unique_ptr create(arch::tgc5c* core, unsigned short port, bool dump) { +template <> +std::unique_ptr create(arch::tgc5c *core, unsigned short port, bool dump) { auto ret = new tgc5c::vm_impl(*core, dump); - if(port != 0) - debugger::server::run_server(ret, port); + if (port != 0) debugger::server::run_server(ret, port); return std::unique_ptr(ret); } } // namespace llvm } // namespace iss +#include #include #include -#include namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("tgc5c|m_p|llvm", - [](unsigned port, void*) -> std::tuple { - auto* cpu = new iss::arch::riscv_hart_m_p(); - auto* vm = new llvm::tgc5c::vm_impl(*cpu, false); - if(port != 0) - debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - }), - core_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned port, void*) -> std::tuple { - auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto* vm = new llvm::tgc5c::vm_impl(*cpu, false); - if(port != 0) - debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - })}; + core_factory::instance().register_creator("tgc5c|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_m_p(); + auto vm = new llvm::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_mu_p(); + auto vm = new llvm::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }) +}; } -} // namespace iss +} +// clang-format on \ No newline at end of file diff --git a/src/vm/tcc/vm_tgc5c.cpp b/src/vm/tcc/vm_tgc5c.cpp index dd767a0..9d4dff7 100644 --- a/src/vm/tcc/vm_tgc5c.cpp +++ b/src/vm/tcc/vm_tgc5c.cpp @@ -29,14 +29,14 @@ * POSSIBILITY OF SUCH DAMAGE. * *******************************************************************************/ - +// clang-format off #include #include #include #include #include -#include #include +#include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY @@ -55,23 +55,23 @@ using namespace iss::debugger; template class vm_impl : public iss::tcc::vm_base { public: using traits = arch::traits; - using super = typename iss::tcc::vm_base; + using super = typename iss::tcc::vm_base; using virt_addr_t = typename super::virt_addr_t; using phys_addr_t = typename super::phys_addr_t; using code_word_t = typename super::code_word_t; - using mem_type_e = typename traits::mem_type_e; - using addr_t = typename super::addr_t; - using tu_builder = typename super::tu_builder; + using mem_type_e = typename traits::mem_type_e; + using addr_t = typename super::addr_t; + using tu_builder = typename super::tu_builder; vm_impl(); - vm_impl(ARCH& core, unsigned core_id = 0, unsigned cluster_id = 0); + vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } - target_adapter_if* accquire_target_adapter(server_if* srv) override { + target_adapter_if *accquire_target_adapter(server_if *srv) override { debugger_if::dbg_enabled = true; - if(vm_base::tgt_adapter == nullptr) + if (vm_base::tgt_adapter == nullptr) vm_base::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); return vm_base::tgt_adapter; } @@ -81,13 +81,15 @@ protected: using this_class = vm_impl; using compile_ret_t = std::tuple; - using compile_func = compile_ret_t (this_class::*)(virt_addr_t& pc, code_word_t instr, tu_builder&); + using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&); - inline const char* name(size_t index) { return traits::reg_aliases.at(index); } + inline const char *name(size_t index){return traits::reg_aliases.at(index);} - void setup_module(std::string m) override { super::setup_module(m); } + void setup_module(std::string m) override { + super::setup_module(m); + } - compile_ret_t gen_single_inst_behavior(virt_addr_t&, unsigned int&, tu_builder&) override; + compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override; void gen_trap_behavior(tu_builder& tu) override; @@ -97,10 +99,12 @@ protected: void gen_wait(tu_builder& tu, unsigned type); - inline void gen_trap_check(tu_builder& tu) { tu("if(*trap_state!=0) goto trap_entry;"); } + inline void gen_trap_check(tu_builder& tu) { + tu("if(*trap_state!=0) goto trap_entry;"); + } inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) { - switch(reg_num) { + switch(reg_num){ case traits::NEXT_PC: tu("*next_pc = {:#x};", pc.val); break; @@ -108,19 +112,21 @@ protected: tu("*pc = {:#x};", pc.val); break; default: - if(!tu.defined_regs[reg_num]) { + if(!tu.defined_regs[reg_num]){ tu("reg_t* reg{:02d} = (reg_t*){:#x};", reg_num, reinterpret_cast(get_reg_ptr(reg_num))); - tu.defined_regs[reg_num] = true; + tu.defined_regs[reg_num]=true; } tu("*reg{:02d} = {:#x};", reg_num, pc.val); } } - template ::type> inline S sext(U from) { - auto mask = (1ULL << W) - 1; - auto sign_mask = 1ULL << (W - 1); + + template::type> + inline S sext(U from) { + auto mask = (1ULL< instrs; std::vector children; uint32_t submask = std::numeric_limits::max(); uint32_t value; - decoding_tree_node(uint32_t value) - : value(value) {} + decoding_tree_node(uint32_t value) : value(value){} }; - decoding_tree_node* root{nullptr}; + decoding_tree_node* root {nullptr}; const std::array instr_descr = {{ - /* entries are: size, valid value, valid mask, function ptr */ + /* entries are: size, valid value, valid mask, function ptr */ /* instruction LUI, encoding '0b00000000000000000000000000110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, /* instruction AUIPC, encoding '0b00000000000000000000000000010111' */ @@ -320,2946 +325,3239 @@ private: /* instruction DII, encoding '0b0000000000000000' */ {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, }}; - + /* instruction definitions */ /* instruction 0: LUI */ - compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LUI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 0); + vm_base::gen_sync(tu, PRE_SYNC,0); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = ((bit_sub<12, 20>(instr) << 12)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)imm), 32)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)((int32_t)imm),32)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 0); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,0); return returnValue; } - + /* instruction 1: AUIPC */ - compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AUIPC_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 1); + vm_base::gen_sync(tu, PRE_SYNC,1); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = ((bit_sub<12, 20>(instr) << 12)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)(PC + (int32_t)imm), 32)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)(PC+(int32_t)imm),32)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 1); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,1); return returnValue; } - + /* instruction 2: JAL */ - compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("JAL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 2); + vm_base::gen_sync(tu, PRE_SYNC,2); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = - ((bit_sub<12, 8>(instr) << 12) | (bit_sub<20, 1>(instr) << 11) | (bit_sub<21, 10>(instr) << 1) | (bit_sub<31, 1>(instr) << 20)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)(PC + 4), 32)); - } - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int32_t)sext<21>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)(PC+ 4),32)); + } + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int32_t)sext<21>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 2); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,2); return returnValue; } - + /* instruction 3: JALR */ - compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("JALR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 3); + vm_base::gen_sync(tu, PRE_SYNC,3); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto addr_mask = tu.assignment(tu.constant((uint32_t)-2, 32), 32); - auto new_pc = tu.assignment( - tu.ext((tu.bitwise_and((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), addr_mask)), 32, - false), - 32); - tu.open_if(tu.urem(new_pc, tu.constant(static_cast(traits::INSTR_ALIGNMENT), 32))); - this->gen_raise_trap(tu, 0, 0); - tu.open_else(); - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)(PC + 4), 32)); - } - auto PC_val_v = tu.assignment("PC_val", new_pc, 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - tu.close_scope(); + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto addr_mask = tu.assignment(tu.constant((uint32_t)- 2,32),32); + auto new_pc = tu.assignment(tu.ext((tu.bitwise_and( + (tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))), + addr_mask)),32,false),32); + tu.open_if(tu.urem( + new_pc, + tu.constant(static_cast(traits:: INSTR_ALIGNMENT),32))); + this->gen_raise_trap(tu, 0, 0); + tu.open_else(); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)(PC+ 4),32)); + } + auto PC_val_v = tu.assignment("PC_val", new_pc,32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 3); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,3); return returnValue; } - + /* instruction 4: BEQ */ - compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BEQ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 4); + vm_base::gen_sync(tu, PRE_SYNC,4); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 4); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,4); return returnValue; } - + /* instruction 5: BNE */ - compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BNE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 5); + vm_base::gen_sync(tu, PRE_SYNC,5); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 5); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,5); return returnValue; } - + /* instruction 6: BLT */ - compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BLT_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 6); + vm_base::gen_sync(tu, PRE_SYNC,6); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), - tu.ext(tu.load(rs2 + traits::X0, 0), 32, true))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_SLT, + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.ext(tu.load(rs2+ traits::X0, 0),32,true))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 6); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,6); return returnValue; } - + /* instruction 7: BGE */ - compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BGE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 7); + vm_base::gen_sync(tu, PRE_SYNC,7); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_SGE, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), - tu.ext(tu.load(rs2 + traits::X0, 0), 32, true))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_SGE, + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.ext(tu.load(rs2+ traits::X0, 0),32,true))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 7); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,7); return returnValue; } - + /* instruction 8: BLTU */ - compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BLTU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 8); + vm_base::gen_sync(tu, PRE_SYNC,8); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_ULT, + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 8); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,8); return returnValue; } - + /* instruction 9: BGEU */ - compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BGEU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 9); + vm_base::gen_sync(tu, PRE_SYNC,9); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_UGE, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_UGE, + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 9); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,9); return returnValue; } - + /* instruction 10: LB */ - compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 10); + vm_base::gen_sync(tu, PRE_SYNC,10); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto load_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 8), 8, true), 8); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto load_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 8),8,true),8); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 10); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,10); return returnValue; } - + /* instruction 11: LH */ - compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 11); + vm_base::gen_sync(tu, PRE_SYNC,11); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto load_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 16), 16, true), 16); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto load_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 16),16,true),16); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 11); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,11); return returnValue; } - + /* instruction 12: LW */ - compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 12); + vm_base::gen_sync(tu, PRE_SYNC,12); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto load_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 32), 32, true), 32); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto load_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 32),32,true),32); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 12); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,12); return returnValue; } - + /* instruction 13: LBU */ - compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LBU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 13); + vm_base::gen_sync(tu, PRE_SYNC,13); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto load_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 8), 8); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto load_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 8),8); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 13); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,13); return returnValue; } - + /* instruction 14: LHU */ - compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LHU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 14); + vm_base::gen_sync(tu, PRE_SYNC,14); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto load_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 16), 16); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto load_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 16),16); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 14); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,14); return returnValue; } - + /* instruction 15: SB */ - compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 15); + vm_base::gen_sync(tu, PRE_SYNC,15); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto store_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0), 8, false)); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto store_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2+ traits::X0, 0),8,false)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 15); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,15); return returnValue; } - + /* instruction 16: SH */ - compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 16); + vm_base::gen_sync(tu, PRE_SYNC,16); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto store_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0), 16, false)); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto store_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2+ traits::X0, 0),16,false)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 16); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,16); return returnValue; } - + /* instruction 17: SW */ - compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 17); + vm_base::gen_sync(tu, PRE_SYNC,17); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto store_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0), 32, false)); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto store_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2+ traits::X0, 0),32,false)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 17); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,17); return returnValue; } - + /* instruction 18: ADDI */ - compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 18); + vm_base::gen_sync(tu, PRE_SYNC,18); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 18); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,18); return returnValue; } - + /* instruction 19: SLTI */ - compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 19); + vm_base::gen_sync(tu, PRE_SYNC,19); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), - tu.constant((int16_t)sext<12>(imm), 16))), - tu.constant(1, 8), tu.constant(0, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_SLT, + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.constant((int16_t)sext<12>(imm),16))), tu.constant( 1,8),tu.constant( 0,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 19); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,19); return returnValue; } - + /* instruction 20: SLTIU */ - compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTIU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 20); + vm_base::gen_sync(tu, PRE_SYNC,20); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1 + traits::X0, 0), - tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32))), - tu.constant(1, 8), tu.constant(0, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_ULT, + tu.load(rs1+ traits::X0, 0), + tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))), tu.constant( 1,8),tu.constant( 0,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 20); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,20); return returnValue; } - + /* instruction 21: XORI */ - compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("XORI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 21); + vm_base::gen_sync(tu, PRE_SYNC,21); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.bitwise_xor(tu.load(rs1 + traits::X0, 0), tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_xor( + tu.load(rs1+ traits::X0, 0), + tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 21); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,21); return returnValue; } - + /* instruction 22: ORI */ - compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ORI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 22); + vm_base::gen_sync(tu, PRE_SYNC,22); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.bitwise_or(tu.load(rs1 + traits::X0, 0), tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_or( + tu.load(rs1+ traits::X0, 0), + tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 22); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,22); return returnValue; } - + /* instruction 23: ANDI */ - compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ANDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 23); + vm_base::gen_sync(tu, PRE_SYNC,23); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.bitwise_and(tu.load(rs1 + traits::X0, 0), tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_and( + tu.load(rs1+ traits::X0, 0), + tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 23); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,23); return returnValue; } - + /* instruction 24: SLLI */ - compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 24); + vm_base::gen_sync(tu, PRE_SYNC,24); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.shl(tu.load(rs1 + traits::X0, 0), tu.constant(shamt, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.shl( + tu.load(rs1+ traits::X0, 0), + tu.constant(shamt,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 24); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,24); return returnValue; } - + /* instruction 25: SRLI */ - compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 25); + vm_base::gen_sync(tu, PRE_SYNC,25); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.lshr(tu.load(rs1 + traits::X0, 0), tu.constant(shamt, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.lshr( + tu.load(rs1+ traits::X0, 0), + tu.constant(shamt,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 25); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,25); return returnValue; } - + /* instruction 26: SRAI */ - compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 26); + vm_base::gen_sync(tu, PRE_SYNC,26); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.ext((tu.ashr(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), tu.constant(shamt, 8))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.ashr( + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.constant(shamt,8))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 26); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,26); return returnValue; } - + /* instruction 27: ADD */ - compile_ret_t __add(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 27); + vm_base::gen_sync(tu, PRE_SYNC,27); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 27); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,27); return returnValue; } - + /* instruction 28: SUB */ - compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SUB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 28); + vm_base::gen_sync(tu, PRE_SYNC,28); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.sub(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.sub( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 28); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,28); return returnValue; } - + /* instruction 29: SLL */ - compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 29); + vm_base::gen_sync(tu, PRE_SYNC,29); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.shl(tu.load(rs1 + traits::X0, 0), - (tu.bitwise_and(tu.load(rs2 + traits::X0, 0), - tu.constant((static_cast(traits::XLEN) - 1), 64))))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.shl( + tu.load(rs1+ traits::X0, 0), + (tu.bitwise_and( + tu.load(rs2+ traits::X0, 0), + tu.constant((static_cast(traits:: XLEN)- 1),64))))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 29); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,29); return returnValue; } - + /* instruction 30: SLT */ - compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLT_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 30); + vm_base::gen_sync(tu, PRE_SYNC,30); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), - tu.ext(tu.load(rs2 + traits::X0, 0), 32, true)), - tu.constant(1, 8), tu.constant(0, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_SLT, + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.ext(tu.load(rs2+ traits::X0, 0),32,true)), tu.constant( 1,8),tu.constant( 0,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 30); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,30); return returnValue; } - + /* instruction 31: SLTU */ - compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 31); + vm_base::gen_sync(tu, PRE_SYNC,31); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0)), - tu.constant(1, 8), tu.constant(0, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_ULT, + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0)), tu.constant( 1,8),tu.constant( 0,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 31); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,31); return returnValue; } - + /* instruction 32: XOR */ - compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("XOR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 32); + vm_base::gen_sync(tu, PRE_SYNC,32); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.bitwise_xor(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_xor( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 32); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,32); return returnValue; } - + /* instruction 33: SRL */ - compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 33); + vm_base::gen_sync(tu, PRE_SYNC,33); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.lshr(tu.load(rs1 + traits::X0, 0), - (tu.bitwise_and(tu.load(rs2 + traits::X0, 0), - tu.constant((static_cast(traits::XLEN) - 1), 64))))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.lshr( + tu.load(rs1+ traits::X0, 0), + (tu.bitwise_and( + tu.load(rs2+ traits::X0, 0), + tu.constant((static_cast(traits:: XLEN)- 1),64))))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 33); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,33); return returnValue; } - + /* instruction 34: SRA */ - compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRA_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 34); + vm_base::gen_sync(tu, PRE_SYNC,34); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.ashr(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), - (tu.bitwise_and(tu.load(rs2 + traits::X0, 0), - tu.constant((static_cast(traits::XLEN) - 1), 64))))), - 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.ashr( + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + (tu.bitwise_and( + tu.load(rs2+ traits::X0, 0), + tu.constant((static_cast(traits:: XLEN)- 1),64))))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 34); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,34); return returnValue; } - + /* instruction 35: OR */ - compile_ret_t __or(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("OR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 35); + vm_base::gen_sync(tu, PRE_SYNC,35); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.bitwise_or(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_or( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 35); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,35); return returnValue; } - + /* instruction 36: AND */ - compile_ret_t __and(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AND_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 36); + vm_base::gen_sync(tu, PRE_SYNC,36); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.bitwise_and(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_and( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 36); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,36); return returnValue; } - + /* instruction 37: FENCE */ - compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FENCE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 37); + vm_base::gen_sync(tu, PRE_SYNC,37); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t succ = ((bit_sub<20, 4>(instr))); - uint8_t pred = ((bit_sub<24, 4>(instr))); - uint8_t fm = ((bit_sub<28, 4>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); + uint8_t fm = ((bit_sub<28,4>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), fmt::arg("pred", pred), - fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); + auto mnemonic = fmt::format( + "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), + fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.write_mem(traits::FENCE, static_cast(traits::fence), tu.constant((uint8_t)pred << 4 | succ, 8)); + tu.write_mem(traits::FENCE, static_cast(traits:: fence), tu.constant((uint8_t)pred<< 4|succ,8)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 37); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,37); return returnValue; } - + /* instruction 38: ECALL */ - compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ECALL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 38); + vm_base::gen_sync(tu, PRE_SYNC,38); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ecall"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 11); + this->gen_raise_trap(tu, 0, 11); auto returnValue = std::make_tuple(TRAP); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 38); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,38); return returnValue; } - + /* instruction 39: EBREAK */ - compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("EBREAK_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 39); + vm_base::gen_sync(tu, PRE_SYNC,39); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ebreak"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 3); + this->gen_raise_trap(tu, 0, 3); auto returnValue = std::make_tuple(TRAP); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 39); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,39); return returnValue; } - + /* instruction 40: MRET */ - compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MRET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 40); + vm_base::gen_sync(tu, PRE_SYNC,40); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "mret"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); this->gen_leave_trap(tu, 3); auto returnValue = std::make_tuple(TRAP); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 40); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,40); return returnValue; } - + /* instruction 41: WFI */ - compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("WFI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 41); + vm_base::gen_sync(tu, PRE_SYNC,41); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "wfi"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); this->gen_wait(tu, 1); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 41); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,41); return returnValue; } - + /* instruction 42: CSRRW */ - compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 42); + vm_base::gen_sync(tu, PRE_SYNC,42); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrs1 = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); - if(rd != 0) { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - tu.write_mem(traits::CSR, csr, xrs1); - tu.store(rd + traits::X0, xrd); - } else { - tu.write_mem(traits::CSR, csr, xrs1); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32); + if(rd!= 0){ auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + tu.write_mem(traits::CSR, csr, xrs1); + tu.store(rd + traits::X0, + xrd); + } + else{ + tu.write_mem(traits::CSR, csr, xrs1); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 42); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,42); return returnValue; } - + /* instruction 43: CSRRS */ - compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRS_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 43); + vm_base::gen_sync(tu, PRE_SYNC,43); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - auto xrs1 = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); - if(rs1 != 0) { - tu.write_mem(traits::CSR, csr, tu.bitwise_or(xrd, xrs1)); - } - if(rd != 0) { - tu.store(rd + traits::X0, xrd); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32); + if(rs1!= 0) { + tu.write_mem(traits::CSR, csr, tu.bitwise_or( + xrd, + xrs1)); + } + if(rd!= 0) { + tu.store(rd + traits::X0, + xrd); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 43); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,43); return returnValue; } - + /* instruction 44: CSRRC */ - compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRC_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 44); + vm_base::gen_sync(tu, PRE_SYNC,44); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - auto xrs1 = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); - if(rs1 != 0) { - tu.write_mem(traits::CSR, csr, tu.bitwise_and(xrd, tu.logical_neg(xrs1))); - } - if(rd != 0) { - tu.store(rd + traits::X0, xrd); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32); + if(rs1!= 0) { + tu.write_mem(traits::CSR, csr, tu.bitwise_and( + xrd, + tu.logical_neg(xrs1))); + } + if(rd!= 0) { + tu.store(rd + traits::X0, + xrd); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 44); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,44); return returnValue; } - + /* instruction 45: CSRRWI */ - compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRWI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 45); + vm_base::gen_sync(tu, PRE_SYNC,45); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - tu.write_mem(traits::CSR, csr, tu.constant((uint32_t)zimm, 32)); - if(rd != 0) { - tu.store(rd + traits::X0, xrd); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + tu.write_mem(traits::CSR, csr, tu.constant((uint32_t)zimm,32)); + if(rd!= 0) { + tu.store(rd + traits::X0, + xrd); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 45); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,45); return returnValue; } - + /* instruction 46: CSRRSI */ - compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRSI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 46); + vm_base::gen_sync(tu, PRE_SYNC,46); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - if(zimm != 0) { - tu.write_mem(traits::CSR, csr, tu.bitwise_or(xrd, tu.constant((uint32_t)zimm, 32))); - } - if(rd != 0) { - tu.store(rd + traits::X0, xrd); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + if(zimm!= 0) { + tu.write_mem(traits::CSR, csr, tu.bitwise_or( + xrd, + tu.constant((uint32_t)zimm,32))); + } + if(rd!= 0) { + tu.store(rd + traits::X0, + xrd); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 46); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,46); return returnValue; } - + /* instruction 47: CSRRCI */ - compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRCI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 47); + vm_base::gen_sync(tu, PRE_SYNC,47); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - if(zimm != 0) { - tu.write_mem(traits::CSR, csr, tu.bitwise_and(xrd, tu.constant(~((uint32_t)zimm), 32))); - } - if(rd != 0) { - tu.store(rd + traits::X0, xrd); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + if(zimm!= 0) { + tu.write_mem(traits::CSR, csr, tu.bitwise_and( + xrd, + tu.constant(~ ((uint32_t)zimm),32))); + } + if(rd!= 0) { + tu.store(rd + traits::X0, + xrd); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 47); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,47); return returnValue; } - + /* instruction 48: FENCE_I */ - compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FENCE_I_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 48); + vm_base::gen_sync(tu, PRE_SYNC,48); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), fmt::arg("rs1", name(rs1)), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), + fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.write_mem(traits::FENCE, static_cast(traits::fencei), tu.constant(imm, 16)); + tu.write_mem(traits::FENCE, static_cast(traits:: fencei), tu.constant(imm,16)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 48); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,48); return returnValue; } - + /* instruction 49: MUL */ - compile_ret_t __mul(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __mul(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MUL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 49); + vm_base::gen_sync(tu, PRE_SYNC,49); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 64, true), - tu.ext(tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), 64, true))), - 64, true), - 64); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto res = tu.assignment(tu.ext((tu.mul( + tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,true), + tu.ext(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),64,true))),64,true),64); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 49); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,49); return returnValue; } - + /* instruction 50: MULH */ - compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 50); + vm_base::gen_sync(tu, PRE_SYNC,50); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 64, true), - tu.ext(tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), 64, true))), - 64, true), - 64); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.ashr(res, tu.constant(static_cast(traits::XLEN), 32))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto res = tu.assignment(tu.ext((tu.mul( + tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,true), + tu.ext(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),64,true))),64,true),64); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext((tu.ashr( + res, + tu.constant(static_cast(traits:: XLEN),32))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 50); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,50); return returnValue; } - + /* instruction 51: MULHSU */ - compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHSU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 51); + vm_base::gen_sync(tu, PRE_SYNC,51); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 64, true), - tu.ext(tu.load(rs2 + traits::X0, 0), 64, false))), - 64, true), - 64); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.ashr(res, tu.constant(static_cast(traits::XLEN), 32))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto res = tu.assignment(tu.ext((tu.mul( + tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,true), + tu.ext(tu.load(rs2+ traits::X0, 0),64,false))),64,true),64); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext((tu.ashr( + res, + tu.constant(static_cast(traits:: XLEN),32))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 51); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,51); return returnValue; } - + /* instruction 52: MULHU */ - compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 52); + vm_base::gen_sync(tu, PRE_SYNC,52); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto res = tu.assignment( - tu.ext((tu.mul(tu.ext(tu.load(rs1 + traits::X0, 0), 64, false), tu.ext(tu.load(rs2 + traits::X0, 0), 64, false))), 64, - false), - 64); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.lshr(res, tu.constant(static_cast(traits::XLEN), 32))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto res = tu.assignment(tu.ext((tu.mul( + tu.ext(tu.load(rs1+ traits::X0, 0),64,false), + tu.ext(tu.load(rs2+ traits::X0, 0),64,false))),64,false),64); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext((tu.lshr( + res, + tu.constant(static_cast(traits:: XLEN),32))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 52); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,52); return returnValue; } - + /* instruction 53: DIV */ - compile_ret_t __div(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __div(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIV_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 53); + vm_base::gen_sync(tu, PRE_SYNC,53); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto dividend = tu.assignment(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 32); - auto divisor = tu.assignment(tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), 32); - if(rd != 0) { - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, divisor, tu.constant(0, 8))); - auto MMIN = tu.assignment(tu.constant(((uint32_t)1) << (static_cast(traits::XLEN) - 1), 32), 32); - tu.open_if(tu.logical_and(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + traits::X0, 0), MMIN), - tu.icmp(ICmpInst::ICMP_EQ, divisor, tu.constant(-1, 8)))); - tu.store(rd + traits::X0, MMIN); - tu.open_else(); - tu.store(rd + traits::X0, tu.ext((tu.sdiv(dividend, divisor)), 32, false)); - tu.close_scope(); - tu.open_else(); - tu.store(rd + traits::X0, tu.constant((uint32_t)-1, 32)); - tu.close_scope(); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto dividend = tu.assignment(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),32); + auto divisor = tu.assignment(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),32); + if(rd!= 0){ tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + divisor, + tu.constant( 0,8))); + auto MMIN = tu.assignment(tu.constant(((uint32_t)1)<<(static_cast(traits:: XLEN)-1),32),32); + tu.open_if(tu.logical_and( + tu.icmp(ICmpInst::ICMP_EQ, + tu.load(rs1+ traits::X0, 0), + MMIN), + tu.icmp(ICmpInst::ICMP_EQ, + divisor, + tu.constant(- 1,8)))); + tu.store(rd + traits::X0, + MMIN); + tu.open_else(); + tu.store(rd + traits::X0, + tu.ext((tu.sdiv( + dividend, + divisor)),32,false)); + tu.close_scope(); + tu.open_else(); + tu.store(rd + traits::X0, + tu.constant((uint32_t)- 1,32)); + tu.close_scope(); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 53); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,53); return returnValue; } - + /* instruction 54: DIVU */ - compile_ret_t __divu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __divu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIVU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 54); + vm_base::gen_sync(tu, PRE_SYNC,54); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2 + traits::X0, 0), tu.constant(0, 8))); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.udiv(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false)); - } - tu.open_else(); - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)-1, 32)); - } - tu.close_scope(); + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + tu.load(rs2+ traits::X0, 0), + tu.constant( 0,8))); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext((tu.udiv( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))),32,false)); + } + tu.open_else(); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)- 1,32)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 54); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,54); return returnValue; } - + /* instruction 55: REM */ - compile_ret_t __rem(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __rem(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REM_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 55); + vm_base::gen_sync(tu, PRE_SYNC,55); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2 + traits::X0, 0), tu.constant(0, 8))); - auto MMIN = tu.assignment(tu.constant((uint32_t)1 << (static_cast(traits::XLEN) - 1), 32), 32); - tu.open_if(tu.logical_and(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + traits::X0, 0), MMIN), - tu.icmp(ICmpInst::ICMP_EQ, tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), tu.constant(-1, 8)))); - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant(0, 8)); - } - tu.open_else(); - if(rd != 0) { - tu.store(rd + traits::X0, - tu.ext((tu.srem(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), tu.ext(tu.load(rs2 + traits::X0, 0), 32, true))), - 32, false)); - } - tu.close_scope(); - tu.open_else(); - if(rd != 0) { - tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0)); - } - tu.close_scope(); + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + tu.load(rs2+ traits::X0, 0), + tu.constant( 0,8))); + auto MMIN = tu.assignment(tu.constant((uint32_t)1<<(static_cast(traits:: XLEN)-1),32),32); + tu.open_if(tu.logical_and( + tu.icmp(ICmpInst::ICMP_EQ, + tu.load(rs1+ traits::X0, 0), + MMIN), + tu.icmp(ICmpInst::ICMP_EQ, + tu.ext(tu.load(rs2+ traits::X0, 0),32,true), + tu.constant(- 1,8)))); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.constant( 0,8)); + } + tu.open_else(); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext((tu.srem( + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.ext(tu.load(rs2+ traits::X0, 0),32,true))),32,false)); + } + tu.close_scope(); + tu.open_else(); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.load(rs1+ traits::X0, 0)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 55); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,55); return returnValue; } - + /* instruction 56: REMU */ - compile_ret_t __remu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __remu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REMU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 56); + vm_base::gen_sync(tu, PRE_SYNC,56); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2 + traits::X0, 0), tu.constant(0, 8))); - if(rd != 0) { - tu.store(rd + traits::X0, tu.urem(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - } - tu.open_else(); - if(rd != 0) { - tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0)); - } - tu.close_scope(); + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + tu.load(rs2+ traits::X0, 0), + tu.constant( 0,8))); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.urem( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + } + tu.open_else(); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.load(rs1+ traits::X0, 0)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 56); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,56); return returnValue; } - + /* instruction 57: C__ADDI4SPN */ - compile_ret_t __c__addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__ADDI4SPN_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 57); + vm_base::gen_sync(tu, PRE_SYNC,57); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<2, 3>(instr))); - uint16_t imm = - ((bit_sub<5, 1>(instr) << 3) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<7, 4>(instr) << 6) | (bit_sub<11, 2>(instr) << 4)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"), fmt::arg("rd", name(8 + rd)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"), + fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(imm) { - tu.store(rd + 8 + traits::X0, tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant(imm, 16))), 32, false)); - } else { - this->gen_raise_trap(tu, 0, 2); + tu.store(rd+ 8 + traits::X0, + tu.ext((tu.add( + tu.load(2+ traits::X0, 0), + tu.constant(imm,16))),32,false)); + } + else{ + this->gen_raise_trap(tu, 0, 2); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 57); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,57); return returnValue; } - + /* instruction 58: C__LW */ - compile_ret_t __c__lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__LW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 58); + vm_base::gen_sync(tu, PRE_SYNC,58); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<2, 3>(instr))); - uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"), - fmt::arg("rd", name(8 + rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - auto offs = tu.assignment(tu.ext((tu.add(tu.load(rs1 + 8 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32); - tu.store(rd + 8 + traits::X0, tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32), 32, true), 32, false)); + auto offs = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant(uimm,8))),32,false),32); + tu.store(rd+ 8 + traits::X0, + tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 58); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,58); return returnValue; } - + /* instruction 59: C__SW */ - compile_ret_t __c__sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 59); + vm_base::gen_sync(tu, PRE_SYNC,59); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"), - fmt::arg("rs2", name(8 + rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - auto offs = tu.assignment(tu.ext((tu.add(tu.load(rs1 + 8 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32); - tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2 + 8 + traits::X0, 0), 32, false)); + auto offs = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant(uimm,8))),32,false),32); + tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2+ 8+ traits::X0, 0),32,false)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 59); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,59); return returnValue; } - + /* instruction 60: C__ADDI */ - compile_ret_t __c__addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__ADDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 60); + vm_base::gen_sync(tu, PRE_SYNC,60); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"), fmt::arg("rs1", name(rs1)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rs1 != 0) { - tu.store(rs1 + traits::X0, tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int8_t)sext<6>(imm), 8))), 32, false)); - } + if(rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rs1!= 0) { + tu.store(rs1 + traits::X0, + tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int8_t)sext<6>(imm),8))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 60); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,60); return returnValue; } - + /* instruction 61: C__NOP */ - compile_ret_t __c__nop(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__nop(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__NOP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 61); + vm_base::gen_sync(tu, PRE_SYNC,61); uint64_t PC = pc.val; - uint8_t nzimm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - if(this->disass_enabled) { + uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c__nop"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 61); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,61); return returnValue; } - + /* instruction 62: C__JAL */ - compile_ret_t __c__jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__JAL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 62); + vm_base::gen_sync(tu, PRE_SYNC,62); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) | - (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11)); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"), + fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(1 + traits::X0, tu.constant((uint32_t)(PC + 2), 32)); - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<12>(imm)), 32); + tu.store(1 + traits::X0, + tu.constant((uint32_t)(PC+ 2),32)); + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<12>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 62); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,62); return returnValue; } - + /* instruction 63: C__LI */ - compile_ret_t __c__li(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__li(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__LI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 63); + vm_base::gen_sync(tu, PRE_SYNC,63); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)((int8_t)sext<6>(imm)), 32)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)((int8_t)sext<6>(imm)),32)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 63); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,63); return returnValue; } - + /* instruction 64: C__LUI */ - compile_ret_t __c__lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__LUI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 64); + vm_base::gen_sync(tu, PRE_SYNC,64); uint64_t PC = pc.val; - uint32_t imm = ((bit_sub<2, 5>(instr) << 12) | (bit_sub<12, 1>(instr) << 17)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(imm == 0 || rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); + if(imm== 0||rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); } - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)sext<18>(imm)), 32)); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)((int32_t)sext<18>(imm)),32)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 64); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,64); return returnValue; } - + /* instruction 65: C__ADDI16SP */ - compile_ret_t __c__addi16sp(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__addi16sp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__ADDI16SP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 65); + vm_base::gen_sync(tu, PRE_SYNC,65); uint64_t PC = pc.val; - uint16_t nzimm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 7) | (bit_sub<5, 1>(instr) << 6) | - (bit_sub<6, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 9)); - if(this->disass_enabled) { + uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"), fmt::arg("nzimm", nzimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"), + fmt::arg("nzimm", nzimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(nzimm) { - tu.store(2 + traits::X0, tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant((int16_t)sext<10>(nzimm), 16))), 32, false)); - } else { - this->gen_raise_trap(tu, 0, 2); + tu.store(2 + traits::X0, + tu.ext((tu.add( + tu.load(2+ traits::X0, 0), + tu.constant((int16_t)sext<10>(nzimm),16))),32,false)); + } + else{ + this->gen_raise_trap(tu, 0, 2); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 65); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,65); return returnValue; } - + /* instruction 66: __reserved_clui */ - compile_ret_t ____reserved_clui(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t ____reserved_clui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("__reserved_clui_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 66); + vm_base::gen_sync(tu, PRE_SYNC,66); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "__reserved_clui"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 66); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,66); return returnValue; } - + /* instruction 67: C__SRLI */ - compile_ret_t __c__srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 67); + vm_base::gen_sync(tu, PRE_SYNC,67); uint64_t PC = pc.val; - uint8_t shamt = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("shamt", shamt)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rs1 + 8 + traits::X0, tu.lshr(tu.load(rs1 + 8 + traits::X0, 0), tu.constant(shamt, 8))); + tu.store(rs1+ 8 + traits::X0, + tu.lshr( + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant(shamt,8))); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 67); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,67); return returnValue; } - + /* instruction 68: C__SRAI */ - compile_ret_t __c__srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 68); + vm_base::gen_sync(tu, PRE_SYNC,68); uint64_t PC = pc.val; - uint8_t shamt = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("shamt", shamt)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(shamt) { - tu.store(rs1 + 8 + traits::X0, - tu.ext((tu.ashr((tu.ext(tu.load(rs1 + 8 + traits::X0, 0), 32, true)), tu.constant(shamt, 8))), 32, false)); - } else { - if(static_cast(traits::XLEN) == 128) { - tu.store(rs1 + 8 + traits::X0, - tu.ext((tu.ashr((tu.ext(tu.load(rs1 + 8 + traits::X0, 0), 32, true)), tu.constant(64, 8))), 32, false)); - } + if(shamt){ tu.store(rs1+ 8 + traits::X0, + tu.ext((tu.ashr( + (tu.ext(tu.load(rs1+ 8+ traits::X0, 0),32,true)), + tu.constant(shamt,8))),32,false)); + } + else{ + if(static_cast(traits:: XLEN)== 128){ tu.store(rs1+ 8 + traits::X0, + tu.ext((tu.ashr( + (tu.ext(tu.load(rs1+ 8+ traits::X0, 0),32,true)), + tu.constant( 64,8))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 68); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,68); return returnValue; } - + /* instruction 69: C__ANDI */ - compile_ret_t __c__andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__ANDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 69); + vm_base::gen_sync(tu, PRE_SYNC,69); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rs1 + 8 + traits::X0, - tu.ext((tu.bitwise_and(tu.load(rs1 + 8 + traits::X0, 0), tu.constant((int8_t)sext<6>(imm), 8))), 32, false)); + tu.store(rs1+ 8 + traits::X0, + tu.ext((tu.bitwise_and( + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant((int8_t)sext<6>(imm),8))),32,false)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 69); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,69); return returnValue; } - + /* instruction 70: C__SUB */ - compile_ret_t __c__sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SUB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 70); + vm_base::gen_sync(tu, PRE_SYNC,70); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd + 8 + traits::X0, tu.ext((tu.sub(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0))), 32, false)); + tu.store(rd+ 8 + traits::X0, + tu.ext((tu.sub( + tu.load(rd+ 8+ traits::X0, 0), + tu.load(rs2+ 8+ traits::X0, 0))),32,false)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 70); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,70); return returnValue; } - + /* instruction 71: C__XOR */ - compile_ret_t __c__xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__XOR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 71); + vm_base::gen_sync(tu, PRE_SYNC,71); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd + 8 + traits::X0, tu.bitwise_xor(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0))); + tu.store(rd+ 8 + traits::X0, + tu.bitwise_xor( + tu.load(rd+ 8+ traits::X0, 0), + tu.load(rs2+ 8+ traits::X0, 0))); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 71); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,71); return returnValue; } - + /* instruction 72: C__OR */ - compile_ret_t __c__or(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__OR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 72); + vm_base::gen_sync(tu, PRE_SYNC,72); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd + 8 + traits::X0, tu.bitwise_or(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0))); + tu.store(rd+ 8 + traits::X0, + tu.bitwise_or( + tu.load(rd+ 8+ traits::X0, 0), + tu.load(rs2+ 8+ traits::X0, 0))); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 72); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,72); return returnValue; } - + /* instruction 73: C__AND */ - compile_ret_t __c__and(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__AND_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 73); + vm_base::gen_sync(tu, PRE_SYNC,73); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd + 8 + traits::X0, tu.bitwise_and(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0))); + tu.store(rd+ 8 + traits::X0, + tu.bitwise_and( + tu.load(rd+ 8+ traits::X0, 0), + tu.load(rs2+ 8+ traits::X0, 0))); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 73); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,73); return returnValue; } - + /* instruction 74: C__J */ - compile_ret_t __c__j(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__j(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__J_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 74); + vm_base::gen_sync(tu, PRE_SYNC,74); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) | - (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11)); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"), + fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<12>(imm)), 32); + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<12>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 74); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,74); return returnValue; } - + /* instruction 75: C__BEQZ */ - compile_ret_t __c__beqz(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__beqz(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__BEQZ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 75); + vm_base::gen_sync(tu, PRE_SYNC,75); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) | - (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + 8 + traits::X0, 0), tu.constant(0, 8))); - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<9>(imm)), 32); + tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant( 0,8))); + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); tu.close_scope(); auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 75); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,75); return returnValue; } - + /* instruction 76: C__BNEZ */ - compile_ret_t __c__bnez(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__bnez(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__BNEZ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 76); + vm_base::gen_sync(tu, PRE_SYNC,76); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) | - (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs1 + 8 + traits::X0, 0), tu.constant(0, 8))); - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<9>(imm)), 32); + tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant( 0,8))); + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); tu.close_scope(); auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 76); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,76); return returnValue; } - + /* instruction 77: C__SLLI */ - compile_ret_t __c__slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 77); + vm_base::gen_sync(tu, PRE_SYNC,77); uint64_t PC = pc.val; - uint8_t nzuimm = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t nzuimm = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"), fmt::arg("rs1", name(rs1)), - fmt::arg("nzuimm", nzuimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rs1 != 0) { - tu.store(rs1 + traits::X0, tu.shl(tu.load(rs1 + traits::X0, 0), tu.constant(nzuimm, 8))); - } + if(rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rs1!= 0) { + tu.store(rs1 + traits::X0, + tu.shl( + tu.load(rs1+ traits::X0, 0), + tu.constant(nzuimm,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 77); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,77); return returnValue; } - + /* instruction 78: C__LWSP */ - compile_ret_t __c__lwsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__lwsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__LWSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 78); + vm_base::gen_sync(tu, PRE_SYNC,78); uint64_t PC = pc.val; - uint8_t uimm = ((bit_sub<2, 2>(instr) << 6) | (bit_sub<4, 3>(instr) << 2) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"), fmt::arg("rd", name(rd)), - fmt::arg("uimm", uimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rd == 0) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto offs = tu.assignment(tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32); - tu.store(rd + traits::X0, tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32), 32, true), 32, false)); + if(rd>=static_cast(traits:: RFS)||rd== 0) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto offs = tu.assignment(tu.ext((tu.add( + tu.load(2+ traits::X0, 0), + tu.constant(uimm,8))),32,false),32); + tu.store(rd + traits::X0, + tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 78); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,78); return returnValue; } - + /* instruction 79: C__MV */ - compile_ret_t __c__mv(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__mv(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__MV_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 79); + vm_base::gen_sync(tu, PRE_SYNC,79); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"), fmt::arg("rd", name(rd)), - fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.load(rs2 + traits::X0, 0)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.load(rs2+ traits::X0, 0)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 79); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,79); return returnValue; } - + /* instruction 80: C__JR */ - compile_ret_t __c__jr(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__jr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__JR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 80); + vm_base::gen_sync(tu, PRE_SYNC,80); uint64_t PC = pc.val; - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"), + fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs1 && rs1 < static_cast(traits::RFS)) { - auto PC_val_v = tu.assignment( - "PC_val", tu.bitwise_and(tu.load(rs1 % static_cast(traits::RFS) + traits::X0, 0), tu.constant(~0x1, 8)), 32); + if(rs1&&rs1(traits:: RFS)) { + auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and( + tu.load(rs1%static_cast(traits:: RFS)+ traits::X0, 0), + tu.constant(~ 0x1,8)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } else { - this->gen_raise_trap(tu, 0, 2); + } + else{ + this->gen_raise_trap(tu, 0, 2); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 80); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,80); return returnValue; } - + /* instruction 81: __reserved_cmv */ - compile_ret_t ____reserved_cmv(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t ____reserved_cmv(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("__reserved_cmv_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 81); + vm_base::gen_sync(tu, PRE_SYNC,81); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "__reserved_cmv"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); this->gen_raise_trap(tu, 0, 2); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 81); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,81); return returnValue; } - + /* instruction 82: C__ADD */ - compile_ret_t __c__add(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__ADD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 82); + vm_base::gen_sync(tu, PRE_SYNC,82); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"), fmt::arg("rd", name(rd)), - fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.add(tu.load(rd + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.add( + tu.load(rd+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 82); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,82); return returnValue; } - + /* instruction 83: C__JALR */ - compile_ret_t __c__jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__JALR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 83); + vm_base::gen_sync(tu, PRE_SYNC,83); uint64_t PC = pc.val; - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"), + fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto new_pc = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); - tu.store(1 + traits::X0, tu.constant((uint32_t)(PC + 2), 32)); - auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(new_pc, tu.constant(~0x1, 8)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + if(rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto new_pc = tu.assignment(tu.load(rs1+ traits::X0, 0),32); + tu.store(1 + traits::X0, + tu.constant((uint32_t)(PC+ 2),32)); + auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and( + new_pc, + tu.constant(~ 0x1,8)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 83); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,83); return returnValue; } - + /* instruction 84: C__EBREAK */ - compile_ret_t __c__ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__EBREAK_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 84); + vm_base::gen_sync(tu, PRE_SYNC,84); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c__ebreak"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 3); + this->gen_raise_trap(tu, 0, 3); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 84); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,84); return returnValue; } - + /* instruction 85: C__SWSP */ - compile_ret_t __c__swsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__swsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SWSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 85); + vm_base::gen_sync(tu, PRE_SYNC,85); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t uimm = ((bit_sub<7, 2>(instr) << 6) | (bit_sub<9, 4>(instr) << 2)); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"), fmt::arg("rs2", name(rs2)), - fmt::arg("uimm", uimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto offs = tu.assignment(tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32); - tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2 + traits::X0, 0), 32, false)); + if(rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto offs = tu.assignment(tu.ext((tu.add( + tu.load(2+ traits::X0, 0), + tu.constant(uimm,8))),32,false),32); + tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2+ traits::X0, 0),32,false)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 85); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,85); return returnValue; } - + /* instruction 86: DII */ - compile_ret_t __dii(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __dii(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DII_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 86); + vm_base::gen_sync(tu, PRE_SYNC,86); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "dii"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 86); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,86); return returnValue; } - + /**************************************************************************** * end opcode definitions ****************************************************************************/ - compile_ret_t illegal_intruction(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) { vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size()); pc = pc + ((instr & 3) == 3 ? 4 : 2); - gen_raise_trap(tu, 0, 2); // illegal instruction trap + gen_raise_trap(tu, 0, 2); // illegal instruction trap vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size()); vm_impl::gen_trap_check(tu); return BRANCH; } + + //decoding functionality - // decoding functionality - - void populate_decoding_tree(decoding_tree_node* root) { - // create submask - for(auto instr : root->instrs) { + void populate_decoding_tree(decoding_tree_node* root){ + //create submask + for(auto instr: root->instrs){ root->submask &= instr.mask; } - // put each instr according to submask&encoding into children - for(auto instr : root->instrs) { + //put each instr according to submask&encoding into children + for(auto instr: root->instrs){ bool foundMatch = false; - for(auto child : root->children) { - // use value as identifying trait - if(child->value == (instr.value & root->submask)) { + for(auto child: root->children){ + //use value as identifying trait + if(child->value == (instr.value&root->submask)){ child->instrs.push_back(instr); foundMatch = true; } } - if(!foundMatch) { - decoding_tree_node* child = new decoding_tree_node(instr.value & root->submask); + if(!foundMatch){ + decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask); child->instrs.push_back(instr); root->children.push_back(child); } } root->instrs.clear(); - // call populate_decoding_tree for all children - if(root->children.size() > 1) - for(auto child : root->children) { - populate_decoding_tree(child); + //call populate_decoding_tree for all children + if(root->children.size() >1) + for(auto child: root->children){ + populate_decoding_tree(child); } - else { - // sort instrs by value of the mask, this works bc we want to have the least restrictive one last - std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), - [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { return instr1.mask > instr2.mask; }); + else{ + //sort instrs by value of the mask, this works bc we want to have the least restrictive one last + std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { + return instr1.mask > instr2.mask; + }); } } - compile_func decode_instr(decoding_tree_node* node, code_word_t word) { - if(!node->children.size()) { - if(node->instrs.size() == 1) - return node->instrs[0].op; - for(auto instr : node->instrs) { - if((instr.mask & word) == instr.value) - return instr.op; + compile_func decode_instr(decoding_tree_node* node, code_word_t word){ + if(!node->children.size()){ + if(node->instrs.size() == 1) return node->instrs[0].op; + for(auto instr : node->instrs){ + if((instr.mask&word) == instr.value) return instr.op; } - } else { - for(auto child : node->children) { - if(child->value == (node->submask & word)) { + } + else{ + for(auto child : node->children){ + if (child->value == (node->submask&word)){ return decode_instr(child, word); - } - } + } + } } return nullptr; } @@ -3273,41 +3571,40 @@ template void debug_fn(CODE_WORD instr) { template vm_impl::vm_impl() { this(new ARCH()); } template -vm_impl::vm_impl(ARCH& core, unsigned core_id, unsigned cluster_id) +vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) : vm_base(core, core_id, cluster_id) { root = new decoding_tree_node(std::numeric_limits::max()); - for(auto instr : instr_descr) { + for(auto instr:instr_descr){ root->instrs.push_back(instr); } populate_decoding_tree(root); } template -std::tuple vm_impl::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, tu_builder& tu) { +std::tuple +vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) { // we fetch at max 4 byte, alignment is 2 - enum { TRAP_ID = 1 << 16 }; + enum {TRAP_ID=1<<16}; code_word_t instr = 0; phys_addr_t paddr(pc); if(this->core.has_mmu()) paddr = this->core.virt2phys(pc); - // TODO: re-add page handling - // if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary - // auto res = this->core.read(paddr, 2, data); - // if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); - // if ((insn & 0x3) == 0x3) { // this is a 32bit instruction - // res = this->core.read(this->core.v2p(pc + 2), 2, data + 2); - // } - // } else { - auto res = this->core.read(paddr, 4, reinterpret_cast(&instr)); - if(res != iss::Ok) - throw trap_access(TRAP_ID, pc.val); - // } - if(instr == 0x0000006f || (instr & 0xffff) == 0xa001) - throw simulation_stopped(0); // 'J 0' or 'C.J 0' + //TODO: re-add page handling +// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary +// auto res = this->core.read(paddr, 2, data); +// if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); +// if ((insn & 0x3) == 0x3) { // this is a 32bit instruction +// res = this->core.read(this->core.v2p(pc + 2), 2, data + 2); +// } +// } else { + auto res = this->core.read(paddr, 4, reinterpret_cast(&instr)); + if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); +// } + if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0' // curr pc on stack ++inst_cnt; auto f = decode_instr(root, instr); - if(f == nullptr) { + if (f == nullptr) { f = &this_class::illegal_intruction; } return (this->*f)(pc, instr, tu); @@ -3324,47 +3621,55 @@ template void vm_impl::gen_leave_trap(tu_builder& tu, unsi tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits::max(), 32)); } -template void vm_impl::gen_wait(tu_builder& tu, unsigned type) {} +template void vm_impl::gen_wait(tu_builder& tu, unsigned type) { +} template void vm_impl::gen_trap_behavior(tu_builder& tu) { tu("trap_entry:"); - this->gen_sync(tu, POST_SYNC, -1); + this->gen_sync(tu, POST_SYNC, -1); tu("enter_trap(core_ptr, *trap_state, *pc, 0);"); - tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits::max(), 32)); + tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits::max(),32)); tu("return *next_pc;"); } } // namespace tgc5c -template <> std::unique_ptr create(arch::tgc5c* core, unsigned short port, bool dump) { +template <> +std::unique_ptr create(arch::tgc5c *core, unsigned short port, bool dump) { auto ret = new tgc5c::vm_impl(*core, dump); - if(port != 0) - debugger::server::run_server(ret, port); + if (port != 0) debugger::server::run_server(ret, port); return std::unique_ptr(ret); } -} // namespace tcc +} // namesapce tcc } // namespace iss +#include #include #include -#include namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("tgc5c|m_p|tcc", - [](unsigned port, void*) -> std::tuple { - auto* cpu = new iss::arch::riscv_hart_m_p(); - auto vm = new tcc::tgc5c::vm_impl(*cpu, false); - if(port != 0) - debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - }), - core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned port, void*) -> std::tuple { - auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto vm = new tcc::tgc5c::vm_impl(*cpu, false); - if(port != 0) - debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - })}; + core_factory::instance().register_creator("tgc5c|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_m_p(); + auto vm = new tcc::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_mu_p(); + auto vm = new tcc::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }) +}; } -} // namespace iss +} +// clang-format on \ No newline at end of file