diff --git a/gen_input/CoreDSL-Instruction-Set-Description b/gen_input/CoreDSL-Instruction-Set-Description
index 8f72c66..d51b3e3 160000
--- a/gen_input/CoreDSL-Instruction-Set-Description
+++ b/gen_input/CoreDSL-Instruction-Set-Description
@@ -1 +1 @@
-Subproject commit 8f72c66a579608bafb7f48e64ed4bb16920e1214
+Subproject commit d51b3e30f5c4b9863411fbecad6ec7e5793f865e
diff --git a/incl/iss/arch/riscv_hart_m_p.h b/incl/iss/arch/riscv_hart_m_p.h
index d13d42f..3edb52d 100644
--- a/incl/iss/arch/riscv_hart_m_p.h
+++ b/incl/iss/arch/riscv_hart_m_p.h
@@ -421,7 +421,7 @@ private:
     iss::status write_ip(unsigned addr, reg_t val);
     iss::status read_hartid(unsigned addr, reg_t &val);
 
-    reg_t mhartid_reg{0xF};
+    reg_t mhartid_reg{0x0};
     std::function<iss::status(phys_addr_t, unsigned, uint8_t *const)>mem_read_cb;
     std::function<iss::status(phys_addr_t, unsigned, const uint8_t *const)> mem_write_cb;
 
diff --git a/src/vm/interp/vm_tgf_c.cpp b/src/vm/interp/vm_tgf_c.cpp
index 5109b91..832d391 100644
--- a/src/vm/interp/vm_tgf_c.cpp
+++ b/src/vm/interp/vm_tgf_c.cpp
@@ -587,7 +587,7 @@ private:
         uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
         *NEXT_PC = *PC + 4;
         // execute instruction
-        if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); 
+        if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); 
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6);
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
@@ -620,7 +620,7 @@ private:
         uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
         *NEXT_PC = *PC + 4;
         // execute instruction
-        if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); 
+        if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm); 
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7);
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
@@ -1084,7 +1084,7 @@ private:
         uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
         *NEXT_PC = *PC + 4;
         // execute instruction
-        if(rd !=  0) *(X+rd) = *(X+rs1) < imm?  1 :  0; 
+        if(rd !=  0) *(X+rd) = *(X+rs1) < (int16_t)sext<12>(imm)?  1 :  0; 
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 20);
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
@@ -1258,7 +1258,7 @@ private:
         	raise(0, 0);
         }
         else {
-        	if(rd !=  0) *(X+rd) = ((uint8_t)*(X+rs1)) >> shamt; 
+        	if(rd !=  0) *(X+rd) = *(X+rs1) >> shamt; 
         }
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 25);
@@ -1296,7 +1296,7 @@ private:
         	raise(0, 0);
         }
         else {
-        	if(rd !=  0) *(X+rd) = *(X+rs1) >> shamt; 
+        	if(rd !=  0) *(X+rd) = (int32_t)*(X+rs1) >> shamt; 
         }
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 26);
@@ -1429,7 +1429,7 @@ private:
         uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
         *NEXT_PC = *PC + 4;
         // execute instruction
-        if(rd !=  0) *(X+rd) = *(X+rs1) < *(X+rs2)?  1 :  0; 
+        if(rd !=  0) *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)?  1 :  0; 
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 30);
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
@@ -1528,7 +1528,7 @@ private:
         uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
         *NEXT_PC = *PC + 4;
         // execute instruction
-        if(rd !=  0) *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1)); 
+        if(rd !=  0) *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); 
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 33);
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
@@ -1561,7 +1561,7 @@ private:
         uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
         *NEXT_PC = *PC + 4;
         // execute instruction
-        if(rd !=  0) *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); 
+        if(rd !=  0) *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); 
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 34);
         auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);