diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h index 6093909..079e320 100644 --- a/src/iss/arch/riscv_hart_common.h +++ b/src/iss/arch/riscv_hart_common.h @@ -36,11 +36,14 @@ #define _RISCV_HART_COMMON #include "iss/vm_types.h" +#include #include #include #include #include #include +#include +#include #include #include #include @@ -56,8 +59,6 @@ namespace iss { namespace arch { -enum { tohost_dflt = 0xF0001000, fromhost_dflt = 0xF0001040 }; - enum features_e { FEAT_NONE, FEAT_PMP = 1, FEAT_EXT_N = 2, FEAT_CLIC = 4, FEAT_DEBUG = 8, FEAT_TCM = 16 }; enum riscv_csr { @@ -316,8 +317,8 @@ struct riscv_hart_common { ~riscv_hart_common(){}; std::unordered_map symbol_table; uint64_t entry_address{0}; - uint64_t tohost = tohost_dflt; - uint64_t fromhost = fromhost_dflt; + uint64_t tohost = std::numeric_limits::max(); + uint64_t fromhost = std::numeric_limits::max(); bool read_elf_file(std::string name, uint8_t expected_elf_class, std::function cb) { @@ -365,11 +366,10 @@ struct riscv_hart_common { } try { tohost = symbol_table.at("tohost"); - try { - fromhost = symbol_table.at("fromhost"); - } catch(std::out_of_range& e) { - fromhost = tohost + 0x40; - } + } catch(std::out_of_range& e) { + } + try { + fromhost = symbol_table.at("fromhost"); } catch(std::out_of_range& e) { } } @@ -377,6 +377,36 @@ struct riscv_hart_common { } return false; }; + iss::status execute_sys_write(arch_if* aif, const std::array& loaded_payload, unsigned mem_type) { + std::stringstream io_buf; + uint64_t fd = loaded_payload[1]; + uint64_t buf_ptr = loaded_payload[2]; + uint64_t len = loaded_payload[3]; + std::vector buf(len); + if(aif->read(address_type::PHYSICAL, access_type::DEBUG_READ, mem_type, buf_ptr, len, reinterpret_cast(buf.data()))) { + CPPLOG(ERR) << "SYS_WRITE buffer read went wrong"; + return iss::Err; + } + // we disregard the fd and just log to stdout + for(size_t i = 0; i < len; i++) { + if(buf[i] == '\n') { + CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'"; + io_buf.str(""); + } else + io_buf << buf[i]; + } + if(io_buf.str().length()) { + CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'"; + } + // Not sure what the correct return value should be + uint8_t ret_val = 1; + if(fromhost != std::numeric_limits::max()) + if(aif->write(address_type::PHYSICAL, access_type::DEBUG_WRITE, mem_type, fromhost, 1, &ret_val)) { + CPPLOG(ERR) << "Fromhost write went wrong"; + return iss::Err; + } + return iss::Ok; + } }; } // namespace arch diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index b50da48..7476c7c 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -41,7 +41,11 @@ #include "iss/vm_if.h" #include "iss/vm_types.h" #include "riscv_hart_common.h" +#include "util/logging.h" +#include +#include #include +#include #include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY @@ -344,7 +348,6 @@ protected: int64_t instret_offset{0}; uint64_t minstret_csr{0}; reg_t fault_data; - bool tohost_lower_written = false; riscv_instrumentation_if instr_if; semihosting_cb_t semihosting_cb; @@ -354,7 +357,6 @@ protected: using csr_page_type = typename csr_type::page_type; mem_type mem; csr_type csr; - std::stringstream uart_buf; std::unordered_map ptw; std::unordered_map atomic_reservation; std::unordered_map csr_rd_cb; @@ -446,7 +448,6 @@ riscv_hart_m_p::riscv_hart_m_p(feature_config cfg) csr[marchid] = traits::MARCHID_VAL; csr[mimpid] = 1; - uart_buf.str(""); if(traits::FLEN > 0) { csr_rd_cb[fcsr] = &this_class::read_fcsr; csr_wr_cb[fcsr] = &this_class::write_fcsr; @@ -610,7 +611,7 @@ iss::status riscv_hart_m_p::read(const address_type type, co try { switch(space) { case traits::MEM: { - auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : length; + auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : std::min(length, sizeof(reg_t)); if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) { fault_data = addr; if(is_debug(access)) @@ -720,7 +721,8 @@ iss::status riscv_hart_m_p::write(const address_type type, c return iss::Err; } try { - if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) { + auto alignment = std::min(length, sizeof(reg_t)); + if(length > 1 && (addr & (alignment - 1)) && !is_debug(access)) { this->reg.trap_state = (1UL << 31) | 6 << 16; fault_data = addr; return iss::Err; @@ -740,7 +742,7 @@ iss::status riscv_hart_m_p::write(const address_type type, c } else { res = write_mem(phys_addr, length, data); } - if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) { + if(unlikely(res != iss::Ok && !is_debug(access))) { this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault) fault_data = addr; } @@ -750,38 +752,6 @@ iss::status riscv_hart_m_p::write(const address_type type, c fault_data = ta.addr; return iss::Err; } - - if((addr + length) > mem.size()) - return iss::Err; - switch(addr) { - case 0x10013000: // UART0 base, TXFIFO reg - case 0x10023000: // UART1 base, TXFIFO reg - uart_buf << (char)data[0]; - if(((char)data[0]) == '\n' || data[0] == 0) { - std::cout << uart_buf.str(); - uart_buf.str(""); - } - return iss::Ok; - case 0x10008000: { // HFROSC base, hfrosccfg reg - auto& p = mem(addr / mem.page_size); - auto offs = addr & mem.page_addr_mask; - std::copy(data, data + length, p.data() + offs); - auto& x = *(p.data() + offs + 3); - if(x & 0x40) - x |= 0x80; // hfroscrdy = 1 if hfroscen==1 - return iss::Ok; - } - case 0x10008008: { // HFROSC base, pllcfg reg - auto& p = mem(addr / mem.page_size); - auto offs = addr & mem.page_addr_mask; - std::copy(data, data + length, p.data() + offs); - auto& x = *(p.data() + offs + 3); - x |= 0x80; // set pll lock upon writing - return iss::Ok; - } break; - default: { - } - } } break; case traits::CSR: { if(length != sizeof(reg_t)) @@ -1094,59 +1064,51 @@ iss::status riscv_hart_m_p::read_mem(phys_addr_t paddr, unsi template iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { - switch(paddr.val) { - // TODO remove UART, Peripherals should not be part of the ISS - case 0xFFFF0000: // UART0 base, TXFIFO reg - if(((char)data[0]) == '\n' || data[0] == 0) { - CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; - uart_buf.str(""); - } else if(((char)data[0]) != '\r') - uart_buf << (char)data[0]; - break; - default: { - mem_type::page_type& p = mem(paddr.val / mem.page_size); - std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); - // tohost handling in case of riscv-test - if(paddr.access && iss::access_type::FUNC) { - auto tohost_upper = - (traits::XLEN == 32 && paddr.val == (tohost + 4)) || (traits::XLEN == 64 && paddr.val == tohost); - auto tohost_lower = (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); - if(tohost_lower || tohost_upper) { - uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); - // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write - if(tohost_upper && (tohost_lower || tohost_lower_written)) { - switch(hostvar >> 48) { - case 0: - if(hostvar != 0x1) { - CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; - } else { - CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; - } - this->reg.trap_state = std::numeric_limits::max(); - this->interrupt_sim = hostvar; - break; - case 0x0101: { - char c = static_cast(hostvar & 0xff); - if(c == '\n' || c == 0) { - CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'"; - uart_buf.str(""); - } else - uart_buf << c; - } break; - default: - break; - } - tohost_lower_written = false; - } else if(tohost_lower) - tohost_lower_written = true; - } else if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { - uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); - *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; + mem_type::page_type& p = mem(paddr.val / mem.page_size); + std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); + // tohost handling in case of riscv-test + // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754: + if(paddr.access && iss::access_type::FUNC) { + if(paddr.val == tohost) { + reg_t cur_data = *reinterpret_cast(data); + // Extract Device (bits 63:56) + uint8_t device = traits::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF; + // Extract Command (bits 55:48) + uint8_t command = traits::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF; + // Extract payload (bits 47:0) + uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL; + if(payload_addr & 1) { + CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr + << "), stopping simulation"; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; + return iss::Ok; + } else if(device == 0 && command == 0) { + std::array loaded_payload; + if(read(address_type::PHYSICAL, access_type::DEBUG_READ, traits::MEM, payload_addr, 8 * sizeof(uint64_t), + reinterpret_cast(loaded_payload.data())) == iss::Err) + CPPLOG(ERR) << "Syscall read went wrong"; + uint64_t syscall_num = loaded_payload.at(0); + if(syscall_num == 64) { // SYS_WRITE + return execute_sys_write(this, loaded_payload, traits::MEM); + } else { + CPPLOG(ERR) << "tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num + << ") not implemented"; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; + return iss::Ok; + } + } else { + CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; + return iss::Ok; } } - } + if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { + uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); + *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; + } } return iss::Ok; } diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index 41bc035..a6b23ac 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -41,6 +41,11 @@ #include "iss/vm_if.h" #include "iss/vm_types.h" #include "riscv_hart_common.h" +#include "util/logging.h" +#include +#include +#include +#include #include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY @@ -393,7 +398,6 @@ protected: uint64_t minstret_csr{0}; reg_t fault_data; std::array vm; - bool tohost_lower_written = false; riscv_instrumentation_if instr_if; std::function semihosting_cb; @@ -404,7 +408,6 @@ protected: mem_type mem; csr_type csr; void update_vm_info(); - std::stringstream uart_buf; std::unordered_map ptw; std::unordered_map atomic_reservation; std::unordered_map csr_rd_cb; @@ -459,7 +462,6 @@ riscv_hart_msu_vp::riscv_hart_msu_vp() csr[marchid] = traits::MARCHID_VAL; csr[mimpid] = 1; - uart_buf.str(""); for(unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr) { csr_rd_cb[addr] = &this_class::read_null; csr_wr_cb[addr] = &this_class::write_csr_reg; @@ -580,7 +582,7 @@ iss::status riscv_hart_msu_vp::read(const address_type type, const access_ try { switch(space) { case traits::MEM: { - auto alignment = is_fetch(access) ? (traits::MISA_VAL & 0x100 ? 2 : 4) : length; + auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : std::min(length, sizeof(reg_t)); if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) { fault_data = addr; if(access && iss::access_type::DEBUG) @@ -699,6 +701,7 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access } phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr}); try { + // TODO: There is no check for alignment if(unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp); if(vm.levels != 0) { // VM is active @@ -721,40 +724,6 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access fault_data = ta.addr; return iss::Err; } - - if((paddr.val + length) > mem.size()) - return iss::Err; - switch(paddr.val) { - case 0x10013000: // UART0 base, TXFIFO reg - case 0x10023000: // UART1 base, TXFIFO reg - uart_buf << (char)data[0]; - if(((char)data[0]) == '\n' || data[0] == 0) { - // CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send - // '"<::CSR: { if(length != sizeof(reg_t)) @@ -1024,61 +993,51 @@ template iss::status riscv_hart_msu_vp::read_mem(phys_addr } template iss::status riscv_hart_msu_vp::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { - switch(paddr.val) { - case 0xFFFF0000: // UART0 base, TXFIFO reg - if(((char)data[0]) == '\n' || data[0] == 0) { - CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; - uart_buf.str(""); - } else if(((char)data[0]) != '\r') - uart_buf << (char)data[0]; - break; - default: { - mem_type::page_type& p = mem(paddr.val / mem.page_size); - std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); - // tohost handling in case of riscv-test - if(paddr.access && iss::access_type::FUNC) { - auto tohost_upper = - (traits::XLEN == 32 && paddr.val == (tohost + 4)) || (traits::XLEN == 64 && paddr.val == tohost); - auto tohost_lower = (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); - if(tohost_lower || tohost_upper) { - uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); - // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write - if(tohost_upper && (tohost_lower || tohost_lower_written)) { - switch(hostvar >> 48) { - case 0: - if(hostvar != 0x1) { - CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; - } else { - CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; - } - this->reg.trap_state = std::numeric_limits::max(); - this->interrupt_sim = hostvar; -#ifndef WITH_TCC - throw(iss::simulation_stopped(hostvar)); -#endif - break; - case 0x0101: { - char c = static_cast(hostvar & 0xff); - if(c == '\n' || c == 0) { - CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'"; - uart_buf.str(""); - } else - uart_buf << c; - } break; - default: - break; - } - tohost_lower_written = false; - } else if(tohost_lower) - tohost_lower_written = true; - } else if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { - uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); - *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; + mem_type::page_type& p = mem(paddr.val / mem.page_size); + std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); + // tohost handling in case of riscv-test + // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754: + if(paddr.access && iss::access_type::FUNC) { + if(paddr.val == tohost) { + reg_t cur_data = *reinterpret_cast(data); + // Extract Device (bits 63:56) + uint8_t device = traits::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF; + // Extract Command (bits 55:48) + uint8_t command = traits::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF; + // Extract payload (bits 47:0) + uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL; + if(payload_addr & 1) { + CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr + << "), stopping simulation"; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; + return iss::Ok; + } else if(device == 0 && command == 0) { + std::array loaded_payload; + if(read(address_type::PHYSICAL, access_type::DEBUG_READ, traits::MEM, payload_addr, 8 * sizeof(uint64_t), + reinterpret_cast(loaded_payload.data())) == iss::Err) + CPPLOG(ERR) << "Syscall read went wrong"; + uint64_t syscall_num = loaded_payload.at(0); + if(syscall_num == 64) { // SYS_WRITE + return execute_sys_write(this, loaded_payload, traits::MEM); + } else { + CPPLOG(ERR) << "tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num + << ") not implemented"; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; + return iss::Ok; + } + } else { + CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; + return iss::Ok; } } - } + if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { + uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); + *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; + } } return iss::Ok; } diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 8620117..4eece12 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -41,6 +41,11 @@ #include "iss/vm_if.h" #include "iss/vm_types.h" #include "riscv_hart_common.h" +#include "util/logging.h" +#include +#include +#include +#include #include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY @@ -370,7 +375,6 @@ protected: int64_t instret_offset{0}; uint64_t minstret_csr{0}; reg_t fault_data; - bool tohost_lower_written = false; riscv_instrumentation_if instr_if; semihosting_cb_t semihosting_cb; @@ -380,7 +384,6 @@ protected: using csr_page_type = typename csr_type::page_type; mem_type mem; csr_type csr; - std::stringstream uart_buf; std::unordered_map ptw; std::unordered_map atomic_reservation; std::unordered_map csr_rd_cb; @@ -475,7 +478,6 @@ riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg) csr[marchid] = traits::MARCHID_VAL; csr[mimpid] = 1; - uart_buf.str(""); if(traits::FLEN > 0) { csr_rd_cb[fcsr] = &this_class::read_fcsr; csr_wr_cb[fcsr] = &this_class::write_fcsr; @@ -783,7 +785,7 @@ iss::status riscv_hart_mu_p::read(const address_type type, c return iss::Err; } } - auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : length; + auto alignment = is_fetch(access) ? (has_compressed() ? 2 : 4) : std::min(length, sizeof(reg_t)); if(unlikely(is_fetch(access) && (addr & (alignment - 1)))) { fault_data = addr; if(is_debug(access)) @@ -902,7 +904,8 @@ iss::status riscv_hart_mu_p::write(const address_type type, return iss::Err; } try { - if(length > 1 && (addr & (length - 1)) && (access & access_type::DEBUG) != access_type::DEBUG) { + auto alignment = std::min(length, sizeof(reg_t)); + if(length > 1 && (addr & (alignment - 1)) && !is_debug(access)) { this->reg.trap_state = (1UL << 31) | 6 << 16; fault_data = addr; return iss::Err; @@ -932,38 +935,6 @@ iss::status riscv_hart_mu_p::write(const address_type type, fault_data = ta.addr; return iss::Err; } - - if((addr + length) > mem.size()) - return iss::Err; - switch(addr) { - case 0x10013000: // UART0 base, TXFIFO reg - case 0x10023000: // UART1 base, TXFIFO reg - uart_buf << (char)data[0]; - if(((char)data[0]) == '\n' || data[0] == 0) { - std::cout << uart_buf.str(); - uart_buf.str(""); - } - return iss::Ok; - case 0x10008000: { // HFROSC base, hfrosccfg reg - auto& p = mem(addr / mem.page_size); - auto offs = addr & mem.page_addr_mask; - std::copy(data, data + length, p.data() + offs); - auto& x = *(p.data() + offs + 3); - if(x & 0x40) - x |= 0x80; // hfroscrdy = 1 if hfroscen==1 - return iss::Ok; - } - case 0x10008008: { // HFROSC base, pllcfg reg - auto& p = mem(addr / mem.page_size); - auto offs = addr & mem.page_addr_mask; - std::copy(data, data + length, p.data() + offs); - auto& x = *(p.data() + offs + 3); - x |= 0x80; // set pll lock upon writing - return iss::Ok; - } break; - default: { - } - } } break; case traits::CSR: { if(length != sizeof(reg_t)) @@ -1312,65 +1283,53 @@ iss::status riscv_hart_mu_p::read_mem(phys_addr_t paddr, uns } return iss::Ok; } - template iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { - switch(paddr.val) { - // TODO remove UART, Peripherals should not be part of the ISS - case 0xFFFF0000: // UART0 base, TXFIFO reg - if(((char)data[0]) == '\n' || data[0] == 0) { - CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; - uart_buf.str(""); - } else if(((char)data[0]) != '\r') - uart_buf << (char)data[0]; - break; - default: { - mem_type::page_type& p = mem(paddr.val / mem.page_size); - std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); - // tohost handling in case of riscv-test - if(paddr.access && iss::access_type::FUNC) { - auto tohost_upper = - (traits::XLEN == 32 && paddr.val == (tohost + 4)) || (traits::XLEN == 64 && paddr.val == tohost); - auto tohost_lower = (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); - if(tohost_lower || tohost_upper) { - uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); - // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write - if(tohost_upper && (tohost_lower || tohost_lower_written)) { - switch(hostvar >> 48) { - case 0: - if(hostvar != 0x1) { - CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; - } else { - CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; - } - this->reg.trap_state = std::numeric_limits::max(); - this->interrupt_sim = hostvar; -#ifndef WITH_TCC - throw(iss::simulation_stopped(hostvar)); -#endif - break; - case 0x0101: { - char c = static_cast(hostvar & 0xff); - if(c == '\n' || c == 0) { - CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'"; - uart_buf.str(""); - } else - uart_buf << c; - } break; - default: - break; - } - tohost_lower_written = false; - } else if(tohost_lower) - tohost_lower_written = true; - } else if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { - uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); - *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; + mem_type::page_type& p = mem(paddr.val / mem.page_size); + std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); + // tohost handling in case of riscv-test + // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754: + if(paddr.access && iss::access_type::FUNC) { + if(paddr.val == tohost) { + reg_t cur_data = *reinterpret_cast(data); + // Extract Device (bits 63:56) + uint8_t device = traits::XLEN == 32 ? 0 : (cur_data >> 56) & 0xFF; + // Extract Command (bits 55:48) + uint8_t command = traits::XLEN == 32 ? 0 : (cur_data >> 48) & 0xFF; + // Extract payload (bits 47:0) + uint64_t payload_addr = cur_data & 0xFFFFFFFFFFFFULL; + if(payload_addr & 1) { + CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr + << "), stopping simulation"; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; + return iss::Ok; + } else if(device == 0 && command == 0) { + std::array loaded_payload; + if(read(address_type::PHYSICAL, access_type::DEBUG_READ, traits::MEM, payload_addr, 8 * sizeof(uint64_t), + reinterpret_cast(loaded_payload.data())) == iss::Err) + CPPLOG(ERR) << "Syscall read went wrong"; + uint64_t syscall_num = loaded_payload.at(0); + if(syscall_num == 64) { // SYS_WRITE + return execute_sys_write(this, loaded_payload, traits::MEM); + } else { + CPPLOG(ERR) << "tohost syscall with number 0x" << std::hex << syscall_num << std::dec << " (" << syscall_num + << ") not implemented"; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; + return iss::Ok; + } + } else { + CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command; + this->reg.trap_state = std::numeric_limits::max(); + this->interrupt_sim = payload_addr; + return iss::Ok; } } - } + if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { + uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); + *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; + } } return iss::Ok; }