diff --git a/.cproject b/.cproject
index 2e0c551..ab7da03 100644
--- a/.cproject
+++ b/.cproject
@@ -82,6 +82,87 @@
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@@ -96,6 +177,8 @@
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diff --git a/dbt-core b/dbt-core
index c3b645f..a0baf6e 160000
--- a/dbt-core
+++ b/dbt-core
@@ -1 +1 @@
-Subproject commit c3b645fb38aee24a3348c41ebc68f4c305ea768a
+Subproject commit a0baf6ef660c50a93d079f5208e9d1c354eb304f
diff --git a/riscv/incl/iss/debugger/riscv_target_adapter.h b/riscv/incl/iss/debugger/riscv_target_adapter.h
index 1346c8a..1ec2f60 100644
--- a/riscv/incl/iss/debugger/riscv_target_adapter.h
+++ b/riscv/incl/iss/debugger/riscv_target_adapter.h
@@ -94,7 +94,9 @@ template struct riscv_target_adapter : public target_adapter_bas
status remove_break(int type, uint64_t addr, unsigned int length) override;
- status resume_from_addr(bool step, int sig, uint64_t addr) override;
+ status resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread, std::function stop_callback) override;
+
+ status target_xml_query(std::string& out_buf) override;
protected:
static inline constexpr addr_t map_addr(const addr_t &i) { return i; }
@@ -157,6 +159,11 @@ status riscv_target_adapter::read_registers(std::vector &data, st
data.push_back(*(reg_base + offset + j));
avail.push_back(0xff);
}
+// if(arch::traits::XLEN < 64)
+// for(unsigned j=0; j<4; ++j){
+// data.push_back(0);
+// avail.push_back(0xff);
+// }
}
// work around fill with F type registers
if (arch::traits::NUM_REGS < 65) {
@@ -166,6 +173,11 @@ status riscv_target_adapter::read_registers(std::vector &data, st
data.push_back(0x0);
avail.push_back(0x00);
}
+// if(arch::traits::XLEN < 64)
+// for(unsigned j=0; j<4; ++j){
+// data.push_back(0x0);
+// avail.push_back(0x00);
+// }
}
}
return Ok;
@@ -292,10 +304,10 @@ template status riscv_target_adapter::add_break(int type,
template status riscv_target_adapter::remove_break(int type, uint64_t addr, unsigned int length) {
auto saddr = map_addr({iss::CODE, iss::PHYSICAL, addr});
unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
- // TODO: check length of addr range
if (handle) {
LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val
<< std::dec;
+ // TODO: check length of addr range
target_adapter_base::bp_lut.removeEntry(handle);
LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
return Ok;
@@ -304,13 +316,102 @@ template status riscv_target_adapter::remove_break(int typ
return Err;
}
-template status riscv_target_adapter::resume_from_addr(bool step, int sig, uint64_t addr) {
+template status riscv_target_adapter::resume_from_addr(bool step, int sig, uint64_t addr, rp_thread_ref thread,
+ std::function stop_callback) {
unsigned reg_no = arch::traits::PC;
std::vector data(8);
*(reinterpret_cast(&data[0])) = addr;
core->set_reg(reg_no, data);
- return resume_from_current(step, sig);
+ return resume_from_current(step, sig, thread, stop_callback);
}
+template status riscv_target_adapter::target_xml_query(std::string& out_buf) {
+ const std::string res{
+ ""
+"riscv:rv32"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+//" \n"
+""};
+ out_buf=res;
+ return Ok;
+}
+
+/*
+ *
+
+
+
+ riscv:rv32
+
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+ */
}
}
diff --git a/riscv/src/internal/vm_riscv.in.cpp b/riscv/src/internal/vm_riscv.in.cpp
index a5d6057..ebe0844 100644
--- a/riscv/src/internal/vm_riscv.in.cpp
+++ b/riscv/src/internal/vm_riscv.in.cpp
@@ -149,7 +149,7 @@ protected:
// some compile time constants
enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
- enum { LUT_SIZE = 1 << bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << bit_count(EXTR_MASK16) };
+ enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
using this_class = vm_impl;
using compile_func = std::tuple (this_class::*)(virt_addr_t &pc,
diff --git a/riscv/src/internal/vm_rv32imac.cpp b/riscv/src/internal/vm_rv32imac.cpp
index 088d903..79e32ae 100644
--- a/riscv/src/internal/vm_rv32imac.cpp
+++ b/riscv/src/internal/vm_rv32imac.cpp
@@ -149,7 +149,7 @@ protected:
// some compile time constants
enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
- enum { LUT_SIZE = 1 << bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << bit_count(EXTR_MASK16) };
+ enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
using this_class = vm_impl;
using compile_func = std::tuple (this_class::*)(virt_addr_t &pc,
diff --git a/riscv/src/internal/vm_rv64ia.cpp b/riscv/src/internal/vm_rv64ia.cpp
index dc6bffa..b9ad8e4 100644
--- a/riscv/src/internal/vm_rv64ia.cpp
+++ b/riscv/src/internal/vm_rv64ia.cpp
@@ -149,7 +149,7 @@ protected:
// some compile time constants
enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
- enum { LUT_SIZE = 1 << bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << bit_count(EXTR_MASK16) };
+ enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
using this_class = vm_impl;
using compile_func = std::tuple (this_class::*)(virt_addr_t &pc,
diff --git a/sc-components b/sc-components
index 5a2b962..27001d6 160000
--- a/sc-components
+++ b/sc-components
@@ -1 +1 @@
-Subproject commit 5a2b9622e59f8a3df846a7df2fd625681dfa52bf
+Subproject commit 27001d6707071fe4727c698c0f777d587dd99a60