From f096b15dbdf7413984430c70da305c9752d86db7 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sun, 19 Jun 2022 12:45:34 +0200 Subject: [PATCH] factors decoder into separate component --- CMakeLists.txt | 3 +- gen_input/templates/CORENAME.h.gtl | 3 + gen_input/templates/CORENAME_decoder.cpp.gtl | 86 ++++ gen_input/templates/CORENAME_instr.yaml.gtl | 3 +- gen_input/templates/interp/CORENAME.cpp.gtl | 92 +--- src/iss/arch/tgc_c.h | 3 + src/iss/arch/tgc_c_decoder.cpp | 175 +++++++ src/vm/interp/vm_tgc_c.cpp | 509 +++++++------------ 8 files changed, 455 insertions(+), 419 deletions(-) create mode 100644 gen_input/templates/CORENAME_decoder.cpp.gtl create mode 100644 src/iss/arch/tgc_c_decoder.cpp diff --git a/CMakeLists.txt b/CMakeLists.txt index f84ed5f..5ae4f32 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -36,7 +36,8 @@ FILE(GLOB GEN_SOURCES set(LIB_SOURCES src/iss/plugin/instruction_count.cpp - src/iss/arch/tgc_c.cpp + src/iss/arch/tgc_c.cpp + src/iss/arch/tgc_c_decoder.cpp src/vm/interp/vm_tgc_c.cpp src/vm/fp_functions.cpp ${GEN_SOURCES} diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl index 1765fde..bd42664 100644 --- a/gen_input/templates/CORENAME.h.gtl +++ b/gen_input/templates/CORENAME.h.gtl @@ -69,6 +69,7 @@ def getCString(def val){ #include #include #include +#include #include namespace iss { @@ -120,6 +121,8 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { ${instr.instruction.name} = ${index},<%}%> MAX_OPCODE }; + + static std::unique_ptr> get_decoder(); }; struct ${coreDef.name.toLowerCase()}: public arch_if { diff --git a/gen_input/templates/CORENAME_decoder.cpp.gtl b/gen_input/templates/CORENAME_decoder.cpp.gtl new file mode 100644 index 0000000..d6b7032 --- /dev/null +++ b/gen_input/templates/CORENAME_decoder.cpp.gtl @@ -0,0 +1,86 @@ +#include "${coreDef.name.toLowerCase()}.h" +#include +#include +#include +#include + +namespace iss { +namespace arch { +namespace { +// according to +// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation +#ifdef __GCC__ +constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); } +#elif __cplusplus < 201402L +constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); } +constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; } +#else +constexpr size_t bit_count(uint32_t u) { + size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); + return ((uCount + (uCount >> 3)) & 030707070707) % 63; +} +#endif + +using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e; + +/**************************************************************************** + * start opcode definitions + ****************************************************************************/ +struct instruction_desriptor { + size_t length; + uint32_t value; + uint32_t mask; + opcode_e op; +}; + +const std::array instr_descr = {{ + /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %> + {${instr.length}, ${instr.encoding}, ${instr.mask}, opcode_e::${instr.instruction.name}},<%}%> +}}; + +} + +template<> +struct instruction_decoder<${coreDef.name.toLowerCase()}> { + using opcode_e = traits<${coreDef.name.toLowerCase()}>::opcode_e; + using code_word_t=traits<${coreDef.name.toLowerCase()}>::code_word_t; + + struct instruction_pattern { + uint32_t value; + uint32_t mask; + opcode_e id; + }; + + std::array, 4> qlut; + + template + unsigned decode_instruction(T); + + instruction_decoder() { + for (auto instr : instr_descr) { + auto quadrant = instr.value & 0x3; + qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op}); + } + for(auto& lut: qlut){ + std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){ + return bit_count(a.mask) > bit_count(b.mask); + }); + } + } +}; + +template<> +unsigned instruction_decoder<${coreDef.name.toLowerCase()}>::decode_instruction::code_word_t>(traits<${coreDef.name.toLowerCase()}>::code_word_t instr){ + auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){ + return !((instr&e.mask) ^ e.value ); + }); + return static_cast(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE); +} + + +std::unique_ptr> traits<${coreDef.name.toLowerCase()}>::get_decoder(){ + return std::make_unique>(); +} + +} +} diff --git a/gen_input/templates/CORENAME_instr.yaml.gtl b/gen_input/templates/CORENAME_instr.yaml.gtl index 122be5e..9b29705 100644 --- a/gen_input/templates/CORENAME_instr.yaml.gtl +++ b/gen_input/templates/CORENAME_instr.yaml.gtl @@ -12,5 +12,6 @@ ${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %> - ${it.instruction.name}: encoding: ${it.encoding} - mask: ${it.mask}<%}}%> + mask: ${it.mask}<%if(it.attributes.size) {%> + attributes: ${it.attributes}<%}}}%> diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 56dc1a1..1566f55 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -73,6 +73,7 @@ public: using addr_t = typename super::addr_t; using reg_t = typename traits::reg_t; using mem_type_e = typename traits::mem_type_e; + using opcode_e = typename traits::opcode_e; vm_impl(); @@ -94,7 +95,6 @@ protected: inline const char *name(size_t index){return traits::reg_aliases.at(index);} - typename arch::traits::opcode_e decode_inst_id(code_word_t instr); virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override; // some compile time constants @@ -111,13 +111,7 @@ protected: std::array lut_00, lut_01, lut_10; std::array lut_11; - struct instruction_pattern { - uint32_t value; - uint32_t mask; - typename arch::traits::opcode_e id; - }; - - std::array, 4> qlut; + std::unique_ptr> decoder; inline void raise(uint16_t trap_id, uint16_t cause){ auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id; @@ -139,42 +133,7 @@ protected: template T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;} - inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){ - auto ret = super::template read_mem(space, addr); - if(this->core.trap_state) throw 0; - return ret; - } - inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){ - auto ret = super::template read_mem(space, addr); - if(this->core.trap_state) throw 0; - return ret; - } - inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){ - auto ret = super::template read_mem(space, addr); - if(this->core.trap_state) throw 0; - return ret; - } - inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){ - auto ret = super::template read_mem(space, addr); - if(this->core.trap_state) throw 0; - return ret; - } - inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){ - super::write_mem(space, addr, data); - if(this->core.trap_state) throw 0; - } - inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){ - super::write_mem(space, addr, data); - if(this->core.trap_state) throw 0; - } - inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){ - super::write_mem(space, addr, data); - if(this->core.trap_state) throw 0; - } - inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){ - super::write_mem(space, addr, data); - if(this->core.trap_state) throw 0; - } + template::type> inline S sext(U from) { auto mask = (1ULL< <%}%> private: - /**************************************************************************** - * start opcode definitions - ****************************************************************************/ - struct InstructionDesriptor { - size_t length; - uint32_t value; - uint32_t mask; - typename arch::traits::opcode_e op; - }; - - const std::array instr_descr = {{ - /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %> - {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits::opcode_e::${instr.instruction.name}},<%}%> - }}; //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK; iss::status fetch_ins(virt_addr_t pc, uint8_t * data){ @@ -247,16 +192,7 @@ constexpr size_t bit_count(uint32_t u) { template vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) : vm_base(core, core_id, cluster_id) { - unsigned id=0; - for (auto instr : instr_descr) { - auto quadrant = instr.value & 0x3; - qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op}); - } - for(auto& lut: qlut){ - std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){ - return bit_count(a.mask) > bit_count(b.mask); - }); - } + decoder = traits::get_decoder(); } inline bool is_count_limit_enabled(finish_cond_e cond){ @@ -267,19 +203,11 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){ return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF; } -template -typename arch::traits::opcode_e vm_impl::decode_inst_id(code_word_t instr){ - for(auto& e: qlut[instr&0x3]){ - if(!((instr&e.mask) ^ e.value )) return e.id; - } - return arch::traits::opcode_e::MAX_OPCODE; -} - template typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){ auto pc=start; - auto* PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::PC]); - auto* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); + auto* PC = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::PC]); + auto* NEXT_PC = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::NEXT_PC]); auto& trap_state = this->core.trap_state; auto& icount = this->core.icount; auto& cycle = this->core.cycle; @@ -296,11 +224,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if (is_jump_to_self_enabled(cond) && (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' - auto inst_id = decode_inst_id(instr); + auto inst_id = static_cast(decoder->decode_instruction(instr)); // pre execution stuff if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast(inst_id)); switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %> - case arch::traits::opcode_e::${instr.name}: { + case opcode_e::${instr.name}: { <%instr.fields.eachLine{%>${it} <%}%>if(this->disass_enabled){ /* generate console output when executing the command */<%instr.disass.eachLine{%> @@ -308,8 +236,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } // used registers<%instr.usedVariables.each{ k,v-> if(v.isArray) {%> - auto* ${k} = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::${k}0]);<% }else{ %> - auto* ${k} = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::${k}]); + auto* ${k} = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::${k}0]);<% }else{ %> + auto* ${k} = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::${k}]); <%}}%>// calculate next pc value *NEXT_PC = *PC + ${instr.length/8}; // execute instruction<%instr.behavior.eachLine{%> diff --git a/src/iss/arch/tgc_c.h b/src/iss/arch/tgc_c.h index 8e2ae8a..02b09b6 100644 --- a/src/iss/arch/tgc_c.h +++ b/src/iss/arch/tgc_c.h @@ -36,6 +36,7 @@ #include #include #include +#include #include namespace iss { @@ -176,6 +177,8 @@ template <> struct traits { DII = 89, MAX_OPCODE }; + + static std::unique_ptr> get_decoder(); }; struct tgc_c: public arch_if { diff --git a/src/iss/arch/tgc_c_decoder.cpp b/src/iss/arch/tgc_c_decoder.cpp new file mode 100644 index 0000000..3526fda --- /dev/null +++ b/src/iss/arch/tgc_c_decoder.cpp @@ -0,0 +1,175 @@ +#include "tgc_c.h" +#include +#include +#include +#include + +namespace iss { +namespace arch { +namespace { +// according to +// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation +#ifdef __GCC__ +constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); } +#elif __cplusplus < 201402L +constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); } +constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; } +#else +constexpr size_t bit_count(uint32_t u) { + size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); + return ((uCount + (uCount >> 3)) & 030707070707) % 63; +} +#endif + +using opcode_e = traits::opcode_e; + +/**************************************************************************** + * start opcode definitions + ****************************************************************************/ +struct instruction_desriptor { + size_t length; + uint32_t value; + uint32_t mask; + opcode_e op; +}; + +const std::array instr_descr = {{ + /* entries are: size, valid value, valid mask, function ptr */ + {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, opcode_e::LUI}, + {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, opcode_e::AUIPC}, + {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, opcode_e::JAL}, + {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, opcode_e::JALR}, + {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, opcode_e::BEQ}, + {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, opcode_e::BNE}, + {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, opcode_e::BLT}, + {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, opcode_e::BGE}, + {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, opcode_e::BLTU}, + {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, opcode_e::BGEU}, + {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, opcode_e::LB}, + {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, opcode_e::LH}, + {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, opcode_e::LW}, + {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, opcode_e::LBU}, + {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, opcode_e::LHU}, + {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, opcode_e::SB}, + {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, opcode_e::SH}, + {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, opcode_e::SW}, + {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, opcode_e::ADDI}, + {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, opcode_e::SLTI}, + {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, opcode_e::SLTIU}, + {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, opcode_e::XORI}, + {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, opcode_e::ORI}, + {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, opcode_e::ANDI}, + {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, opcode_e::SLLI}, + {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRLI}, + {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, opcode_e::SRAI}, + {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::ADD}, + {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::SUB}, + {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::SLL}, + {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::SLT}, + {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::SLTU}, + {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::XOR}, + {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRL}, + {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::SRA}, + {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::OR}, + {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::AND}, + {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE}, + {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, opcode_e::ECALL}, + {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, opcode_e::EBREAK}, + {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::URET}, + {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::SRET}, + {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::MRET}, + {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, opcode_e::WFI}, + {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, opcode_e::DRET}, + {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRW}, + {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRS}, + {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRC}, + {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRWI}, + {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRSI}, + {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, opcode_e::CSRRCI}, + {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, opcode_e::FENCE_I}, + {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, opcode_e::MUL}, + {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, opcode_e::MULH}, + {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, opcode_e::MULHSU}, + {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, opcode_e::MULHU}, + {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, opcode_e::DIV}, + {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, opcode_e::DIVU}, + {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, opcode_e::REM}, + {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, opcode_e::REMU}, + {16, 0b0000000000000000, 0b1110000000000011, opcode_e::CADDI4SPN}, + {16, 0b0100000000000000, 0b1110000000000011, opcode_e::CLW}, + {16, 0b1100000000000000, 0b1110000000000011, opcode_e::CSW}, + {16, 0b0000000000000001, 0b1110000000000011, opcode_e::CADDI}, + {16, 0b0000000000000001, 0b1110111110000011, opcode_e::CNOP}, + {16, 0b0010000000000001, 0b1110000000000011, opcode_e::CJAL}, + {16, 0b0100000000000001, 0b1110000000000011, opcode_e::CLI}, + {16, 0b0110000000000001, 0b1110000000000011, opcode_e::CLUI}, + {16, 0b0110000100000001, 0b1110111110000011, opcode_e::CADDI16SP}, + {16, 0b0110000000000001, 0b1111000001111111, opcode_e::__reserved_clui}, + {16, 0b1000000000000001, 0b1111110000000011, opcode_e::CSRLI}, + {16, 0b1000010000000001, 0b1111110000000011, opcode_e::CSRAI}, + {16, 0b1000100000000001, 0b1110110000000011, opcode_e::CANDI}, + {16, 0b1000110000000001, 0b1111110001100011, opcode_e::CSUB}, + {16, 0b1000110000100001, 0b1111110001100011, opcode_e::CXOR}, + {16, 0b1000110001000001, 0b1111110001100011, opcode_e::COR}, + {16, 0b1000110001100001, 0b1111110001100011, opcode_e::CAND}, + {16, 0b1010000000000001, 0b1110000000000011, opcode_e::CJ}, + {16, 0b1100000000000001, 0b1110000000000011, opcode_e::CBEQZ}, + {16, 0b1110000000000001, 0b1110000000000011, opcode_e::CBNEZ}, + {16, 0b0000000000000010, 0b1111000000000011, opcode_e::CSLLI}, + {16, 0b0100000000000010, 0b1110000000000011, opcode_e::CLWSP}, + {16, 0b1000000000000010, 0b1111000000000011, opcode_e::CMV}, + {16, 0b1000000000000010, 0b1111000001111111, opcode_e::CJR}, + {16, 0b1000000000000010, 0b1111111111111111, opcode_e::__reserved_cmv}, + {16, 0b1001000000000010, 0b1111000000000011, opcode_e::CADD}, + {16, 0b1001000000000010, 0b1111000001111111, opcode_e::CJALR}, + {16, 0b1001000000000010, 0b1111111111111111, opcode_e::CEBREAK}, + {16, 0b1100000000000010, 0b1110000000000011, opcode_e::CSWSP}, + {16, 0b0000000000000000, 0b1111111111111111, opcode_e::DII}, +}}; + +} + +template<> +struct instruction_decoder { + using opcode_e = traits::opcode_e; + using code_word_t=traits::code_word_t; + + struct instruction_pattern { + uint32_t value; + uint32_t mask; + opcode_e id; + }; + + std::array, 4> qlut; + + template + unsigned decode_instruction(T); + + instruction_decoder() { + for (auto instr : instr_descr) { + auto quadrant = instr.value & 0x3; + qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op}); + } + for(auto& lut: qlut){ + std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){ + return bit_count(a.mask) > bit_count(b.mask); + }); + } + } +}; + +template<> +unsigned instruction_decoder::decode_instruction::code_word_t>(traits::code_word_t instr){ + auto res = std::find_if(std::begin(qlut[instr&0x3]), std::end(qlut[instr&0x3]), [instr](instruction_pattern const& e){ + return !((instr&e.mask) ^ e.value ); + }); + return static_cast(res!=std::end(qlut[instr&0x3])? res->id : opcode_e::MAX_OPCODE); +} + + +std::unique_ptr> traits::get_decoder(){ + return std::make_unique>(); +} + +} +} diff --git a/src/vm/interp/vm_tgc_c.cpp b/src/vm/interp/vm_tgc_c.cpp index c8b2461..af51eed 100644 --- a/src/vm/interp/vm_tgc_c.cpp +++ b/src/vm/interp/vm_tgc_c.cpp @@ -67,6 +67,7 @@ public: using addr_t = typename super::addr_t; using reg_t = typename traits::reg_t; using mem_type_e = typename traits::mem_type_e; + using opcode_e = typename traits::opcode_e; vm_impl(); @@ -88,7 +89,6 @@ protected: inline const char *name(size_t index){return traits::reg_aliases.at(index);} - typename arch::traits::opcode_e decode_inst_id(code_word_t instr); virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override; // some compile time constants @@ -105,13 +105,7 @@ protected: std::array lut_00, lut_01, lut_10; std::array lut_11; - struct instruction_pattern { - uint32_t value; - uint32_t mask; - typename arch::traits::opcode_e id; - }; - - std::array, 4> qlut; + std::unique_ptr> decoder; inline void raise(uint16_t trap_id, uint16_t cause){ auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id; @@ -133,42 +127,7 @@ protected: template T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;} - inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){ - auto ret = super::template read_mem(space, addr); - if(this->core.trap_state) throw 0; - return ret; - } - inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){ - auto ret = super::template read_mem(space, addr); - if(this->core.trap_state) throw 0; - return ret; - } - inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){ - auto ret = super::template read_mem(space, addr); - if(this->core.trap_state) throw 0; - return ret; - } - inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){ - auto ret = super::template read_mem(space, addr); - if(this->core.trap_state) throw 0; - return ret; - } - inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){ - super::write_mem(space, addr, data); - if(this->core.trap_state) throw 0; - } - inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){ - super::write_mem(space, addr, data); - if(this->core.trap_state) throw 0; - } - inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){ - super::write_mem(space, addr, data); - if(this->core.trap_state) throw 0; - } - inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){ - super::write_mem(space, addr, data); - if(this->core.trap_state) throw 0; - } + template::type> inline S sext(U from) { auto mask = (1ULL<::opcode_e op; - }; - - const std::array instr_descr = {{ - /* entries are: size, valid value, valid mask, function ptr */ - {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits::opcode_e::LUI}, - {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits::opcode_e::AUIPC}, - {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, arch::traits::opcode_e::JAL}, - {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::JALR}, - {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BEQ}, - {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BNE}, - {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLT}, - {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGE}, - {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLTU}, - {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGEU}, - {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LB}, - {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LH}, - {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LW}, - {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LBU}, - {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LHU}, - {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SB}, - {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SH}, - {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SW}, - {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ADDI}, - {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTI}, - {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTIU}, - {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::XORI}, - {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ORI}, - {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ANDI}, - {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLLI}, - {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRLI}, - {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRAI}, - {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::ADD}, - {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SUB}, - {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLL}, - {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLT}, - {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLTU}, - {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::XOR}, - {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRL}, - {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRA}, - {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::OR}, - {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::AND}, - {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE}, - {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::ECALL}, - {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::EBREAK}, - {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::URET}, - {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::SRET}, - {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::MRET}, - {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::WFI}, - {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::DRET}, - {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRW}, - {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRS}, - {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRC}, - {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRWI}, - {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRSI}, - {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRCI}, - {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE_I}, - {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MUL}, - {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULH}, - {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULHSU}, - {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::MULHU}, - {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::DIV}, - {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::DIVU}, - {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REM}, - {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REMU}, - {16, 0b0000000000000000, 0b1110000000000011, arch::traits::opcode_e::CADDI4SPN}, - {16, 0b0100000000000000, 0b1110000000000011, arch::traits::opcode_e::CLW}, - {16, 0b1100000000000000, 0b1110000000000011, arch::traits::opcode_e::CSW}, - {16, 0b0000000000000001, 0b1110000000000011, arch::traits::opcode_e::CADDI}, - {16, 0b0000000000000001, 0b1110111110000011, arch::traits::opcode_e::CNOP}, - {16, 0b0010000000000001, 0b1110000000000011, arch::traits::opcode_e::CJAL}, - {16, 0b0100000000000001, 0b1110000000000011, arch::traits::opcode_e::CLI}, - {16, 0b0110000000000001, 0b1110000000000011, arch::traits::opcode_e::CLUI}, - {16, 0b0110000100000001, 0b1110111110000011, arch::traits::opcode_e::CADDI16SP}, - {16, 0b0110000000000001, 0b1111000001111111, arch::traits::opcode_e::__reserved_clui}, - {16, 0b1000000000000001, 0b1111110000000011, arch::traits::opcode_e::CSRLI}, - {16, 0b1000010000000001, 0b1111110000000011, arch::traits::opcode_e::CSRAI}, - {16, 0b1000100000000001, 0b1110110000000011, arch::traits::opcode_e::CANDI}, - {16, 0b1000110000000001, 0b1111110001100011, arch::traits::opcode_e::CSUB}, - {16, 0b1000110000100001, 0b1111110001100011, arch::traits::opcode_e::CXOR}, - {16, 0b1000110001000001, 0b1111110001100011, arch::traits::opcode_e::COR}, - {16, 0b1000110001100001, 0b1111110001100011, arch::traits::opcode_e::CAND}, - {16, 0b1010000000000001, 0b1110000000000011, arch::traits::opcode_e::CJ}, - {16, 0b1100000000000001, 0b1110000000000011, arch::traits::opcode_e::CBEQZ}, - {16, 0b1110000000000001, 0b1110000000000011, arch::traits::opcode_e::CBNEZ}, - {16, 0b0000000000000010, 0b1111000000000011, arch::traits::opcode_e::CSLLI}, - {16, 0b0100000000000010, 0b1110000000000011, arch::traits::opcode_e::CLWSP}, - {16, 0b1000000000000010, 0b1111000000000011, arch::traits::opcode_e::CMV}, - {16, 0b1000000000000010, 0b1111000001111111, arch::traits::opcode_e::CJR}, - {16, 0b1000000000000010, 0b1111111111111111, arch::traits::opcode_e::__reserved_cmv}, - {16, 0b1001000000000010, 0b1111000000000011, arch::traits::opcode_e::CADD}, - {16, 0b1001000000000010, 0b1111000001111111, arch::traits::opcode_e::CJALR}, - {16, 0b1001000000000010, 0b1111111111111111, arch::traits::opcode_e::CEBREAK}, - {16, 0b1100000000000010, 0b1110000000000011, arch::traits::opcode_e::CSWSP}, - {16, 0b0000000000000000, 0b1111111111111111, arch::traits::opcode_e::DII}, - }}; //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK; iss::status fetch_ins(virt_addr_t pc, uint8_t * data){ @@ -328,16 +184,7 @@ constexpr size_t bit_count(uint32_t u) { template vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) : vm_base(core, core_id, cluster_id) { - unsigned id=0; - for (auto instr : instr_descr) { - auto quadrant = instr.value & 0x3; - qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op}); - } - for(auto& lut: qlut){ - std::sort(std::begin(lut), std::end(lut), [](instruction_pattern const& a, instruction_pattern const& b){ - return bit_count(a.mask) > bit_count(b.mask); - }); - } + decoder = traits::get_decoder(); } inline bool is_count_limit_enabled(finish_cond_e cond){ @@ -348,19 +195,11 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){ return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF; } -template -typename arch::traits::opcode_e vm_impl::decode_inst_id(code_word_t instr){ - for(auto& e: qlut[instr&0x3]){ - if(!((instr&e.mask) ^ e.value )) return e.id; - } - return arch::traits::opcode_e::MAX_OPCODE; -} - template typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){ auto pc=start; - auto* PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::PC]); - auto* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); + auto* PC = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::PC]); + auto* NEXT_PC = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::NEXT_PC]); auto& trap_state = this->core.trap_state; auto& icount = this->core.icount; auto& cycle = this->core.cycle; @@ -377,11 +216,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if (is_jump_to_self_enabled(cond) && (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' - auto inst_id = decode_inst_id(instr); + auto inst_id = static_cast(decoder->decode_instruction(instr)); // pre execution stuff if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast(inst_id)); switch(inst_id){ - case arch::traits::opcode_e::LUI: { + case opcode_e::LUI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint32_t imm = ((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ @@ -392,7 +231,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -402,7 +241,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_LUI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::AUIPC: { + case opcode_e::AUIPC: { uint8_t rd = ((bit_sub<7,5>(instr))); uint32_t imm = ((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ @@ -413,7 +252,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -423,7 +262,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_AUIPC:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::JAL: { + case opcode_e::JAL: { uint8_t rd = ((bit_sub<7,5>(instr))); uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); if(this->disass_enabled){ @@ -434,7 +273,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -451,7 +290,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_JAL:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::JALR: { + case opcode_e::JALR: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -463,7 +302,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -481,7 +320,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_JALR:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::BEQ: { + case opcode_e::BEQ: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -493,7 +332,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -509,7 +348,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_BEQ:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::BNE: { + case opcode_e::BNE: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -521,7 +360,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -537,7 +376,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_BNE:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::BLT: { + case opcode_e::BLT: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -549,7 +388,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -565,7 +404,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_BLT:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::BGE: { + case opcode_e::BGE: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -577,7 +416,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -593,7 +432,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_BGE:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::BLTU: { + case opcode_e::BLTU: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -605,7 +444,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -621,7 +460,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_BLTU:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::BGEU: { + case opcode_e::BGEU: { uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -633,7 +472,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -649,7 +488,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_BGEU:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::LB: { + case opcode_e::LB: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -661,7 +500,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -674,7 +513,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_LB:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::LH: { + case opcode_e::LH: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -686,7 +525,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -700,7 +539,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_LH:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::LW: { + case opcode_e::LW: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -712,7 +551,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -726,7 +565,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_LW:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::LBU: { + case opcode_e::LBU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -738,7 +577,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -751,7 +590,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_LBU:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::LHU: { + case opcode_e::LHU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -763,7 +602,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -777,7 +616,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_LHU:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SB: { + case opcode_e::SB: { uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -789,7 +628,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -798,7 +637,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SB:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SH: { + case opcode_e::SH: { uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -810,7 +649,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -820,7 +659,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SH:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SW: { + case opcode_e::SW: { uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -832,7 +671,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -842,7 +681,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SW:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::ADDI: { + case opcode_e::ADDI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -854,7 +693,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -864,7 +703,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_ADDI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLTI: { + case opcode_e::SLTI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -876,7 +715,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -886,7 +725,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SLTI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLTIU: { + case opcode_e::SLTIU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -898,7 +737,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -908,7 +747,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SLTIU:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::XORI: { + case opcode_e::XORI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -920,7 +759,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -930,7 +769,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_XORI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::ORI: { + case opcode_e::ORI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -942,7 +781,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -952,7 +791,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_ORI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::ANDI: { + case opcode_e::ANDI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -964,7 +803,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -974,7 +813,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_ANDI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLLI: { + case opcode_e::SLLI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -986,7 +825,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1001,7 +840,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SLLI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRLI: { + case opcode_e::SRLI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -1013,7 +852,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1028,7 +867,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SRLI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRAI: { + case opcode_e::SRAI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -1040,7 +879,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1055,7 +894,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SRAI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::ADD: { + case opcode_e::ADD: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1067,7 +906,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1077,7 +916,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_ADD:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SUB: { + case opcode_e::SUB: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1089,7 +928,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1099,7 +938,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SUB:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLL: { + case opcode_e::SLL: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1111,7 +950,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1121,7 +960,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SLL:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLT: { + case opcode_e::SLT: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1133,7 +972,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1143,7 +982,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SLT:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLTU: { + case opcode_e::SLTU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1155,7 +994,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1165,7 +1004,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SLTU:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::XOR: { + case opcode_e::XOR: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1177,7 +1016,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1187,7 +1026,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_XOR:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRL: { + case opcode_e::SRL: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1199,7 +1038,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1209,7 +1048,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SRL:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRA: { + case opcode_e::SRA: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1221,7 +1060,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1231,7 +1070,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SRA:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::OR: { + case opcode_e::OR: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1243,7 +1082,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1253,7 +1092,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_OR:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::AND: { + case opcode_e::AND: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1265,7 +1104,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1275,7 +1114,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_AND:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::FENCE: { + case opcode_e::FENCE: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t succ = ((bit_sub<20,4>(instr))); @@ -1297,7 +1136,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_FENCE:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::ECALL: { + case opcode_e::ECALL: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "ecall"); @@ -1310,7 +1149,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_ECALL:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::EBREAK: { + case opcode_e::EBREAK: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "ebreak"); @@ -1323,7 +1162,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_EBREAK:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::URET: { + case opcode_e::URET: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "uret"); @@ -1336,7 +1175,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_URET:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRET: { + case opcode_e::SRET: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "sret"); @@ -1349,7 +1188,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_SRET:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::MRET: { + case opcode_e::MRET: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "mret"); @@ -1362,7 +1201,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_MRET:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::WFI: { + case opcode_e::WFI: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "wfi"); @@ -1375,15 +1214,15 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_WFI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::DRET: { + case opcode_e::DRET: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "dret"); } // used registers - auto* PRIV = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::PRIV]); + auto* PRIV = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::PRIV]); - auto* DPC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::DPC]); + auto* DPC = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::DPC]); // calculate next pc value *NEXT_PC = *PC + 4; // execute instruction @@ -1399,7 +1238,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_DRET:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRW: { + case opcode_e::CSRRW: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1411,7 +1250,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1431,7 +1270,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSRRW:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRS: { + case opcode_e::CSRRS: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1443,7 +1282,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1461,7 +1300,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSRRS:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRC: { + case opcode_e::CSRRC: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1473,7 +1312,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1491,7 +1330,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSRRC:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRWI: { + case opcode_e::CSRRWI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1503,7 +1342,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1518,7 +1357,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSRRWI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRSI: { + case opcode_e::CSRRSI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1530,7 +1369,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1547,7 +1386,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSRRSI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRCI: { + case opcode_e::CSRRCI: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); uint16_t csr = ((bit_sub<20,12>(instr))); @@ -1559,7 +1398,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1576,7 +1415,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSRRCI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::FENCE_I: { + case opcode_e::FENCE_I: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint16_t imm = ((bit_sub<20,12>(instr))); @@ -1596,7 +1435,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_FENCE_I:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::MUL: { + case opcode_e::MUL: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1608,7 +1447,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1619,7 +1458,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_MUL:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::MULH: { + case opcode_e::MULH: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1631,7 +1470,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1642,7 +1481,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_MULH:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::MULHSU: { + case opcode_e::MULHSU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1654,7 +1493,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1665,7 +1504,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_MULHSU:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::MULHU: { + case opcode_e::MULHU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1677,7 +1516,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1688,7 +1527,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_MULHU:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::DIV: { + case opcode_e::DIV: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1700,7 +1539,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1721,7 +1560,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_DIV:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::DIVU: { + case opcode_e::DIVU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1733,7 +1572,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1748,7 +1587,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_DIVU:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::REM: { + case opcode_e::REM: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1760,7 +1599,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1781,7 +1620,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_REM:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::REMU: { + case opcode_e::REMU: { uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -1793,7 +1632,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 4; // execute instruction { @@ -1808,7 +1647,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_REMU:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CADDI4SPN: { + case opcode_e::CADDI4SPN: { uint8_t rd = ((bit_sub<2,3>(instr))); uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); if(this->disass_enabled){ @@ -1819,7 +1658,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -1832,7 +1671,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CADDI4SPN:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CLW: { + case opcode_e::CLW: { uint8_t rd = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -1844,7 +1683,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -1855,7 +1694,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CLW:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSW: { + case opcode_e::CSW: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -1867,7 +1706,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -1877,7 +1716,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSW:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CADDI: { + case opcode_e::CADDI: { uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -1888,7 +1727,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -1896,7 +1735,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CADDI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CNOP: { + case opcode_e::CNOP: { uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -1909,7 +1748,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CNOP:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CJAL: { + case opcode_e::CJAL: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -1919,7 +1758,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -1929,7 +1768,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CJAL:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CLI: { + case opcode_e::CLI: { uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -1940,7 +1779,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -1950,7 +1789,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CLI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CLUI: { + case opcode_e::CLUI: { uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -1961,7 +1800,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -1974,7 +1813,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CLUI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CADDI16SP: { + case opcode_e::CADDI16SP: { uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -1984,7 +1823,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -1997,7 +1836,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CADDI16SP:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::__reserved_clui: { + case opcode_e::__reserved_clui: { uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -2011,7 +1850,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP___reserved_clui:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRLI: { + case opcode_e::CSRLI: { uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -2022,7 +1861,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2031,7 +1870,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSRLI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRAI: { + case opcode_e::CSRAI: { uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -2042,7 +1881,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2059,7 +1898,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSRAI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CANDI: { + case opcode_e::CANDI: { uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -2070,7 +1909,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2079,7 +1918,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CANDI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSUB: { + case opcode_e::CSUB: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -2090,7 +1929,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2099,7 +1938,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSUB:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CXOR: { + case opcode_e::CXOR: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -2110,7 +1949,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2119,7 +1958,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CXOR:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::COR: { + case opcode_e::COR: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -2130,7 +1969,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2139,7 +1978,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_COR:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CAND: { + case opcode_e::CAND: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -2150,7 +1989,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2159,7 +1998,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CAND:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CJ: { + case opcode_e::CJ: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -2177,7 +2016,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CJ:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CBEQZ: { + case opcode_e::CBEQZ: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -2188,7 +2027,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2199,7 +2038,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CBEQZ:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CBNEZ: { + case opcode_e::CBNEZ: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -2210,7 +2049,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2221,7 +2060,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CBNEZ:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSLLI: { + case opcode_e::CSLLI: { uint8_t nzuimm = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -2232,7 +2071,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2242,7 +2081,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSLLI:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CLWSP: { + case opcode_e::CLWSP: { uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -2253,7 +2092,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2269,7 +2108,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CLWSP:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CMV: { + case opcode_e::CMV: { uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -2280,7 +2119,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2290,7 +2129,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CMV:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CJR: { + case opcode_e::CJR: { uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -2300,7 +2139,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2314,7 +2153,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CJR:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::__reserved_cmv: { + case opcode_e::__reserved_cmv: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "__reserved_cmv"); @@ -2327,7 +2166,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP___reserved_cmv:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CADD: { + case opcode_e::CADD: { uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -2338,7 +2177,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2348,7 +2187,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CADD:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CJALR: { + case opcode_e::CJALR: { uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -2358,7 +2197,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2369,7 +2208,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CJALR:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CEBREAK: { + case opcode_e::CEBREAK: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "cebreak"); @@ -2382,7 +2221,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CEBREAK:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSWSP: { + case opcode_e::CSWSP: { uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); if(this->disass_enabled){ @@ -2393,7 +2232,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co this->core.disass_output(pc.val, mnemonic); } // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + auto* X = reinterpret_cast(this->regs_base_ptr+traits::reg_byte_offsets[traits::X0]);// calculate next pc value *NEXT_PC = *PC + 2; // execute instruction { @@ -2403,7 +2242,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } TRAP_CSWSP:break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::DII: { + case opcode_e::DII: { if(this->disass_enabled){ /* generate console output when executing the command */ this->core.disass_output(pc.val, "dii");