From 40f50b0ec079b912ed7ab76756772bd0527ebe05 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sat, 9 Sep 2023 18:54:18 +0200 Subject: [PATCH 1/2] changes register names to lower case in printing --- CMakeLists.txt | 4 ++- gen_input/templates/CORENAME.h.gtl | 4 +-- src/iss/arch/tgc5c.h | 4 +-- src/vm/interp/vm_tgc5c.cpp | 52 +++++++++++++++--------------- 4 files changed, 33 insertions(+), 31 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 001a346..aa62c97 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -80,7 +80,9 @@ target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core) get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES) target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL}) get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS) -target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS}) +if(NOT (DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND)) + target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS}) +endif() target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine) if(TARGET jsoncpp::jsoncpp) diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl index 96ba762..7d3a38c 100644 --- a/gen_input/templates/CORENAME.h.gtl +++ b/gen_input/templates/CORENAME.h.gtl @@ -76,10 +76,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { constexpr static char const* const core_type = "${coreDef.name}"; static constexpr std::array reg_names{ - {"${registers.collect{it.name}.join('", "')}"}}; + {"${registers.collect{it.name.toLowerCase()}.join('", "')}"}}; static constexpr std::array reg_aliases{ - {"${registers.collect{it.alias}.join('", "')}"}}; + {"${registers.collect{it.alias.toLowerCase()}.join('", "')}"}}; enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}}; diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 319f31f..76e6200 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -48,10 +48,10 @@ template <> struct traits { constexpr static char const* const core_type = "TGC5C"; static constexpr std::array reg_names{ - {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV", "DPC"}}; + {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}}; static constexpr std::array reg_aliases{ - {"ZERO", "RA", "SP", "GP", "TP", "T0", "T1", "T2", "S0", "S1", "A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "T3", "T4", "T5", "T6", "PC", "NEXT_PC", "PRIV", "DPC"}}; + {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}}; enum constants {MISA_VAL=1073746180ULL, MARCHID_VAL=2147483651ULL, XLEN=32ULL, INSTR_ALIGNMENT=2ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL, MUL_LEN=64ULL}; diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index 4ba2443..639cb6d 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -719,9 +719,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int8_t read_res = super::template read_mem(traits::MEM, load_address); + int8_t res_27 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int8_t res = (int8_t)read_res; + int8_t res = (int8_t)res_27; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -750,9 +750,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int16_t read_res = super::template read_mem(traits::MEM, load_address); + int16_t res_28 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int16_t res = (int16_t)read_res; + int16_t res = (int16_t)res_28; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -781,9 +781,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int32_t read_res = super::template read_mem(traits::MEM, load_address); + int32_t res_29 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int32_t res = (int32_t)read_res; + int32_t res = (int32_t)res_29; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -812,9 +812,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - uint8_t read_res = super::template read_mem(traits::MEM, load_address); + uint8_t res_30 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint8_t res = read_res; + uint8_t res = res_30; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -843,9 +843,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - uint16_t read_res = super::template read_mem(traits::MEM, load_address); + uint16_t res_31 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint16_t res = read_res; + uint16_t res = res_31; if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -1543,9 +1543,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { uint32_t xrs1 = *(X+rs1); if(rd != 0) { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_32 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_32; super::template write_mem(traits::CSR, csr, xrs1); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); *(X+rd) = xrd; @@ -1578,9 +1578,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_33 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_33; uint32_t xrs1 = *(X+rs1); if(rs1 != 0) { super::template write_mem(traits::CSR, csr, xrd | xrs1); @@ -1613,9 +1613,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_34 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_34; uint32_t xrs1 = *(X+rs1); if(rs1 != 0) { super::template write_mem(traits::CSR, csr, xrd & ~ xrs1); @@ -1648,9 +1648,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_35 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_35; super::template write_mem(traits::CSR, csr, (uint32_t)zimm); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); if(rd != 0) { @@ -1680,9 +1680,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_36 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_36; if(zimm != 0) { super::template write_mem(traits::CSR, csr, xrd | (uint32_t)zimm); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); @@ -1714,9 +1714,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t read_res = super::template read_mem(traits::CSR, csr); + uint32_t res_37 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = read_res; + uint32_t xrd = res_37; if(zimm != 0) { super::template write_mem(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); @@ -2051,9 +2051,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { uint32_t offs = (uint32_t)(*(X+rs1 + 8) + uimm); - int32_t read_res = super::template read_mem(traits::MEM, offs); + int32_t res_38 = super::template read_mem(traits::MEM, offs); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - *(X+rd + 8) = (uint32_t)(int32_t)read_res; + *(X+rd + 8) = (uint32_t)(int32_t)res_38; } break; }// @suppress("No break at end of case") @@ -2473,9 +2473,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t offs = (uint32_t)(*(X+2) + uimm); - int32_t read_res = super::template read_mem(traits::MEM, offs); + int32_t res_39 = super::template read_mem(traits::MEM, offs); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - *(X+rd) = (uint32_t)(int32_t)read_res; + *(X+rd) = (uint32_t)(int32_t)res_39; } } break; From c7038cafa5f1df1ab5a435308e8b34a95d7da793 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 19 Sep 2023 12:11:49 +0200 Subject: [PATCH 2/2] updates naming in checked-in sources --- src/iss/arch/tgc5c.h | 54 ++++++------- src/vm/interp/vm_tgc5c.cpp | 162 ++++++++++++++++++------------------- 2 files changed, 108 insertions(+), 108 deletions(-) diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 76e6200..2dddbb3 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -141,35 +141,35 @@ template <> struct traits { DIVU = 54, REM = 55, REMU = 56, - CADDI4SPN = 57, - CLW = 58, - CSW = 59, - CADDI = 60, - CNOP = 61, - CJAL = 62, - CLI = 63, - CLUI = 64, - CADDI16SP = 65, + C__ADDI4SPN = 57, + C__LW = 58, + C__SW = 59, + C__ADDI = 60, + C__NOP = 61, + C__JAL = 62, + C__LI = 63, + C__LUI = 64, + C__ADDI16SP = 65, __reserved_clui = 66, - CSRLI = 67, - CSRAI = 68, - CANDI = 69, - CSUB = 70, - CXOR = 71, - COR = 72, - CAND = 73, - CJ = 74, - CBEQZ = 75, - CBNEZ = 76, - CSLLI = 77, - CLWSP = 78, - CMV = 79, - CJR = 80, + C__SRLI = 67, + C__SRAI = 68, + C__ANDI = 69, + C__SUB = 70, + C__XOR = 71, + C__OR = 72, + C__AND = 73, + C__J = 74, + C__BEQZ = 75, + C__BNEZ = 76, + C__SLLI = 77, + C__LWSP = 78, + C__MV = 79, + C__JR = 80, __reserved_cmv = 81, - CADD = 82, - CJALR = 83, - CEBREAK = 84, - CSWSP = 85, + C__ADD = 82, + C__JALR = 83, + C__EBREAK = 84, + C__SWSP = 85, DII = 86, MAX_OPCODE }; diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index 639cb6d..02c5144 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -210,35 +210,35 @@ private: {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::DIVU}, {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REM}, {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::REMU}, - {16, 0b0000000000000000, 0b1110000000000011, arch::traits::opcode_e::CADDI4SPN}, - {16, 0b0100000000000000, 0b1110000000000011, arch::traits::opcode_e::CLW}, - {16, 0b1100000000000000, 0b1110000000000011, arch::traits::opcode_e::CSW}, - {16, 0b0000000000000001, 0b1110000000000011, arch::traits::opcode_e::CADDI}, - {16, 0b0000000000000001, 0b1110111110000011, arch::traits::opcode_e::CNOP}, - {16, 0b0010000000000001, 0b1110000000000011, arch::traits::opcode_e::CJAL}, - {16, 0b0100000000000001, 0b1110000000000011, arch::traits::opcode_e::CLI}, - {16, 0b0110000000000001, 0b1110000000000011, arch::traits::opcode_e::CLUI}, - {16, 0b0110000100000001, 0b1110111110000011, arch::traits::opcode_e::CADDI16SP}, + {16, 0b0000000000000000, 0b1110000000000011, arch::traits::opcode_e::C__ADDI4SPN}, + {16, 0b0100000000000000, 0b1110000000000011, arch::traits::opcode_e::C__LW}, + {16, 0b1100000000000000, 0b1110000000000011, arch::traits::opcode_e::C__SW}, + {16, 0b0000000000000001, 0b1110000000000011, arch::traits::opcode_e::C__ADDI}, + {16, 0b0000000000000001, 0b1110111110000011, arch::traits::opcode_e::C__NOP}, + {16, 0b0010000000000001, 0b1110000000000011, arch::traits::opcode_e::C__JAL}, + {16, 0b0100000000000001, 0b1110000000000011, arch::traits::opcode_e::C__LI}, + {16, 0b0110000000000001, 0b1110000000000011, arch::traits::opcode_e::C__LUI}, + {16, 0b0110000100000001, 0b1110111110000011, arch::traits::opcode_e::C__ADDI16SP}, {16, 0b0110000000000001, 0b1111000001111111, arch::traits::opcode_e::__reserved_clui}, - {16, 0b1000000000000001, 0b1111110000000011, arch::traits::opcode_e::CSRLI}, - {16, 0b1000010000000001, 0b1111110000000011, arch::traits::opcode_e::CSRAI}, - {16, 0b1000100000000001, 0b1110110000000011, arch::traits::opcode_e::CANDI}, - {16, 0b1000110000000001, 0b1111110001100011, arch::traits::opcode_e::CSUB}, - {16, 0b1000110000100001, 0b1111110001100011, arch::traits::opcode_e::CXOR}, - {16, 0b1000110001000001, 0b1111110001100011, arch::traits::opcode_e::COR}, - {16, 0b1000110001100001, 0b1111110001100011, arch::traits::opcode_e::CAND}, - {16, 0b1010000000000001, 0b1110000000000011, arch::traits::opcode_e::CJ}, - {16, 0b1100000000000001, 0b1110000000000011, arch::traits::opcode_e::CBEQZ}, - {16, 0b1110000000000001, 0b1110000000000011, arch::traits::opcode_e::CBNEZ}, - {16, 0b0000000000000010, 0b1111000000000011, arch::traits::opcode_e::CSLLI}, - {16, 0b0100000000000010, 0b1110000000000011, arch::traits::opcode_e::CLWSP}, - {16, 0b1000000000000010, 0b1111000000000011, arch::traits::opcode_e::CMV}, - {16, 0b1000000000000010, 0b1111000001111111, arch::traits::opcode_e::CJR}, + {16, 0b1000000000000001, 0b1111110000000011, arch::traits::opcode_e::C__SRLI}, + {16, 0b1000010000000001, 0b1111110000000011, arch::traits::opcode_e::C__SRAI}, + {16, 0b1000100000000001, 0b1110110000000011, arch::traits::opcode_e::C__ANDI}, + {16, 0b1000110000000001, 0b1111110001100011, arch::traits::opcode_e::C__SUB}, + {16, 0b1000110000100001, 0b1111110001100011, arch::traits::opcode_e::C__XOR}, + {16, 0b1000110001000001, 0b1111110001100011, arch::traits::opcode_e::C__OR}, + {16, 0b1000110001100001, 0b1111110001100011, arch::traits::opcode_e::C__AND}, + {16, 0b1010000000000001, 0b1110000000000011, arch::traits::opcode_e::C__J}, + {16, 0b1100000000000001, 0b1110000000000011, arch::traits::opcode_e::C__BEQZ}, + {16, 0b1110000000000001, 0b1110000000000011, arch::traits::opcode_e::C__BNEZ}, + {16, 0b0000000000000010, 0b1111000000000011, arch::traits::opcode_e::C__SLLI}, + {16, 0b0100000000000010, 0b1110000000000011, arch::traits::opcode_e::C__LWSP}, + {16, 0b1000000000000010, 0b1111000000000011, arch::traits::opcode_e::C__MV}, + {16, 0b1000000000000010, 0b1111000001111111, arch::traits::opcode_e::C__JR}, {16, 0b1000000000000010, 0b1111111111111111, arch::traits::opcode_e::__reserved_cmv}, - {16, 0b1001000000000010, 0b1111000000000011, arch::traits::opcode_e::CADD}, - {16, 0b1001000000000010, 0b1111000001111111, arch::traits::opcode_e::CJALR}, - {16, 0b1001000000000010, 0b1111111111111111, arch::traits::opcode_e::CEBREAK}, - {16, 0b1100000000000010, 0b1110000000000011, arch::traits::opcode_e::CSWSP}, + {16, 0b1001000000000010, 0b1111000000000011, arch::traits::opcode_e::C__ADD}, + {16, 0b1001000000000010, 0b1111000001111111, arch::traits::opcode_e::C__JALR}, + {16, 0b1001000000000010, 0b1111111111111111, arch::traits::opcode_e::C__EBREAK}, + {16, 0b1100000000000010, 0b1110000000000011, arch::traits::opcode_e::C__SWSP}, {16, 0b0000000000000000, 0b1111111111111111, arch::traits::opcode_e::DII}, }}; @@ -2010,13 +2010,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CADDI4SPN: { + case arch::traits::opcode_e::C__ADDI4SPN: { uint8_t rd = ((bit_sub<2,3>(instr))); uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"), + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.addi4spn"), fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } @@ -2034,14 +2034,14 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CLW: { + case arch::traits::opcode_e::C__LW: { uint8_t rd = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "clw"), + "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.lw"), fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); this->core.disass_output(pc.val, mnemonic); } @@ -2057,14 +2057,14 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSW: { + case arch::traits::opcode_e::C__SW: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "csw"), + "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c.sw"), fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); this->core.disass_output(pc.val, mnemonic); } @@ -2079,13 +2079,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CADDI: { + case arch::traits::opcode_e::C__ADDI: { uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "caddi"), + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addi"), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } @@ -2105,11 +2105,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CNOP: { + case arch::traits::opcode_e::C__NOP: { uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); if(this->disass_enabled){ /* generate console output when executing the command */ - this->core.disass_output(pc.val, "cnop"); + this->core.disass_output(pc.val, "c__nop"); } // used registers// calculate next pc value *NEXT_PC = *PC + 2; @@ -2118,12 +2118,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CJAL: { + case arch::traits::opcode_e::C__JAL: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cjal"), + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } @@ -2138,13 +2138,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CLI: { + case arch::traits::opcode_e::C__LI: { uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "cli"), + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.li"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } @@ -2164,13 +2164,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CLUI: { + case arch::traits::opcode_e::C__LUI: { uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "clui"), + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c.lui"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } @@ -2188,12 +2188,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CADDI16SP: { + case arch::traits::opcode_e::C__ADDI16SP: { uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "caddi16sp"), + "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c.addi16sp"), fmt::arg("nzimm", nzimm)); this->core.disass_output(pc.val, mnemonic); } @@ -2225,13 +2225,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRLI: { + case arch::traits::opcode_e::C__SRLI: { uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrli"), + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"), fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); this->core.disass_output(pc.val, mnemonic); } @@ -2244,13 +2244,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRAI: { + case arch::traits::opcode_e::C__SRAI: { uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrai"), + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"), fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); this->core.disass_output(pc.val, mnemonic); } @@ -2270,13 +2270,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CANDI: { + case arch::traits::opcode_e::C__ANDI: { uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "candi"), + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.andi"), fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } @@ -2289,13 +2289,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSUB: { + case arch::traits::opcode_e::C__SUB: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "csub"), + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.sub"), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); this->core.disass_output(pc.val, mnemonic); } @@ -2308,13 +2308,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CXOR: { + case arch::traits::opcode_e::C__XOR: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cxor"), + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.xor"), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); this->core.disass_output(pc.val, mnemonic); } @@ -2327,13 +2327,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::COR: { + case arch::traits::opcode_e::C__OR: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cor"), + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.or"), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); this->core.disass_output(pc.val, mnemonic); } @@ -2346,13 +2346,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CAND: { + case arch::traits::opcode_e::C__AND: { uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cand"), + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.and"), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); this->core.disass_output(pc.val, mnemonic); } @@ -2365,12 +2365,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CJ: { + case arch::traits::opcode_e::C__J: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cj"), + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.j"), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } @@ -2383,13 +2383,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CBEQZ: { + case arch::traits::opcode_e::C__BEQZ: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbeqz"), + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.beqz"), fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } @@ -2405,13 +2405,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CBNEZ: { + case arch::traits::opcode_e::C__BNEZ: { uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbnez"), + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.bnez"), fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); this->core.disass_output(pc.val, mnemonic); } @@ -2427,13 +2427,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSLLI: { + case arch::traits::opcode_e::C__SLLI: { uint8_t nzuimm = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "cslli"), + "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c.slli"), fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm)); this->core.disass_output(pc.val, mnemonic); } @@ -2453,13 +2453,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CLWSP: { + case arch::traits::opcode_e::C__LWSP: { uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "clwsp"), + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c.lwsp"), fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); this->core.disass_output(pc.val, mnemonic); } @@ -2480,13 +2480,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CMV: { + case arch::traits::opcode_e::C__MV: { uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cmv"), + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.mv"), fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } @@ -2506,12 +2506,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CJR: { + case arch::traits::opcode_e::C__JR: { uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjr"), + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jr"), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } @@ -2543,13 +2543,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CADD: { + case arch::traits::opcode_e::C__ADD: { uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cadd"), + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c.add"), fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); this->core.disass_output(pc.val, mnemonic); } @@ -2569,12 +2569,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CJALR: { + case arch::traits::opcode_e::C__JALR: { uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjalr"), + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c.jalr"), fmt::arg("rs1", name(rs1))); this->core.disass_output(pc.val, mnemonic); } @@ -2595,10 +2595,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CEBREAK: { + case arch::traits::opcode_e::C__EBREAK: { if(this->disass_enabled){ /* generate console output when executing the command */ - this->core.disass_output(pc.val, "cebreak"); + this->core.disass_output(pc.val, "c__ebreak"); } // used registers// calculate next pc value *NEXT_PC = *PC + 2; @@ -2608,13 +2608,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } break; }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSWSP: { + case arch::traits::opcode_e::C__SWSP: { uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "cswsp"), + "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c.swsp"), fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); this->core.disass_output(pc.val, mnemonic); }