diff --git a/incl/iss/arch/riscv_hart_m_p.h b/incl/iss/arch/riscv_hart_m_p.h
index 538071d..36d31c9 100644
--- a/incl/iss/arch/riscv_hart_m_p.h
+++ b/incl/iss/arch/riscv_hart_m_p.h
@@ -233,11 +233,11 @@ protected:
          */
         const std::string core_type_name() const override { return traits<BASE>::core_type; }
 
-        virtual uint64_t get_pc() { return arch.get_pc(); };
+        uint64_t get_pc() override { return arch.get_pc(); };
 
-        virtual uint64_t get_next_pc() { return arch.get_next_pc(); };
+        uint64_t get_next_pc() override { return arch.get_next_pc(); };
 
-        virtual void set_curr_instr_cycles(unsigned cycles) { arch.cycle_offset += cycles - 1; };
+        void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
 
         riscv_hart_m_p<BASE, FEAT> &arch;
     };
diff --git a/incl/iss/arch/riscv_hart_msu_vp.h b/incl/iss/arch/riscv_hart_msu_vp.h
index efbe605..5ac10f1 100644
--- a/incl/iss/arch/riscv_hart_msu_vp.h
+++ b/incl/iss/arch/riscv_hart_msu_vp.h
@@ -293,16 +293,16 @@ public:
 
     std::pair<uint64_t, bool> load_file(std::string name, int type = -1) override;
 
-    virtual phys_addr_t virt2phys(const iss::addr_t &addr) override;
+    phys_addr_t virt2phys(const iss::addr_t &addr) override;
 
     iss::status read(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, uint8_t *const data) override;
     iss::status write(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
-    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
-    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
-    virtual uint64_t leave_trap(uint64_t flags) override;
+    uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data, fault_data); }
+    uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
+    uint64_t leave_trap(uint64_t flags) override;
     void wait_until(uint64_t flags) override;
 
     void disass_output(uint64_t pc, const std::string instr) override {
diff --git a/incl/iss/arch/riscv_hart_mu_p.h b/incl/iss/arch/riscv_hart_mu_p.h
index 7ff8eb3..99d1803 100644
--- a/incl/iss/arch/riscv_hart_mu_p.h
+++ b/incl/iss/arch/riscv_hart_mu_p.h
@@ -207,9 +207,9 @@ public:
     iss::status write(const address_type type, const access_type access, const uint32_t space,
             const uint64_t addr, const unsigned length, const uint8_t *const data) override;
 
-    virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_mu_p::enter_trap(flags, fault_data, fault_data); }
-    virtual uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
-    virtual uint64_t leave_trap(uint64_t flags) override;
+    uint64_t enter_trap(uint64_t flags) override { return riscv_hart_mu_p::enter_trap(flags, fault_data, fault_data); }
+    uint64_t enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) override;
+    uint64_t leave_trap(uint64_t flags) override;
 
     const reg_t& get_mhartid() const { return mhartid_reg;	}
 	void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
diff --git a/src/vm/interp/vm_tgc_c.cpp b/src/vm/interp/vm_tgc_c.cpp
index ad50b5a..a201ec8 100644
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
@@ -568,12 +568,13 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        {
-            if(*(X+rs1) == *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
+            if(*(X+rs1) == *(X+rs2)){
+                if(imm % traits::INSTR_ALIGNMENT) {
+                    raise(0,  0);
+                }
+            }else{
+                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
             }
-            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-        }
         } catch(...){}
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 4);
@@ -614,12 +615,14 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        {
-            if(*(X+rs1) != *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
+            if(*(X+rs1) != *(X+rs2)){
+                if(imm % traits::INSTR_ALIGNMENT) {
+                    raise(0,  0);
+                }
             }
-            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-        }
+            else{
+
+                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);}
         } catch(...){}
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 5);
@@ -660,12 +663,14 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        {
-            if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
+            if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)){
+                if(imm % traits::INSTR_ALIGNMENT) {
+                    raise(0,  0);
+                }
+            }
+            else{
+                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
             }
-            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-        }
         } catch(...){}
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6);
@@ -706,12 +711,14 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        {
-            if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
+            if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)){
+                if(imm % traits::INSTR_ALIGNMENT) {
+                    raise(0,  0);
+                }
+            }
+            else{
+                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
             }
-            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-        }
         } catch(...){}
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7);
@@ -752,12 +759,14 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        {
-            if(*(X+rs1) < *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
+            if(*(X+rs1) < *(X+rs2)){
+                if(imm % traits::INSTR_ALIGNMENT) {
+                    raise(0,  0);
+                }
+            }
+            else{
+                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
             }
-            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-        }
         } catch(...){}
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 8);
@@ -798,12 +807,14 @@ private:
         *NEXT_PC = *PC + 4;
         // execute instruction
         try {
-        {
-            if(*(X+rs1) >= *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
+            if(*(X+rs1) >= *(X+rs2)){
+                if(imm % traits::INSTR_ALIGNMENT) {
+                    raise(0,  0);
+                }
+            }
+            else{
+                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
             }
-            else pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-        }
         } catch(...){}
         // post execution stuff
         if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 9);