From f4f90c5e65573d3bc979f447e3f78f794499d36e Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sat, 2 Dec 2023 17:42:57 +0100 Subject: [PATCH 01/33] backports clang-format changes to template --- gen_input/templates/interp/CORENAME.cpp.gtl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index c2eb071..c9d0c8d 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -357,9 +357,9 @@ std::unique_ptr create(arch::${coreD } // namespace interp } // namespace iss -#include #include #include +#include namespace iss { namespace { volatile std::array dummy = { From 207f778ee62cdeeae36fcf6ddac9e3652887deb1 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Mon, 8 Jan 2024 17:17:59 +0100 Subject: [PATCH 02/33] adds initial semihosting host capabilities --- CMakeLists.txt | 242 +++++++++++--------- gen_input/templates/asmjit/CORENAME.cpp.gtl | 20 +- gen_input/templates/interp/CORENAME.cpp.gtl | 8 + gen_input/templates/llvm/CORENAME.cpp.gtl | 20 +- src/iss/arch/riscv_hart_m_p.h | 44 +++- src/iss/arch/riscv_hart_msu_vp.h | 46 +++- src/iss/arch/riscv_hart_mu_p.h | 45 +++- src/iss/arch/tgc5c.h | 1 - src/iss/semihosting/semihosting.cpp | 22 ++ src/iss/semihosting/semihosting.h | 6 + src/main.cpp | 9 +- src/vm/interp/vm_tgc5c.cpp | 12 +- 12 files changed, 332 insertions(+), 143 deletions(-) create mode 100644 src/iss/semihosting/semihosting.cpp create mode 100644 src/iss/semihosting/semihosting.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 3070844..994aff2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,8 +1,9 @@ cmake_minimum_required(VERSION 3.12) list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake) -############################################################################### + +# ############################################################################## # -############################################################################### +# ############################################################################## project(dbt-rise-tgc VERSION 1.0.0) include(GNUInstallDirs) @@ -14,59 +15,69 @@ find_package(Boost COMPONENTS coroutine REQUIRED) add_subdirectory(softfloat) -set(LIB_SOURCES +set(LIB_SOURCES src/iss/plugin/instruction_count.cpp - src/iss/arch/tgc5c.cpp - src/vm/interp/vm_tgc5c.cpp - src/vm/fp_functions.cpp + src/iss/arch/tgc5c.cpp + src/vm/interp/vm_tgc5c.cpp + src/vm/fp_functions.cpp + src/iss/semihosting/semihosting.cpp ) + if(WITH_TCC) - list(APPEND LIB_SOURCES - src/vm/tcc/vm_tgc5c.cpp + list(APPEND LIB_SOURCES + src/vm/tcc/vm_tgc5c.cpp ) endif() + if(WITH_LLVM) - list(APPEND LIB_SOURCES - src/vm/llvm/vm_tgc5c.cpp - src/vm/llvm/fp_impl.cpp - ) -endif() -if(WITH_ASMJIT) - list(APPEND LIB_SOURCES - src/vm/asmjit/vm_tgc5c.cpp + list(APPEND LIB_SOURCES + src/vm/llvm/vm_tgc5c.cpp + src/vm/llvm/fp_impl.cpp ) endif() + +if(WITH_ASMJIT) + list(APPEND LIB_SOURCES + src/vm/asmjit/vm_tgc5c.cpp + ) +endif() + # library files FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp) FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp) FILE(GLOB GEN_YAML_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/contrib/instr/*.yaml) list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES}) + foreach(FILEPATH ${GEN_ISS_SOURCES}) get_filename_component(CORE ${FILEPATH} NAME_WE) string(TOUPPER ${CORE} CORE) list(APPEND LIB_DEFINES CORE_${CORE}) endforeach() + message(STATUS "Core defines are ${LIB_DEFINES}") if(WITH_LLVM) - FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp) - list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES}) + FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp) + list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES}) endif() if(WITH_TCC) - FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp) - list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES}) + FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp) + list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES}) endif() + if(WITH_ASMJIT) - FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/asmjit/vm_*.cpp) - list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES}) + FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/asmjit/vm_*.cpp) + list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES}) endif() + if(TARGET yaml-cpp::yaml-cpp) - list(APPEND LIB_SOURCES - src/iss/plugin/cycle_estimate.cpp - src/iss/plugin/instruction_count.cpp + list(APPEND LIB_SOURCES + src/iss/plugin/cycle_estimate.cpp + src/iss/plugin/instruction_count.cpp ) endif() + # Define the library add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES}) @@ -75,60 +86,67 @@ if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU") elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC") target_compile_options(${PROJECT_NAME} PRIVATE /wd4293) endif() + target_include_directories(${PROJECT_NAME} PUBLIC src) target_include_directories(${PROJECT_NAME} PUBLIC src-gen) target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core) + # only re-export the include paths get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES) target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL}) get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS) -if(NOT (DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND)) - target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS}) + +if(NOT(DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND)) + target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS}) endif() target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine) + if(TARGET yaml-cpp::yaml-cpp) - target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS) - target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp) + target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS) + target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp) endif() if(WITH_LLVM) find_package(LLVM) - target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS}) - target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS}) - if(BUILD_SHARED_LIBS) - target_link_libraries( ${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES}) - endif() + target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS}) + target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS}) + + if(BUILD_SHARED_LIBS) + target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES}) + endif() endif() set_target_properties(${PROJECT_NAME} PROPERTIES - VERSION ${PROJECT_VERSION} - FRAMEWORK FALSE + VERSION ${PROJECT_VERSION} + FRAMEWORK FALSE ) install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME} - EXPORT ${PROJECT_NAME}Targets # for downstream dependencies - ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib - RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries - LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib - FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac - PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package) - INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers + EXPORT ${PROJECT_NAME}Targets # for downstream dependencies + ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib + RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries + LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib + FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac + PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package) + INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers ) install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME} - DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory - FILES_MATCHING # install only matched files - PATTERN "*.h" # select header files - ) + DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory + FILES_MATCHING # install only matched files + PATTERN "*.h" # select header files +) install(FILES ${GEN_YAML_SOURCES} DESTINATION share/tgc-vp) -############################################################################### + +# ############################################################################## # -############################################################################### +# ############################################################################## set(CMAKE_INSTALL_RPATH $ORIGIN/../${CMAKE_INSTALL_LIBDIR}) project(tgc-sim) find_package(Boost COMPONENTS program_options thread REQUIRED) add_executable(${PROJECT_NAME} src/main.cpp) + if(TARGET ${CORE_NAME}_cpp) list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES}) else() @@ -140,21 +158,20 @@ else() endif() foreach(F IN LISTS TGC_SOURCES) - if (${F} MATCHES ".*/arch/([^/]*)\.cpp") - string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F}) + if(${F} MATCHES ".*/arch/([^/]*)\.cpp") + string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F}) string(TOUPPER ${CORE_NAME_LC} CORE_NAME) target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME}) endif() endforeach() -#if(WITH_LLVM) -# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM) -# #target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs}) -#endif() -#if(WITH_TCC) -# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC) -#endif() - +# if(WITH_LLVM) +# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM) +# #target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs}) +# endif() +# if(WITH_TCC) +# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC) +# endif() target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc fmt::fmt) if(TARGET Boost::program_options) @@ -162,78 +179,85 @@ if(TARGET Boost::program_options) else() target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY}) endif() + target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS}) -if (Tcmalloc_FOUND) + +if(Tcmalloc_FOUND) target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES}) endif(Tcmalloc_FOUND) install(TARGETS tgc-sim - EXPORT ${PROJECT_NAME}Targets # for downstream dependencies - ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib - RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries - LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib - FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac - PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package) - INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers + EXPORT ${PROJECT_NAME}Targets # for downstream dependencies + ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib + RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries + LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib + FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac + PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package) + INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers ) if(BUILD_TESTING) - # ... CMake code to create tests ... - add_test(NAME tgc-sim-interp - COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp) - if(WITH_TCC) - add_test(NAME tgc-sim-tcc - COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc) - endif() - if(WITH_LLVM) - add_test(NAME tgc-sim-llvm - COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm) - endif() + # ... CMake code to create tests ... + add_test(NAME tgc-sim-interp + COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp) + + if(WITH_TCC) + add_test(NAME tgc-sim-tcc + COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc) + endif() + + if(WITH_LLVM) + add_test(NAME tgc-sim-llvm + COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm) + endif() + if(WITH_ASMJIT) - add_test(NAME tgc-sim-asmjit - COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend asmjit) - endif() + add_test(NAME tgc-sim-asmjit + COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend asmjit) + endif() endif() -############################################################################### + +# ############################################################################## # -############################################################################### +# ############################################################################## if(TARGET scc-sysc) - project(dbt-rise-tgc_sc VERSION 1.0.0) - set(LIB_SOURCES - src/sysc/core_complex.cpp - src/sysc/register_tgc_c.cpp - ) - FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/sysc/register_*.cpp) - list(APPEND LIB_SOURCES ${GEN_SC_SOURCES}) + project(dbt-rise-tgc_sc VERSION 1.0.0) + set(LIB_SOURCES + src/sysc/core_complex.cpp + src/sysc/register_tgc_c.cpp + ) + FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/sysc/register_*.cpp) + list(APPEND LIB_SOURCES ${GEN_SC_SOURCES}) add_library(${PROJECT_NAME} ${LIB_SOURCES}) target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC) target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME}) + foreach(F IN LISTS TGC_SOURCES) - if (${F} MATCHES ".*/arch/([^/]*)\.cpp") - string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F}) + if(${F} MATCHES ".*/arch/([^/]*)\.cpp") + string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F}) string(TOUPPER ${CORE_NAME_LC} CORE_NAME) target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME}) endif() endforeach() + target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc) -# if(WITH_LLVM) -# target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs}) -# endif() - - set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h) + + # if(WITH_LLVM) + # target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs}) + # endif() + set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h) set_target_properties(${PROJECT_NAME} PROPERTIES - VERSION ${PROJECT_VERSION} - FRAMEWORK FALSE - PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers + VERSION ${PROJECT_VERSION} + FRAMEWORK FALSE + PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers ) install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME} - EXPORT ${PROJECT_NAME}Targets # for downstream dependencies - ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib - RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries - LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib - FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac - PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc # headers for mac (note the different component -> different package) - INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers - ) + EXPORT ${PROJECT_NAME}Targets # for downstream dependencies + ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib + RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries + LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib + FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac + PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc # headers for mac (note the different component -> different package) + INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers + ) endif() - diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 74f54d4..4dfc294 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -263,16 +263,24 @@ std::unique_ptr create(arch::${coreD namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); - auto* vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); + auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto* vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); + auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }) }; diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index c9d0c8d..099b638 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -367,12 +367,20 @@ volatile std::array dummy = { auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }) }; diff --git a/gen_input/templates/llvm/CORENAME.cpp.gtl b/gen_input/templates/llvm/CORENAME.cpp.gtl index 5945e35..da04ae1 100644 --- a/gen_input/templates/llvm/CORENAME.cpp.gtl +++ b/gen_input/templates/llvm/CORENAME.cpp.gtl @@ -365,16 +365,24 @@ std::unique_ptr create(arch::${coreD namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); - auto* vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); + auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto* vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); + auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }) }; diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index e22c970..99a7f06 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -55,6 +55,8 @@ #include #include +#include + #if defined(__GNUC__) #define likely(x) __builtin_expect(!!(x), 1) #define unlikely(x) __builtin_expect(!!(x), 0) @@ -290,6 +292,8 @@ public: void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); } + void set_semihosting_callback(std::function& cb) { semihosting_cb = cb; }; + protected: struct riscv_instrumentation_if : public iss::instrumentation_if { @@ -344,9 +348,11 @@ protected: reg_t fault_data; uint64_t tohost = tohost_dflt; uint64_t fromhost = fromhost_dflt; - unsigned to_host_wr_cnt = 0; + bool tohost_lower_written = false; riscv_instrumentation_if instr_if; + std::function semihosting_cb; + using mem_type = util::sparse_array; using csr_type = util::sparse_array::reg_t, 1ULL << 12, 12>; using csr_page_type = typename csr_type::page_type; @@ -419,6 +425,7 @@ protected: feature_config cfg; unsigned mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? std::max(16U, static_cast(traits::CLIC_NUM_IRQ)) : 16U}; inline bool debug_mode_active() { return this->reg.PRIV & 0x4; } + std::pair, std::function> replace_mem_access(std::function rd, std::function wr) { std::pair, std::function> ret{hart_mem_rd_delegate, hart_mem_wr_delegate}; @@ -784,7 +791,7 @@ iss::status riscv_hart_m_p::write(const address_type type, const acc res = write_mem(phys_addr, length, data); } if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) { - this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault) + this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault) fault_data = addr; } return res; @@ -1098,6 +1105,7 @@ iss::status riscv_hart_m_p::read_mem(phys_addr_t paddr, unsigned len template iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { switch(paddr.val) { + // TODO remove UART, Peripherals should not be part of the ISS case 0xFFFF0000: // UART0 base, TXFIFO reg if(((char)data[0]) == '\n' || data[0] == 0) { LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; @@ -1115,7 +1123,8 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned le auto tohost_lower = (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); if(tohost_lower || tohost_upper) { uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); - if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) { + // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write + if(tohost_upper && (tohost_lower || tohost_lower_written)) { switch(hostvar >> 48) { case 0: if(hostvar != 0x1) { @@ -1138,13 +1147,13 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned le uart_buf.str(""); } else uart_buf << c; - to_host_wr_cnt = 0; } break; default: break; } + tohost_lower_written = false; } else if(tohost_lower) - to_host_wr_cnt++; + tohost_lower_written = true; } else if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; @@ -1253,6 +1262,31 @@ template uint64_t riscv_hart_m_p::e } else { csr[mtval] = addr; } + if(semihosting_cb) { + // Check for semihosting call + phys_addr_t p_addr(access_type::DEBUG_READ, traits::MEM, addr - 4); + std::array data; + // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07 + this->read_mem(p_addr, 4, data.data()); + p_addr.val += 8; + this->read_mem(p_addr, 4, data.data() + 4); + + const std::array ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40}; + if(data == ref_data) { + this->reg.NEXT_PC = addr + 8; + + std::array buffer; +#if defined(_MSC_VER) + sprintf(buffer.data(), "0x%016llx", addr); +#else + sprintf(buffer.data(), "0x%016lx", addr); +#endif + CLOG(INFO, disass) << "Semihosting call at address " << buffer.data() << " occurred "; + + semihosting_callback(this, this->reg.X10 /*a0*/, this->reg.X11 /*a1*/); + return this->reg.NEXT_PC; + } + } break; case 4: case 6: diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index 2a4bc90..4329160 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -55,6 +55,8 @@ #include #include +#include + #if defined(__GNUC__) #define likely(x) __builtin_expect(!!(x), 1) #define unlikely(x) __builtin_expect(!!(x), 0) @@ -341,6 +343,8 @@ public: void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); } + void set_semihosting_callback(std::function& cb) { semihosting_cb = cb; }; + protected: struct riscv_instrumentation_if : public iss::instrumentation_if { @@ -395,9 +399,11 @@ protected: std::array vm; uint64_t tohost = tohost_dflt; uint64_t fromhost = fromhost_dflt; - unsigned to_host_wr_cnt = 0; + bool tohost_lower_written = false; riscv_instrumentation_if instr_if; + std::function semihosting_cb; + using mem_type = util::sparse_array; using csr_type = util::sparse_array::reg_t, 1ULL << 12, 12>; using csr_page_type = typename csr_type::page_type; @@ -1092,7 +1098,8 @@ template iss::status riscv_hart_msu_vp::write_mem(phys_add auto tohost_lower = (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); if(tohost_lower || tohost_upper) { uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); - if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) { + // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write + if(tohost_upper && (tohost_lower || tohost_lower_written)) { switch(hostvar >> 48) { case 0: if(hostvar != 0x1) { @@ -1104,8 +1111,10 @@ template iss::status riscv_hart_msu_vp::write_mem(phys_add } this->reg.trap_state = std::numeric_limits::max(); this->interrupt_sim = hostvar; +#ifndef WITH_TCC + throw(iss::simulation_stopped(hostvar)); +#endif break; - // throw(iss::simulation_stopped(hostvar)); case 0x0101: { char c = static_cast(hostvar & 0xff); if(c == '\n' || c == 0) { @@ -1113,13 +1122,13 @@ template iss::status riscv_hart_msu_vp::write_mem(phys_add uart_buf.str(""); } else uart_buf << c; - to_host_wr_cnt = 0; } break; default: break; } + tohost_lower_written = false; } else if(tohost_lower) - to_host_wr_cnt++; + tohost_lower_written = true; } else if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; @@ -1304,6 +1313,31 @@ template uint64_t riscv_hart_msu_vp::enter_trap(uint64_t f // csr[dpc] = addr; // csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi) csr[utval | (new_priv << 8)] = addr; + if(semihosting_cb) { + // Check for semihosting call + phys_addr_t p_addr(access_type::DEBUG_READ, traits::MEM, addr - 4); + std::array data; + // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07 + this->read_mem(p_addr, 4, data.data()); + p_addr.val += 8; + this->read_mem(p_addr, 4, data.data() + 4); + + const std::array ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40}; + if(data == ref_data) { + this->reg.NEXT_PC = addr + 8; + + std::array buffer; +#if defined(_MSC_VER) + sprintf(buffer.data(), "0x%016llx", addr); +#else + sprintf(buffer.data(), "0x%016lx", addr); +#endif + CLOG(INFO, disass) << "Semihosting call at address " << buffer.data() << " occurred "; + + semihosting_callback(this, this->reg.X10 /*a0*/, this->reg.X11 /*a1*/); + return this->reg.NEXT_PC; + } + } break; case 4: case 6: @@ -1321,7 +1355,7 @@ template uint64_t riscv_hart_msu_vp::enter_trap(uint64_t f this->reg.pending_trap = 0; } size_t adr = ucause | (new_priv << 8); - csr[adr] = (trap_id << 31) + cause; + csr[adr] = (trap_id << (traits::XLEN - 1)) + cause; // update mstatus // xPP field of mstatus is written with the active privilege mode at the time // of the trap; the x PIE field of mstatus diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 7aa8b21..362fece 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -55,6 +55,8 @@ #include #include +#include + #if defined(__GNUC__) #define likely(x) __builtin_expect(!!(x), 1) #define unlikely(x) __builtin_expect(!!(x), 0) @@ -317,6 +319,8 @@ public: void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); } + void set_semihosting_callback(std::function& cb) { semihosting_cb = cb; }; + protected: struct riscv_instrumentation_if : public iss::instrumentation_if { @@ -371,9 +375,11 @@ protected: reg_t fault_data; uint64_t tohost = tohost_dflt; uint64_t fromhost = fromhost_dflt; - unsigned to_host_wr_cnt = 0; + bool tohost_lower_written = false; riscv_instrumentation_if instr_if; + std::function semihosting_cb; + using mem_type = util::sparse_array; using csr_type = util::sparse_array::reg_t, 1ULL << 12, 12>; using csr_page_type = typename csr_type::page_type; @@ -1317,6 +1323,7 @@ iss::status riscv_hart_mu_p::read_mem(phys_addr_t paddr, unsigned le template iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { switch(paddr.val) { + // TODO remove UART, Peripherals should not be part of the ISS case 0xFFFF0000: // UART0 base, TXFIFO reg if(((char)data[0]) == '\n' || data[0] == 0) { LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; @@ -1334,7 +1341,8 @@ iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned l auto tohost_lower = (traits::XLEN == 32 && paddr.val == tohost) || (traits::XLEN == 64 && paddr.val == tohost); if(tohost_lower || tohost_upper) { uint64_t hostvar = *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)); - if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) { + // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write + if(tohost_upper && (tohost_lower || tohost_lower_written)) { switch(hostvar >> 48) { case 0: if(hostvar != 0x1) { @@ -1346,8 +1354,10 @@ iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned l } this->reg.trap_state = std::numeric_limits::max(); this->interrupt_sim = hostvar; +#ifndef WITH_TCC + throw(iss::simulation_stopped(hostvar)); +#endif break; - // throw(iss::simulation_stopped(hostvar)); case 0x0101: { char c = static_cast(hostvar & 0xff); if(c == '\n' || c == 0) { @@ -1355,13 +1365,13 @@ iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned l uart_buf.str(""); } else uart_buf << c; - to_host_wr_cnt = 0; } break; default: break; } + tohost_lower_written = false; } else if(tohost_lower) - to_host_wr_cnt++; + tohost_lower_written = true; } else if((traits::XLEN == 32 && paddr.val == fromhost + 4) || (traits::XLEN == 64 && paddr.val == fromhost)) { uint64_t fhostvar = *reinterpret_cast(p.data() + (fromhost & mem.page_addr_mask)); *reinterpret_cast(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; @@ -1474,6 +1484,31 @@ template uint64_t riscv_hart_mu_p:: } else { csr[utval | (new_priv << 8)] = addr; } + if(semihosting_cb) { + // Check for semihosting call + phys_addr_t p_addr(access_type::DEBUG_READ, traits::MEM, addr - 4); + std::array data; + // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07 + this->read_mem(p_addr, 4, data.data()); + p_addr.val += 8; + this->read_mem(p_addr, 4, data.data() + 4); + + const std::array ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40}; + if(data == ref_data) { + this->reg.NEXT_PC = addr + 8; + + std::array buffer; +#if defined(_MSC_VER) + sprintf(buffer.data(), "0x%016llx", addr); +#else + sprintf(buffer.data(), "0x%016lx", addr); +#endif + CLOG(INFO, disass) << "Semihosting call at address " << buffer.data() << " occurred "; + + semihosting_callback(this, this->reg.X10 /*a0*/, this->reg.X11 /*a1*/); + return this->reg.NEXT_PC; + } + } break; case 4: case 6: diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 7285edd..36254f7 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -201,7 +201,6 @@ struct tgc5c: public arch_if { inline uint32_t get_last_branch() { return reg.last_branch; } - #pragma pack(push, 1) struct TGC5C_regs { uint32_t X0 = 0; diff --git a/src/iss/semihosting/semihosting.cpp b/src/iss/semihosting/semihosting.cpp new file mode 100644 index 0000000..183ae03 --- /dev/null +++ b/src/iss/semihosting/semihosting.cpp @@ -0,0 +1,22 @@ +#include "semihosting.h" +#include +#include +#include +template void semihosting_callback(iss::arch_if* arch_if_ptr, T a0, T a1) { + if(a0 == 0x04 /*WRITE0*/) { + uint8_t character; + while(1) { + auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, a1, 1, &character); + if(res != iss::Ok) + return; + if(character == 0) + break; + putchar(character); + a1++; + } + } else { + throw std::runtime_error("Not Implemented Error"); + } +} +template void semihosting_callback(iss::arch_if* arch_if_ptr, uint32_t a0, uint32_t a1); +template void semihosting_callback(iss::arch_if* arch_if_ptr, uint64_t a0, uint64_t a1); diff --git a/src/iss/semihosting/semihosting.h b/src/iss/semihosting/semihosting.h new file mode 100644 index 0000000..cf396e4 --- /dev/null +++ b/src/iss/semihosting/semihosting.h @@ -0,0 +1,6 @@ +#ifndef _SEMIHOSTING_H_ +#define _SEMIHOSTING_H_ +#include +template void semihosting_callback(iss::arch_if* arch_if_ptr, T a0, T a1); + +#endif \ No newline at end of file diff --git a/src/main.cpp b/src/main.cpp index 61f3947..aad92da 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -31,8 +31,10 @@ *******************************************************************************/ #include +#include #include #include +#include #include #include "iss/arch/tgc_mapper.h" @@ -52,7 +54,6 @@ #endif namespace po = boost::program_options; - int main(int argc, char* argv[]) { /* * Define and parse the program options @@ -116,6 +117,7 @@ int main(int argc, char* argv[]) { // instantiate the simulator iss::vm_ptr vm{nullptr}; iss::cpu_ptr cpu{nullptr}; + std::function semihosting_cb = &semihosting_callback; std::string isa_opt(clim["isa"].as()); if(isa_opt.size() == 0 || isa_opt == "?") { auto list = f.get_names(); @@ -123,7 +125,8 @@ int main(int argc, char* argv[]) { std::cout << "Available implementations (core|platform|backend):\n - " << util::join(list, "\n - ") << std::endl; return 0; } else if(isa_opt.find('|') != std::string::npos) { - std::tie(cpu, vm) = f.create(isa_opt + "|" + clim["backend"].as(), clim["gdb-port"].as()); + std::tie(cpu, vm) = + f.create(isa_opt + "|" + clim["backend"].as(), clim["gdb-port"].as(), &semihosting_cb); } else { auto base_isa = isa_opt.substr(0, 5); if(base_isa == "tgc5d" || base_isa == "tgc5e") { @@ -131,7 +134,7 @@ int main(int argc, char* argv[]) { } else { isa_opt += "|m_p|" + clim["backend"].as(); } - std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as()); + std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as(), &semihosting_cb); } if(!cpu) { LOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as() << std::endl; diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index 99419ac..10b6296 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -2695,16 +2695,24 @@ std::unique_ptr create(arch::tgc5c *core, unsigned short por namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }) }; From 075e04249ab94f23dd3eed28616847cb451f8a16 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Tue, 9 Jan 2024 12:50:41 +0100 Subject: [PATCH 03/33] adds semihosting skeleton --- src/iss/semihosting/semihosting.cpp | 676 +++++++++++++++++++++++++++- src/iss/semihosting/semihosting.h | 53 ++- 2 files changed, 719 insertions(+), 10 deletions(-) diff --git a/src/iss/semihosting/semihosting.cpp b/src/iss/semihosting/semihosting.cpp index 183ae03..02f8d65 100644 --- a/src/iss/semihosting/semihosting.cpp +++ b/src/iss/semihosting/semihosting.cpp @@ -1,22 +1,680 @@ #include "semihosting.h" -#include #include #include -template void semihosting_callback(iss::arch_if* arch_if_ptr, T a0, T a1) { - if(a0 == 0x04 /*WRITE0*/) { + +template void semihosting_callback(iss::arch_if* arch_if_ptr, T call_number, T parameter) { + switch(call_number) { + case SEMIHOSTING_ENTER_SVC: { + throw std::runtime_error("Semihosting Call not Implemented"); + } /* DEPRECATED */ + case SEMIHOSTING_SYS_CLOCK: { + /* + * Returns the number of centiseconds (hundredths of a second) + * since the execution started. + * + * Values returned can be of limited use for some benchmarking + * purposes because of communication overhead or other + * agent-specific factors. For example, with a debug hardware + * unit the request is passed back to the host for execution. + * This can lead to unpredictable delays in transmission and + * process scheduling. + * + * Use this function to calculate time intervals, by calculating + * differences between intervals with and without the code + * sequence to be timed. + * + * Entry + * The PARAMETER REGISTER must contain 0. There are no other + * parameters. + * + * Return + * On exit, the RETURN REGISTER contains: + * - The number of centiseconds since some arbitrary start + * point, if the call is successful. + * - –1 if the call is not successful. For example, because + * of a communications error. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_CLOSE: { + /* + * Closes a file on the host system. The handle must reference + * a file that was opened with SYS_OPEN. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * one-field argument block: + * - field 1 Contains a handle for an open file. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the call is successful + * - –1 if the call is not successful. + */ + + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_ELAPSED: { + /* + * Returns the number of elapsed target ticks since execution + * started. + * Use SYS_TICKFREQ to determine the tick frequency. + * + * Entry (32-bit) + * On entry, the PARAMETER REGISTER points to a two-field data + * block to be used for returning the number of elapsed ticks: + * - field 1 The least significant field and is at the low address. + * - field 2 The most significant field and is at the high address. + * + * Entry (64-bit) + * On entry the PARAMETER REGISTER points to a one-field data + * block to be used for returning the number of elapsed ticks: + * - field 1 The number of elapsed ticks as a 64-bit value. + * + * Return + * On exit: + * - On success, the RETURN REGISTER contains 0, the PARAMETER + * REGISTER is unchanged, and the data block pointed to by the + * PARAMETER REGISTER is filled in with the number of elapsed + * ticks. + * - On failure, the RETURN REGISTER contains -1, and the + * PARAMETER REGISTER contains -1. + * + * Note: Some semihosting implementations might not support this + * semihosting operation, and they always return -1 in the + * RETURN REGISTER. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_ERRNO: { + /* + * Returns the value of the C library errno variable that is + * associated with the semihosting implementation. The errno + * variable can be set by a number of C library semihosted + * functions, including: + * - SYS_REMOVE + * - SYS_OPEN + * - SYS_CLOSE + * - SYS_READ + * - SYS_WRITE + * - SYS_SEEK. + * + * Whether errno is set or not, and to what value, is entirely + * host-specific, except where the ISO C standard defines the + * behavior. + * + * Entry + * There are no parameters. The PARAMETER REGISTER must be 0. + * + * Return + * On exit, the RETURN REGISTER contains the value of the C + * library errno variable. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_EXIT: { + /* + * Note: SYS_EXIT was called angel_SWIreason_ReportException in + * previous versions of the documentation. + * + * An application calls this operation to report an exception + * to the debugger directly. The most common use is to report + * that execution has completed, using ADP_Stopped_ApplicationExit. + * + * Note: This semihosting operation provides no means for 32-bit + * callers to indicate an application exit with a specified exit + * code. Semihosting callers may prefer to check for the presence + * of the SH_EXT_EXTENDED_REPORT_EXCEPTION extension and use + * the SYS_REPORT_EXCEPTION_EXTENDED operation instead, if it + * is available. + * + * Entry (32-bit) + * On entry, the PARAMETER register is set to a reason code + * describing the cause of the trap. Not all semihosting client + * implementations will necessarily trap every corresponding + * event. Important reason codes are: + * + * - ADP_Stopped_ApplicationExit 0x20026 + * - ADP_Stopped_RunTimeErrorUnknown 0x20023 + * + * Entry (64-bit) + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field argument block: + * - field 1 The exception type, which is one of the set of + * reason codes in the above tables. + * - field 2 A subcode, whose meaning depends on the reason + * code in field 1. + * In particular, if field 1 is ADP_Stopped_ApplicationExit + * then field 2 is an exit status code, as passed to the C + * standard library exit() function. A simulator receiving + * this request must notify a connected debugger, if present, + * and then exit with the specified status. + * + * Return + * No return is expected from these calls. However, it is + * possible for the debugger to request that the application + * continues by performing an RDI_Execute request or equivalent. + * In this case, execution continues with the registers as they + * were on entry to the operation, or as subsequently modified + * by the debugger. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_EXIT_EXTENDED: { + /* + * This operation is only supported if the semihosting extension + * SH_EXT_EXIT_EXTENDED is implemented. SH_EXT_EXIT_EXTENDED is + * reported using feature byte 0, bit 0. If this extension is + * supported, then the implementation provides a means to + * report a normal exit with a nonzero exit status in both 32-bit + * and 64-bit semihosting APIs. + * + * The implementation must provide the semihosting call + * SYS_EXIT_EXTENDED for both A64 and A32/T32 semihosting APIs. + * + * SYS_EXIT_EXTENDED is used by an application to report an + * exception or exit to the debugger directly. The most common + * use is to report that execution has completed, using + * ADP_Stopped_ApplicationExit. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field argument block: + * - field 1 The exception type, which should be one of the set + * of reason codes that are documented for the SYS_EXIT + * (0x18) call. For example, ADP_Stopped_ApplicationExit. + * - field 2 A subcode, whose meaning depends on the reason + * code in field 1. In particular, if field 1 is + * ADP_Stopped_ApplicationExit then field 2 is an exit status + * code, as passed to the C standard library exit() function. + * A simulator receiving this request must notify a connected + * debugger, if present, and then exit with the specified status. + * + * Return + * No return is expected from these calls. + * + * For the A64 API, this call is identical to the behavior of + * the mandatory SYS_EXIT (0x18) call. If this extension is + * supported, then both calls must be implemented. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_FLEN: { + /* + * Returns the length of a specified file. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * one-field argument block: + * - field 1 A handle for a previously opened, seekable file + * object. + * + * Return + * On exit, the RETURN REGISTER contains: + * - The current length of the file object, if the call is + * successful. + * - –1 if an error occurs. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_GET_CMDLINE: { + /* + * Returns the command line that is used for the call to the + * executable, that is, argc and argv. + * + * Entry + * On entry, the PARAMETER REGISTER points to a two-field data + * block to be used for returning the command string and its length: + * - field 1 A pointer to a buffer of at least the size that is + * specified in field 2. + * - field 2 The length of the buffer in bytes. + * + * Return + * On exit: + * If the call is successful, then the RETURN REGISTER contains 0, + * the PARAMETER REGISTER is unchanged, and the data block is + * updated as follows: + * - field 1 A pointer to a null-terminated string of the command + * line. + * - field 2 The length of the string in bytes. + * If the call is not successful, then the RETURN REGISTER + * contains -1. + * + * Note: The semihosting implementation might impose limits on + * the maximum length of the string that can be transferred. + * However, the implementation must be able to support a + * command-line length of at least 80 bytes. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_HEAPINFO: { + /* + * Returns the system stack and heap parameters. + * + * Entry + * On entry, the PARAMETER REGISTER contains the address of a + * pointer to a four-field data block. The contents of the data + * block are filled by the function. The following C-like + * pseudocode describes the layout of the block: + * struct block { + * void* heap_base; + * void* heap_limit; + * void* stack_base; + * void* stack_limit; + * }; + * + * Return + * On exit, the PARAMETER REGISTER is unchanged and the data + * block has been updated. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_ISERROR: { + /* + * Determines whether the return code from another semihosting + * call is an error status or not. + * + * This call is passed a parameter block containing the error + * code to examine. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * one-field data block: + * - field 1 The required status word to check. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the status field is not an error indication + * - A nonzero value if the status field is an error indication. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_ISTTY: { + /* + * Checks whether a file is connected to an interactive device. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * one-field argument block: + * field 1 A handle for a previously opened file object. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 1 if the handle identifies an interactive device. + * - 0 if the handle identifies a file. + * - A value other than 1 or 0 if an error occurs. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_OPEN: { + /* + * Opens a file on the host system. + * + * The file path is specified either as relative to the current + * directory of the host process, or absolute, using the path + * conventions of the host operating system. + * + * Semihosting implementations must support opening the special + * path name :semihosting-features as part of the semihosting + * extensions reporting mechanism. + * + * ARM targets interpret the special path name :tt as meaning + * the console input stream, for an open-read or the console + * output stream, for an open-write. Opening these streams is + * performed as part of the standard startup code for those + * applications that reference the C stdio streams. The + * semihosting extension SH_EXT_STDOUT_STDERR allows the + * semihosting caller to open separate output streams + * corresponding to stdout and stderr. This extension is + * reported using feature byte 0, bit 1. Use SYS_OPEN with + * the special path name :semihosting-features to access the + * feature bits. + * + * If this extension is supported, the implementation must + * support the following additional semantics to SYS_OPEN: + * - If the special path name :tt is opened with an fopen + * mode requesting write access (w, wb, w+, or w+b), then + * this is a request to open stdout. + * - If the special path name :tt is opened with a mode + * requesting append access (a, ab, a+, or a+b), then this is + * a request to open stderr. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * three-field argument block: + * - field 1 A pointer to a null-terminated string containing + * a file or device name. + * - field 2 An integer that specifies the file opening mode. + * - field 3 An integer that gives the length of the string + * pointed to by field 1. + * + * The length does not include the terminating null character + * that must be present. + * + * Return + * On exit, the RETURN REGISTER contains: + * - A nonzero handle if the call is successful. + * - –1 if the call is not successful. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_READ: { + /* + * Reads the contents of a file into a buffer. The file position + * is specified either: + * - Explicitly by a SYS_SEEK. + * - Implicitly one byte beyond the previous SYS_READ or + * SYS_WRITE request. + * + * The file position is at the start of the file when it is + * opened, and is lost when the file is closed. Perform the + * file operation as a single action whenever possible. For + * example, do not split a read of 16KB into four 4KB chunks + * unless there is no alternative. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * three-field data block: + * - field 1 Contains a handle for a file previously opened + * with SYS_OPEN. + * - field 2 Points to a buffer. + * - field 3 Contains the number of bytes to read to the buffer + * from the file. + * + * Return + * On exit, the RETURN REGISTER contains the number of bytes not + * filled in the buffer (buffer_length - bytes_read) as follows: + * - If the RETURN REGISTER is 0, the entire buffer was + * successfully filled. + * - If the RETURN REGISTER is the same as field 3, no bytes + * were read (EOF can be assumed). + * - If the RETURN REGISTER contains a value smaller than + * field 3, the read succeeded but the buffer was only partly + * filled. For interactive devices, this is the most common + * return value. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_READC: { + /* + * Reads a byte from the console. + * + * Entry + * The PARAMETER REGISTER must contain 0. There are no other + * parameters or values possible. + * + * Return + * On exit, the RETURN REGISTER contains the byte read from + * the console. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_REMOVE: { + /* + * Deletes a specified file on the host filing system. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field argument block: + * - field 1 Points to a null-terminated string that gives the + * path name of the file to be deleted. + * - field 2 The length of the string. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the delete is successful + * - A nonzero, host-specific error code if the delete fails. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_RENAME: { + /* + * Renames a specified file. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * four-field data block: + * - field 1 A pointer to the name of the old file. + * - field 2 The length of the old filename. + * - field 3 A pointer to the new filename. + * - field 4 The length of the new filename. Both strings are + * null-terminated. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the rename is successful. + * - A nonzero, host-specific error code if the rename fails. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_SEEK: { + /* + * Seeks to a specified position in a file using an offset + * specified from the start of the file. The file is assumed + * to be a byte array and the offset is given in bytes. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field data block: + * - field 1 A handle for a seekable file object. + * - field 2 The absolute byte position to seek to. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the request is successful. + * - A negative value if the request is not successful. + * Use SYS_ERRNO to read the value of the host errno variable + * describing the error. + * + * Note: The effect of seeking outside the current extent of + * the file object is undefined. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_SYSTEM: { + /* + * Passes a command to the host command-line interpreter. + * This enables you to execute a system command such as dir, + * ls, or pwd. The terminal I/O is on the host, and is not + * visible to the target. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field argument block: + * - field 1 Points to a string to be passed to the host + * command-line interpreter. + * - field 2 The length of the string. + * + * Return + * On exit, the RETURN REGISTER contains the return status. + */ + + /* Provide SYS_SYSTEM functionality. Uses the + * libc system command, there may be a reason *NOT* + * to use this, but as I can't think of one, I + * implemented it this way. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_TICKFREQ: { + /* + * Returns the tick frequency. + * + * Entry + * The PARAMETER REGISTER must contain 0 on entry to this routine. + * + * Return + * On exit, the RETURN REGISTER contains either: + * - The number of ticks per second. + * - –1 if the target does not know the value of one tick. + * + * Note: Some semihosting implementations might not support + * this semihosting operation, and they always return -1 in the + * RETURN REGISTER. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_TIME: { + /* + * Returns the number of seconds since 00:00 January 1, 1970. + * This value is real-world time, regardless of any debug agent + * configuration. + * + * Entry + * There are no parameters. + * + * Return + * On exit, the RETURN REGISTER contains the number of seconds. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_TMPNAM: { + /* + * Returns a temporary name for a file identified by a system + * file identifier. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * three-word argument block: + * - field 1 A pointer to a buffer. + * - field 2 A target identifier for this filename. Its value + * must be an integer in the range 0-255. + * - field 3 Contains the length of the buffer. The length must + * be at least the value of L_tmpnam on the host system. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the call is successful. + * - –1 if an error occurs. + * + * The buffer pointed to by the PARAMETER REGISTER contains + * the filename, prefixed with a suitable directory name. + * If you use the same target identifier again, the same + * filename is returned. + * + * Note: The returned string must be null-terminated. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_WRITE: { + /* + * Writes the contents of a buffer to a specified file at the + * current file position. The file position is specified either: + * - Explicitly, by a SYS_SEEK. + * - Implicitly as one byte beyond the previous SYS_READ or + * SYS_WRITE request. + * + * The file position is at the start of the file when the file + * is opened, and is lost when the file is closed. + * + * Perform the file operation as a single action whenever + * possible. For example, do not split a write of 16KB into + * four 4KB chunks unless there is no alternative. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * three-field data block: + * - field 1 Contains a handle for a file previously opened + * with SYS_OPEN. + * - field 2 Points to the memory containing the data to be written. + * - field 3 Contains the number of bytes to be written from + * the buffer to the file. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the call is successful. + * - The number of bytes that are not written, if there is an error. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_WRITEC: { + /* + * Writes a character byte, pointed to by the PARAMETER REGISTER, + * to the debug channel. When executed under a semihosting + * debugger, the character appears on the host debugger console. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to the + * character. + * + * Return + * None. The RETURN REGISTER is corrupted. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } + case SEMIHOSTING_SYS_WRITE0: { + /* + * Writes a null-terminated string to the debug channel. + * When executed under a semihosting debugger, the characters + * appear on the host debugger console. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to the + * first byte of the string. + * + * Return + * None. The RETURN REGISTER is corrupted. + */ + uint8_t character; while(1) { - auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, a1, 1, &character); + auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, parameter, 1, &character); if(res != iss::Ok) return; if(character == 0) break; putchar(character); - a1++; + parameter++; } - } else { - throw std::runtime_error("Not Implemented Error"); + } + case SEMIHOSTING_USER_CMD_0x100: { + /** + * + * This is a user defined operation (while user cmds 0x100-0x1ff + * are possible, none are currently implemented). + * + * Reads the user operation parameters from target, then fires the + * corresponding target event. When the target callbacks returned, + * cleans up the command parameter buffer. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field data block: + * - field 1 Contains a pointer to the bound command parameter + * string + * - field 2 Contains the command parameter string length + * + * Return + * On exit, the RETURN REGISTER contains the return status. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } /* First user cmd op code */ + + case SEMIHOSTING_USER_CMD_0x1FF: { + /** + * + * This is a user defined operation (while user cmds 0x100-0x1ff + * are possible, none are currently implemented). + * + * Reads the user operation parameters from target, then fires the + * corresponding target event. When the target callbacks returned, + * cleans up the command parameter buffer. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field data block: + * - field 1 Contains a pointer to the bound command parameter + * string + * - field 2 Contains the command parameter string length + * + * Return + * On exit, the RETURN REGISTER contains the return status. + */ + throw std::runtime_error("Semihosting Call not Implemented"); + } /* Last user cmd op code */ + default: + throw std::runtime_error("Semihosting Call not Implemented"); } } -template void semihosting_callback(iss::arch_if* arch_if_ptr, uint32_t a0, uint32_t a1); -template void semihosting_callback(iss::arch_if* arch_if_ptr, uint64_t a0, uint64_t a1); +template void semihosting_callback(iss::arch_if* arch_if_ptr, uint32_t call_number, uint32_t parameter); +template void semihosting_callback(iss::arch_if* arch_if_ptr, uint64_t call_number, uint64_t parameter); diff --git a/src/iss/semihosting/semihosting.h b/src/iss/semihosting/semihosting.h index cf396e4..ea6a5c6 100644 --- a/src/iss/semihosting/semihosting.h +++ b/src/iss/semihosting/semihosting.h @@ -1,6 +1,57 @@ #ifndef _SEMIHOSTING_H_ #define _SEMIHOSTING_H_ #include -template void semihosting_callback(iss::arch_if* arch_if_ptr, T a0, T a1); +/* + * According to: + * "Semihosting for AArch32 and AArch64, Release 2.0" + * https://static.docs.arm.com/100863/0200/semihosting.pdf + * from ARM Ltd. + * + * The available semihosting operation numbers passed in R0 are allocated + * as follows: + * - 0x00-0x31 Used by ARM. + * - 0x32-0xFF Reserved for future use by ARM. + * - 0x100-0x1FF Reserved for user applications. These are not used by ARM. + * However, if you are writing your own SVC operations, you are advised + * to use a different SVC number rather than using the semihosted + * SVC number and these operation type numbers. + * - 0x200-0xFFFFFFFF Undefined and currently unused. It is recommended + * that you do not use these. + */ +enum semihosting_operation_numbers { + /* + * ARM semihosting operations, in lexicographic order. + */ + SEMIHOSTING_ENTER_SVC = 0x17, /* DEPRECATED */ + + SEMIHOSTING_SYS_CLOCK = 0x10, + SEMIHOSTING_SYS_CLOSE = 0x02, + SEMIHOSTING_SYS_ELAPSED = 0x30, + SEMIHOSTING_SYS_ERRNO = 0x13, + SEMIHOSTING_SYS_EXIT = 0x18, + SEMIHOSTING_SYS_EXIT_EXTENDED = 0x20, + SEMIHOSTING_SYS_FLEN = 0x0C, + SEMIHOSTING_SYS_GET_CMDLINE = 0x15, + SEMIHOSTING_SYS_HEAPINFO = 0x16, + SEMIHOSTING_SYS_ISERROR = 0x08, + SEMIHOSTING_SYS_ISTTY = 0x09, + SEMIHOSTING_SYS_OPEN = 0x01, + SEMIHOSTING_SYS_READ = 0x06, + SEMIHOSTING_SYS_READC = 0x07, + SEMIHOSTING_SYS_REMOVE = 0x0E, + SEMIHOSTING_SYS_RENAME = 0x0F, + SEMIHOSTING_SYS_SEEK = 0x0A, + SEMIHOSTING_SYS_SYSTEM = 0x12, + SEMIHOSTING_SYS_TICKFREQ = 0x31, + SEMIHOSTING_SYS_TIME = 0x11, + SEMIHOSTING_SYS_TMPNAM = 0x0D, + SEMIHOSTING_SYS_WRITE = 0x05, + SEMIHOSTING_SYS_WRITEC = 0x03, + SEMIHOSTING_SYS_WRITE0 = 0x04, + SEMIHOSTING_USER_CMD_0x100 = 0x100, /* First user cmd op code */ + SEMIHOSTING_USER_CMD_0x1FF = 0x1FF, /* Last user cmd op code */ +}; + +template void semihosting_callback(iss::arch_if* arch_if_ptr, T call_number, T parameter); #endif \ No newline at end of file From db5765b3429efd6674e349ab5a6cd2b8b258dd1a Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Wed, 10 Jan 2024 09:36:42 +0100 Subject: [PATCH 04/33] makes softfloat always a static library --- softfloat/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/softfloat/CMakeLists.txt b/softfloat/CMakeLists.txt index b2ff9df..b5766c6 100644 --- a/softfloat/CMakeLists.txt +++ b/softfloat/CMakeLists.txt @@ -327,7 +327,7 @@ set(OTHERS set(LIB_SOURCES ${PRIMITIVES} ${SPECIALIZE} ${OTHERS}) -add_library(softfloat ${LIB_SOURCES}) +add_library(softfloat STATIC ${LIB_SOURCES}) set_property(TARGET softfloat PROPERTY C_STANDARD 99) target_compile_definitions(softfloat PRIVATE SOFTFLOAT_ROUND_ODD @@ -347,7 +347,7 @@ set_target_properties(softfloat PROPERTIES install(TARGETS softfloat EXPORT ${PROJECT_NAME}Targets # for downstream dependencies - ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # static lib + ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}/static COMPONENT libs # static lib LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # shared lib FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} COMPONENT devel # headers for mac (note the different component -> different package) From 3ff59ba45d7793b791cacba3d89ecdc8ccfe5fa4 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Wed, 10 Jan 2024 10:15:05 +0100 Subject: [PATCH 05/33] small refactor, adds baisc functionality --- src/iss/semihosting/semihosting.cpp | 690 +++------------------------- src/iss/semihosting/semihosting.h | 60 ++- 2 files changed, 99 insertions(+), 651 deletions(-) diff --git a/src/iss/semihosting/semihosting.cpp b/src/iss/semihosting/semihosting.cpp index 02f8d65..00124fb 100644 --- a/src/iss/semihosting/semihosting.cpp +++ b/src/iss/semihosting/semihosting.cpp @@ -1,621 +1,108 @@ #include "semihosting.h" +#include #include #include - +// explanation of syscalls can be found at https://github.com/SpinalHDL/openocd_riscv/blob/riscv_spinal/src/target/semihosting_common.h template void semihosting_callback(iss::arch_if* arch_if_ptr, T call_number, T parameter) { - switch(call_number) { - case SEMIHOSTING_ENTER_SVC: { - throw std::runtime_error("Semihosting Call not Implemented"); - } /* DEPRECATED */ - case SEMIHOSTING_SYS_CLOCK: { - /* - * Returns the number of centiseconds (hundredths of a second) - * since the execution started. - * - * Values returned can be of limited use for some benchmarking - * purposes because of communication overhead or other - * agent-specific factors. For example, with a debug hardware - * unit the request is passed back to the host for execution. - * This can lead to unpredictable delays in transmission and - * process scheduling. - * - * Use this function to calculate time intervals, by calculating - * differences between intervals with and without the code - * sequence to be timed. - * - * Entry - * The PARAMETER REGISTER must contain 0. There are no other - * parameters. - * - * Return - * On exit, the RETURN REGISTER contains: - * - The number of centiseconds since some arbitrary start - * point, if the call is successful. - * - –1 if the call is not successful. For example, because - * of a communications error. - */ + switch(static_cast(call_number)) { + case semihosting_syscalls::SYS_CLOCK: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_CLOSE: { - /* - * Closes a file on the host system. The handle must reference - * a file that was opened with SYS_OPEN. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * one-field argument block: - * - field 1 Contains a handle for an open file. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the call is successful - * - –1 if the call is not successful. - */ + case semihosting_syscalls::SYS_CLOSE: { + throw std::runtime_error("Semihosting Call not Implemented"); + break; + } + case semihosting_syscalls::SYS_ELAPSED: { + throw std::runtime_error("Semihosting Call not Implemented"); + break; + } + case semihosting_syscalls::SYS_ERRNO: { + throw std::runtime_error("Semihosting Call not Implemented"); + break; + } + case semihosting_syscalls::SYS_EXIT: { - throw std::runtime_error("Semihosting Call not Implemented"); + throw std::runtime_error("ISS terminated by Semihost: SYS_EXIT"); + break; } - case SEMIHOSTING_SYS_ELAPSED: { - /* - * Returns the number of elapsed target ticks since execution - * started. - * Use SYS_TICKFREQ to determine the tick frequency. - * - * Entry (32-bit) - * On entry, the PARAMETER REGISTER points to a two-field data - * block to be used for returning the number of elapsed ticks: - * - field 1 The least significant field and is at the low address. - * - field 2 The most significant field and is at the high address. - * - * Entry (64-bit) - * On entry the PARAMETER REGISTER points to a one-field data - * block to be used for returning the number of elapsed ticks: - * - field 1 The number of elapsed ticks as a 64-bit value. - * - * Return - * On exit: - * - On success, the RETURN REGISTER contains 0, the PARAMETER - * REGISTER is unchanged, and the data block pointed to by the - * PARAMETER REGISTER is filled in with the number of elapsed - * ticks. - * - On failure, the RETURN REGISTER contains -1, and the - * PARAMETER REGISTER contains -1. - * - * Note: Some semihosting implementations might not support this - * semihosting operation, and they always return -1 in the - * RETURN REGISTER. - */ - throw std::runtime_error("Semihosting Call not Implemented"); + case semihosting_syscalls::SYS_EXIT_EXTENDED: { + throw std::runtime_error("ISS terminated by Semihost: SYS_EXIT_EXTENDED"); + break; } - case SEMIHOSTING_SYS_ERRNO: { - /* - * Returns the value of the C library errno variable that is - * associated with the semihosting implementation. The errno - * variable can be set by a number of C library semihosted - * functions, including: - * - SYS_REMOVE - * - SYS_OPEN - * - SYS_CLOSE - * - SYS_READ - * - SYS_WRITE - * - SYS_SEEK. - * - * Whether errno is set or not, and to what value, is entirely - * host-specific, except where the ISO C standard defines the - * behavior. - * - * Entry - * There are no parameters. The PARAMETER REGISTER must be 0. - * - * Return - * On exit, the RETURN REGISTER contains the value of the C - * library errno variable. - */ + case semihosting_syscalls::SYS_FLEN: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_EXIT: { - /* - * Note: SYS_EXIT was called angel_SWIreason_ReportException in - * previous versions of the documentation. - * - * An application calls this operation to report an exception - * to the debugger directly. The most common use is to report - * that execution has completed, using ADP_Stopped_ApplicationExit. - * - * Note: This semihosting operation provides no means for 32-bit - * callers to indicate an application exit with a specified exit - * code. Semihosting callers may prefer to check for the presence - * of the SH_EXT_EXTENDED_REPORT_EXCEPTION extension and use - * the SYS_REPORT_EXCEPTION_EXTENDED operation instead, if it - * is available. - * - * Entry (32-bit) - * On entry, the PARAMETER register is set to a reason code - * describing the cause of the trap. Not all semihosting client - * implementations will necessarily trap every corresponding - * event. Important reason codes are: - * - * - ADP_Stopped_ApplicationExit 0x20026 - * - ADP_Stopped_RunTimeErrorUnknown 0x20023 - * - * Entry (64-bit) - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field argument block: - * - field 1 The exception type, which is one of the set of - * reason codes in the above tables. - * - field 2 A subcode, whose meaning depends on the reason - * code in field 1. - * In particular, if field 1 is ADP_Stopped_ApplicationExit - * then field 2 is an exit status code, as passed to the C - * standard library exit() function. A simulator receiving - * this request must notify a connected debugger, if present, - * and then exit with the specified status. - * - * Return - * No return is expected from these calls. However, it is - * possible for the debugger to request that the application - * continues by performing an RDI_Execute request or equivalent. - * In this case, execution continues with the registers as they - * were on entry to the operation, or as subsequently modified - * by the debugger. - */ + case semihosting_syscalls::SYS_GET_CMDLINE: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_EXIT_EXTENDED: { - /* - * This operation is only supported if the semihosting extension - * SH_EXT_EXIT_EXTENDED is implemented. SH_EXT_EXIT_EXTENDED is - * reported using feature byte 0, bit 0. If this extension is - * supported, then the implementation provides a means to - * report a normal exit with a nonzero exit status in both 32-bit - * and 64-bit semihosting APIs. - * - * The implementation must provide the semihosting call - * SYS_EXIT_EXTENDED for both A64 and A32/T32 semihosting APIs. - * - * SYS_EXIT_EXTENDED is used by an application to report an - * exception or exit to the debugger directly. The most common - * use is to report that execution has completed, using - * ADP_Stopped_ApplicationExit. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field argument block: - * - field 1 The exception type, which should be one of the set - * of reason codes that are documented for the SYS_EXIT - * (0x18) call. For example, ADP_Stopped_ApplicationExit. - * - field 2 A subcode, whose meaning depends on the reason - * code in field 1. In particular, if field 1 is - * ADP_Stopped_ApplicationExit then field 2 is an exit status - * code, as passed to the C standard library exit() function. - * A simulator receiving this request must notify a connected - * debugger, if present, and then exit with the specified status. - * - * Return - * No return is expected from these calls. - * - * For the A64 API, this call is identical to the behavior of - * the mandatory SYS_EXIT (0x18) call. If this extension is - * supported, then both calls must be implemented. - */ + case semihosting_syscalls::SYS_HEAPINFO: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_FLEN: { - /* - * Returns the length of a specified file. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * one-field argument block: - * - field 1 A handle for a previously opened, seekable file - * object. - * - * Return - * On exit, the RETURN REGISTER contains: - * - The current length of the file object, if the call is - * successful. - * - –1 if an error occurs. - */ + case semihosting_syscalls::SYS_ISERROR: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_GET_CMDLINE: { - /* - * Returns the command line that is used for the call to the - * executable, that is, argc and argv. - * - * Entry - * On entry, the PARAMETER REGISTER points to a two-field data - * block to be used for returning the command string and its length: - * - field 1 A pointer to a buffer of at least the size that is - * specified in field 2. - * - field 2 The length of the buffer in bytes. - * - * Return - * On exit: - * If the call is successful, then the RETURN REGISTER contains 0, - * the PARAMETER REGISTER is unchanged, and the data block is - * updated as follows: - * - field 1 A pointer to a null-terminated string of the command - * line. - * - field 2 The length of the string in bytes. - * If the call is not successful, then the RETURN REGISTER - * contains -1. - * - * Note: The semihosting implementation might impose limits on - * the maximum length of the string that can be transferred. - * However, the implementation must be able to support a - * command-line length of at least 80 bytes. - */ + case semihosting_syscalls::SYS_ISTTY: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_HEAPINFO: { - /* - * Returns the system stack and heap parameters. - * - * Entry - * On entry, the PARAMETER REGISTER contains the address of a - * pointer to a four-field data block. The contents of the data - * block are filled by the function. The following C-like - * pseudocode describes the layout of the block: - * struct block { - * void* heap_base; - * void* heap_limit; - * void* stack_base; - * void* stack_limit; - * }; - * - * Return - * On exit, the PARAMETER REGISTER is unchanged and the data - * block has been updated. - */ + case semihosting_syscalls::SYS_OPEN: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_ISERROR: { - /* - * Determines whether the return code from another semihosting - * call is an error status or not. - * - * This call is passed a parameter block containing the error - * code to examine. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * one-field data block: - * - field 1 The required status word to check. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the status field is not an error indication - * - A nonzero value if the status field is an error indication. - */ + case semihosting_syscalls::SYS_READ: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_ISTTY: { - /* - * Checks whether a file is connected to an interactive device. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * one-field argument block: - * field 1 A handle for a previously opened file object. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 1 if the handle identifies an interactive device. - * - 0 if the handle identifies a file. - * - A value other than 1 or 0 if an error occurs. - */ + case semihosting_syscalls::SYS_READC: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_OPEN: { - /* - * Opens a file on the host system. - * - * The file path is specified either as relative to the current - * directory of the host process, or absolute, using the path - * conventions of the host operating system. - * - * Semihosting implementations must support opening the special - * path name :semihosting-features as part of the semihosting - * extensions reporting mechanism. - * - * ARM targets interpret the special path name :tt as meaning - * the console input stream, for an open-read or the console - * output stream, for an open-write. Opening these streams is - * performed as part of the standard startup code for those - * applications that reference the C stdio streams. The - * semihosting extension SH_EXT_STDOUT_STDERR allows the - * semihosting caller to open separate output streams - * corresponding to stdout and stderr. This extension is - * reported using feature byte 0, bit 1. Use SYS_OPEN with - * the special path name :semihosting-features to access the - * feature bits. - * - * If this extension is supported, the implementation must - * support the following additional semantics to SYS_OPEN: - * - If the special path name :tt is opened with an fopen - * mode requesting write access (w, wb, w+, or w+b), then - * this is a request to open stdout. - * - If the special path name :tt is opened with a mode - * requesting append access (a, ab, a+, or a+b), then this is - * a request to open stderr. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * three-field argument block: - * - field 1 A pointer to a null-terminated string containing - * a file or device name. - * - field 2 An integer that specifies the file opening mode. - * - field 3 An integer that gives the length of the string - * pointed to by field 1. - * - * The length does not include the terminating null character - * that must be present. - * - * Return - * On exit, the RETURN REGISTER contains: - * - A nonzero handle if the call is successful. - * - –1 if the call is not successful. - */ + case semihosting_syscalls::SYS_REMOVE: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_READ: { - /* - * Reads the contents of a file into a buffer. The file position - * is specified either: - * - Explicitly by a SYS_SEEK. - * - Implicitly one byte beyond the previous SYS_READ or - * SYS_WRITE request. - * - * The file position is at the start of the file when it is - * opened, and is lost when the file is closed. Perform the - * file operation as a single action whenever possible. For - * example, do not split a read of 16KB into four 4KB chunks - * unless there is no alternative. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * three-field data block: - * - field 1 Contains a handle for a file previously opened - * with SYS_OPEN. - * - field 2 Points to a buffer. - * - field 3 Contains the number of bytes to read to the buffer - * from the file. - * - * Return - * On exit, the RETURN REGISTER contains the number of bytes not - * filled in the buffer (buffer_length - bytes_read) as follows: - * - If the RETURN REGISTER is 0, the entire buffer was - * successfully filled. - * - If the RETURN REGISTER is the same as field 3, no bytes - * were read (EOF can be assumed). - * - If the RETURN REGISTER contains a value smaller than - * field 3, the read succeeded but the buffer was only partly - * filled. For interactive devices, this is the most common - * return value. - */ + case semihosting_syscalls::SYS_RENAME: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_READC: { - /* - * Reads a byte from the console. - * - * Entry - * The PARAMETER REGISTER must contain 0. There are no other - * parameters or values possible. - * - * Return - * On exit, the RETURN REGISTER contains the byte read from - * the console. - */ + case semihosting_syscalls::SYS_SEEK: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_REMOVE: { - /* - * Deletes a specified file on the host filing system. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field argument block: - * - field 1 Points to a null-terminated string that gives the - * path name of the file to be deleted. - * - field 2 The length of the string. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the delete is successful - * - A nonzero, host-specific error code if the delete fails. - */ + case semihosting_syscalls::SYS_SYSTEM: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_RENAME: { - /* - * Renames a specified file. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * four-field data block: - * - field 1 A pointer to the name of the old file. - * - field 2 The length of the old filename. - * - field 3 A pointer to the new filename. - * - field 4 The length of the new filename. Both strings are - * null-terminated. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the rename is successful. - * - A nonzero, host-specific error code if the rename fails. - */ + case semihosting_syscalls::SYS_TICKFREQ: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_SEEK: { - /* - * Seeks to a specified position in a file using an offset - * specified from the start of the file. The file is assumed - * to be a byte array and the offset is given in bytes. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field data block: - * - field 1 A handle for a seekable file object. - * - field 2 The absolute byte position to seek to. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the request is successful. - * - A negative value if the request is not successful. - * Use SYS_ERRNO to read the value of the host errno variable - * describing the error. - * - * Note: The effect of seeking outside the current extent of - * the file object is undefined. - */ + case semihosting_syscalls::SYS_TIME: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_SYSTEM: { - /* - * Passes a command to the host command-line interpreter. - * This enables you to execute a system command such as dir, - * ls, or pwd. The terminal I/O is on the host, and is not - * visible to the target. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field argument block: - * - field 1 Points to a string to be passed to the host - * command-line interpreter. - * - field 2 The length of the string. - * - * Return - * On exit, the RETURN REGISTER contains the return status. - */ - - /* Provide SYS_SYSTEM functionality. Uses the - * libc system command, there may be a reason *NOT* - * to use this, but as I can't think of one, I - * implemented it this way. - */ + case semihosting_syscalls::SYS_TMPNAM: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_TICKFREQ: { - /* - * Returns the tick frequency. - * - * Entry - * The PARAMETER REGISTER must contain 0 on entry to this routine. - * - * Return - * On exit, the RETURN REGISTER contains either: - * - The number of ticks per second. - * - –1 if the target does not know the value of one tick. - * - * Note: Some semihosting implementations might not support - * this semihosting operation, and they always return -1 in the - * RETURN REGISTER. - */ + case semihosting_syscalls::SYS_WRITE: { throw std::runtime_error("Semihosting Call not Implemented"); + break; } - case SEMIHOSTING_SYS_TIME: { - /* - * Returns the number of seconds since 00:00 January 1, 1970. - * This value is real-world time, regardless of any debug agent - * configuration. - * - * Entry - * There are no parameters. - * - * Return - * On exit, the RETURN REGISTER contains the number of seconds. - */ - throw std::runtime_error("Semihosting Call not Implemented"); + case semihosting_syscalls::SYS_WRITEC: { + uint8_t character; + auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, parameter, 1, &character); + if(res != iss::Ok) + return; + putchar(character); + break; } - case SEMIHOSTING_SYS_TMPNAM: { - /* - * Returns a temporary name for a file identified by a system - * file identifier. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * three-word argument block: - * - field 1 A pointer to a buffer. - * - field 2 A target identifier for this filename. Its value - * must be an integer in the range 0-255. - * - field 3 Contains the length of the buffer. The length must - * be at least the value of L_tmpnam on the host system. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the call is successful. - * - –1 if an error occurs. - * - * The buffer pointed to by the PARAMETER REGISTER contains - * the filename, prefixed with a suitable directory name. - * If you use the same target identifier again, the same - * filename is returned. - * - * Note: The returned string must be null-terminated. - */ - throw std::runtime_error("Semihosting Call not Implemented"); - } - case SEMIHOSTING_SYS_WRITE: { - /* - * Writes the contents of a buffer to a specified file at the - * current file position. The file position is specified either: - * - Explicitly, by a SYS_SEEK. - * - Implicitly as one byte beyond the previous SYS_READ or - * SYS_WRITE request. - * - * The file position is at the start of the file when the file - * is opened, and is lost when the file is closed. - * - * Perform the file operation as a single action whenever - * possible. For example, do not split a write of 16KB into - * four 4KB chunks unless there is no alternative. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * three-field data block: - * - field 1 Contains a handle for a file previously opened - * with SYS_OPEN. - * - field 2 Points to the memory containing the data to be written. - * - field 3 Contains the number of bytes to be written from - * the buffer to the file. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the call is successful. - * - The number of bytes that are not written, if there is an error. - */ - throw std::runtime_error("Semihosting Call not Implemented"); - } - case SEMIHOSTING_SYS_WRITEC: { - /* - * Writes a character byte, pointed to by the PARAMETER REGISTER, - * to the debug channel. When executed under a semihosting - * debugger, the character appears on the host debugger console. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to the - * character. - * - * Return - * None. The RETURN REGISTER is corrupted. - */ - throw std::runtime_error("Semihosting Call not Implemented"); - } - case SEMIHOSTING_SYS_WRITE0: { - /* - * Writes a null-terminated string to the debug channel. - * When executed under a semihosting debugger, the characters - * appear on the host debugger console. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to the - * first byte of the string. - * - * Return - * None. The RETURN REGISTER is corrupted. - */ - + case semihosting_syscalls::SYS_WRITE0: { uint8_t character; while(1) { auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, parameter, 1, &character); @@ -626,54 +113,19 @@ template void semihosting_callback(iss::arch_if* arch_if_ptr, T cal putchar(character); parameter++; } + break; } - case SEMIHOSTING_USER_CMD_0x100: { - /** - * - * This is a user defined operation (while user cmds 0x100-0x1ff - * are possible, none are currently implemented). - * - * Reads the user operation parameters from target, then fires the - * corresponding target event. When the target callbacks returned, - * cleans up the command parameter buffer. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field data block: - * - field 1 Contains a pointer to the bound command parameter - * string - * - field 2 Contains the command parameter string length - * - * Return - * On exit, the RETURN REGISTER contains the return status. - */ + case semihosting_syscalls::USER_CMD_0x100: { throw std::runtime_error("Semihosting Call not Implemented"); - } /* First user cmd op code */ - - case SEMIHOSTING_USER_CMD_0x1FF: { - /** - * - * This is a user defined operation (while user cmds 0x100-0x1ff - * are possible, none are currently implemented). - * - * Reads the user operation parameters from target, then fires the - * corresponding target event. When the target callbacks returned, - * cleans up the command parameter buffer. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field data block: - * - field 1 Contains a pointer to the bound command parameter - * string - * - field 2 Contains the command parameter string length - * - * Return - * On exit, the RETURN REGISTER contains the return status. - */ + break; + } + case semihosting_syscalls::USER_CMD_0x1FF: { throw std::runtime_error("Semihosting Call not Implemented"); - } /* Last user cmd op code */ + break; + } default: throw std::runtime_error("Semihosting Call not Implemented"); + break; } } template void semihosting_callback(iss::arch_if* arch_if_ptr, uint32_t call_number, uint32_t parameter); diff --git a/src/iss/semihosting/semihosting.h b/src/iss/semihosting/semihosting.h index ea6a5c6..e551f78 100644 --- a/src/iss/semihosting/semihosting.h +++ b/src/iss/semihosting/semihosting.h @@ -7,7 +7,7 @@ * https://static.docs.arm.com/100863/0200/semihosting.pdf * from ARM Ltd. * - * The available semihosting operation numbers passed in R0 are allocated + * The available semihosting operation numbers passed in A0 are allocated * as follows: * - 0x00-0x31 Used by ARM. * - 0x32-0xFF Reserved for future use by ARM. @@ -18,38 +18,34 @@ * - 0x200-0xFFFFFFFF Undefined and currently unused. It is recommended * that you do not use these. */ -enum semihosting_operation_numbers { - /* - * ARM semihosting operations, in lexicographic order. - */ - SEMIHOSTING_ENTER_SVC = 0x17, /* DEPRECATED */ +enum class semihosting_syscalls { - SEMIHOSTING_SYS_CLOCK = 0x10, - SEMIHOSTING_SYS_CLOSE = 0x02, - SEMIHOSTING_SYS_ELAPSED = 0x30, - SEMIHOSTING_SYS_ERRNO = 0x13, - SEMIHOSTING_SYS_EXIT = 0x18, - SEMIHOSTING_SYS_EXIT_EXTENDED = 0x20, - SEMIHOSTING_SYS_FLEN = 0x0C, - SEMIHOSTING_SYS_GET_CMDLINE = 0x15, - SEMIHOSTING_SYS_HEAPINFO = 0x16, - SEMIHOSTING_SYS_ISERROR = 0x08, - SEMIHOSTING_SYS_ISTTY = 0x09, - SEMIHOSTING_SYS_OPEN = 0x01, - SEMIHOSTING_SYS_READ = 0x06, - SEMIHOSTING_SYS_READC = 0x07, - SEMIHOSTING_SYS_REMOVE = 0x0E, - SEMIHOSTING_SYS_RENAME = 0x0F, - SEMIHOSTING_SYS_SEEK = 0x0A, - SEMIHOSTING_SYS_SYSTEM = 0x12, - SEMIHOSTING_SYS_TICKFREQ = 0x31, - SEMIHOSTING_SYS_TIME = 0x11, - SEMIHOSTING_SYS_TMPNAM = 0x0D, - SEMIHOSTING_SYS_WRITE = 0x05, - SEMIHOSTING_SYS_WRITEC = 0x03, - SEMIHOSTING_SYS_WRITE0 = 0x04, - SEMIHOSTING_USER_CMD_0x100 = 0x100, /* First user cmd op code */ - SEMIHOSTING_USER_CMD_0x1FF = 0x1FF, /* Last user cmd op code */ + SYS_OPEN = 0x01, + SYS_CLOSE = 0x02, + SYS_WRITEC = 0x03, + SYS_WRITE0 = 0x04, + SYS_WRITE = 0x05, + SYS_READ = 0x06, + SYS_READC = 0x07, + SYS_ISERROR = 0x08, + SYS_ISTTY = 0x09, + SYS_SEEK = 0x0A, + SYS_FLEN = 0x0C, + SYS_TMPNAM = 0x0D, + SYS_REMOVE = 0x0E, + SYS_RENAME = 0x0F, + SYS_CLOCK = 0x10, + SYS_TIME = 0x11, + SYS_SYSTEM = 0x12, + SYS_ERRNO = 0x13, + SYS_GET_CMDLINE = 0x15, + SYS_HEAPINFO = 0x16, + SYS_EXIT = 0x18, + SYS_EXIT_EXTENDED = 0x20, + SYS_ELAPSED = 0x30, + SYS_TICKFREQ = 0x31, + USER_CMD_0x100 = 0x100, + USER_CMD_0x1FF = 0x1FF, }; template void semihosting_callback(iss::arch_if* arch_if_ptr, T call_number, T parameter); From fe2d5cb2f99c5e4cb1609db627c3a68435f0b40a Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Wed, 10 Jan 2024 11:47:12 +0100 Subject: [PATCH 06/33] adds semihosting to all backends --- gen_input/templates/asmjit/CORENAME.cpp.gtl | 8 +- gen_input/templates/interp/CORENAME.cpp.gtl | 4 +- gen_input/templates/llvm/CORENAME.cpp.gtl | 8 +- gen_input/templates/tcc/CORENAME.cpp.gtl | 12 +- src/iss/arch/tgc5c.h | 1 + src/vm/asmjit/vm_tgc5c.cpp | 20 +- src/vm/llvm/vm_tgc5c.cpp | 5244 ++++++++++--------- src/vm/tcc/vm_tgc5c.cpp | 3841 +++++++------- 8 files changed, 4961 insertions(+), 4177 deletions(-) diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 4dfc294..863628c 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -263,9 +263,9 @@ std::unique_ptr create(arch::${coreD namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); - auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); @@ -273,9 +273,9 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index 099b638..e8062c8 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -363,7 +363,7 @@ std::unique_ptr create(arch::${coreD namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); @@ -373,7 +373,7 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); diff --git a/gen_input/templates/llvm/CORENAME.cpp.gtl b/gen_input/templates/llvm/CORENAME.cpp.gtl index da04ae1..d31802f 100644 --- a/gen_input/templates/llvm/CORENAME.cpp.gtl +++ b/gen_input/templates/llvm/CORENAME.cpp.gtl @@ -365,9 +365,9 @@ std::unique_ptr create(arch::${coreD namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); - auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); @@ -375,9 +375,9 @@ volatile std::array dummy = { } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); + auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); diff --git a/gen_input/templates/tcc/CORENAME.cpp.gtl b/gen_input/templates/tcc/CORENAME.cpp.gtl index 252df3d..5ac57ae 100644 --- a/gen_input/templates/tcc/CORENAME.cpp.gtl +++ b/gen_input/templates/tcc/CORENAME.cpp.gtl @@ -329,16 +329,24 @@ std::unique_ptr create(arch::${coreD namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }) }; diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 36254f7..7285edd 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -201,6 +201,7 @@ struct tgc5c: public arch_if { inline uint32_t get_last_branch() { return reg.last_branch; } + #pragma pack(push, 1) struct TGC5C_regs { uint32_t X0 = 0; diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index c9656ae..497cc1e 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -3752,16 +3752,24 @@ std::unique_ptr create(arch::tgc5c *core, unsigned short por namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("tgc5c|m_p|asmjit", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("tgc5c|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_m_p(); - auto* vm = new asmjit::tgc5c::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); + auto vm = new asmjit::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }), - core_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned port, void*) -> std::tuple{ + core_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple{ auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto* vm = new asmjit::tgc5c::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); + auto vm = new asmjit::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } return {cpu_ptr{cpu}, vm_ptr{vm}}; }) }; diff --git a/src/vm/llvm/vm_tgc5c.cpp b/src/vm/llvm/vm_tgc5c.cpp index 94fe033..5447fa1 100644 --- a/src/vm/llvm/vm_tgc5c.cpp +++ b/src/vm/llvm/vm_tgc5c.cpp @@ -29,7 +29,7 @@ * POSSIBILITY OF SUCH DAMAGE. * *******************************************************************************/ - +// clang-format off #include #include #include @@ -48,7 +48,7 @@ namespace iss { namespace llvm { namespace fp_impl { -void add_fp_functions_2_module(::llvm::Module*, unsigned, unsigned); +void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned); } namespace tgc5c { @@ -67,13 +67,13 @@ public: vm_impl(); - vm_impl(ARCH& core, unsigned core_id = 0, unsigned cluster_id = 0); + vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } - target_adapter_if* accquire_target_adapter(server_if* srv) override { + target_adapter_if *accquire_target_adapter(server_if *srv) override { debugger_if::dbg_enabled = true; - if(vm_base::tgt_adapter == nullptr) + if (vm_base::tgt_adapter == nullptr) vm_base::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); return vm_base::tgt_adapter; } @@ -81,9 +81,9 @@ public: protected: using vm_base::get_reg_ptr; - inline const char* name(size_t index) { return traits::reg_aliases.at(index); } + inline const char *name(size_t index){return traits::reg_aliases.at(index);} - template inline ConstantInt* size(T type) { + template inline ConstantInt *size(T type) { return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits())); } @@ -92,13 +92,13 @@ protected: iss::llvm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE, traits::XLEN); } - inline Value* gen_choose(Value* cond, Value* trueVal, Value* falseVal, unsigned size) { + inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) { return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size)); } - std::tuple gen_single_inst_behavior(virt_addr_t&, unsigned int&, BasicBlock*) override; + std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override; - void gen_leave_behavior(BasicBlock* leave_blk) override; + void gen_leave_behavior(BasicBlock *leave_blk) override; void gen_raise_trap(uint16_t trap_id, uint16_t cause); @@ -106,28 +106,32 @@ protected: void gen_wait(unsigned type); - void gen_trap_behavior(BasicBlock*) override; + void gen_trap_behavior(BasicBlock *) override; - void gen_trap_check(BasicBlock* bb); + void gen_trap_check(BasicBlock *bb); - inline Value* gen_reg_load(unsigned i, unsigned level = 0) { + inline Value *gen_reg_load(unsigned i, unsigned level = 0) { return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false); } inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) { - Value* next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), this->get_type(traits::XLEN)); + Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), + this->get_type(traits::XLEN)); this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true); } // some compile time constants using this_class = vm_impl; - using compile_func = std::tuple (this_class::*)(virt_addr_t& pc, code_word_t instr, BasicBlock* bb); - template ::type> inline S sext(U from) { - auto mask = (1ULL << W) - 1; - auto sign_mask = 1ULL << (W - 1); + using compile_func = std::tuple (this_class::*)(virt_addr_t &pc, + code_word_t instr, + BasicBlock *bb); + template::type> + inline S sext(U from) { + auto mask = (1ULL< instrs; std::vector children; uint32_t submask = std::numeric_limits::max(); uint32_t value; - decoding_tree_node(uint32_t value) - : value(value) {} + decoding_tree_node(uint32_t value) : value(value){} }; - decoding_tree_node* root{nullptr}; + decoding_tree_node* root {nullptr}; const std::array instr_descr = {{ - /* entries are: size, valid value, valid mask, function ptr */ + /* entries are: size, valid value, valid mask, function ptr */ /* instruction LUI, encoding '0b00000000000000000000000000110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, /* instruction AUIPC, encoding '0b00000000000000000000000000010111' */ @@ -327,3649 +330,4101 @@ private: /* instruction DII, encoding '0b0000000000000000' */ {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, }}; - + /* instruction definitions */ /* instruction 0: LUI */ - std::tuple __lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LUI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 0); + std::tuple __lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LUI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,0); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = ((bit_sub<12, 20>(instr) << 12)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)((int32_t)imm)), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)((int32_t)imm)), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 0); + this->gen_sync(POST_SYNC, 0); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 1: AUIPC */ - std::tuple __auipc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("AUIPC_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 1); + std::tuple __auipc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("AUIPC_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,1); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = ((bit_sub<12, 20>(instr) << 12)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + (int32_t)imm)), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)(PC+(int32_t)imm)), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 1); + this->gen_sync(POST_SYNC, 1); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 2: JAL */ - std::tuple __jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("JAL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 2); + std::tuple __jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("JAL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,2); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = - ((bit_sub<12, 8>(instr) << 12) | (bit_sub<20, 1>(instr) << 11) | (bit_sub<21, 10>(instr) << 1) | (bit_sub<31, 1>(instr) << 20)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 4)), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)(PC+ 4)), + get_reg_ptr(rd + traits::X0), false); } - auto PC_val_v = (uint32_t)(PC + (int32_t)sext<21>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + auto PC_val_v = (uint32_t)(PC+(int32_t)sext<21>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 2); + this->gen_sync(POST_SYNC, 2); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 3: JALR */ - std::tuple __jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("JALR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 3); + std::tuple __jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("JALR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,3); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto addr_mask = this->gen_const(32, (uint32_t)-2); - auto new_pc = this->gen_ext( - (this->builder.CreateAnd((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - this->gen_ext(addr_mask, 64, false))), + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto addr_mask =this->gen_const(32,(uint32_t)- 2); + auto new_pc =this->gen_ext( + (this->builder.CreateAnd( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + this->gen_ext(addr_mask, 64,false)) + ), 32, true); auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext(this->builder.CreateURem(new_pc, this->gen_const(32, static_cast(traits::INSTR_ALIGNMENT))), 1), - bb_then, bb_else); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateURem( + new_pc, + this->gen_const(32,static_cast(traits::INSTR_ALIGNMENT))) + , 1), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); - { this->gen_raise_trap(0, 0); } + { + this->gen_raise_trap(0, 0); + } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_else); { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 4)), get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)(PC+ 4)), + get_reg_ptr(rd + traits::X0), false); } auto PC_val_v = new_pc; - this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 3); + this->gen_sync(POST_SYNC, 3); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 4: BEQ */ - std::tuple __beq(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BEQ_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 4); + std::tuple __beq(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BEQ_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,4); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 4); + this->gen_sync(POST_SYNC, 4); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 5: BNE */ - std::tuple __bne(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BNE_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 5); + std::tuple __bne(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BNE_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,5); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 5); + this->gen_sync(POST_SYNC, 5); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 6: BLT */ - std::tuple __blt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BLT_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 6); + std::tuple __blt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BLT_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,6); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SLT, - this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), + 32, false), + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 6); + this->gen_sync(POST_SYNC, 6); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 7: BGE */ - std::tuple __bge(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BGE_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 7); + std::tuple __bge(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BGE_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,7); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SGE, - this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SGE, + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), + 32, false), + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 7); + this->gen_sync(POST_SYNC, 7); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 8: BLTU */ - std::tuple __bltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BLTU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 8); + std::tuple __bltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BLTU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,8); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_ULT, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 8); + this->gen_sync(POST_SYNC, 8); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 9: BGEU */ - std::tuple __bgeu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("BGEU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 9); + std::tuple __bgeu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("BGEU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,9); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_UGE, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_UGE, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(0, 0); - } else { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + } + else{ + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 9); + this->gen_sync(POST_SYNC, 9); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 10: LB */ - std::tuple __lb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LB_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 10); + std::tuple __lb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,10); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto load_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - auto res = this->gen_ext(this->gen_read_mem(traits::MEM, load_address, 1), 8, false); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto load_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + auto res =this->gen_ext( + this->gen_read_mem(traits::MEM, load_address, 1), + 8, false); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 10); + this->gen_sync(POST_SYNC, 10); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 11: LH */ - std::tuple __lh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LH_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 11); + std::tuple __lh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LH_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,11); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto load_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - auto res = this->gen_ext(this->gen_read_mem(traits::MEM, load_address, 2), 16, false); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto load_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + auto res =this->gen_ext( + this->gen_read_mem(traits::MEM, load_address, 2), + 16, false); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 11); + this->gen_sync(POST_SYNC, 11); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 12: LW */ - std::tuple __lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LW_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 12); + std::tuple __lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,12); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto load_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - auto res = this->gen_ext(this->gen_read_mem(traits::MEM, load_address, 4), 32, false); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto load_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + auto res =this->gen_ext( + this->gen_read_mem(traits::MEM, load_address, 4), + 32, false); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 12); + this->gen_sync(POST_SYNC, 12); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 13: LBU */ - std::tuple __lbu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LBU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 13); + std::tuple __lbu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LBU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,13); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto load_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - auto res = this->gen_read_mem(traits::MEM, load_address, 1); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, false), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto load_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + auto res =this->gen_read_mem(traits::MEM, load_address, 1); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 13); + this->gen_sync(POST_SYNC, 13); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 14: LHU */ - std::tuple __lhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("LHU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 14); + std::tuple __lhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("LHU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,14); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto load_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - auto res = this->gen_read_mem(traits::MEM, load_address, 2); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, false), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto load_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + auto res =this->gen_read_mem(traits::MEM, load_address, 2); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 14); + this->gen_sync(POST_SYNC, 14); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 15: SB */ - std::tuple __sb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SB_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 15); + std::tuple __sb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,15); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto store_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - this->gen_write_mem(traits::MEM, store_address, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 8, false)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto store_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + this->gen_write_mem(traits::MEM, + store_address, + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 8, false)); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 15); + this->gen_sync(POST_SYNC, 15); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 16: SH */ - std::tuple __sh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SH_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 16); + std::tuple __sh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SH_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,16); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto store_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - this->gen_write_mem(traits::MEM, store_address, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 16, false)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto store_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + this->gen_write_mem(traits::MEM, + store_address, + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 16, false)); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 16); + this->gen_sync(POST_SYNC, 16); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 17: SW */ - std::tuple __sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SW_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 17); + std::tuple __sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,17); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto store_address = - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true); - this->gen_write_mem(traits::MEM, store_address, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false)); + if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto store_address =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true); + this->gen_write_mem(traits::MEM, + store_address, + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false)); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 17); + this->gen_sync(POST_SYNC, 17); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 18: ADDI */ - std::tuple __addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("ADDI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 18); + std::tuple __addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("ADDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,18); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 18); + this->gen_sync(POST_SYNC, 18); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 19: SLTI */ - std::tuple __slti(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLTI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 19); + std::tuple __slti(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLTI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,19); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext(this->gen_choose((this->builder.CreateICmp( - ICmpInst::ICMP_SLT, this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 32, true))), - this->gen_const(8, 1), this->gen_const(8, 0), 1), - 32), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->gen_choose((this->builder.CreateICmp(ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 32,true)) + ), + this->gen_const(8, 1), + this->gen_const(8, 0), + 1), 32), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 19); + this->gen_sync(POST_SYNC, 19); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 20: SLTIU */ - std::tuple __sltiu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLTIU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 20); + std::tuple __sltiu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLTIU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,20); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext(this->gen_choose((this->builder.CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm))))), - this->gen_const(8, 1), this->gen_const(8, 0), 1), - 32), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->gen_choose((this->builder.CreateICmp(ICmpInst::ICMP_ULT, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm)))) + ), + this->gen_const(8, 1), + this->gen_const(8, 0), + 1), 32), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 20); + this->gen_sync(POST_SYNC, 20); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 21: XORI */ - std::tuple __xori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("XORI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 21); + std::tuple __xori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("XORI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,21); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->builder.CreateXor(this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm)))), - get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->builder.CreateXor( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm)))) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 21); + this->gen_sync(POST_SYNC, 21); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 22: ORI */ - std::tuple __ori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("ORI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 22); + std::tuple __ori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("ORI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,22); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->builder.CreateOr(this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm)))), - get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->builder.CreateOr( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm)))) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 22); + this->gen_sync(POST_SYNC, 22); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 23: ANDI */ - std::tuple __andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("ANDI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 23); + std::tuple __andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("ANDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,23); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->builder.CreateAnd(this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm)))), - get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->builder.CreateAnd( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm)))) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 23); + this->gen_sync(POST_SYNC, 23); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 24: SLLI */ - std::tuple __slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLLI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 24); + std::tuple __slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,24); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->builder.CreateShl(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_ext(this->gen_const(8, shamt), 32, false)), - get_reg_ptr(rd + traits::X0), false); + this->builder.CreateShl( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_ext(this->gen_const(8,shamt), 32,false)) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 24); + this->gen_sync(POST_SYNC, 24); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 25: SRLI */ - std::tuple __srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SRLI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 25); + std::tuple __srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SRLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,25); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->builder.CreateLShr(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_ext(this->gen_const(8, shamt), 32, false)), - get_reg_ptr(rd + traits::X0), false); + this->builder.CreateLShr( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_ext(this->gen_const(8,shamt), 32,false)) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 25); + this->gen_sync(POST_SYNC, 25); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 26: SRAI */ - std::tuple __srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SRAI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 26); + std::tuple __srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SRAI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,26); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAShr(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_ext(this->gen_const(8, shamt), 32, false))), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateAShr( + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + this->gen_ext(this->gen_const(8,shamt), 32,false)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 26); + this->gen_sync(POST_SYNC, 26); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 27: ADD */ - std::tuple __add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("ADD_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 27); + std::tuple __add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("ADD_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,27); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false))), - 32, false), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false)) + ), + 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 27); + this->gen_sync(POST_SYNC, 27); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 28: SUB */ - std::tuple __sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SUB_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 28); + std::tuple __sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SUB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,28); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateSub(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false))), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateSub( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 28); + this->gen_sync(POST_SYNC, 28); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 29: SLL */ - std::tuple __sll(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 29); + std::tuple __sll(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,29); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext( - this->builder.CreateShl(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - (this->builder.CreateAnd(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), - this->gen_const(64, (static_cast(traits::XLEN) - 1))))), - 32, false), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->builder.CreateShl( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + (this->builder.CreateAnd( + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false), + this->gen_const(64,(static_cast(traits::XLEN)- 1))) + )) + , 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 29); + this->gen_sync(POST_SYNC, 29); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 30: SLT */ - std::tuple __slt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLT_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 30); + std::tuple __slt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLT_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,30); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext(this->gen_choose(this->builder.CreateICmp( - ICmpInst::ICMP_SLT, this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, true)), - this->gen_const(8, 1), this->gen_const(8, 0), 1), - 32), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->gen_choose(this->builder.CreateICmp(ICmpInst::ICMP_SLT, + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), 32,true)) + , + this->gen_const(8, 1), + this->gen_const(8, 0), + 1), 32), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 30); + this->gen_sync(POST_SYNC, 30); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 31: SLTU */ - std::tuple __sltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SLTU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 31); + std::tuple __sltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SLTU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,31); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext(this->gen_choose(this->builder.CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0)), - this->gen_const(8, 1), this->gen_const(8, 0), 1), - 32), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->gen_choose(this->builder.CreateICmp(ICmpInst::ICMP_ULT, + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , + this->gen_const(8, 1), + this->gen_const(8, 0), + 1), 32), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 31); + this->gen_sync(POST_SYNC, 31); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 32: XOR */ - std::tuple __xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("XOR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 32); + std::tuple __xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("XOR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,32); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->builder.CreateXor(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)), - get_reg_ptr(rd + traits::X0), false); + this->builder.CreateXor( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 32); + this->gen_sync(POST_SYNC, 32); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 33: SRL */ - std::tuple __srl(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SRL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 33); + std::tuple __srl(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SRL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,33); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext( - this->builder.CreateLShr(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - (this->builder.CreateAnd(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), - this->gen_const(64, (static_cast(traits::XLEN) - 1))))), - 32, false), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext(this->builder.CreateLShr( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + (this->builder.CreateAnd( + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false), + this->gen_const(64,(static_cast(traits::XLEN)- 1))) + )) + , 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 33); + this->gen_sync(POST_SYNC, 33); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 34: SRA */ - std::tuple __sra(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("SRA_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 34); + std::tuple __sra(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("SRA_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,34); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext( - (this->gen_ext(this->builder.CreateAShr( - this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true), - (this->builder.CreateAnd(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), - this->gen_const(64, (static_cast(traits::XLEN) - 1))))), - 32, true)), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->gen_ext(this->builder.CreateAShr( + this->gen_ext(this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), 64,true), + (this->builder.CreateAnd( + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false), + this->gen_const(64,(static_cast(traits::XLEN)- 1))) + )) + , 32, true)), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 34); + this->gen_sync(POST_SYNC, 34); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 35: OR */ - std::tuple __or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("OR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 35); + std::tuple __or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("OR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,35); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->builder.CreateOr(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)), - get_reg_ptr(rd + traits::X0), false); + this->builder.CreateOr( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 35); + this->gen_sync(POST_SYNC, 35); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 36: AND */ - std::tuple __and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("AND_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 36); + std::tuple __and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("AND_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,36); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { this->builder.CreateStore( - this->builder.CreateAnd(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)), - get_reg_ptr(rd + traits::X0), false); + this->builder.CreateAnd( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 36); + this->gen_sync(POST_SYNC, 36); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 37: FENCE */ - std::tuple __fence(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("FENCE_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 37); + std::tuple __fence(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("FENCE_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,37); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t succ = ((bit_sub<20, 4>(instr))); - uint8_t pred = ((bit_sub<24, 4>(instr))); - uint8_t fm = ((bit_sub<28, 4>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); + uint8_t fm = ((bit_sub<28,4>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), fmt::arg("pred", pred), - fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), + fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_write_mem(traits::FENCE, static_cast(traits::fence), this->gen_const(8, (uint8_t)pred << 4 | succ)); + this->gen_write_mem(traits::FENCE, + static_cast(traits::fence), + this->gen_const(8,(uint8_t)pred<< 4|succ)); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 37); + this->gen_sync(POST_SYNC, 37); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 38: ECALL */ - std::tuple __ecall(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("ECALL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 38); + std::tuple __ecall(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("ECALL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,38); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_raise_trap(0, 11); + this->gen_raise_trap(0, 11); bb = this->leave_blk; - auto returnValue = std::make_tuple(TRAP, nullptr); - + auto returnValue = std::make_tuple(TRAP,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 38); + this->gen_sync(POST_SYNC, 38); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 39: EBREAK */ - std::tuple __ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("EBREAK_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 39); + std::tuple __ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("EBREAK_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,39); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_raise_trap(0, 3); + this->gen_raise_trap(0, 3); bb = this->leave_blk; - auto returnValue = std::make_tuple(TRAP, nullptr); - + auto returnValue = std::make_tuple(TRAP,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 39); + this->gen_sync(POST_SYNC, 39); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 40: MRET */ - std::tuple __mret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("MRET_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 40); + std::tuple __mret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("MRET_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,40); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); this->gen_leave_trap(3); bb = this->leave_blk; - auto returnValue = std::make_tuple(TRAP, nullptr); - + auto returnValue = std::make_tuple(TRAP,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 40); + this->gen_sync(POST_SYNC, 40); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 41: WFI */ - std::tuple __wfi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("WFI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 41); + std::tuple __wfi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("WFI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,41); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); this->gen_wait(1); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 41); + this->gen_sync(POST_SYNC, 41); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 42: CSRRW */ - std::tuple __csrrw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRW_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 42); + std::tuple __csrrw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,42); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrs1 = this->gen_reg_load(rs1 + traits::X0, 0); - if(rd != 0) { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - this->gen_write_mem(traits::CSR, csr, xrs1); - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); - } else { - this->gen_write_mem(traits::CSR, csr, xrs1); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0); + if(rd!= 0){ auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + this->gen_write_mem(traits::CSR, + csr, + xrs1); + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); + } + else{ + this->gen_write_mem(traits::CSR, + csr, + xrs1); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 42); + this->gen_sync(POST_SYNC, 42); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 43: CSRRS */ - std::tuple __csrrs(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRS_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 43); + std::tuple __csrrs(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRS_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,43); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - auto xrs1 = this->gen_reg_load(rs1 + traits::X0, 0); - if(rs1 != 0) { - this->gen_write_mem(traits::CSR, csr, this->builder.CreateOr(xrd, xrs1)); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0); + if(rs1!= 0) { + this->gen_write_mem(traits::CSR, + csr, + this->builder.CreateOr( + xrd, + xrs1) + ); } - if(rd != 0) { - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 43); + this->gen_sync(POST_SYNC, 43); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 44: CSRRC */ - std::tuple __csrrc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRC_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 44); + std::tuple __csrrc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRC_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,44); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - auto xrs1 = this->gen_reg_load(rs1 + traits::X0, 0); - if(rs1 != 0) { - this->gen_write_mem(traits::CSR, csr, this->builder.CreateAnd(xrd, this->builder.CreateNeg(xrs1))); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0); + if(rs1!= 0) { + this->gen_write_mem(traits::CSR, + csr, + this->builder.CreateAnd( + xrd, + this->builder.CreateNeg(xrs1)) + ); } - if(rd != 0) { - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 44); + this->gen_sync(POST_SYNC, 44); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 45: CSRRWI */ - std::tuple __csrrwi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRWI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 45); + std::tuple __csrrwi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRWI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,45); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - this->gen_write_mem(traits::CSR, csr, this->gen_const(32, (uint32_t)zimm)); - if(rd != 0) { - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + this->gen_write_mem(traits::CSR, + csr, + this->gen_const(32,(uint32_t)zimm)); + if(rd!= 0) { + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 45); + this->gen_sync(POST_SYNC, 45); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 46: CSRRSI */ - std::tuple __csrrsi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRSI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 46); + std::tuple __csrrsi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRSI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,46); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - if(zimm != 0) { - this->gen_write_mem(traits::CSR, csr, this->builder.CreateOr(xrd, this->gen_const(32, (uint32_t)zimm))); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + if(zimm!= 0) { + this->gen_write_mem(traits::CSR, + csr, + this->builder.CreateOr( + xrd, + this->gen_const(32,(uint32_t)zimm)) + ); } - if(rd != 0) { - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 46); + this->gen_sync(POST_SYNC, 46); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 47: CSRRCI */ - std::tuple __csrrci(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("CSRRCI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 47); + std::tuple __csrrci(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("CSRRCI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,47); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto xrd = this->gen_read_mem(traits::CSR, csr, 4); - if(zimm != 0) { - this->gen_write_mem(traits::CSR, csr, this->builder.CreateAnd(xrd, this->gen_const(32, ~((uint32_t)zimm)))); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + if(zimm!= 0) { + this->gen_write_mem(traits::CSR, + csr, + this->builder.CreateAnd( + xrd, + this->gen_const(32,~ ((uint32_t)zimm))) + ); } - if(rd != 0) { - this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + xrd, + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 47); + this->gen_sync(POST_SYNC, 47); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 48: FENCE_I */ - std::tuple __fence_i(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("FENCE_I_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 48); + std::tuple __fence_i(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("FENCE_I_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,48); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), fmt::arg("rs1", name(rs1)), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), + fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_write_mem(traits::FENCE, static_cast(traits::fencei), this->gen_const(16, imm)); + this->gen_write_mem(traits::FENCE, + static_cast(traits::fencei), + this->gen_const(16,imm)); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 48); + this->gen_sync(POST_SYNC, 48); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 49: MUL */ - std::tuple __mul(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("MUL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 49); + std::tuple __mul(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("MUL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,49); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto res = this->gen_ext( + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto res =this->gen_ext( (this->builder.CreateMul( - this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true), 128, true), - this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, true), 64, true), 128, true))), + this->gen_ext(this->gen_ext( + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + 64, true), 128,true), + this->gen_ext(this->gen_ext( + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), 32,true), + 64, true), 128,true)) + ), 64, true); - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false); + if(rd!=0) { + this->builder.CreateStore( + this->gen_ext( + res, + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 49); + this->gen_sync(POST_SYNC, 49); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 50: MULH */ - std::tuple __mulh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("MULH_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 50); + std::tuple __mulh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("MULH_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,50); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto res = this->gen_ext( + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto res =this->gen_ext( (this->builder.CreateMul( - this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true), 128, true), - this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, true), 64, true), 128, true))), + this->gen_ext(this->gen_ext( + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + 64, true), 128,true), + this->gen_ext(this->gen_ext( + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), 32,true), + 64, true), 128,true)) + ), 64, true); - if(rd != 0) { + if(rd!=0) { this->builder.CreateStore( - this->gen_ext( - (this->builder.CreateAShr(res, this->gen_ext(this->gen_const(32, static_cast(traits::XLEN)), 64, false))), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateAShr( + res, + this->gen_ext(this->gen_const(32,static_cast(traits::XLEN)), 64,false)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 50); + this->gen_sync(POST_SYNC, 50); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 51: MULHSU */ - std::tuple __mulhsu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("MULHSU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 51); + std::tuple __mulhsu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("MULHSU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,51); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto res = this->gen_ext( + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto res =this->gen_ext( (this->builder.CreateMul( - this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true), 128, true), - this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), 128, false))), + this->gen_ext(this->gen_ext( + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), 32,true), + 64, true), 128,true), + this->gen_ext(this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 64, false), 128,false)) + ), 64, true); - if(rd != 0) { + if(rd!=0) { this->builder.CreateStore( - this->gen_ext( - (this->builder.CreateAShr(res, this->gen_ext(this->gen_const(32, static_cast(traits::XLEN)), 64, false))), - 32, true), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateAShr( + res, + this->gen_ext(this->gen_const(32,static_cast(traits::XLEN)), 64,false)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 51); + this->gen_sync(POST_SYNC, 51); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 52: MULHU */ - std::tuple __mulhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("MULHU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 52); + std::tuple __mulhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("MULHU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,52); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto res = this->gen_ext( - (this->builder.CreateMul(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), 128, false), - this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), 128, false))), + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto res =this->gen_ext( + (this->builder.CreateMul( + this->gen_ext(this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), + 64, false), 128,false), + this->gen_ext(this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 64, false), 128,false)) + ), 64, false); - if(rd != 0) { + if(rd!=0) { this->builder.CreateStore( - this->gen_ext( - (this->builder.CreateLShr(res, this->gen_ext(this->gen_const(32, static_cast(traits::XLEN)), 64, false))), - 32, false), - get_reg_ptr(rd + traits::X0), false); + this->gen_ext( + (this->builder.CreateLShr( + res, + this->gen_ext(this->gen_const(32,static_cast(traits::XLEN)), 64,false)) + ), + 32, false), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 52); + this->gen_sync(POST_SYNC, 52); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 53: DIV */ - std::tuple __div(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("DIV_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 53); + std::tuple __div(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("DIV_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,53); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto dividend = this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false); - auto divisor = this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false); - if(rd != 0) { + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto dividend =this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), + 32, false); + auto divisor =this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false); + if(rd!= 0){ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); + auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); + auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + divisor, + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_else); + this->builder.SetInsertPoint(bb_then); + { + auto MMIN =this->gen_const(32,((uint32_t)1)<<(static_cast(traits::XLEN)-1)); auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, divisor, this->gen_ext(this->gen_const(8, 0), 32, false)), 1), - bb_then, bb_else); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateAnd( + this->builder.CreateICmp(ICmpInst::ICMP_EQ, + this->gen_reg_load(rs1+ traits::X0, 0), + MMIN) + , + this->builder.CreateICmp(ICmpInst::ICMP_EQ, + divisor, + this->gen_ext(this->gen_const(8,- 1), 32,true)) + ) + , 1), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); { - auto MMIN = this->gen_const(32, ((uint32_t)1) << (static_cast(traits::XLEN) - 1)); - auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); - auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext( - this->builder.CreateAnd( - this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + traits::X0, 0), MMIN), - this->builder.CreateICmp(ICmpInst::ICMP_EQ, divisor, this->gen_ext(this->gen_const(8, -1), 32, true))), - 1), - bb_then, bb_else); - this->builder.SetInsertPoint(bb_then); - { this->builder.CreateStore(MMIN, get_reg_ptr(rd + traits::X0), false); } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_else); - { - this->builder.CreateStore( - this->gen_ext((this->builder.CreateSDiv(this->gen_ext(dividend, 64, true), this->gen_ext(divisor, 64, true))), - 32, true), - get_reg_ptr(rd + traits::X0), false); - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_merge); - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_else); - { this->builder.CreateStore(this->gen_const(32, (uint32_t)-1), get_reg_ptr(rd + traits::X0), false); } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_merge); - } - } - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 53); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 54: DIVU */ - std::tuple __divu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("DIVU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 54); - uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); - auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2 + traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32, false)), - 1), - bb_then, bb_else); - this->builder.SetInsertPoint(bb_then); - { - if(rd != 0) { - this->builder.CreateStore(this->gen_ext((this->builder.CreateUDiv(this->gen_reg_load(rs1 + traits::X0, 0), - this->gen_reg_load(rs2 + traits::X0, 0))), - 32, false), - get_reg_ptr(rd + traits::X0), false); - } - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_else); - { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)-1), get_reg_ptr(rd + traits::X0), false); - } - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_merge); - } - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 54); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 55: REM */ - std::tuple __rem(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("REM_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 55); - uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); - auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2 + traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32, false)), - 1), - bb_then, bb_else); - this->builder.SetInsertPoint(bb_then); - { - auto MMIN = this->gen_const(32, (uint32_t)1 << (static_cast(traits::XLEN) - 1)); - auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); - auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr( - this->gen_ext( - this->builder.CreateAnd(this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + traits::X0, 0), MMIN), - this->builder.CreateICmp(ICmpInst::ICMP_EQ, - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false), - this->gen_ext(this->gen_const(8, -1), 32, true))), - 1), - bb_then, bb_else); - this->builder.SetInsertPoint(bb_then); - { - if(rd != 0) { - this->builder.CreateStore(this->gen_ext(this->gen_const(8, 0), 32), get_reg_ptr(rd + traits::X0), false); - } - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_else); - { - if(rd != 0) { - this->builder.CreateStore( - this->gen_ext((this->builder.CreateSRem(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false))), - 32, true), - get_reg_ptr(rd + traits::X0), false); - } - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_merge); - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_else); - { - if(rd != 0) { - this->builder.CreateStore(this->gen_reg_load(rs1 + traits::X0, 0), get_reg_ptr(rd + traits::X0), false); - } - } - this->builder.CreateBr(bb_merge); - this->builder.SetInsertPoint(bb_merge); - } - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 55); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 56: REMU */ - std::tuple __remu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("REMU_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 56); - uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 4; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); - auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2 + traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32, false)), - 1), - bb_then, bb_else); - this->builder.SetInsertPoint(bb_then); - { - if(rd != 0) { this->builder.CreateStore( - this->builder.CreateURem(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)), - get_reg_ptr(rd + traits::X0), false); + MMIN, + get_reg_ptr(rd + traits::X0), false); } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_else); + { + this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateSDiv( + this->gen_ext(dividend, 64,true), + this->gen_ext(divisor, 64,true)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_merge); } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_else); { - if(rd != 0) { - this->builder.CreateStore(this->gen_reg_load(rs1 + traits::X0, 0), get_reg_ptr(rd + traits::X0), false); - } + this->builder.CreateStore( + this->gen_const(32,(uint32_t)- 1), + get_reg_ptr(rd + traits::X0), false); } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); + } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 56); + this->gen_sync(POST_SYNC, 53); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - - /* instruction 57: C__ADDI4SPN */ - std::tuple __c__addi4spn(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__ADDI4SPN_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 57); + + /* instruction 54: DIVU */ + std::tuple __divu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("DIVU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,54); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<2, 3>(instr))); - uint16_t imm = - ((bit_sub<5, 1>(instr) << 3) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<7, 4>(instr) << 6) | (bit_sub<11, 2>(instr) << 4)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"), fmt::arg("rd", name(8 + rd)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); + auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); + auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + this->gen_reg_load(rs2+ traits::X0, 0), + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_else); + this->builder.SetInsertPoint(bb_then); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateUDiv( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + ), + 32, false), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_else); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)- 1), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_merge); + } + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 54); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 55: REM */ + std::tuple __rem(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("REM_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,55); + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); + auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); + auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + this->gen_reg_load(rs2+ traits::X0, 0), + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_else); + this->builder.SetInsertPoint(bb_then); + { + auto MMIN =this->gen_const(32,(uint32_t)1<<(static_cast(traits::XLEN)-1)); + auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); + auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); + auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateAnd( + this->builder.CreateICmp(ICmpInst::ICMP_EQ, + this->gen_reg_load(rs1+ traits::X0, 0), + MMIN) + , + this->builder.CreateICmp(ICmpInst::ICMP_EQ, + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false), + this->gen_ext(this->gen_const(8,- 1), 32,true)) + ) + , 1), bb_then, bb_else); + this->builder.SetInsertPoint(bb_then); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_ext(this->gen_const(8, 0), 32), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_else); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateSRem( + this->gen_ext( + this->gen_reg_load(rs1+ traits::X0, 0), + 32, false), + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false)) + ), + 32, true), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_merge); + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_else); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_reg_load(rs1+ traits::X0, 0), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_merge); + } + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 55); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 56: REMU */ + std::tuple __remu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("REMU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,56); + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 4; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); + auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); + auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + this->gen_reg_load(rs2+ traits::X0, 0), + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_else); + this->builder.SetInsertPoint(bb_then); + { + if(rd!=0) { + this->builder.CreateStore( + this->builder.CreateURem( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_reg_load(rs2+ traits::X0, 0)) + , + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_else); + { + if(rd!=0) { + this->builder.CreateStore( + this->gen_reg_load(rs1+ traits::X0, 0), + get_reg_ptr(rd + traits::X0), false); + } + } + this->builder.CreateBr(bb_merge); + this->builder.SetInsertPoint(bb_merge); + } + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 56); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 57: C__ADDI4SPN */ + std::tuple __c__addi4spn(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__ADDI4SPN_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,57); + uint64_t PC = pc.val; + uint8_t rd = ((bit_sub<2,3>(instr))); + uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"), + fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm)); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); if(imm) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, imm), 64, false))), - 32, false), - get_reg_ptr(rd + 8 + traits::X0), false); - } else { - this->gen_raise_trap(0, 2); + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,imm), 64,false)) + ), + 32, false), + get_reg_ptr(rd+ 8 + traits::X0), false); + } + else{ + this->gen_raise_trap(0, 2); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 57); + this->gen_sync(POST_SYNC, 57); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 58: C__LW */ - std::tuple __c__lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__LW_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 58); + std::tuple __c__lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__LW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,58); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<2, 3>(instr))); - uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"), - fmt::arg("rd", name(8 + rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(8, uimm), 64, false))), - 32, false); - this->builder.CreateStore(this->gen_ext(this->gen_ext(this->gen_read_mem(traits::MEM, offs, 4), 32, false), 32, true), - get_reg_ptr(rd + 8 + traits::X0), false); + auto offs =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ 8+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(8,uimm), 64,false)) + ), + 32, false); + this->builder.CreateStore( + this->gen_ext( + this->gen_ext( + this->gen_read_mem(traits::MEM, offs, 4), + 32, false), + 32, true), + get_reg_ptr(rd+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 58); + this->gen_sync(POST_SYNC, 58); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 59: C__SW */ - std::tuple __c__sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SW_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 59); + std::tuple __c__sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,59); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"), - fmt::arg("rs2", name(8 + rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(8, uimm), 64, false))), - 32, false); - this->gen_write_mem(traits::MEM, offs, this->gen_ext(this->gen_reg_load(rs2 + 8 + traits::X0, 0), 32, false)); + auto offs =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ 8+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(8,uimm), 64,false)) + ), + 32, false); + this->gen_write_mem(traits::MEM, + offs, + this->gen_ext( + this->gen_reg_load(rs2+ 8+ traits::X0, 0), + 32, false)); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 59); + this->gen_sync(POST_SYNC, 59); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 60: C__ADDI */ - std::tuple __c__addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__ADDI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 60); + std::tuple __c__addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__ADDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,60); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"), fmt::arg("rs1", name(rs1)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rs1 != 0) { + if(rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rs1!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(8, (int8_t)sext<6>(imm)), 64, true))), - 32, true), - get_reg_ptr(rs1 + traits::X0), false); + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(8,(int8_t)sext<6>(imm)), 64,true)) + ), + 32, true), + get_reg_ptr(rs1 + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 60); + this->gen_sync(POST_SYNC, 60); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 61: C__NOP */ - std::tuple __c__nop(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__NOP_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 61); + std::tuple __c__nop(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__NOP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,61); uint64_t PC = pc.val; - uint8_t nzimm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - if(this->disass_enabled) { + uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 61); + this->gen_sync(POST_SYNC, 61); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 62: C__JAL */ - std::tuple __c__jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__JAL_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 62); + std::tuple __c__jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__JAL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,62); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) | - (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11)); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"), + fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 2)), get_reg_ptr(1 + traits::X0), false); - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<12>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + this->builder.CreateStore( + this->gen_const(32,(uint32_t)(PC+ 2)), + get_reg_ptr(1 + traits::X0), false); + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 62); + this->gen_sync(POST_SYNC, 62); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 63: C__LI */ - std::tuple __c__li(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__LI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 63); + std::tuple __c__li(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__LI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,63); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)((int8_t)sext<6>(imm))), get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)((int8_t)sext<6>(imm))), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 63); + this->gen_sync(POST_SYNC, 63); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 64: C__LUI */ - std::tuple __c__lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__LUI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 64); + std::tuple __c__lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__LUI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,64); uint64_t PC = pc.val; - uint32_t imm = ((bit_sub<2, 5>(instr) << 12) | (bit_sub<12, 1>(instr) << 17)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(imm == 0 || rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + if(imm== 0||rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); } - if(rd != 0) { - this->builder.CreateStore(this->gen_const(32, (uint32_t)((int32_t)sext<18>(imm))), get_reg_ptr(rd + traits::X0), false); + if(rd!= 0) { + this->builder.CreateStore( + this->gen_const(32,(uint32_t)((int32_t)sext<18>(imm))), + get_reg_ptr(rd + traits::X0), false); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 64); + this->gen_sync(POST_SYNC, 64); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 65: C__ADDI16SP */ - std::tuple __c__addi16sp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__ADDI16SP_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 65); + std::tuple __c__addi16sp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__ADDI16SP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,65); uint64_t PC = pc.val; - uint16_t nzimm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 7) | (bit_sub<5, 1>(instr) << 6) | - (bit_sub<6, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 9)); - if(this->disass_enabled) { + uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"), fmt::arg("nzimm", nzimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"), + fmt::arg("nzimm", nzimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); if(nzimm) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(16, (int16_t)sext<10>(nzimm)), 64, true))), - 32, true), - get_reg_ptr(2 + traits::X0), false); - } else { - this->gen_raise_trap(0, 2); + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(16,(int16_t)sext<10>(nzimm)), 64,true)) + ), + 32, true), + get_reg_ptr(2 + traits::X0), false); + } + else{ + this->gen_raise_trap(0, 2); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 65); + this->gen_sync(POST_SYNC, 65); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 66: __reserved_clui */ - std::tuple ____reserved_clui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("__reserved_clui_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 66); + std::tuple ____reserved_clui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("__reserved_clui_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,66); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 66); + this->gen_sync(POST_SYNC, 66); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 67: C__SRLI */ - std::tuple __c__srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SRLI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 67); + std::tuple __c__srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SRLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,67); uint64_t PC = pc.val; - uint8_t shamt = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("shamt", shamt)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->builder.CreateLShr(this->gen_reg_load(rs1 + 8 + traits::X0, 0), this->gen_ext(this->gen_const(8, shamt), 32, false)), - get_reg_ptr(rs1 + 8 + traits::X0), false); + this->builder.CreateLShr( + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_ext(this->gen_const(8,shamt), 32,false)) + , + get_reg_ptr(rs1+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 67); + this->gen_sync(POST_SYNC, 67); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 68: C__SRAI */ - std::tuple __c__srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SRAI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 68); + std::tuple __c__srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SRAI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,68); uint64_t PC = pc.val; - uint8_t shamt = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("shamt", shamt)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(shamt) { - this->builder.CreateStore( - this->gen_ext((this->builder.CreateAShr((this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 32, false)), - this->gen_ext(this->gen_const(8, shamt), 32, false))), - 32, true), - get_reg_ptr(rs1 + 8 + traits::X0), false); - } else { - if(static_cast(traits::XLEN) == 128) { - this->builder.CreateStore( - this->gen_ext((this->builder.CreateAShr((this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 32, false)), - this->gen_ext(this->gen_const(8, 64), 32, false))), - 32, true), - get_reg_ptr(rs1 + 8 + traits::X0), false); + if(shamt){ this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateAShr( + (this->gen_ext( + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + 32, false)), + this->gen_ext(this->gen_const(8,shamt), 32,false)) + ), + 32, true), + get_reg_ptr(rs1+ 8 + traits::X0), false); + } + else{ + if(static_cast(traits::XLEN)== 128){ this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateAShr( + (this->gen_ext( + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + 32, false)), + this->gen_ext(this->gen_const(8, 64), 32,false)) + ), + 32, true), + get_reg_ptr(rs1+ 8 + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 68); + this->gen_sync(POST_SYNC, 68); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 69: C__ANDI */ - std::tuple __c__andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__ANDI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 69); + std::tuple __c__andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__ANDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,69); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->gen_ext((this->builder.CreateAnd(this->gen_reg_load(rs1 + 8 + traits::X0, 0), - this->gen_ext(this->gen_const(8, (int8_t)sext<6>(imm)), 32, true))), - 32, true), - get_reg_ptr(rs1 + 8 + traits::X0), false); + this->gen_ext( + (this->builder.CreateAnd( + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_ext(this->gen_const(8,(int8_t)sext<6>(imm)), 32,true)) + ), + 32, true), + get_reg_ptr(rs1+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 69); + this->gen_sync(POST_SYNC, 69); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 70: C__SUB */ - std::tuple __c__sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SUB_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 70); + std::tuple __c__sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SUB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,70); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->gen_ext((this->builder.CreateSub(this->gen_ext(this->gen_reg_load(rd + 8 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_reg_load(rs2 + 8 + traits::X0, 0), 64, false))), - 32, true), - get_reg_ptr(rd + 8 + traits::X0), false); + this->gen_ext( + (this->builder.CreateSub( + this->gen_ext(this->gen_reg_load(rd+ 8+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_reg_load(rs2+ 8+ traits::X0, 0), 64,false)) + ), + 32, true), + get_reg_ptr(rd+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 70); + this->gen_sync(POST_SYNC, 70); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 71: C__XOR */ - std::tuple __c__xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__XOR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 71); + std::tuple __c__xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__XOR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,71); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->builder.CreateXor(this->gen_reg_load(rd + 8 + traits::X0, 0), this->gen_reg_load(rs2 + 8 + traits::X0, 0)), - get_reg_ptr(rd + 8 + traits::X0), false); + this->builder.CreateXor( + this->gen_reg_load(rd+ 8+ traits::X0, 0), + this->gen_reg_load(rs2+ 8+ traits::X0, 0)) + , + get_reg_ptr(rd+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 71); + this->gen_sync(POST_SYNC, 71); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 72: C__OR */ - std::tuple __c__or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__OR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 72); + std::tuple __c__or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__OR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,72); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->builder.CreateOr(this->gen_reg_load(rd + 8 + traits::X0, 0), this->gen_reg_load(rs2 + 8 + traits::X0, 0)), - get_reg_ptr(rd + 8 + traits::X0), false); + this->builder.CreateOr( + this->gen_reg_load(rd+ 8+ traits::X0, 0), + this->gen_reg_load(rs2+ 8+ traits::X0, 0)) + , + get_reg_ptr(rd+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 72); + this->gen_sync(POST_SYNC, 72); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 73: C__AND */ - std::tuple __c__and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__AND_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 73); + std::tuple __c__and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__AND_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,73); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->builder.CreateStore( - this->builder.CreateAnd(this->gen_reg_load(rd + 8 + traits::X0, 0), this->gen_reg_load(rs2 + 8 + traits::X0, 0)), - get_reg_ptr(rd + 8 + traits::X0), false); + this->builder.CreateAnd( + this->gen_reg_load(rd+ 8+ traits::X0, 0), + this->gen_reg_load(rs2+ 8+ traits::X0, 0)) + , + get_reg_ptr(rd+ 8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 73); + this->gen_sync(POST_SYNC, 73); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 74: C__J */ - std::tuple __c__j(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__J_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 74); + std::tuple __c__j(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__J_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,74); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) | - (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11)); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"), fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"), + fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<12>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 74); + this->gen_sync(POST_SYNC, 74); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 75: C__BEQZ */ - std::tuple __c__beqz(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__BEQZ_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 75); + std::tuple __c__beqz(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__BEQZ_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,75); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) | - (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + 8 + traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32, false)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<9>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 75); + this->gen_sync(POST_SYNC, 75); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 76: C__BNEZ */ - std::tuple __c__bnez(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__BNEZ_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 76); + std::tuple __c__bnez(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__BNEZ_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,76); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) | - (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); - this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs1 + 8 + traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32, false)), - 1), - bb_then, bb_merge); + this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, + this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_ext(this->gen_const(8, 0), 32,false)) + , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - auto PC_val_v = (uint32_t)(PC + (int16_t)sext<9>(imm)); - this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); + auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm)); + this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_merge); bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 76); + this->gen_sync(POST_SYNC, 76); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 77: C__SLLI */ - std::tuple __c__slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SLLI_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 77); + std::tuple __c__slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SLLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,77); uint64_t PC = pc.val; - uint8_t nzuimm = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t nzuimm = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"), fmt::arg("rs1", name(rs1)), - fmt::arg("nzuimm", nzuimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rs1 != 0) { + if(rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rs1!= 0) { this->builder.CreateStore( - this->builder.CreateShl(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_ext(this->gen_const(8, nzuimm), 32, false)), - get_reg_ptr(rs1 + traits::X0), false); + this->builder.CreateShl( + this->gen_reg_load(rs1+ traits::X0, 0), + this->gen_ext(this->gen_const(8,nzuimm), 32,false)) + , + get_reg_ptr(rs1 + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 77); + this->gen_sync(POST_SYNC, 77); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 78: C__LWSP */ - std::tuple __c__lwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__LWSP_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 78); + std::tuple __c__lwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__LWSP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,78); uint64_t PC = pc.val; - uint8_t uimm = ((bit_sub<2, 2>(instr) << 6) | (bit_sub<4, 3>(instr) << 2) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"), fmt::arg("rd", name(rd)), - fmt::arg("uimm", uimm)); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS) || rd == 0) { - this->gen_raise_trap(0, 2); - } else { - auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(8, uimm), 64, false))), - 32, false); - this->builder.CreateStore(this->gen_ext(this->gen_ext(this->gen_read_mem(traits::MEM, offs, 4), 32, false), 32, true), - get_reg_ptr(rd + traits::X0), false); + if(rd>=static_cast(traits::RFS)||rd== 0) { + this->gen_raise_trap(0, 2); + } + else{ + auto offs =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(8,uimm), 64,false)) + ), + 32, false); + this->builder.CreateStore( + this->gen_ext( + this->gen_ext( + this->gen_read_mem(traits::MEM, offs, 4), + 32, false), + 32, true), + get_reg_ptr(rd + traits::X0), false); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 78); + this->gen_sync(POST_SYNC, 78); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + /* instruction 79: C__MV */ - std::tuple __c__mv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__MV_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 79); + std::tuple __c__mv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__MV_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,79); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"), fmt::arg("rd", name(rd)), - fmt::arg("rs2", name(rs2))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { - this->builder.CreateStore(this->gen_reg_load(rs2 + traits::X0, 0), get_reg_ptr(rd + traits::X0), false); - } + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); } - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 79); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 80: C__JR */ - std::tuple __c__jr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__JR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 80); - uint64_t PC = pc.val; - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"), fmt::arg("rs1", name(rs1))); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rs1 && rs1 < static_cast(traits::RFS)) { - auto addr_mask = this->gen_const(32, (uint32_t)-2); - auto PC_val_v = - this->builder.CreateAnd(this->gen_reg_load(rs1 % static_cast(traits::RFS) + traits::X0, 0), addr_mask); - this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); - } else { - this->gen_raise_trap(0, 2); - } - bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 80); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 81: __reserved_cmv */ - std::tuple ____reserved_cmv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("__reserved_cmv_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 81); - uint64_t PC = pc.val; - if(this->disass_enabled) { - /* generate console output when executing the command */ - // This disass is not yet implemented - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; - this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_raise_trap(0, 2); - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 81); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 82: C__ADD */ - std::tuple __c__add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__ADD_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 82); - uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"), fmt::arg("rd", name(rd)), - fmt::arg("rs2", name(rs2))); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - if(rd != 0) { + else{ + if(rd!= 0) { this->builder.CreateStore( - this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rd + traits::X0, 0), 64, false), - this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false))), - 32, false), - get_reg_ptr(rd + traits::X0), false); + this->gen_reg_load(rs2+ traits::X0, 0), + get_reg_ptr(rd + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 82); + this->gen_sync(POST_SYNC, 79); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - - /* instruction 83: C__JALR */ - std::tuple __c__jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__JALR_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 83); + + /* instruction 80: C__JR */ + std::tuple __c__jr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__JR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,80); uint64_t PC = pc.val; - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"), fmt::arg("rs1", name(rs1))); - std::vector args{ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"), + fmt::arg("rs1", name(rs1))); + std::vector args { this->core_ptr, this->gen_const(64, pc.val), this->builder.CreateGlobalStringPtr(mnemonic), }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs1 >= static_cast(traits::RFS)) { + if(rs1&&rs1(traits::RFS)) { + auto PC_val_v = this->builder.CreateAnd( + this->gen_reg_load(rs1%static_cast(traits::RFS)+ traits::X0, 0), + this->gen_ext(this->gen_const(8,~ 0x1), 32,false)) + ; + this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); + } + else{ this->gen_raise_trap(0, 2); - } else { - auto addr_mask = this->gen_const(32, (uint32_t)-2); - auto new_pc = this->gen_reg_load(rs1 + traits::X0, 0); - this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 2)), get_reg_ptr(1 + traits::X0), false); - auto PC_val_v = this->builder.CreateAnd(new_pc, addr_mask); - this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false); } bb = this->leave_blk; - auto returnValue = std::make_tuple(BRANCH, nullptr); - + auto returnValue = std::make_tuple(BRANCH,nullptr); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 83); + this->gen_sync(POST_SYNC, 80); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - - /* instruction 84: C__EBREAK */ - std::tuple __c__ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__EBREAK_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 84); + + /* instruction 81: __reserved_cmv */ + std::tuple ____reserved_cmv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("__reserved_cmv_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,81); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ - // This disass is not yet implemented + //This disass is not yet implemented } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; - this->gen_set_pc(pc, traits::NEXT_PC); - this->gen_raise_trap(0, 3); - bb = this->leave_blk; - auto returnValue = std::make_tuple(TRAP, nullptr); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 84); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 85: C__SWSP */ - std::tuple __c__swsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("C__SWSP_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 85); - uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t uimm = ((bit_sub<7, 2>(instr) << 6) | (bit_sub<9, 4>(instr) << 2)); - if(this->disass_enabled) { - /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"), fmt::arg("rs2", name(rs2)), - fmt::arg("uimm", uimm)); - std::vector args{ - this->core_ptr, - this->gen_const(64, pc.val), - this->builder.CreateGlobalStringPtr(mnemonic), - }; - this->builder.CreateCall(this->mod->getFunction("print_disass"), args); - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; - this->gen_set_pc(pc, traits::NEXT_PC); - if(rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); - } else { - auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false), - this->gen_ext(this->gen_const(8, uimm), 64, false))), - 32, false); - this->gen_write_mem(traits::MEM, offs, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false)); - } - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT, bb); - - this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 85); - this->builder.CreateBr(bb); - return returnValue; - } - - /* instruction 86: DII */ - std::tuple __dii(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - bb->setName(fmt::format("DII_0x{:X}", pc.val)); - this->gen_sync(PRE_SYNC, 86); - uint64_t PC = pc.val; - if(this->disass_enabled) { - /* generate console output when executing the command */ - // This disass is not yet implemented - } - auto cur_pc_val = this->gen_const(32, pc.val); - pc = pc + 2; + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); this->gen_raise_trap(0, 2); - bb = this->leave_blk; - auto returnValue = std::make_tuple(TRAP, nullptr); - + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + this->gen_trap_check(bb); - this->gen_sync(POST_SYNC, 86); + this->gen_sync(POST_SYNC, 81); this->builder.CreateBr(bb); - return returnValue; + return returnValue; } - + + /* instruction 82: C__ADD */ + std::tuple __c__add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__ADD_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,82); + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + if(rd!= 0) { + this->builder.CreateStore( + this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(rd+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false)) + ), + 32, false), + get_reg_ptr(rd + traits::X0), false); + } + } + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 82); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 83: C__JALR */ + std::tuple __c__jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__JALR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,83); + uint64_t PC = pc.val; + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"), + fmt::arg("rs1", name(rs1))); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rs1>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto new_pc =this->gen_reg_load(rs1+ traits::X0, 0); + this->builder.CreateStore( + this->gen_const(32,(uint32_t)(PC+ 2)), + get_reg_ptr(1 + traits::X0), false); + auto PC_val_v = this->builder.CreateAnd( + new_pc, + this->gen_ext(this->gen_const(8,~ 0x1), 32,false)) + ; + this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); + } + bb = this->leave_blk; + auto returnValue = std::make_tuple(BRANCH,nullptr); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 83); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 84: C__EBREAK */ + std::tuple __c__ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__EBREAK_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,84); + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate console output when executing the command */ + //This disass is not yet implemented + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; + this->gen_set_pc(pc, traits::NEXT_PC); + this->gen_raise_trap(0, 3); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 84); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 85: C__SWSP */ + std::tuple __c__swsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("C__SWSP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,85); + uint64_t PC = pc.val; + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); + std::vector args { + this->core_ptr, + this->gen_const(64, pc.val), + this->builder.CreateGlobalStringPtr(mnemonic), + }; + this->builder.CreateCall(this->mod->getFunction("print_disass"), args); + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; + this->gen_set_pc(pc, traits::NEXT_PC); + if(rs2>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); + } + else{ + auto offs =this->gen_ext( + (this->builder.CreateAdd( + this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_const(8,uimm), 64,false)) + ), + 32, false); + this->gen_write_mem(traits::MEM, + offs, + this->gen_ext( + this->gen_reg_load(rs2+ traits::X0, 0), + 32, false)); + } + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 85); + this->builder.CreateBr(bb); + return returnValue; + } + + /* instruction 86: DII */ + std::tuple __dii(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ + bb->setName(fmt::format("DII_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,86); + uint64_t PC = pc.val; + if(this->disass_enabled){ + /* generate console output when executing the command */ + //This disass is not yet implemented + } + auto cur_pc_val = this->gen_const(32,pc.val); + pc=pc+ 2; + this->gen_set_pc(pc, traits::NEXT_PC); + this->gen_raise_trap(0, 2); + bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); + auto returnValue = std::make_tuple(CONT,bb); + + this->gen_trap_check(bb); + this->gen_sync(POST_SYNC, 86); + this->builder.CreateBr(bb); + return returnValue; + } + /**************************************************************************** * end opcode definitions ****************************************************************************/ - std::tuple illegal_intruction(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) { - this->gen_sync(iss::PRE_SYNC, instr_descr.size()); + std::tuple illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) { + this->gen_sync(iss::PRE_SYNC, instr_descr.size()); this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true), - get_reg_ptr(traits::PC), true); + get_reg_ptr(traits::PC), true); this->builder.CreateStore( this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits::ICOUNT), get_reg_ptr(traits::ICOUNT), true), - this->gen_const(64U, 1)), + this->gen_const(64U, 1)), get_reg_ptr(traits::ICOUNT), true); pc = pc + ((instr & 3) == 3 ? 4 : 2); - this->gen_raise_trap(0, 2); // illegal instruction trap - this->gen_sync(iss::POST_SYNC, instr_descr.size()); + this->gen_raise_trap(0, 2); // illegal instruction trap + this->gen_sync(iss::POST_SYNC, instr_descr.size()); this->gen_trap_check(this->leave_blk); return std::make_tuple(BRANCH, nullptr); - } - // decoding functionality + } + //decoding functionality - void populate_decoding_tree(decoding_tree_node* root) { - // create submask - for(auto instr : root->instrs) { + void populate_decoding_tree(decoding_tree_node* root){ + //create submask + for(auto instr: root->instrs){ root->submask &= instr.mask; } - // put each instr according to submask&encoding into children - for(auto instr : root->instrs) { + //put each instr according to submask&encoding into children + for(auto instr: root->instrs){ bool foundMatch = false; - for(auto child : root->children) { - // use value as identifying trait - if(child->value == (instr.value & root->submask)) { + for(auto child: root->children){ + //use value as identifying trait + if(child->value == (instr.value&root->submask)){ child->instrs.push_back(instr); foundMatch = true; } } - if(!foundMatch) { - decoding_tree_node* child = new decoding_tree_node(instr.value & root->submask); + if(!foundMatch){ + decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask); child->instrs.push_back(instr); root->children.push_back(child); } } root->instrs.clear(); - // call populate_decoding_tree for all children - if(root->children.size() > 1) - for(auto child : root->children) { - populate_decoding_tree(child); + //call populate_decoding_tree for all children + if(root->children.size() >1) + for(auto child: root->children){ + populate_decoding_tree(child); } - else { - // sort instrs by value of the mask, this works bc we want to have the least restrictive one last - std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), - [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { return instr1.mask > instr2.mask; }); + else{ + //sort instrs by value of the mask, this works bc we want to have the least restrictive one last + std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { + return instr1.mask > instr2.mask; + }); } } - compile_func decode_instr(decoding_tree_node* node, code_word_t word) { - if(!node->children.size()) { - if(node->instrs.size() == 1) - return node->instrs[0].op; - for(auto instr : node->instrs) { - if((instr.mask & word) == instr.value) - return instr.op; + compile_func decode_instr(decoding_tree_node* node, code_word_t word){ + if(!node->children.size()){ + if(node->instrs.size() == 1) return node->instrs[0].op; + for(auto instr : node->instrs){ + if((instr.mask&word) == instr.value) return instr.op; } - } else { - for(auto child : node->children) { - if(child->value == (node->submask & word)) { + } + else{ + for(auto child : node->children){ + if (child->value == (node->submask&word)){ return decode_instr(child, word); - } - } + } + } } return nullptr; } @@ -3983,125 +4438,132 @@ template void debug_fn(CODE_WORD instr) { template vm_impl::vm_impl() { this(new ARCH()); } template -vm_impl::vm_impl(ARCH& core, unsigned core_id, unsigned cluster_id) +vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) : vm_base(core, core_id, cluster_id) { root = new decoding_tree_node(std::numeric_limits::max()); - for(auto instr : instr_descr) { + for(auto instr:instr_descr){ root->instrs.push_back(instr); } populate_decoding_tree(root); } template -std::tuple vm_impl::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, - BasicBlock* this_block) { +std::tuple +vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) { // we fetch at max 4 byte, alignment is 2 - enum { TRAP_ID = 1 << 16 }; + enum {TRAP_ID=1<<16}; code_word_t instr = 0; // const typename traits::addr_t upper_bits = ~traits::PGMASK; phys_addr_t paddr(pc); - auto* const data = (uint8_t*)&instr; + auto *const data = (uint8_t *)&instr; if(this->core.has_mmu()) paddr = this->core.virt2phys(pc); - // TODO: re-add page handling - // if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary - // auto res = this->core.read(paddr, 2, data); - // if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); - // if ((instr & 0x3) == 0x3) { // this is a 32bit instruction - // res = this->core.read(this->core.v2p(pc + 2), 2, data + 2); - // } - // } else { - auto res = this->core.read(paddr, 4, data); - if(res != iss::Ok) - throw trap_access(TRAP_ID, pc.val); - // } - if(instr == 0x0000006f || (instr & 0xffff) == 0xa001) - throw simulation_stopped(0); // 'J 0' or 'C.J 0' + //TODO: re-add page handling +// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary +// auto res = this->core.read(paddr, 2, data); +// if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); +// if ((instr & 0x3) == 0x3) { // this is a 32bit instruction +// res = this->core.read(this->core.v2p(pc + 2), 2, data + 2); +// } +// } else { + auto res = this->core.read(paddr, 4, data); + if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); +// } + if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0' // curr pc on stack ++inst_cnt; auto f = decode_instr(root, instr); - if(f == nullptr) { + if (f == nullptr) { f = &this_class::illegal_intruction; } return (this->*f)(pc, instr, this_block); } -template void vm_impl::gen_leave_behavior(BasicBlock* leave_blk) { +template void vm_impl::gen_leave_behavior(BasicBlock *leave_blk) { this->builder.SetInsertPoint(leave_blk); - this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false)); + this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false)); } template void vm_impl::gen_raise_trap(uint16_t trap_id, uint16_t cause) { - auto* TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id); + auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id); this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } template void vm_impl::gen_leave_trap(unsigned lvl) { - std::vector args{this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl))}; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) }; this->builder.CreateCall(this->mod->getFunction("leave_trap"), args); - auto* PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8); + auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8); this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } template void vm_impl::gen_wait(unsigned type) { - std::vector args{this->core_ptr, ConstantInt::get(getContext(), APInt(64, type))}; + std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) }; this->builder.CreateCall(this->mod->getFunction("wait"), args); } -template void vm_impl::gen_trap_behavior(BasicBlock* trap_blk) { +template void vm_impl::gen_trap_behavior(BasicBlock *trap_blk) { this->builder.SetInsertPoint(trap_blk); - this->gen_sync(POST_SYNC, -1); // TODO get right InstrId - auto* trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); - this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); - std::vector args{this->core_ptr, this->adj_to64(trap_state_val), - this->adj_to64(this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), false))}; + this->gen_sync(POST_SYNC, -1); //TODO get right InstrId + auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); + this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), + get_reg_ptr(traits::LAST_BRANCH), false); + std::vector args{this->core_ptr, this->adj_to64(trap_state_val), + this->adj_to64(this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), false))}; this->builder.CreateCall(this->mod->getFunction("enter_trap"), args); - auto* trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false); + auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateRet(trap_addr_val); } -template inline void vm_impl::gen_trap_check(BasicBlock* bb) { +template inline void vm_impl::gen_trap_check(BasicBlock *bb) { auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb); - auto* v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); - this->gen_cond_branch( - this->builder.CreateICmp(ICmpInst::ICMP_EQ, v, ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))), - target_bb, this->trap_blk, 1); + auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); + this->gen_cond_branch(this->builder.CreateICmp( + ICmpInst::ICMP_EQ, v, + ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))), + target_bb, this->trap_blk, 1); this->builder.SetInsertPoint(target_bb); } } // namespace tgc5c -template <> std::unique_ptr create(arch::tgc5c* core, unsigned short port, bool dump) { +template <> +std::unique_ptr create(arch::tgc5c *core, unsigned short port, bool dump) { auto ret = new tgc5c::vm_impl(*core, dump); - if(port != 0) - debugger::server::run_server(ret, port); + if (port != 0) debugger::server::run_server(ret, port); return std::unique_ptr(ret); } } // namespace llvm } // namespace iss +#include #include #include -#include namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("tgc5c|m_p|llvm", - [](unsigned port, void*) -> std::tuple { - auto* cpu = new iss::arch::riscv_hart_m_p(); - auto* vm = new llvm::tgc5c::vm_impl(*cpu, false); - if(port != 0) - debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - }), - core_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned port, void*) -> std::tuple { - auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto* vm = new llvm::tgc5c::vm_impl(*cpu, false); - if(port != 0) - debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - })}; + core_factory::instance().register_creator("tgc5c|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_m_p(); + auto vm = new llvm::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_mu_p(); + auto vm = new llvm::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }) +}; } -} // namespace iss +} +// clang-format on \ No newline at end of file diff --git a/src/vm/tcc/vm_tgc5c.cpp b/src/vm/tcc/vm_tgc5c.cpp index dd767a0..9d4dff7 100644 --- a/src/vm/tcc/vm_tgc5c.cpp +++ b/src/vm/tcc/vm_tgc5c.cpp @@ -29,14 +29,14 @@ * POSSIBILITY OF SUCH DAMAGE. * *******************************************************************************/ - +// clang-format off #include #include #include #include #include -#include #include +#include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY @@ -55,23 +55,23 @@ using namespace iss::debugger; template class vm_impl : public iss::tcc::vm_base { public: using traits = arch::traits; - using super = typename iss::tcc::vm_base; + using super = typename iss::tcc::vm_base; using virt_addr_t = typename super::virt_addr_t; using phys_addr_t = typename super::phys_addr_t; using code_word_t = typename super::code_word_t; - using mem_type_e = typename traits::mem_type_e; - using addr_t = typename super::addr_t; - using tu_builder = typename super::tu_builder; + using mem_type_e = typename traits::mem_type_e; + using addr_t = typename super::addr_t; + using tu_builder = typename super::tu_builder; vm_impl(); - vm_impl(ARCH& core, unsigned core_id = 0, unsigned cluster_id = 0); + vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } - target_adapter_if* accquire_target_adapter(server_if* srv) override { + target_adapter_if *accquire_target_adapter(server_if *srv) override { debugger_if::dbg_enabled = true; - if(vm_base::tgt_adapter == nullptr) + if (vm_base::tgt_adapter == nullptr) vm_base::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); return vm_base::tgt_adapter; } @@ -81,13 +81,15 @@ protected: using this_class = vm_impl; using compile_ret_t = std::tuple; - using compile_func = compile_ret_t (this_class::*)(virt_addr_t& pc, code_word_t instr, tu_builder&); + using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&); - inline const char* name(size_t index) { return traits::reg_aliases.at(index); } + inline const char *name(size_t index){return traits::reg_aliases.at(index);} - void setup_module(std::string m) override { super::setup_module(m); } + void setup_module(std::string m) override { + super::setup_module(m); + } - compile_ret_t gen_single_inst_behavior(virt_addr_t&, unsigned int&, tu_builder&) override; + compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override; void gen_trap_behavior(tu_builder& tu) override; @@ -97,10 +99,12 @@ protected: void gen_wait(tu_builder& tu, unsigned type); - inline void gen_trap_check(tu_builder& tu) { tu("if(*trap_state!=0) goto trap_entry;"); } + inline void gen_trap_check(tu_builder& tu) { + tu("if(*trap_state!=0) goto trap_entry;"); + } inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) { - switch(reg_num) { + switch(reg_num){ case traits::NEXT_PC: tu("*next_pc = {:#x};", pc.val); break; @@ -108,19 +112,21 @@ protected: tu("*pc = {:#x};", pc.val); break; default: - if(!tu.defined_regs[reg_num]) { + if(!tu.defined_regs[reg_num]){ tu("reg_t* reg{:02d} = (reg_t*){:#x};", reg_num, reinterpret_cast(get_reg_ptr(reg_num))); - tu.defined_regs[reg_num] = true; + tu.defined_regs[reg_num]=true; } tu("*reg{:02d} = {:#x};", reg_num, pc.val); } } - template ::type> inline S sext(U from) { - auto mask = (1ULL << W) - 1; - auto sign_mask = 1ULL << (W - 1); + + template::type> + inline S sext(U from) { + auto mask = (1ULL< instrs; std::vector children; uint32_t submask = std::numeric_limits::max(); uint32_t value; - decoding_tree_node(uint32_t value) - : value(value) {} + decoding_tree_node(uint32_t value) : value(value){} }; - decoding_tree_node* root{nullptr}; + decoding_tree_node* root {nullptr}; const std::array instr_descr = {{ - /* entries are: size, valid value, valid mask, function ptr */ + /* entries are: size, valid value, valid mask, function ptr */ /* instruction LUI, encoding '0b00000000000000000000000000110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, /* instruction AUIPC, encoding '0b00000000000000000000000000010111' */ @@ -320,2946 +325,3239 @@ private: /* instruction DII, encoding '0b0000000000000000' */ {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, }}; - + /* instruction definitions */ /* instruction 0: LUI */ - compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LUI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 0); + vm_base::gen_sync(tu, PRE_SYNC,0); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = ((bit_sub<12, 20>(instr) << 12)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)imm), 32)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)((int32_t)imm),32)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 0); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,0); return returnValue; } - + /* instruction 1: AUIPC */ - compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AUIPC_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 1); + vm_base::gen_sync(tu, PRE_SYNC,1); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = ((bit_sub<12, 20>(instr) << 12)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)(PC + (int32_t)imm), 32)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)(PC+(int32_t)imm),32)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 1); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,1); return returnValue; } - + /* instruction 2: JAL */ - compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("JAL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 2); + vm_base::gen_sync(tu, PRE_SYNC,2); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint32_t imm = - ((bit_sub<12, 8>(instr) << 12) | (bit_sub<20, 1>(instr) << 11) | (bit_sub<21, 10>(instr) << 1) | (bit_sub<31, 1>(instr) << 20)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)(PC + 4), 32)); - } - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int32_t)sext<21>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)(PC+ 4),32)); + } + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int32_t)sext<21>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 2); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,2); return returnValue; } - + /* instruction 3: JALR */ - compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("JALR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 3); + vm_base::gen_sync(tu, PRE_SYNC,3); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto addr_mask = tu.assignment(tu.constant((uint32_t)-2, 32), 32); - auto new_pc = tu.assignment( - tu.ext((tu.bitwise_and((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), addr_mask)), 32, - false), - 32); - tu.open_if(tu.urem(new_pc, tu.constant(static_cast(traits::INSTR_ALIGNMENT), 32))); - this->gen_raise_trap(tu, 0, 0); - tu.open_else(); - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)(PC + 4), 32)); - } - auto PC_val_v = tu.assignment("PC_val", new_pc, 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - tu.close_scope(); + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto addr_mask = tu.assignment(tu.constant((uint32_t)- 2,32),32); + auto new_pc = tu.assignment(tu.ext((tu.bitwise_and( + (tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))), + addr_mask)),32,false),32); + tu.open_if(tu.urem( + new_pc, + tu.constant(static_cast(traits:: INSTR_ALIGNMENT),32))); + this->gen_raise_trap(tu, 0, 0); + tu.open_else(); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)(PC+ 4),32)); + } + auto PC_val_v = tu.assignment("PC_val", new_pc,32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 3); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,3); return returnValue; } - + /* instruction 4: BEQ */ - compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BEQ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 4); + vm_base::gen_sync(tu, PRE_SYNC,4); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 4); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,4); return returnValue; } - + /* instruction 5: BNE */ - compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BNE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 5); + vm_base::gen_sync(tu, PRE_SYNC,5); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 5); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,5); return returnValue; } - + /* instruction 6: BLT */ - compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BLT_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 6); + vm_base::gen_sync(tu, PRE_SYNC,6); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), - tu.ext(tu.load(rs2 + traits::X0, 0), 32, true))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_SLT, + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.ext(tu.load(rs2+ traits::X0, 0),32,true))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 6); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,6); return returnValue; } - + /* instruction 7: BGE */ - compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BGE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 7); + vm_base::gen_sync(tu, PRE_SYNC,7); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_SGE, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), - tu.ext(tu.load(rs2 + traits::X0, 0), 32, true))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_SGE, + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.ext(tu.load(rs2+ traits::X0, 0),32,true))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 7); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,7); return returnValue; } - + /* instruction 8: BLTU */ - compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BLTU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 8); + vm_base::gen_sync(tu, PRE_SYNC,8); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_ULT, + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 8); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,8); return returnValue; } - + /* instruction 9: BGEU */ - compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("BGEU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 9); + vm_base::gen_sync(tu, PRE_SYNC,9); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), fmt::arg("rs1", name(rs1)), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_UGE, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - if(imm % static_cast(traits::INSTR_ALIGNMENT)) { - this->gen_raise_trap(tu, 0, 0); - } else { - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } - tu.close_scope(); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_UGE, + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + } + else{ + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 9); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,9); return returnValue; } - + /* instruction 10: LB */ - compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 10); + vm_base::gen_sync(tu, PRE_SYNC,10); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto load_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 8), 8, true), 8); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto load_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 8),8,true),8); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 10); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,10); return returnValue; } - + /* instruction 11: LH */ - compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 11); + vm_base::gen_sync(tu, PRE_SYNC,11); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto load_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 16), 16, true), 16); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto load_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 16),16,true),16); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 11); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,11); return returnValue; } - + /* instruction 12: LW */ - compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 12); + vm_base::gen_sync(tu, PRE_SYNC,12); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto load_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 32), 32, true), 32); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto load_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 32),32,true),32); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 12); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,12); return returnValue; } - + /* instruction 13: LBU */ - compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LBU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 13); + vm_base::gen_sync(tu, PRE_SYNC,13); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto load_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 8), 8); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto load_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 8),8); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 13); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,13); return returnValue; } - + /* instruction 14: LHU */ - compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LHU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 14); + vm_base::gen_sync(tu, PRE_SYNC,14); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto load_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 16), 16); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto load_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 16),16); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 14); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,14); return returnValue; } - + /* instruction 15: SB */ - compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 15); + vm_base::gen_sync(tu, PRE_SYNC,15); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto store_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0), 8, false)); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto store_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2+ traits::X0, 0),8,false)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 15); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,15); return returnValue; } - + /* instruction 16: SH */ - compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 16); + vm_base::gen_sync(tu, PRE_SYNC,16); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto store_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0), 16, false)); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto store_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2+ traits::X0, 0),16,false)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 16); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,16); return returnValue; } - + /* instruction 17: SW */ - compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 17); + vm_base::gen_sync(tu, PRE_SYNC,17); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), fmt::arg("rs2", name(rs2)), - fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto store_address = - tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32); - tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0), 32, false)); + if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto store_address = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false),32); + tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2+ traits::X0, 0),32,false)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 17); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,17); return returnValue; } - + /* instruction 18: ADDI */ - compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 18); + vm_base::gen_sync(tu, PRE_SYNC,18); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int16_t)sext<12>(imm),16))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 18); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,18); return returnValue; } - + /* instruction 19: SLTI */ - compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 19); + vm_base::gen_sync(tu, PRE_SYNC,19); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), - tu.constant((int16_t)sext<12>(imm), 16))), - tu.constant(1, 8), tu.constant(0, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_SLT, + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.constant((int16_t)sext<12>(imm),16))), tu.constant( 1,8),tu.constant( 0,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 19); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,19); return returnValue; } - + /* instruction 20: SLTIU */ - compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTIU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 20); + vm_base::gen_sync(tu, PRE_SYNC,20); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1 + traits::X0, 0), - tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32))), - tu.constant(1, 8), tu.constant(0, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_ULT, + tu.load(rs1+ traits::X0, 0), + tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))), tu.constant( 1,8),tu.constant( 0,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 20); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,20); return returnValue; } - + /* instruction 21: XORI */ - compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("XORI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 21); + vm_base::gen_sync(tu, PRE_SYNC,21); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.bitwise_xor(tu.load(rs1 + traits::X0, 0), tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_xor( + tu.load(rs1+ traits::X0, 0), + tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 21); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,21); return returnValue; } - + /* instruction 22: ORI */ - compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ORI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 22); + vm_base::gen_sync(tu, PRE_SYNC,22); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.bitwise_or(tu.load(rs1 + traits::X0, 0), tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_or( + tu.load(rs1+ traits::X0, 0), + tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 22); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,22); return returnValue; } - + /* instruction 23: ANDI */ - compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ANDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 23); + vm_base::gen_sync(tu, PRE_SYNC,23); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.bitwise_and(tu.load(rs1 + traits::X0, 0), tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_and( + tu.load(rs1+ traits::X0, 0), + tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 23); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,23); return returnValue; } - + /* instruction 24: SLLI */ - compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 24); + vm_base::gen_sync(tu, PRE_SYNC,24); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.shl(tu.load(rs1 + traits::X0, 0), tu.constant(shamt, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.shl( + tu.load(rs1+ traits::X0, 0), + tu.constant(shamt,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 24); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,24); return returnValue; } - + /* instruction 25: SRLI */ - compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 25); + vm_base::gen_sync(tu, PRE_SYNC,25); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.lshr(tu.load(rs1 + traits::X0, 0), tu.constant(shamt, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.lshr( + tu.load(rs1+ traits::X0, 0), + tu.constant(shamt,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 25); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,25); return returnValue; } - + /* instruction 26: SRAI */ - compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 26); + vm_base::gen_sync(tu, PRE_SYNC,26); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t shamt = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.ext((tu.ashr(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), tu.constant(shamt, 8))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.ashr( + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.constant(shamt,8))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 26); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,26); return returnValue; } - + /* instruction 27: ADD */ - compile_ret_t __add(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 27); + vm_base::gen_sync(tu, PRE_SYNC,27); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 27); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,27); return returnValue; } - + /* instruction 28: SUB */ - compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SUB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 28); + vm_base::gen_sync(tu, PRE_SYNC,28); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.sub(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.sub( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 28); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,28); return returnValue; } - + /* instruction 29: SLL */ - compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 29); + vm_base::gen_sync(tu, PRE_SYNC,29); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.shl(tu.load(rs1 + traits::X0, 0), - (tu.bitwise_and(tu.load(rs2 + traits::X0, 0), - tu.constant((static_cast(traits::XLEN) - 1), 64))))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.shl( + tu.load(rs1+ traits::X0, 0), + (tu.bitwise_and( + tu.load(rs2+ traits::X0, 0), + tu.constant((static_cast(traits:: XLEN)- 1),64))))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 29); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,29); return returnValue; } - + /* instruction 30: SLT */ - compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLT_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 30); + vm_base::gen_sync(tu, PRE_SYNC,30); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), - tu.ext(tu.load(rs2 + traits::X0, 0), 32, true)), - tu.constant(1, 8), tu.constant(0, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_SLT, + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.ext(tu.load(rs2+ traits::X0, 0),32,true)), tu.constant( 1,8),tu.constant( 0,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 30); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,30); return returnValue; } - + /* instruction 31: SLTU */ - compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLTU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 31); + vm_base::gen_sync(tu, PRE_SYNC,31); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, - tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0)), - tu.constant(1, 8), tu.constant(0, 8))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_ULT, + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0)), tu.constant( 1,8),tu.constant( 0,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 31); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,31); return returnValue; } - + /* instruction 32: XOR */ - compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("XOR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 32); + vm_base::gen_sync(tu, PRE_SYNC,32); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.bitwise_xor(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_xor( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 32); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,32); return returnValue; } - + /* instruction 33: SRL */ - compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 33); + vm_base::gen_sync(tu, PRE_SYNC,33); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.lshr(tu.load(rs1 + traits::X0, 0), - (tu.bitwise_and(tu.load(rs2 + traits::X0, 0), - tu.constant((static_cast(traits::XLEN) - 1), 64))))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.lshr( + tu.load(rs1+ traits::X0, 0), + (tu.bitwise_and( + tu.load(rs2+ traits::X0, 0), + tu.constant((static_cast(traits:: XLEN)- 1),64))))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 33); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,33); return returnValue; } - + /* instruction 34: SRA */ - compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRA_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 34); + vm_base::gen_sync(tu, PRE_SYNC,34); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.ashr(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), - (tu.bitwise_and(tu.load(rs2 + traits::X0, 0), - tu.constant((static_cast(traits::XLEN) - 1), 64))))), - 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.ashr( + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + (tu.bitwise_and( + tu.load(rs2+ traits::X0, 0), + tu.constant((static_cast(traits:: XLEN)- 1),64))))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 34); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,34); return returnValue; } - + /* instruction 35: OR */ - compile_ret_t __or(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("OR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 35); + vm_base::gen_sync(tu, PRE_SYNC,35); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.bitwise_or(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_or( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 35); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,35); return returnValue; } - + /* instruction 36: AND */ - compile_ret_t __and(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AND_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 36); + vm_base::gen_sync(tu, PRE_SYNC,36); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.bitwise_and(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.bitwise_and( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 36); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,36); return returnValue; } - + /* instruction 37: FENCE */ - compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FENCE_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 37); + vm_base::gen_sync(tu, PRE_SYNC,37); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t succ = ((bit_sub<20, 4>(instr))); - uint8_t pred = ((bit_sub<24, 4>(instr))); - uint8_t fm = ((bit_sub<28, 4>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); + uint8_t fm = ((bit_sub<28,4>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = - fmt::format("{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), fmt::arg("pred", pred), - fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); + auto mnemonic = fmt::format( + "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), + fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.write_mem(traits::FENCE, static_cast(traits::fence), tu.constant((uint8_t)pred << 4 | succ, 8)); + tu.write_mem(traits::FENCE, static_cast(traits:: fence), tu.constant((uint8_t)pred<< 4|succ,8)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 37); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,37); return returnValue; } - + /* instruction 38: ECALL */ - compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ECALL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 38); + vm_base::gen_sync(tu, PRE_SYNC,38); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ecall"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 11); + this->gen_raise_trap(tu, 0, 11); auto returnValue = std::make_tuple(TRAP); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 38); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,38); return returnValue; } - + /* instruction 39: EBREAK */ - compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("EBREAK_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 39); + vm_base::gen_sync(tu, PRE_SYNC,39); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ebreak"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 3); + this->gen_raise_trap(tu, 0, 3); auto returnValue = std::make_tuple(TRAP); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 39); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,39); return returnValue; } - + /* instruction 40: MRET */ - compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MRET_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 40); + vm_base::gen_sync(tu, PRE_SYNC,40); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "mret"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); this->gen_leave_trap(tu, 3); auto returnValue = std::make_tuple(TRAP); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 40); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,40); return returnValue; } - + /* instruction 41: WFI */ - compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("WFI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 41); + vm_base::gen_sync(tu, PRE_SYNC,41); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "wfi"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); this->gen_wait(tu, 1); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 41); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,41); return returnValue; } - + /* instruction 42: CSRRW */ - compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 42); + vm_base::gen_sync(tu, PRE_SYNC,42); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrs1 = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); - if(rd != 0) { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - tu.write_mem(traits::CSR, csr, xrs1); - tu.store(rd + traits::X0, xrd); - } else { - tu.write_mem(traits::CSR, csr, xrs1); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32); + if(rd!= 0){ auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + tu.write_mem(traits::CSR, csr, xrs1); + tu.store(rd + traits::X0, + xrd); + } + else{ + tu.write_mem(traits::CSR, csr, xrs1); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 42); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,42); return returnValue; } - + /* instruction 43: CSRRS */ - compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRS_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 43); + vm_base::gen_sync(tu, PRE_SYNC,43); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - auto xrs1 = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); - if(rs1 != 0) { - tu.write_mem(traits::CSR, csr, tu.bitwise_or(xrd, xrs1)); - } - if(rd != 0) { - tu.store(rd + traits::X0, xrd); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32); + if(rs1!= 0) { + tu.write_mem(traits::CSR, csr, tu.bitwise_or( + xrd, + xrs1)); + } + if(rd!= 0) { + tu.store(rd + traits::X0, + xrd); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 43); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,43); return returnValue; } - + /* instruction 44: CSRRC */ - compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRC_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 44); + vm_base::gen_sync(tu, PRE_SYNC,44); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - auto xrs1 = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); - if(rs1 != 0) { - tu.write_mem(traits::CSR, csr, tu.bitwise_and(xrd, tu.logical_neg(xrs1))); - } - if(rd != 0) { - tu.store(rd + traits::X0, xrd); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32); + if(rs1!= 0) { + tu.write_mem(traits::CSR, csr, tu.bitwise_and( + xrd, + tu.logical_neg(xrs1))); + } + if(rd!= 0) { + tu.store(rd + traits::X0, + xrd); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 44); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,44); return returnValue; } - + /* instruction 45: CSRRWI */ - compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRWI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 45); + vm_base::gen_sync(tu, PRE_SYNC,45); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - tu.write_mem(traits::CSR, csr, tu.constant((uint32_t)zimm, 32)); - if(rd != 0) { - tu.store(rd + traits::X0, xrd); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + tu.write_mem(traits::CSR, csr, tu.constant((uint32_t)zimm,32)); + if(rd!= 0) { + tu.store(rd + traits::X0, + xrd); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 45); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,45); return returnValue; } - + /* instruction 46: CSRRSI */ - compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRSI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 46); + vm_base::gen_sync(tu, PRE_SYNC,46); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - if(zimm != 0) { - tu.write_mem(traits::CSR, csr, tu.bitwise_or(xrd, tu.constant((uint32_t)zimm, 32))); - } - if(rd != 0) { - tu.store(rd + traits::X0, xrd); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + if(zimm!= 0) { + tu.write_mem(traits::CSR, csr, tu.bitwise_or( + xrd, + tu.constant((uint32_t)zimm,32))); + } + if(rd!= 0) { + tu.store(rd + traits::X0, + xrd); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 46); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,46); return returnValue; } - + /* instruction 47: CSRRCI */ - compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("CSRRCI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 47); + vm_base::gen_sync(tu, PRE_SYNC,47); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t zimm = ((bit_sub<15, 5>(instr))); - uint16_t csr = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), fmt::arg("rd", name(rd)), - fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32); - if(zimm != 0) { - tu.write_mem(traits::CSR, csr, tu.bitwise_and(xrd, tu.constant(~((uint32_t)zimm), 32))); - } - if(rd != 0) { - tu.store(rd + traits::X0, xrd); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + if(zimm!= 0) { + tu.write_mem(traits::CSR, csr, tu.bitwise_and( + xrd, + tu.constant(~ ((uint32_t)zimm),32))); + } + if(rd!= 0) { + tu.store(rd + traits::X0, + xrd); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 47); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,47); return returnValue; } - + /* instruction 48: FENCE_I */ - compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FENCE_I_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 48); + vm_base::gen_sync(tu, PRE_SYNC,48); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint16_t imm = ((bit_sub<20, 12>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), fmt::arg("rs1", name(rs1)), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), + fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.write_mem(traits::FENCE, static_cast(traits::fencei), tu.constant(imm, 16)); + tu.write_mem(traits::FENCE, static_cast(traits:: fencei), tu.constant(imm,16)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 48); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,48); return returnValue; } - + /* instruction 49: MUL */ - compile_ret_t __mul(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __mul(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MUL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 49); + vm_base::gen_sync(tu, PRE_SYNC,49); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 64, true), - tu.ext(tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), 64, true))), - 64, true), - 64); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext(res, 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto res = tu.assignment(tu.ext((tu.mul( + tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,true), + tu.ext(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),64,true))),64,true),64); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext(res,32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 49); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,49); return returnValue; } - + /* instruction 50: MULH */ - compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 50); + vm_base::gen_sync(tu, PRE_SYNC,50); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 64, true), - tu.ext(tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), 64, true))), - 64, true), - 64); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.ashr(res, tu.constant(static_cast(traits::XLEN), 32))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto res = tu.assignment(tu.ext((tu.mul( + tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,true), + tu.ext(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),64,true))),64,true),64); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext((tu.ashr( + res, + tu.constant(static_cast(traits:: XLEN),32))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 50); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,50); return returnValue; } - + /* instruction 51: MULHSU */ - compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHSU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 51); + vm_base::gen_sync(tu, PRE_SYNC,51); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 64, true), - tu.ext(tu.load(rs2 + traits::X0, 0), 64, false))), - 64, true), - 64); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.ashr(res, tu.constant(static_cast(traits::XLEN), 32))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto res = tu.assignment(tu.ext((tu.mul( + tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,true), + tu.ext(tu.load(rs2+ traits::X0, 0),64,false))),64,true),64); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext((tu.ashr( + res, + tu.constant(static_cast(traits:: XLEN),32))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 51); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,51); return returnValue; } - + /* instruction 52: MULHU */ - compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 52); + vm_base::gen_sync(tu, PRE_SYNC,52); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto res = tu.assignment( - tu.ext((tu.mul(tu.ext(tu.load(rs1 + traits::X0, 0), 64, false), tu.ext(tu.load(rs2 + traits::X0, 0), 64, false))), 64, - false), - 64); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.lshr(res, tu.constant(static_cast(traits::XLEN), 32))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto res = tu.assignment(tu.ext((tu.mul( + tu.ext(tu.load(rs1+ traits::X0, 0),64,false), + tu.ext(tu.load(rs2+ traits::X0, 0),64,false))),64,false),64); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext((tu.lshr( + res, + tu.constant(static_cast(traits:: XLEN),32))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 52); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,52); return returnValue; } - + /* instruction 53: DIV */ - compile_ret_t __div(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __div(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIV_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 53); + vm_base::gen_sync(tu, PRE_SYNC,53); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto dividend = tu.assignment(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 32); - auto divisor = tu.assignment(tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), 32); - if(rd != 0) { - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, divisor, tu.constant(0, 8))); - auto MMIN = tu.assignment(tu.constant(((uint32_t)1) << (static_cast(traits::XLEN) - 1), 32), 32); - tu.open_if(tu.logical_and(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + traits::X0, 0), MMIN), - tu.icmp(ICmpInst::ICMP_EQ, divisor, tu.constant(-1, 8)))); - tu.store(rd + traits::X0, MMIN); - tu.open_else(); - tu.store(rd + traits::X0, tu.ext((tu.sdiv(dividend, divisor)), 32, false)); - tu.close_scope(); - tu.open_else(); - tu.store(rd + traits::X0, tu.constant((uint32_t)-1, 32)); - tu.close_scope(); - } + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto dividend = tu.assignment(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),32); + auto divisor = tu.assignment(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),32); + if(rd!= 0){ tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + divisor, + tu.constant( 0,8))); + auto MMIN = tu.assignment(tu.constant(((uint32_t)1)<<(static_cast(traits:: XLEN)-1),32),32); + tu.open_if(tu.logical_and( + tu.icmp(ICmpInst::ICMP_EQ, + tu.load(rs1+ traits::X0, 0), + MMIN), + tu.icmp(ICmpInst::ICMP_EQ, + divisor, + tu.constant(- 1,8)))); + tu.store(rd + traits::X0, + MMIN); + tu.open_else(); + tu.store(rd + traits::X0, + tu.ext((tu.sdiv( + dividend, + divisor)),32,false)); + tu.close_scope(); + tu.open_else(); + tu.store(rd + traits::X0, + tu.constant((uint32_t)- 1,32)); + tu.close_scope(); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 53); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,53); return returnValue; } - + /* instruction 54: DIVU */ - compile_ret_t __divu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __divu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIVU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 54); + vm_base::gen_sync(tu, PRE_SYNC,54); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2 + traits::X0, 0), tu.constant(0, 8))); - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.udiv(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false)); - } - tu.open_else(); - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)-1, 32)); - } - tu.close_scope(); + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + tu.load(rs2+ traits::X0, 0), + tu.constant( 0,8))); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext((tu.udiv( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))),32,false)); + } + tu.open_else(); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)- 1,32)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 54); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,54); return returnValue; } - + /* instruction 55: REM */ - compile_ret_t __rem(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __rem(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REM_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 55); + vm_base::gen_sync(tu, PRE_SYNC,55); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2 + traits::X0, 0), tu.constant(0, 8))); - auto MMIN = tu.assignment(tu.constant((uint32_t)1 << (static_cast(traits::XLEN) - 1), 32), 32); - tu.open_if(tu.logical_and(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + traits::X0, 0), MMIN), - tu.icmp(ICmpInst::ICMP_EQ, tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), tu.constant(-1, 8)))); - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant(0, 8)); - } - tu.open_else(); - if(rd != 0) { - tu.store(rd + traits::X0, - tu.ext((tu.srem(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), tu.ext(tu.load(rs2 + traits::X0, 0), 32, true))), - 32, false)); - } - tu.close_scope(); - tu.open_else(); - if(rd != 0) { - tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0)); - } - tu.close_scope(); + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + tu.load(rs2+ traits::X0, 0), + tu.constant( 0,8))); + auto MMIN = tu.assignment(tu.constant((uint32_t)1<<(static_cast(traits:: XLEN)-1),32),32); + tu.open_if(tu.logical_and( + tu.icmp(ICmpInst::ICMP_EQ, + tu.load(rs1+ traits::X0, 0), + MMIN), + tu.icmp(ICmpInst::ICMP_EQ, + tu.ext(tu.load(rs2+ traits::X0, 0),32,true), + tu.constant(- 1,8)))); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.constant( 0,8)); + } + tu.open_else(); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.ext((tu.srem( + tu.ext(tu.load(rs1+ traits::X0, 0),32,true), + tu.ext(tu.load(rs2+ traits::X0, 0),32,true))),32,false)); + } + tu.close_scope(); + tu.open_else(); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.load(rs1+ traits::X0, 0)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 55); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,55); return returnValue; } - + /* instruction 56: REMU */ - compile_ret_t __remu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __remu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REMU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 56); + vm_base::gen_sync(tu, PRE_SYNC,56); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - uint8_t rs1 = ((bit_sub<15, 5>(instr))); - uint8_t rs2 = ((bit_sub<20, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), fmt::arg("rd", name(rd)), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 4; + pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rs1 >= static_cast(traits::RFS) || - rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2 + traits::X0, 0), tu.constant(0, 8))); - if(rd != 0) { - tu.store(rd + traits::X0, tu.urem(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))); - } - tu.open_else(); - if(rd != 0) { - tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0)); - } - tu.close_scope(); + if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + tu.load(rs2+ traits::X0, 0), + tu.constant( 0,8))); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.urem( + tu.load(rs1+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))); + } + tu.open_else(); + if(rd!=0) { + tu.store(rd + traits::X0, + tu.load(rs1+ traits::X0, 0)); + } + tu.close_scope(); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 56); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,56); return returnValue; } - + /* instruction 57: C__ADDI4SPN */ - compile_ret_t __c__addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__ADDI4SPN_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 57); + vm_base::gen_sync(tu, PRE_SYNC,57); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<2, 3>(instr))); - uint16_t imm = - ((bit_sub<5, 1>(instr) << 3) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<7, 4>(instr) << 6) | (bit_sub<11, 2>(instr) << 4)); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"), fmt::arg("rd", name(8 + rd)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"), + fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(imm) { - tu.store(rd + 8 + traits::X0, tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant(imm, 16))), 32, false)); - } else { - this->gen_raise_trap(tu, 0, 2); + tu.store(rd+ 8 + traits::X0, + tu.ext((tu.add( + tu.load(2+ traits::X0, 0), + tu.constant(imm,16))),32,false)); + } + else{ + this->gen_raise_trap(tu, 0, 2); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 57); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,57); return returnValue; } - + /* instruction 58: C__LW */ - compile_ret_t __c__lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__LW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 58); + vm_base::gen_sync(tu, PRE_SYNC,58); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<2, 3>(instr))); - uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"), - fmt::arg("rd", name(8 + rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - auto offs = tu.assignment(tu.ext((tu.add(tu.load(rs1 + 8 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32); - tu.store(rd + 8 + traits::X0, tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32), 32, true), 32, false)); + auto offs = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant(uimm,8))),32,false),32); + tu.store(rd+ 8 + traits::X0, + tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 58); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,58); return returnValue; } - + /* instruction 59: C__SW */ - compile_ret_t __c__sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 59); + vm_base::gen_sync(tu, PRE_SYNC,59); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"), - fmt::arg("rs2", name(8 + rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - auto offs = tu.assignment(tu.ext((tu.add(tu.load(rs1 + 8 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32); - tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2 + 8 + traits::X0, 0), 32, false)); + auto offs = tu.assignment(tu.ext((tu.add( + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant(uimm,8))),32,false),32); + tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2+ 8+ traits::X0, 0),32,false)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 59); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,59); return returnValue; } - + /* instruction 60: C__ADDI */ - compile_ret_t __c__addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__ADDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 60); + vm_base::gen_sync(tu, PRE_SYNC,60); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"), fmt::arg("rs1", name(rs1)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rs1 != 0) { - tu.store(rs1 + traits::X0, tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int8_t)sext<6>(imm), 8))), 32, false)); - } + if(rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rs1!= 0) { + tu.store(rs1 + traits::X0, + tu.ext((tu.add( + tu.load(rs1+ traits::X0, 0), + tu.constant((int8_t)sext<6>(imm),8))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 60); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,60); return returnValue; } - + /* instruction 61: C__NOP */ - compile_ret_t __c__nop(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__nop(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__NOP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 61); + vm_base::gen_sync(tu, PRE_SYNC,61); uint64_t PC = pc.val; - uint8_t nzimm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - if(this->disass_enabled) { + uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c__nop"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 61); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,61); return returnValue; } - + /* instruction 62: C__JAL */ - compile_ret_t __c__jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__JAL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 62); + vm_base::gen_sync(tu, PRE_SYNC,62); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) | - (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11)); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"), + fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(1 + traits::X0, tu.constant((uint32_t)(PC + 2), 32)); - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<12>(imm)), 32); + tu.store(1 + traits::X0, + tu.constant((uint32_t)(PC+ 2),32)); + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<12>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 62); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,62); return returnValue; } - + /* instruction 63: C__LI */ - compile_ret_t __c__li(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__li(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__LI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 63); + vm_base::gen_sync(tu, PRE_SYNC,63); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)((int8_t)sext<6>(imm)), 32)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)((int8_t)sext<6>(imm)),32)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 63); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,63); return returnValue; } - + /* instruction 64: C__LUI */ - compile_ret_t __c__lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__LUI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 64); + vm_base::gen_sync(tu, PRE_SYNC,64); uint64_t PC = pc.val; - uint32_t imm = ((bit_sub<2, 5>(instr) << 12) | (bit_sub<12, 1>(instr) << 17)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"), fmt::arg("rd", name(rd)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(imm == 0 || rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); + if(imm== 0||rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); } - if(rd != 0) { - tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)sext<18>(imm)), 32)); + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.constant((uint32_t)((int32_t)sext<18>(imm)),32)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 64); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,64); return returnValue; } - + /* instruction 65: C__ADDI16SP */ - compile_ret_t __c__addi16sp(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__addi16sp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__ADDI16SP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 65); + vm_base::gen_sync(tu, PRE_SYNC,65); uint64_t PC = pc.val; - uint16_t nzimm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 7) | (bit_sub<5, 1>(instr) << 6) | - (bit_sub<6, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 9)); - if(this->disass_enabled) { + uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"), fmt::arg("nzimm", nzimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"), + fmt::arg("nzimm", nzimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(nzimm) { - tu.store(2 + traits::X0, tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant((int16_t)sext<10>(nzimm), 16))), 32, false)); - } else { - this->gen_raise_trap(tu, 0, 2); + tu.store(2 + traits::X0, + tu.ext((tu.add( + tu.load(2+ traits::X0, 0), + tu.constant((int16_t)sext<10>(nzimm),16))),32,false)); + } + else{ + this->gen_raise_trap(tu, 0, 2); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 65); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,65); return returnValue; } - + /* instruction 66: __reserved_clui */ - compile_ret_t ____reserved_clui(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t ____reserved_clui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("__reserved_clui_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 66); + vm_base::gen_sync(tu, PRE_SYNC,66); uint64_t PC = pc.val; - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "__reserved_clui"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 66); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,66); return returnValue; } - + /* instruction 67: C__SRLI */ - compile_ret_t __c__srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 67); + vm_base::gen_sync(tu, PRE_SYNC,67); uint64_t PC = pc.val; - uint8_t shamt = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("shamt", shamt)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rs1 + 8 + traits::X0, tu.lshr(tu.load(rs1 + 8 + traits::X0, 0), tu.constant(shamt, 8))); + tu.store(rs1+ 8 + traits::X0, + tu.lshr( + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant(shamt,8))); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 67); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,67); return returnValue; } - + /* instruction 68: C__SRAI */ - compile_ret_t __c__srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 68); + vm_base::gen_sync(tu, PRE_SYNC,68); uint64_t PC = pc.val; - uint8_t shamt = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t shamt = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("shamt", shamt)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(shamt) { - tu.store(rs1 + 8 + traits::X0, - tu.ext((tu.ashr((tu.ext(tu.load(rs1 + 8 + traits::X0, 0), 32, true)), tu.constant(shamt, 8))), 32, false)); - } else { - if(static_cast(traits::XLEN) == 128) { - tu.store(rs1 + 8 + traits::X0, - tu.ext((tu.ashr((tu.ext(tu.load(rs1 + 8 + traits::X0, 0), 32, true)), tu.constant(64, 8))), 32, false)); - } + if(shamt){ tu.store(rs1+ 8 + traits::X0, + tu.ext((tu.ashr( + (tu.ext(tu.load(rs1+ 8+ traits::X0, 0),32,true)), + tu.constant(shamt,8))),32,false)); + } + else{ + if(static_cast(traits:: XLEN)== 128){ tu.store(rs1+ 8 + traits::X0, + tu.ext((tu.ashr( + (tu.ext(tu.load(rs1+ 8+ traits::X0, 0),32,true)), + tu.constant( 64,8))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 68); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,68); return returnValue; } - + /* instruction 69: C__ANDI */ - compile_ret_t __c__andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__ANDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 69); + vm_base::gen_sync(tu, PRE_SYNC,69); uint64_t PC = pc.val; - uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rs1 + 8 + traits::X0, - tu.ext((tu.bitwise_and(tu.load(rs1 + 8 + traits::X0, 0), tu.constant((int8_t)sext<6>(imm), 8))), 32, false)); + tu.store(rs1+ 8 + traits::X0, + tu.ext((tu.bitwise_and( + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant((int8_t)sext<6>(imm),8))),32,false)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 69); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,69); return returnValue; } - + /* instruction 70: C__SUB */ - compile_ret_t __c__sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SUB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 70); + vm_base::gen_sync(tu, PRE_SYNC,70); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd + 8 + traits::X0, tu.ext((tu.sub(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0))), 32, false)); + tu.store(rd+ 8 + traits::X0, + tu.ext((tu.sub( + tu.load(rd+ 8+ traits::X0, 0), + tu.load(rs2+ 8+ traits::X0, 0))),32,false)); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 70); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,70); return returnValue; } - + /* instruction 71: C__XOR */ - compile_ret_t __c__xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__XOR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 71); + vm_base::gen_sync(tu, PRE_SYNC,71); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd + 8 + traits::X0, tu.bitwise_xor(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0))); + tu.store(rd+ 8 + traits::X0, + tu.bitwise_xor( + tu.load(rd+ 8+ traits::X0, 0), + tu.load(rs2+ 8+ traits::X0, 0))); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 71); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,71); return returnValue; } - + /* instruction 72: C__OR */ - compile_ret_t __c__or(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__OR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 72); + vm_base::gen_sync(tu, PRE_SYNC,72); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd + 8 + traits::X0, tu.bitwise_or(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0))); + tu.store(rd+ 8 + traits::X0, + tu.bitwise_or( + tu.load(rd+ 8+ traits::X0, 0), + tu.load(rs2+ 8+ traits::X0, 0))); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 72); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,72); return returnValue; } - + /* instruction 73: C__AND */ - compile_ret_t __c__and(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__AND_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 73); + vm_base::gen_sync(tu, PRE_SYNC,73); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 3>(instr))); - uint8_t rd = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"), fmt::arg("rd", name(8 + rd)), - fmt::arg("rs2", name(8 + rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd + 8 + traits::X0, tu.bitwise_and(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0))); + tu.store(rd+ 8 + traits::X0, + tu.bitwise_and( + tu.load(rd+ 8+ traits::X0, 0), + tu.load(rs2+ 8+ traits::X0, 0))); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 73); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,73); return returnValue; } - + /* instruction 74: C__J */ - compile_ret_t __c__j(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__j(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__J_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 74); + vm_base::gen_sync(tu, PRE_SYNC,74); uint64_t PC = pc.val; - uint16_t imm = - ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) | - (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11)); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"), fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"), + fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<12>(imm)), 32); + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<12>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 74); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,74); return returnValue; } - + /* instruction 75: C__BEQZ */ - compile_ret_t __c__beqz(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__beqz(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__BEQZ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 75); + vm_base::gen_sync(tu, PRE_SYNC,75); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) | - (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + 8 + traits::X0, 0), tu.constant(0, 8))); - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<9>(imm)), 32); + tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant( 0,8))); + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); tu.close_scope(); auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 75); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,75); return returnValue; } - + /* instruction 76: C__BNEZ */ - compile_ret_t __c__bnez(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__bnez(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__BNEZ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 76); + vm_base::gen_sync(tu, PRE_SYNC,76); uint64_t PC = pc.val; - uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) | - (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8)); - uint8_t rs1 = ((bit_sub<7, 3>(instr))); - if(this->disass_enabled) { + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"), fmt::arg("rs1", name(8 + rs1)), - fmt::arg("imm", imm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs1 + 8 + traits::X0, 0), tu.constant(0, 8))); - auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<9>(imm)), 32); + tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + tu.load(rs1+ 8+ traits::X0, 0), + tu.constant( 0,8))); + auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); tu.close_scope(); auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 76); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,76); return returnValue; } - + /* instruction 77: C__SLLI */ - compile_ret_t __c__slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 77); + vm_base::gen_sync(tu, PRE_SYNC,77); uint64_t PC = pc.val; - uint8_t nzuimm = ((bit_sub<2, 5>(instr))); - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t nzuimm = ((bit_sub<2,5>(instr))); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"), fmt::arg("rs1", name(rs1)), - fmt::arg("nzuimm", nzuimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rs1 != 0) { - tu.store(rs1 + traits::X0, tu.shl(tu.load(rs1 + traits::X0, 0), tu.constant(nzuimm, 8))); - } + if(rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rs1!= 0) { + tu.store(rs1 + traits::X0, + tu.shl( + tu.load(rs1+ traits::X0, 0), + tu.constant(nzuimm,8))); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 77); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,77); return returnValue; } - + /* instruction 78: C__LWSP */ - compile_ret_t __c__lwsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__lwsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__LWSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 78); + vm_base::gen_sync(tu, PRE_SYNC,78); uint64_t PC = pc.val; - uint8_t uimm = ((bit_sub<2, 2>(instr) << 6) | (bit_sub<4, 3>(instr) << 2) | (bit_sub<12, 1>(instr) << 5)); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"), fmt::arg("rd", name(rd)), - fmt::arg("uimm", uimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS) || rd == 0) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto offs = tu.assignment(tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32); - tu.store(rd + traits::X0, tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32), 32, true), 32, false)); + if(rd>=static_cast(traits:: RFS)||rd== 0) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto offs = tu.assignment(tu.ext((tu.add( + tu.load(2+ traits::X0, 0), + tu.constant(uimm,8))),32,false),32); + tu.store(rd + traits::X0, + tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 78); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,78); return returnValue; } - + /* instruction 79: C__MV */ - compile_ret_t __c__mv(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__mv(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__MV_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 79); + vm_base::gen_sync(tu, PRE_SYNC,79); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"), fmt::arg("rd", name(rd)), - fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.load(rs2 + traits::X0, 0)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.load(rs2+ traits::X0, 0)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 79); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,79); return returnValue; } - + /* instruction 80: C__JR */ - compile_ret_t __c__jr(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__jr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__JR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 80); + vm_base::gen_sync(tu, PRE_SYNC,80); uint64_t PC = pc.val; - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"), + fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs1 && rs1 < static_cast(traits::RFS)) { - auto PC_val_v = tu.assignment( - "PC_val", tu.bitwise_and(tu.load(rs1 % static_cast(traits::RFS) + traits::X0, 0), tu.constant(~0x1, 8)), 32); + if(rs1&&rs1(traits:: RFS)) { + auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and( + tu.load(rs1%static_cast(traits:: RFS)+ traits::X0, 0), + tu.constant(~ 0x1,8)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); - } else { - this->gen_raise_trap(tu, 0, 2); + } + else{ + this->gen_raise_trap(tu, 0, 2); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 80); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,80); return returnValue; } - + /* instruction 81: __reserved_cmv */ - compile_ret_t ____reserved_cmv(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t ____reserved_cmv(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("__reserved_cmv_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 81); + vm_base::gen_sync(tu, PRE_SYNC,81); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "__reserved_cmv"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); this->gen_raise_trap(tu, 0, 2); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 81); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,81); return returnValue; } - + /* instruction 82: C__ADD */ - compile_ret_t __c__add(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__ADD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 82); + vm_base::gen_sync(tu, PRE_SYNC,82); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t rd = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t rd = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"), fmt::arg("rd", name(rd)), - fmt::arg("rs2", name(rs2))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - if(rd != 0) { - tu.store(rd + traits::X0, tu.ext((tu.add(tu.load(rd + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false)); - } + if(rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + if(rd!= 0) { + tu.store(rd + traits::X0, + tu.ext((tu.add( + tu.load(rd+ traits::X0, 0), + tu.load(rs2+ traits::X0, 0))),32,false)); + } } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 82); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,82); return returnValue; } - + /* instruction 83: C__JALR */ - compile_ret_t __c__jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__JALR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 83); + vm_base::gen_sync(tu, PRE_SYNC,83); uint64_t PC = pc.val; - uint8_t rs1 = ((bit_sub<7, 5>(instr))); - if(this->disass_enabled) { + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"), fmt::arg("rs1", name(rs1))); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"), + fmt::arg("rs1", name(rs1))); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs1 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto new_pc = tu.assignment(tu.load(rs1 + traits::X0, 0), 32); - tu.store(1 + traits::X0, tu.constant((uint32_t)(PC + 2), 32)); - auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(new_pc, tu.constant(~0x1, 8)), 32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + if(rs1>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto new_pc = tu.assignment(tu.load(rs1+ traits::X0, 0),32); + tu.store(1 + traits::X0, + tu.constant((uint32_t)(PC+ 2),32)); + auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and( + new_pc, + tu.constant(~ 0x1,8)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); } auto returnValue = std::make_tuple(BRANCH); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 83); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,83); return returnValue; } - + /* instruction 84: C__EBREAK */ - compile_ret_t __c__ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__EBREAK_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 84); + vm_base::gen_sync(tu, PRE_SYNC,84); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c__ebreak"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 3); + this->gen_raise_trap(tu, 0, 3); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 84); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,84); return returnValue; } - + /* instruction 85: C__SWSP */ - compile_ret_t __c__swsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __c__swsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C__SWSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 85); + vm_base::gen_sync(tu, PRE_SYNC,85); uint64_t PC = pc.val; - uint8_t rs2 = ((bit_sub<2, 5>(instr))); - uint8_t uimm = ((bit_sub<7, 2>(instr) << 6) | (bit_sub<9, 4>(instr) << 2)); - if(this->disass_enabled) { + uint8_t rs2 = ((bit_sub<2,5>(instr))); + uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); + if(this->disass_enabled){ /* generate console output when executing the command */ - auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"), fmt::arg("rs2", name(rs2)), - fmt::arg("uimm", uimm)); + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs2 >= static_cast(traits::RFS)) { - this->gen_raise_trap(tu, 0, 2); - } else { - auto offs = tu.assignment(tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32); - tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2 + traits::X0, 0), 32, false)); + if(rs2>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); + } + else{ + auto offs = tu.assignment(tu.ext((tu.add( + tu.load(2+ traits::X0, 0), + tu.constant(uimm,8))),32,false),32); + tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2+ traits::X0, 0),32,false)); } auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 85); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,85); return returnValue; } - + /* instruction 86: DII */ - compile_ret_t __dii(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t __dii(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DII_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 86); + vm_base::gen_sync(tu, PRE_SYNC,86); uint64_t PC = pc.val; - if(this->disass_enabled) { + if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "dii"); } auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]); - pc = pc + 2; + pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); auto returnValue = std::make_tuple(CONT); - + tu.close_scope(); - gen_trap_check(tu); - vm_base::gen_sync(tu, POST_SYNC, 86); + gen_trap_check(tu); + vm_base::gen_sync(tu, POST_SYNC,86); return returnValue; } - + /**************************************************************************** * end opcode definitions ****************************************************************************/ - compile_ret_t illegal_intruction(virt_addr_t& pc, code_word_t instr, tu_builder& tu) { + compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) { vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size()); pc = pc + ((instr & 3) == 3 ? 4 : 2); - gen_raise_trap(tu, 0, 2); // illegal instruction trap + gen_raise_trap(tu, 0, 2); // illegal instruction trap vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size()); vm_impl::gen_trap_check(tu); return BRANCH; } + + //decoding functionality - // decoding functionality - - void populate_decoding_tree(decoding_tree_node* root) { - // create submask - for(auto instr : root->instrs) { + void populate_decoding_tree(decoding_tree_node* root){ + //create submask + for(auto instr: root->instrs){ root->submask &= instr.mask; } - // put each instr according to submask&encoding into children - for(auto instr : root->instrs) { + //put each instr according to submask&encoding into children + for(auto instr: root->instrs){ bool foundMatch = false; - for(auto child : root->children) { - // use value as identifying trait - if(child->value == (instr.value & root->submask)) { + for(auto child: root->children){ + //use value as identifying trait + if(child->value == (instr.value&root->submask)){ child->instrs.push_back(instr); foundMatch = true; } } - if(!foundMatch) { - decoding_tree_node* child = new decoding_tree_node(instr.value & root->submask); + if(!foundMatch){ + decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask); child->instrs.push_back(instr); root->children.push_back(child); } } root->instrs.clear(); - // call populate_decoding_tree for all children - if(root->children.size() > 1) - for(auto child : root->children) { - populate_decoding_tree(child); + //call populate_decoding_tree for all children + if(root->children.size() >1) + for(auto child: root->children){ + populate_decoding_tree(child); } - else { - // sort instrs by value of the mask, this works bc we want to have the least restrictive one last - std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), - [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { return instr1.mask > instr2.mask; }); + else{ + //sort instrs by value of the mask, this works bc we want to have the least restrictive one last + std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { + return instr1.mask > instr2.mask; + }); } } - compile_func decode_instr(decoding_tree_node* node, code_word_t word) { - if(!node->children.size()) { - if(node->instrs.size() == 1) - return node->instrs[0].op; - for(auto instr : node->instrs) { - if((instr.mask & word) == instr.value) - return instr.op; + compile_func decode_instr(decoding_tree_node* node, code_word_t word){ + if(!node->children.size()){ + if(node->instrs.size() == 1) return node->instrs[0].op; + for(auto instr : node->instrs){ + if((instr.mask&word) == instr.value) return instr.op; } - } else { - for(auto child : node->children) { - if(child->value == (node->submask & word)) { + } + else{ + for(auto child : node->children){ + if (child->value == (node->submask&word)){ return decode_instr(child, word); - } - } + } + } } return nullptr; } @@ -3273,41 +3571,40 @@ template void debug_fn(CODE_WORD instr) { template vm_impl::vm_impl() { this(new ARCH()); } template -vm_impl::vm_impl(ARCH& core, unsigned core_id, unsigned cluster_id) +vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) : vm_base(core, core_id, cluster_id) { root = new decoding_tree_node(std::numeric_limits::max()); - for(auto instr : instr_descr) { + for(auto instr:instr_descr){ root->instrs.push_back(instr); } populate_decoding_tree(root); } template -std::tuple vm_impl::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, tu_builder& tu) { +std::tuple +vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) { // we fetch at max 4 byte, alignment is 2 - enum { TRAP_ID = 1 << 16 }; + enum {TRAP_ID=1<<16}; code_word_t instr = 0; phys_addr_t paddr(pc); if(this->core.has_mmu()) paddr = this->core.virt2phys(pc); - // TODO: re-add page handling - // if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary - // auto res = this->core.read(paddr, 2, data); - // if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); - // if ((insn & 0x3) == 0x3) { // this is a 32bit instruction - // res = this->core.read(this->core.v2p(pc + 2), 2, data + 2); - // } - // } else { - auto res = this->core.read(paddr, 4, reinterpret_cast(&instr)); - if(res != iss::Ok) - throw trap_access(TRAP_ID, pc.val); - // } - if(instr == 0x0000006f || (instr & 0xffff) == 0xa001) - throw simulation_stopped(0); // 'J 0' or 'C.J 0' + //TODO: re-add page handling +// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary +// auto res = this->core.read(paddr, 2, data); +// if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); +// if ((insn & 0x3) == 0x3) { // this is a 32bit instruction +// res = this->core.read(this->core.v2p(pc + 2), 2, data + 2); +// } +// } else { + auto res = this->core.read(paddr, 4, reinterpret_cast(&instr)); + if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val); +// } + if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0' // curr pc on stack ++inst_cnt; auto f = decode_instr(root, instr); - if(f == nullptr) { + if (f == nullptr) { f = &this_class::illegal_intruction; } return (this->*f)(pc, instr, tu); @@ -3324,47 +3621,55 @@ template void vm_impl::gen_leave_trap(tu_builder& tu, unsi tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits::max(), 32)); } -template void vm_impl::gen_wait(tu_builder& tu, unsigned type) {} +template void vm_impl::gen_wait(tu_builder& tu, unsigned type) { +} template void vm_impl::gen_trap_behavior(tu_builder& tu) { tu("trap_entry:"); - this->gen_sync(tu, POST_SYNC, -1); + this->gen_sync(tu, POST_SYNC, -1); tu("enter_trap(core_ptr, *trap_state, *pc, 0);"); - tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits::max(), 32)); + tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits::max(),32)); tu("return *next_pc;"); } } // namespace tgc5c -template <> std::unique_ptr create(arch::tgc5c* core, unsigned short port, bool dump) { +template <> +std::unique_ptr create(arch::tgc5c *core, unsigned short port, bool dump) { auto ret = new tgc5c::vm_impl(*core, dump); - if(port != 0) - debugger::server::run_server(ret, port); + if (port != 0) debugger::server::run_server(ret, port); return std::unique_ptr(ret); } -} // namespace tcc +} // namesapce tcc } // namespace iss +#include #include #include -#include namespace iss { namespace { volatile std::array dummy = { - core_factory::instance().register_creator("tgc5c|m_p|tcc", - [](unsigned port, void*) -> std::tuple { - auto* cpu = new iss::arch::riscv_hart_m_p(); - auto vm = new tcc::tgc5c::vm_impl(*cpu, false); - if(port != 0) - debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - }), - core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned port, void*) -> std::tuple { - auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto vm = new tcc::tgc5c::vm_impl(*cpu, false); - if(port != 0) - debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - })}; + core_factory::instance().register_creator("tgc5c|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_m_p(); + auto vm = new tcc::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_mu_p(); + auto vm = new tcc::tgc5c::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + if(init_data){ + auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + cpu->set_semihosting_callback(*cb); + } + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }) +}; } -} // namespace iss +} +// clang-format on \ No newline at end of file From 9841b16122b2f51d772020a7a11df44ddb02dd40 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Fri, 12 Jan 2024 11:49:11 +0100 Subject: [PATCH 07/33] fixes clang-format failures --- gen_input/templates/llvm/CORENAME.cpp.gtl | 2 +- gen_input/templates/tcc/CORENAME.cpp.gtl | 2 +- src/vm/llvm/vm_tgc5c.cpp | 2 +- src/vm/tcc/vm_tgc5c.cpp | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gen_input/templates/llvm/CORENAME.cpp.gtl b/gen_input/templates/llvm/CORENAME.cpp.gtl index d31802f..b6bef39 100644 --- a/gen_input/templates/llvm/CORENAME.cpp.gtl +++ b/gen_input/templates/llvm/CORENAME.cpp.gtl @@ -359,9 +359,9 @@ std::unique_ptr create(arch::${coreD } // namespace llvm } // namespace iss -#include #include #include +#include namespace iss { namespace { volatile std::array dummy = { diff --git a/gen_input/templates/tcc/CORENAME.cpp.gtl b/gen_input/templates/tcc/CORENAME.cpp.gtl index 5ac57ae..e378bb6 100644 --- a/gen_input/templates/tcc/CORENAME.cpp.gtl +++ b/gen_input/templates/tcc/CORENAME.cpp.gtl @@ -323,9 +323,9 @@ std::unique_ptr create(arch::${coreD } // namesapce tcc } // namespace iss -#include #include #include +#include namespace iss { namespace { volatile std::array dummy = { diff --git a/src/vm/llvm/vm_tgc5c.cpp b/src/vm/llvm/vm_tgc5c.cpp index 5447fa1..fe03630 100644 --- a/src/vm/llvm/vm_tgc5c.cpp +++ b/src/vm/llvm/vm_tgc5c.cpp @@ -4537,9 +4537,9 @@ std::unique_ptr create(arch::tgc5c *core, unsigned short por } // namespace llvm } // namespace iss -#include #include #include +#include namespace iss { namespace { volatile std::array dummy = { diff --git a/src/vm/tcc/vm_tgc5c.cpp b/src/vm/tcc/vm_tgc5c.cpp index 9d4dff7..9015757 100644 --- a/src/vm/tcc/vm_tgc5c.cpp +++ b/src/vm/tcc/vm_tgc5c.cpp @@ -3643,9 +3643,9 @@ std::unique_ptr create(arch::tgc5c *core, unsigned short por } // namesapce tcc } // namespace iss -#include #include #include +#include namespace iss { namespace { volatile std::array dummy = { From 119d4a8b43a9253b498eb91d209c478edc7c9ff4 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Wed, 21 Feb 2024 07:08:24 +0100 Subject: [PATCH 08/33] adds generation if IMEM space --- gen_input/templates/CORENAME.h.gtl | 2 +- src/iss/arch/tgc5c.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl index d5ba6c4..02ecb68 100644 --- a/gen_input/templates/CORENAME.h.gtl +++ b/gen_input/templates/CORENAME.h.gtl @@ -109,7 +109,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { enum sreg_flag_e { FLAGS }; - enum mem_type_e { ${spaces.collect{it.name}.join(', ')} }; + enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM }; enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %> ${instr.instruction.name} = ${index},<%}%> diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 7285edd..cff086d 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -81,7 +81,7 @@ template <> struct traits { enum sreg_flag_e { FLAGS }; - enum mem_type_e { MEM, FENCE, RES, CSR }; + enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM }; enum class opcode_e { LUI = 0, From 1e6a0086e9ed15ad2ad6a9a09a8a92372406412d Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Thu, 7 Mar 2024 13:58:08 +0100 Subject: [PATCH 09/33] adds disass functionality --- gen_input/templates/asmjit/CORENAME.cpp.gtl | 12 +- src/vm/asmjit/helper_func.h | 6 +- src/vm/asmjit/vm_tgc5c.cpp | 1209 ++++++++++++++++--- 3 files changed, 1049 insertions(+), 178 deletions(-) diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 863628c..00e86e9 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -127,10 +127,18 @@ private: <%instr.fields.eachLine{%>${it} <%}%>if(this->disass_enabled){ /* generate disass */ + <%instr.disass.eachLine{%> + ${it}<%}%> + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\\n${instr.name}_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, ${idx}); pc=pc+ ${instr.length/8}; diff --git a/src/vm/asmjit/helper_func.h b/src/vm/asmjit/helper_func.h index f209e46..88aceba 100644 --- a/src/vm/asmjit/helper_func.h +++ b/src/vm/asmjit/helper_func.h @@ -1,4 +1,5 @@ - +#include +#include x86::Mem get_reg_ptr(jit_holder& jh, unsigned idx) { @@ -74,6 +75,7 @@ inline void write_reg_to_mem(jit_holder& jh, x86::Gp reg, unsigned idx) { void gen_instr_prologue(jit_holder& jh, addr_t pc) { auto& cc = jh.cc; + cc.mov(jh.pc, pc); cc.comment("\n//(*icount)++;"); cc.inc(get_reg_ptr(jh, traits::ICOUNT)); @@ -534,4 +536,4 @@ inline void gen_write_mem(jit_holder& jh, mem_type_e type, uint64_t addr, int64_ auto addr_reg = jh.cc.newUInt64(); jh.cc.mov(addr_reg, addr); gen_write_mem(jh, type, addr_reg, val_reg, length); -} \ No newline at end of file +} diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index 497cc1e..84b4a7e 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -300,10 +300,20 @@ private: uint32_t imm = ((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nLUI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 0); pc=pc+ 4; @@ -334,10 +344,20 @@ private: uint32_t imm = ((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nAUIPC_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 1); pc=pc+ 4; @@ -368,10 +388,20 @@ private: uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nJAL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 2); pc=pc+ 4; @@ -411,10 +441,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nJALR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 3); pc=pc+ 4; @@ -470,10 +510,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nBEQ_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 4); pc=pc+ 4; @@ -517,10 +567,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nBNE_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 5); pc=pc+ 4; @@ -564,10 +624,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nBLT_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 6); pc=pc+ 4; @@ -613,10 +683,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nBGE_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 7); pc=pc+ 4; @@ -662,10 +742,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nBLTU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 8); pc=pc+ 4; @@ -709,10 +799,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nBGEU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 9); pc=pc+ 4; @@ -756,10 +856,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nLB_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 10); pc=pc+ 4; @@ -798,10 +908,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nLH_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 11); pc=pc+ 4; @@ -840,10 +960,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nLW_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 12); pc=pc+ 4; @@ -882,10 +1012,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nLBU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 13); pc=pc+ 4; @@ -923,10 +1063,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nLHU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 14); pc=pc+ 4; @@ -964,10 +1114,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSB_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 15); pc=pc+ 4; @@ -1001,10 +1161,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSH_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 16); pc=pc+ 4; @@ -1038,10 +1208,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSW_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 17); pc=pc+ 4; @@ -1075,10 +1255,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nADDI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 18); pc=pc+ 4; @@ -1113,10 +1303,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSLTI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 19); pc=pc+ 4; @@ -1163,10 +1363,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSLTIU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 20); pc=pc+ 4; @@ -1212,10 +1422,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nXORI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 21); pc=pc+ 4; @@ -1249,10 +1469,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nORI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 22); pc=pc+ 4; @@ -1286,10 +1516,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nANDI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 23); pc=pc+ 4; @@ -1323,10 +1563,20 @@ private: uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSLLI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 24); pc=pc+ 4; @@ -1360,10 +1610,20 @@ private: uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSRLI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 25); pc=pc+ 4; @@ -1397,10 +1657,20 @@ private: uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSRAI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 26); pc=pc+ 4; @@ -1436,10 +1706,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nADD_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 27); pc=pc+ 4; @@ -1474,10 +1754,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSUB_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 28); pc=pc+ 4; @@ -1512,10 +1802,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSLL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 29); pc=pc+ 4; @@ -1551,10 +1851,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSLT_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 30); pc=pc+ 4; @@ -1602,10 +1912,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSLTU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 31); pc=pc+ 4; @@ -1651,10 +1971,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nXOR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 32); pc=pc+ 4; @@ -1688,10 +2018,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSRL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 33); pc=pc+ 4; @@ -1727,10 +2067,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nSRA_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 34); pc=pc+ 4; @@ -1768,10 +2118,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nOR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 35); pc=pc+ 4; @@ -1805,10 +2165,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nAND_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 36); pc=pc+ 4; @@ -1844,10 +2214,20 @@ private: uint8_t fm = ((bit_sub<28,4>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), + fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nFENCE_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 37); pc=pc+ 4; @@ -1868,10 +2248,19 @@ private: uint64_t PC = pc.val; if(this->disass_enabled){ /* generate disass */ + + //This disass is not yet implemented + std::string mnemonic = "ecall"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nECALL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 38); pc=pc+ 4; @@ -1892,10 +2281,19 @@ private: uint64_t PC = pc.val; if(this->disass_enabled){ /* generate disass */ + + //This disass is not yet implemented + std::string mnemonic = "ebreak"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nEBREAK_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 39); pc=pc+ 4; @@ -1916,10 +2314,19 @@ private: uint64_t PC = pc.val; if(this->disass_enabled){ /* generate disass */ + + //This disass is not yet implemented + std::string mnemonic = "mret"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nMRET_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 40); pc=pc+ 4; @@ -1940,10 +2347,19 @@ private: uint64_t PC = pc.val; if(this->disass_enabled){ /* generate disass */ + + //This disass is not yet implemented + std::string mnemonic = "wfi"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nWFI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 41); pc=pc+ 4; @@ -1967,10 +2383,20 @@ private: uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nCSRRW_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 42); pc=pc+ 4; @@ -2008,10 +2434,20 @@ private: uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nCSRRS_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 43); pc=pc+ 4; @@ -2050,10 +2486,20 @@ private: uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nCSRRC_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 44); pc=pc+ 4; @@ -2092,10 +2538,20 @@ private: uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nCSRRWI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 45); pc=pc+ 4; @@ -2129,10 +2585,20 @@ private: uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nCSRRSI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 46); pc=pc+ 4; @@ -2170,10 +2636,20 @@ private: uint16_t csr = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nCSRRCI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 47); pc=pc+ 4; @@ -2211,10 +2687,20 @@ private: uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), + fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nFENCE_I_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 48); pc=pc+ 4; @@ -2238,10 +2724,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nMUL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 49); pc=pc+ 4; @@ -2282,10 +2778,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nMULH_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 50); pc=pc+ 4; @@ -2328,10 +2834,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nMULHSU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 51); pc=pc+ 4; @@ -2373,10 +2889,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nMULHU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 52); pc=pc+ 4; @@ -2417,10 +2943,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nDIV_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 53); pc=pc+ 4; @@ -2494,10 +3030,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nDIVU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 54); pc=pc+ 4; @@ -2549,10 +3095,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nREM_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 55); pc=pc+ 4; @@ -2630,10 +3186,20 @@ private: uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nREMU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 56); pc=pc+ 4; @@ -2683,10 +3249,20 @@ private: uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"), + fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__ADDI4SPN_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 57); pc=pc+ 2; @@ -2719,10 +3295,20 @@ private: uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"), + fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__LW_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 58); pc=pc+ 2; @@ -2753,10 +3339,20 @@ private: uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"), + fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__SW_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 59); pc=pc+ 2; @@ -2784,10 +3380,20 @@ private: uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__ADDI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 60); pc=pc+ 2; @@ -2820,10 +3426,19 @@ private: uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); if(this->disass_enabled){ /* generate disass */ + + //This disass is not yet implemented + std::string mnemonic = "c__nop"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__NOP_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 61); pc=pc+ 2; @@ -2844,10 +3459,20 @@ private: uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"), + fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__JAL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 62); pc=pc+ 2; @@ -2874,10 +3499,20 @@ private: uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__LI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 63); pc=pc+ 2; @@ -2908,10 +3543,20 @@ private: uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__LUI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 64); pc=pc+ 2; @@ -2939,10 +3584,20 @@ private: uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"), + fmt::arg("nzimm", nzimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__ADDI16SP_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 65); pc=pc+ 2; @@ -2973,10 +3628,19 @@ private: uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + //This disass is not yet implemented + std::string mnemonic = "__reserved_clui"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\n__reserved_clui_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 66); pc=pc+ 2; @@ -2999,10 +3663,20 @@ private: uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__SRLI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 67); pc=pc+ 2; @@ -3028,10 +3702,20 @@ private: uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__SRAI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 68); pc=pc+ 2; @@ -3071,10 +3755,20 @@ private: uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__ANDI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 69); pc=pc+ 2; @@ -3101,10 +3795,20 @@ private: uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__SUB_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 70); pc=pc+ 2; @@ -3131,10 +3835,20 @@ private: uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__XOR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 71); pc=pc+ 2; @@ -3160,10 +3874,20 @@ private: uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__OR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 72); pc=pc+ 2; @@ -3189,10 +3913,20 @@ private: uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"), + fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__AND_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 73); pc=pc+ 2; @@ -3217,10 +3951,20 @@ private: uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"), + fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__J_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 74); pc=pc+ 2; @@ -3245,10 +3989,20 @@ private: uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__BEQZ_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 75); pc=pc+ 2; @@ -3281,10 +4035,20 @@ private: uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__BNEZ_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 76); pc=pc+ 2; @@ -3317,10 +4081,20 @@ private: uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__SLLI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 77); pc=pc+ 2; @@ -3353,10 +4127,20 @@ private: uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"), + fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__LWSP_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 78); pc=pc+ 2; @@ -3391,10 +4175,20 @@ private: uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__MV_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 79); pc=pc+ 2; @@ -3424,10 +4218,20 @@ private: uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"), + fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__JR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 80); pc=pc+ 2; @@ -3457,10 +4261,19 @@ private: uint64_t PC = pc.val; if(this->disass_enabled){ /* generate disass */ + + //This disass is not yet implemented + std::string mnemonic = "__reserved_cmv"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\n__reserved_cmv_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 81); pc=pc+ 2; @@ -3483,10 +4296,20 @@ private: uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"), + fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__ADD_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 82); pc=pc+ 2; @@ -3519,10 +4342,20 @@ private: uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"), + fmt::arg("rs1", name(rs1))); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__JALR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 83); pc=pc+ 2; @@ -3555,10 +4388,19 @@ private: uint64_t PC = pc.val; if(this->disass_enabled){ /* generate disass */ + + //This disass is not yet implemented + std::string mnemonic = "c__ebreak"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__EBREAK_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 84); pc=pc+ 2; @@ -3581,10 +4423,20 @@ private: uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); if(this->disass_enabled){ /* generate disass */ + + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"), + fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm)); + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nC__SWSP_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 85); pc=pc+ 2; @@ -3615,10 +4467,19 @@ private: uint64_t PC = pc.val; if(this->disass_enabled){ /* generate disass */ + + //This disass is not yet implemented + std::string mnemonic = "dii"; + InvokeNode* call_print_disass; + char* mnemonic_ptr = strdup(mnemonic.c_str()); + jh.disass_collection.push_back(mnemonic_ptr); + jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT()); + call_print_disass->setArg(0, jh.arch_if_ptr); + call_print_disass->setArg(1, pc.val); + call_print_disass->setArg(2, mnemonic_ptr); + } x86::Compiler& cc = jh.cc; - //ideally only do this if necessary (someone / plugin needs it) - cc.mov(jh.pc,PC); cc.comment(fmt::format("\nDII_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 86); pc=pc+ 2; From 8aed551813128b4a9363eb0223bb88b318699f4c Mon Sep 17 00:00:00 2001 From: stas Date: Thu, 14 Mar 2024 09:43:08 +0100 Subject: [PATCH 10/33] Add a new LOG macro in SCC to avoid conflicts with other libraries. --- src/iss/arch/riscv_hart_m_p.h | 28 ++++++++++++------------- src/iss/arch/riscv_hart_msu_vp.h | 28 ++++++++++++------------- src/iss/arch/riscv_hart_mu_p.h | 28 ++++++++++++------------- src/iss/debugger/riscv_target_adapter.h | 12 +++++------ src/iss/plugin/cycle_estimate.cpp | 6 +++--- src/iss/plugin/instruction_count.cpp | 8 +++---- src/main.cpp | 8 +++---- 7 files changed, 59 insertions(+), 59 deletions(-) diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 99a7f06..1a3d84b 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -600,7 +600,7 @@ template std::pair riscv_hart_m auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits::MEM, pseg->get_physical_address(), fsize, reinterpret_cast(seg_data)); if(res != iss::Ok) - LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); + CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); } } for(const auto sec : reader.sections) { @@ -654,11 +654,11 @@ iss::status riscv_hart_m_p::read(const address_type type, const acce const unsigned length, uint8_t* const data) { #ifndef NDEBUG if(access && iss::access_type::DEBUG) { - LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; } else if(access && iss::access_type::FETCH) { - LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; } else { - LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; } #endif try { @@ -740,23 +740,23 @@ iss::status riscv_hart_m_p::write(const address_type type, const acc const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; switch(length) { case 8: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 4: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 2: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 1: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; default: - LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; + CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; } #endif try { @@ -808,7 +808,7 @@ iss::status riscv_hart_m_p::write(const address_type type, const acc case 0x10023000: // UART1 base, TXFIFO reg uart_buf << (char)data[0]; if(((char)data[0]) == '\n' || data[0] == 0) { - // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send + // CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send // '"<::write_mem(phys_addr_t paddr, unsigned le // TODO remove UART, Peripherals should not be part of the ISS case 0xFFFF0000: // UART0 base, TXFIFO reg if(((char)data[0]) == '\n' || data[0] == 0) { - LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; uart_buf.str(""); } else if(((char)data[0]) != '\r') uart_buf << (char)data[0]; @@ -1128,10 +1128,10 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned le switch(hostvar >> 48) { case 0: if(hostvar != 0x1) { - LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } else { - LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } this->reg.trap_state = std::numeric_limits::max(); @@ -1143,7 +1143,7 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned le case 0x0101: { char c = static_cast(hostvar & 0xff); if(c == '\n' || c == 0) { - LOG(INFO) << "tohost send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'"; uart_buf.str(""); } else uart_buf << c; diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index 4329160..7384abc 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -591,7 +591,7 @@ template std::pair riscv_hart_msu_vp::load auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits::MEM, pseg->get_physical_address(), fsize, reinterpret_cast(seg_data)); if(res != iss::Ok) - LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); + CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); } } for(const auto sec : reader.sections) { @@ -632,11 +632,11 @@ iss::status riscv_hart_msu_vp::read(const address_type type, const access_ const unsigned length, uint8_t* const data) { #ifndef NDEBUG if(access && iss::access_type::DEBUG) { - LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; } else if(access && iss::access_type::FETCH) { - LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; } else { - LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; } #endif try { @@ -726,23 +726,23 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; switch(length) { case 8: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 4: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 2: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 1: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; default: - LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; + CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; } #endif try { @@ -787,7 +787,7 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access case 0x10023000: // UART1 base, TXFIFO reg uart_buf << (char)data[0]; if(((char)data[0]) == '\n' || data[0] == 0) { - // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send + // CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send // '"< iss::status riscv_hart_msu_vp::write_mem(phys_add switch(paddr.val) { case 0xFFFF0000: // UART0 base, TXFIFO reg if(((char)data[0]) == '\n' || data[0] == 0) { - LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; uart_buf.str(""); } else if(((char)data[0]) != '\r') uart_buf << (char)data[0]; @@ -1103,10 +1103,10 @@ template iss::status riscv_hart_msu_vp::write_mem(phys_add switch(hostvar >> 48) { case 0: if(hostvar != 0x1) { - LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } else { - LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } this->reg.trap_state = std::numeric_limits::max(); @@ -1118,7 +1118,7 @@ template iss::status riscv_hart_msu_vp::write_mem(phys_add case 0x0101: { char c = static_cast(hostvar & 0xff); if(c == '\n' || c == 0) { - LOG(INFO) << "tohost send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'"; uart_buf.str(""); } else uart_buf << c; diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 362fece..9d5355b 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -678,7 +678,7 @@ template std::pair riscv_hart_m auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits::MEM, pseg->get_physical_address(), fsize, reinterpret_cast(seg_data)); if(res != iss::Ok) - LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); + CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); } } for(const auto sec : reader.sections) { @@ -818,11 +818,11 @@ iss::status riscv_hart_mu_p::read(const address_type type, const acc const unsigned length, uint8_t* const data) { #ifndef NDEBUG if(access && iss::access_type::DEBUG) { - LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; } else if(is_fetch(access)) { - LOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACEALL) << "fetch of " << length << " bytes @addr 0x" << std::hex << addr; } else { - LOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; + CPPLOG(TRACE) << "read of " << length << " bytes @addr 0x" << std::hex << addr; } #endif try { @@ -913,23 +913,23 @@ iss::status riscv_hart_mu_p::write(const address_type type, const ac const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; switch(length) { case 8: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 4: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 2: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; case 1: - LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" + CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" << std::hex << addr; break; default: - LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; + CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; } #endif try { @@ -990,7 +990,7 @@ iss::status riscv_hart_mu_p::write(const address_type type, const ac case 0x10023000: // UART1 base, TXFIFO reg uart_buf << (char)data[0]; if(((char)data[0]) == '\n' || data[0] == 0) { - // LOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send + // CPPLOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send // '"<::write_mem(phys_addr_t paddr, unsigned l // TODO remove UART, Peripherals should not be part of the ISS case 0xFFFF0000: // UART0 base, TXFIFO reg if(((char)data[0]) == '\n' || data[0] == 0) { - LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; uart_buf.str(""); } else if(((char)data[0]) != '\r') uart_buf << (char)data[0]; @@ -1346,10 +1346,10 @@ iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned l switch(hostvar >> 48) { case 0: if(hostvar != 0x1) { - LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } else { - LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar + CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation"; } this->reg.trap_state = std::numeric_limits::max(); @@ -1361,7 +1361,7 @@ iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned l case 0x0101: { char c = static_cast(hostvar & 0xff); if(c == '\n' || c == 0) { - LOG(INFO) << "tohost send '" << uart_buf.str() << "'"; + CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'"; uart_buf.str(""); } else uart_buf << c; diff --git a/src/iss/debugger/riscv_target_adapter.h b/src/iss/debugger/riscv_target_adapter.h index 6a2a527..ac85a67 100644 --- a/src/iss/debugger/riscv_target_adapter.h +++ b/src/iss/debugger/riscv_target_adapter.h @@ -174,7 +174,7 @@ template status riscv_target_adapter::current_thread_query } template status riscv_target_adapter::read_registers(std::vector& data, std::vector& avail) { - LOG(TRACE) << "reading target registers"; + CPPLOG(TRACE) << "reading target registers"; // return idx<0?:; data.clear(); avail.clear(); @@ -328,9 +328,9 @@ template status riscv_target_adapter::add_break(break_type auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr}); auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length}); target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val); - LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val + CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val << std::dec; - LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; + CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; return Ok; } } @@ -345,13 +345,13 @@ template status riscv_target_adapter::remove_break(break_t auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr}); unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val); if(handle) { - LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec; + CPPLOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec; // TODO: check length of addr range target_adapter_base::bp_lut.removeEntry(handle); - LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; + CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; return Ok; } - LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; + CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; return Err; } } diff --git a/src/iss/plugin/cycle_estimate.cpp b/src/iss/plugin/cycle_estimate.cpp index 69e466a..463e2fa 100644 --- a/src/iss/plugin/cycle_estimate.cpp +++ b/src/iss/plugin/cycle_estimate.cpp @@ -61,7 +61,7 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& try { auto root = YAML::LoadAll(is); if(root.size() != 1) { - LOG(ERR) << "Too many root nodes in YAML file " << config_file_name; + CPPLOG(ERR) << "Too many root nodes in YAML file " << config_file_name; } for(auto p : root[0]) { auto isa_subset = p.first; @@ -87,11 +87,11 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if& } } } catch(YAML::ParserException& e) { - LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); + CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); return false; } } else { - LOG(ERR) << "Could not open input file " << config_file_name; + CPPLOG(ERR) << "Could not open input file " << config_file_name; return false; } } diff --git a/src/iss/plugin/instruction_count.cpp b/src/iss/plugin/instruction_count.cpp index bb47e53..000712f 100644 --- a/src/iss/plugin/instruction_count.cpp +++ b/src/iss/plugin/instruction_count.cpp @@ -47,7 +47,7 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name) try { auto root = YAML::LoadAll(is); if(root.size() != 1) { - LOG(ERR) << "Too many rro nodes in YAML file " << config_file_name; + CPPLOG(ERR) << "Too many rro nodes in YAML file " << config_file_name; } for(auto p : root[0]) { auto isa_subset = p.first; @@ -69,10 +69,10 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name) } rep_counts.resize(delays.size()); } catch(YAML::ParserException& e) { - LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); + CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what(); } } else { - LOG(ERR) << "Could not open input file " << config_file_name; + CPPLOG(ERR) << "Could not open input file " << config_file_name; } } } @@ -81,7 +81,7 @@ iss::plugin::instruction_count::~instruction_count() { size_t idx = 0; for(auto it : delays) { if(rep_counts[idx] > 0 && it.instr_name.find("__" != 0)) - LOG(INFO) << it.instr_name << ";" << rep_counts[idx]; + CPPLOG(INFO) << it.instr_name << ";" << rep_counts[idx]; idx++; } } diff --git a/src/main.cpp b/src/main.cpp index aad92da..9a32241 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -137,11 +137,11 @@ int main(int argc, char* argv[]) { std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as(), &semihosting_cb); } if(!cpu) { - LOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as() << std::endl; + CPPLOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as() << std::endl; return 127; } if(!vm) { - LOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " << clim["backend"].as() << std::endl; + CPPLOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " << clim["backend"].as() << std::endl; return 127; } if(clim.count("plugin")) { @@ -177,7 +177,7 @@ int main(int argc, char* argv[]) { } else #endif { - LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl; + CPPLOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl; return 127; } } @@ -215,7 +215,7 @@ int main(int argc, char* argv[]) { auto cycles = clim["instructions"].as(); res = vm->start(cycles, dump); } catch(std::exception& e) { - LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl; + CPPLOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl; res = 2; } // cleanup to let plugins report of needed From a1ebd83d2a1b401c03b62668f96719c660ba641d Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Tue, 19 Mar 2024 11:02:03 +0100 Subject: [PATCH 11/33] adds riscv_hart_common and signature output --- src/iss/arch/riscv_hart_common.h | 60 ++++++++++++++++++++++++++++++++ src/iss/arch/riscv_hart_m_p.h | 33 ++++++------------ src/iss/arch/riscv_hart_msu_vp.h | 4 ++- src/iss/arch/riscv_hart_mu_p.h | 4 ++- src/main.cpp | 39 +++++++++++++++++++-- 5 files changed, 113 insertions(+), 27 deletions(-) diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h index 4ac086d..037b801 100644 --- a/src/iss/arch/riscv_hart_common.h +++ b/src/iss/arch/riscv_hart_common.h @@ -36,7 +36,12 @@ #define _RISCV_HART_COMMON #include "iss/arch_if.h" +#include "iss/log_categories.h" #include +#include +#include +#include +#include namespace iss { namespace arch { @@ -296,6 +301,61 @@ inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t* const break; } } +struct riscv_hart_common { + riscv_hart_common(){}; + ~riscv_hart_common(){}; + std::unordered_map symbol_table; + + std::unordered_map get_sym_table(std::string name) { + if(!symbol_table.empty()) + return symbol_table; + FILE* fp = fopen(name.c_str(), "r"); + if(fp) { + std::array buf; + auto n = fread(buf.data(), 1, 4, fp); + fclose(fp); + if(n != 4) + throw std::runtime_error("input file has insufficient size"); + buf[4] = 0; + if(strcmp(buf.data() + 1, "ELF") == 0) { + // Create elfio reader + ELFIO::elfio reader; + // Load ELF data + if(!reader.load(name)) + throw std::runtime_error("could not process elf file"); + // check elf properties + if(reader.get_type() != ET_EXEC) + throw std::runtime_error("wrong elf type in file"); + if(reader.get_machine() != EM_RISCV) + throw std::runtime_error("wrong elf machine in file"); + const auto sym_sec = reader.sections[".symtab"]; + if(SHT_SYMTAB == sym_sec->get_type() || SHT_DYNSYM == sym_sec->get_type()) { + ELFIO::symbol_section_accessor symbols(reader, sym_sec); + auto sym_no = symbols.get_symbols_num(); + std::string name; + ELFIO::Elf64_Addr value = 0; + ELFIO::Elf_Xword size = 0; + unsigned char bind = 0; + unsigned char type = 0; + ELFIO::Elf_Half section = 0; + unsigned char other = 0; + for(auto i = 0U; i < sym_no; ++i) { + symbols.get_symbol(i, name, value, size, bind, type, section, other); + if(name != "") { + this->symbol_table[name] = value; +#ifndef NDEBUG + LOG(DEBUG) << "Found Symbol " << name; +#endif + } + } + } + return symbol_table; + } + throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name)); + } else + throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name)); + }; +}; } // namespace arch } // namespace iss diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 99a7f06..0f480a3 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -40,6 +40,7 @@ #include "iss/log_categories.h" #include "iss/vm_if.h" #include "riscv_hart_common.h" +#include #ifndef FMT_HEADER_ONLY #define FMT_HEADER_ONLY #endif @@ -68,7 +69,7 @@ namespace iss { namespace arch { -template class riscv_hart_m_p : public BASE { +template class riscv_hart_m_p : public BASE, public riscv_hart_common { protected: const std::array lvl = {{'U', 'S', 'H', 'M'}}; const std::array trap_str = {{"" @@ -326,6 +327,8 @@ protected: unsigned get_reg_size(unsigned num) override { return traits::reg_bit_widths[num]; } + std::unordered_map get_symbol_table(std::string name) override { return arch.get_sym_table(name); } + riscv_hart_m_p& arch; }; @@ -570,6 +573,12 @@ riscv_hart_m_p::riscv_hart_m_p(feature_config cfg) } template std::pair riscv_hart_m_p::load_file(std::string name, int type) { + get_sym_table(name); + try { + tohost = symbol_table.at("tohost"); + fromhost = symbol_table.at("fromhost"); + } catch(std::out_of_range& e) { + } FILE* fp = fopen(name.c_str(), "r"); if(fp) { std::array buf; @@ -604,27 +613,7 @@ template std::pair riscv_hart_m } } for(const auto sec : reader.sections) { - if(sec->get_name() == ".symtab") { - if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) { - ELFIO::symbol_section_accessor symbols(reader, sec); - auto sym_no = symbols.get_symbols_num(); - std::string name; - ELFIO::Elf64_Addr value = 0; - ELFIO::Elf_Xword size = 0; - unsigned char bind = 0; - unsigned char type = 0; - ELFIO::Elf_Half section = 0; - unsigned char other = 0; - for(auto i = 0U; i < sym_no; ++i) { - symbols.get_symbol(i, name, value, size, bind, type, section, other); - if(name == "tohost") { - tohost = value; - } else if(name == "fromhost") { - fromhost = value; - } - } - } - } else if(sec->get_name() == ".tohost") { + if(sec->get_name() == ".tohost") { tohost = sec->get_address(); fromhost = tohost + 0x40; } diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index 4329160..58e5bb3 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -68,7 +68,7 @@ namespace iss { namespace arch { -template class riscv_hart_msu_vp : public BASE { +template class riscv_hart_msu_vp : public BASE, public riscv_hart_common { protected: const std::array lvl = {{'U', 'S', 'H', 'M'}}; const std::array trap_str = {{"" @@ -377,6 +377,8 @@ protected: unsigned get_reg_size(unsigned num) override { return traits::reg_bit_widths[num]; } + std::unordered_map get_symbol_table(std::string name) override { return arch.get_sym_table(name); } + riscv_hart_msu_vp& arch; }; diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 362fece..6f4bbd4 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -68,7 +68,7 @@ namespace iss { namespace arch { -template class riscv_hart_mu_p : public BASE { +template class riscv_hart_mu_p : public BASE, public riscv_hart_common { protected: const std::array lvl = {{'U', 'S', 'H', 'M'}}; const std::array trap_str = {{"" @@ -353,6 +353,8 @@ protected: unsigned get_reg_size(unsigned num) override { return traits::reg_bit_widths[num]; } + std::unordered_map get_symbol_table(std::string name) override { return arch.get_sym_table(name); } + riscv_hart_mu_p& arch; }; diff --git a/src/main.cpp b/src/main.cpp index aad92da..c5d3d3b 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -35,6 +35,8 @@ #include #include #include +#include +#include #include #include "iss/arch/tgc_mapper.h" @@ -199,12 +201,12 @@ int main(int argc, char* argv[]) { if(clim.count("elf")) for(std::string input : clim["elf"].as>()) { auto start_addr = vm->get_arch()->load_file(input); - if(start_addr.second) + if(start_addr.second) // FIXME: this always evaluates to true as load file always returns start_address = start_addr.first; } for(std::string input : args) { auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files - if(start_addr.second) + if(start_addr.second) // FIXME: this always evaluates to true as load file always returns start_address = start_addr.first; } if(clim.count("reset")) { @@ -214,11 +216,42 @@ int main(int argc, char* argv[]) { vm->reset(start_address); auto cycles = clim["instructions"].as(); res = vm->start(cycles, dump); + + auto instr_if = vm->get_arch()->get_instrumentation_if(); + // this assumes a single input file + std::unordered_map sym_table; + if(args.empty()) + sym_table = instr_if->get_symbol_table(clim["elf"].as>()[0]); + else + sym_table = instr_if->get_symbol_table(args[0]); + if(sym_table.find("begin_signature") != std::end(sym_table) && sym_table.find("end_signature") != std::end(sym_table)) { + auto start_addr = sym_table["begin_signature"]; + auto end_addr = sym_table["end_signature"]; + std::array data; + std::ofstream file; + std::string filename = fmt::format("{}.signature", isa_opt); + std::replace(std::begin(filename), std::end(filename), '|', '_'); + // default riscof requires this filename + filename = "DUT-tgc.signature"; + file.open(filename, std::ios::out); + if(!file.is_open()) { + LOG(ERR) << "Error opening file " << filename << std::endl; + return 1; + } + for(auto addr = start_addr; addr < end_addr; addr += data.size()) { + vm->get_arch()->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0 /*MEM*/, addr, data.size(), + data.data()); // FIXME: get space from iss::arch::traits::mem_type_e::MEM + + // TODO : obey Target endianess + uint32_t to_print = (data[3] << 24) + (data[2] << 16) + (data[1] << 8) + data[0]; + file << std::hex << fmt::format("{:08x}", to_print) << std::dec << std::endl; + } + } } catch(std::exception& e) { LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl; res = 2; } - // cleanup to let plugins report of needed + // cleanup to let plugins report if needed for(auto* p : plugin_list) { delete p; } From b25b7848c614c505b77239b59ae5f75575cb642d Mon Sep 17 00:00:00 2001 From: stas Date: Tue, 19 Mar 2024 11:47:12 +0100 Subject: [PATCH 12/33] fix formatting --- src/iss/arch/riscv_hart_m_p.h | 12 ++++++------ src/iss/arch/riscv_hart_msu_vp.h | 12 ++++++------ src/iss/arch/riscv_hart_mu_p.h | 12 ++++++------ src/iss/debugger/riscv_target_adapter.h | 2 +- src/vm/asmjit/vm_tgc5c.cpp | 2 +- 5 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index db7e715..90a7d5f 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -730,19 +730,19 @@ iss::status riscv_hart_m_p::write(const address_type type, const acc switch(length) { case 8: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; case 4: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; case 2: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; case 1: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; default: CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; @@ -1118,10 +1118,10 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned le case 0: if(hostvar != 0x1) { CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; + << "), stopping simulation"; } else { CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; + << "), stopping simulation"; } this->reg.trap_state = std::numeric_limits::max(); this->interrupt_sim = hostvar; diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index d3339e3..1a350b8 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -729,19 +729,19 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access switch(length) { case 8: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; case 4: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; case 2: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; case 1: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; default: CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; @@ -1106,10 +1106,10 @@ template iss::status riscv_hart_msu_vp::write_mem(phys_add case 0: if(hostvar != 0x1) { CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; + << "), stopping simulation"; } else { CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; + << "), stopping simulation"; } this->reg.trap_state = std::numeric_limits::max(); this->interrupt_sim = hostvar; diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 4597ce7..8f2a07f 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -916,19 +916,19 @@ iss::status riscv_hart_mu_p::write(const address_type type, const ac switch(length) { case 8: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; case 4: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; case 2: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; case 1: CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x" - << std::hex << addr; + << std::hex << addr; break; default: CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr; @@ -1349,10 +1349,10 @@ iss::status riscv_hart_mu_p::write_mem(phys_addr_t paddr, unsigned l case 0: if(hostvar != 0x1) { CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; + << "), stopping simulation"; } else { CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar - << "), stopping simulation"; + << "), stopping simulation"; } this->reg.trap_state = std::numeric_limits::max(); this->interrupt_sim = hostvar; diff --git a/src/iss/debugger/riscv_target_adapter.h b/src/iss/debugger/riscv_target_adapter.h index ac85a67..7e18339 100644 --- a/src/iss/debugger/riscv_target_adapter.h +++ b/src/iss/debugger/riscv_target_adapter.h @@ -329,7 +329,7 @@ template status riscv_target_adapter::add_break(break_type auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length}); target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val); CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val - << std::dec; + << std::dec; CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints"; return Ok; } diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index 84b4a7e..6a6033c 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -4607,9 +4607,9 @@ std::unique_ptr create(arch::tgc5c *core, unsigned short por } // namespace asmjit } // namespace iss -#include #include #include +#include namespace iss { namespace { volatile std::array dummy = { From fbcd389580cb7257aeebc61e249a830fd0d3920a Mon Sep 17 00:00:00 2001 From: stas Date: Mon, 15 Apr 2024 13:03:47 +0200 Subject: [PATCH 13/33] fix log macro --- src/iss/arch/riscv_hart_common.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h index 037b801..829fbb1 100644 --- a/src/iss/arch/riscv_hart_common.h +++ b/src/iss/arch/riscv_hart_common.h @@ -35,13 +35,14 @@ #ifndef _RISCV_HART_COMMON #define _RISCV_HART_COMMON -#include "iss/arch_if.h" -#include "iss/log_categories.h" #include #include #include +#include +#include #include #include +#include namespace iss { namespace arch { @@ -344,7 +345,7 @@ struct riscv_hart_common { if(name != "") { this->symbol_table[name] = value; #ifndef NDEBUG - LOG(DEBUG) << "Found Symbol " << name; + CPPLOG(DEBUG) << "Found Symbol " << name; #endif } } From 6cb76fc256e6e3f54faf36b7f0c66c5259f6bc05 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 16 Apr 2024 13:09:14 +0200 Subject: [PATCH 14/33] updates tgc5c according to latest CoreDSL --- contrib/instr/TGC5C_instr.yaml | 2 +- src/vm/interp/vm_tgc5c.cpp | 114 ++++++++++++++++----------------- 2 files changed, 58 insertions(+), 58 deletions(-) diff --git a/contrib/instr/TGC5C_instr.yaml b/contrib/instr/TGC5C_instr.yaml index c1692e0..1663d37 100644 --- a/contrib/instr/TGC5C_instr.yaml +++ b/contrib/instr/TGC5C_instr.yaml @@ -349,7 +349,7 @@ Zifencei: size: 32 branch: false delay: 1 -RV32M: +RVM: MUL: index: 49 encoding: 0b00000010000000000000000000110011 diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index 10b6296..e98f30c 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -429,7 +429,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + (int32_t)imm); + *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)imm )); } } } @@ -459,9 +459,9 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + 4); + *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 4 )); } - *NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)sext<21>(imm) )); this->core.reg.last_branch = 1; } } @@ -489,13 +489,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t addr_mask = (uint32_t)- 2; - uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & addr_mask); + uint32_t new_pc = (uint32_t)(((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )) & (int64_t)(addr_mask )); if(new_pc % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + 4); + *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 4 )); } *NEXT_PC = new_pc; this->core.reg.last_branch = 1; @@ -525,11 +525,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) == *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -558,11 +558,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) != *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -591,11 +591,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -624,11 +624,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -657,11 +657,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) < *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -690,11 +690,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs1) >= *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { + if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { raise(0, 0); } else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); this->core.reg.last_branch = 1; } } @@ -722,7 +722,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); int8_t res_27 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int8_t res = (int8_t)res_27; @@ -753,7 +753,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); int16_t res_28 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int16_t res = (int16_t)res_28; @@ -784,7 +784,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); int32_t res_29 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int32_t res = (int32_t)res_29; @@ -815,7 +815,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); uint8_t res_30 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint8_t res = res_30; @@ -846,7 +846,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); uint16_t res_31 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint16_t res = res_31; @@ -877,7 +877,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); super::template write_mem(traits::MEM, store_address, (uint8_t)*(X+rs2)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } @@ -904,7 +904,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); super::template write_mem(traits::MEM, store_address, (uint16_t)*(X+rs2)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } @@ -931,7 +931,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); super::template write_mem(traits::MEM, store_address, (uint32_t)*(X+rs2)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } @@ -959,7 +959,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); } } } @@ -1202,7 +1202,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2)); + *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)(*(X+rs2) )); } } } @@ -1229,7 +1229,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2)); + *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) - (uint64_t)(*(X+rs2) )); } } } @@ -1256,7 +1256,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1)); + *(X+rd) = *(X+rs1) << ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 ))); } } } @@ -1364,7 +1364,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); + *(X+rd) = *(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 ))); } } } @@ -1391,7 +1391,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1))); + *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 )))); } } } @@ -1772,7 +1772,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2)); + int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) ); if(rd != 0) { *(X+rd) = (uint32_t)res; } @@ -1800,7 +1800,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2)); + int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) ); if(rd != 0) { *(X+rd) = (uint32_t)(res >> traits::XLEN); } @@ -1828,7 +1828,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2)); + int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)(*(X+rs2) ); if(rd != 0) { *(X+rd) = (uint32_t)(res >> traits::XLEN); } @@ -1856,7 +1856,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint64_t res = (uint64_t)((uint64_t)*(X+rs1) * (uint64_t)*(X+rs2)); + uint64_t res = (uint64_t)(*(X+rs1) ) * (uint64_t)(*(X+rs2) ); if(rd != 0) { *(X+rd) = (uint32_t)(res >> traits::XLEN); } @@ -1888,7 +1888,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co int32_t divisor = (int32_t)*(X+rs2); if(rd != 0) { if(divisor != 0) { - uint32_t MMIN = ((uint32_t)1) << (traits::XLEN - 1); + uint32_t MMIN = ((uint32_t)1) << ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )); if(*(X+rs1) == MMIN && divisor == - 1) { *(X+rd) = MMIN; } @@ -1926,7 +1926,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co else { if(*(X+rs2) != 0) { if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) / *(X+rs2)); + *(X+rd) = *(X+rs1) / *(X+rs2); } } else { @@ -1959,7 +1959,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(*(X+rs2) != 0) { - uint32_t MMIN = (uint32_t)1 << (traits::XLEN - 1); + uint32_t MMIN = (uint32_t)1 << ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )); if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) { if(rd != 0) { *(X+rd) = 0; @@ -1967,7 +1967,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2)); + *(X+rd) = ((uint32_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2))); } } } @@ -2030,7 +2030,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(imm) { - *(X+rd + 8) = (uint32_t)(*(X+2) + imm); + *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(imm )); } else { raise(0, 2); @@ -2054,7 +2054,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - uint32_t offs = (uint32_t)(*(X+rs1 + 8) + uimm); + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm )); int32_t res_38 = super::template read_mem(traits::MEM, offs); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); *(X+rd + 8) = (uint32_t)(int32_t)res_38; @@ -2077,7 +2077,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - uint32_t offs = (uint32_t)(*(X+rs1 + 8) + uimm); + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm )); super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2 + 8)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } @@ -2103,7 +2103,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rs1 != 0) { - *(X+rs1) = (uint32_t)(*(X+rs1) + (int8_t)sext<6>(imm)); + *(X+rs1) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int8_t)sext<6>(imm) )); } } } @@ -2136,8 +2136,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+1) = (uint32_t)(*PC + 2); - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm)); + *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 2 )); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) )); this->core.reg.last_branch = 1; } break; @@ -2207,7 +2207,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(nzimm) { - *(X+2) = (uint32_t)(*(X+2) + (int16_t)sext<10>(nzimm)); + *(X+2) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)((int16_t)sext<10>(nzimm) )); } else { raise(0, 2); @@ -2289,7 +2289,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (int8_t)sext<6>(imm)); + *(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (uint32_t)((int8_t)sext<6>(imm) )); } break; }// @suppress("No break at end of case") @@ -2308,7 +2308,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+rd + 8) = (uint32_t)(*(X+rd + 8) - *(X+rs2 + 8)); + *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+rd + 8) ) - (uint64_t)(*(X+rs2 + 8) )); } break; }// @suppress("No break at end of case") @@ -2382,7 +2382,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) )); this->core.reg.last_branch = 1; } break; @@ -2403,7 +2403,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(*(X+rs1 + 8) == 0) { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) )); this->core.reg.last_branch = 1; } } @@ -2425,7 +2425,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(*(X+rs1 + 8) != 0) { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm)); + *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) )); this->core.reg.last_branch = 1; } } @@ -2476,7 +2476,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t offs = (uint32_t)(*(X+2) + uimm); + uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm )); int32_t res_39 = super::template read_mem(traits::MEM, offs); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); *(X+rd) = (uint32_t)(int32_t)res_39; @@ -2525,7 +2525,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs1 && rs1 < traits::RFS) { - *NEXT_PC = *(X+rs1 % traits::RFS) & ~ 0x1; + *NEXT_PC = *(X+(uint32_t)(rs1 ) % traits::RFS) & (uint32_t)(~ 0x1 ); this->core.reg.last_branch = 1; } else { @@ -2567,7 +2567,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rd) + *(X+rs2)); + *(X+rd) = (uint32_t)((uint64_t)(*(X+rd) ) + (uint64_t)(*(X+rs2) )); } } } @@ -2592,8 +2592,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co } else { uint32_t new_pc = *(X+rs1); - *(X+1) = (uint32_t)(*PC + 2); - *NEXT_PC = new_pc & ~ 0x1; + *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 2 )); + *NEXT_PC = new_pc & (uint32_t)(~ 0x1 ); this->core.reg.last_branch = 1; } } @@ -2631,7 +2631,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co raise(0, 2); } else { - uint32_t offs = (uint32_t)(*(X+2) + uimm); + uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm )); super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } From 602bc6e06a244d68a581d67f96097a63d44e5d89 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Fri, 26 Apr 2024 17:06:26 +0200 Subject: [PATCH 15/33] checking: working --- src/vm/asmjit/vm_tgc5c.cpp | 283 +++++++++++++++++++++++++------------ 1 file changed, 191 insertions(+), 92 deletions(-) diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index 6a6033c..1669219 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -79,21 +79,36 @@ public: } protected: - using vm_base::get_reg_ptr; + using super::get_ptr_for; + using super::get_reg; + using super::get_reg_for; + using super::load_reg_from_mem; + using super::write_reg_to_mem; + using super::gen_ext; + using super::gen_read_mem; + using super::gen_write_mem; + using super::gen_wait; + using super::gen_leave; + using super::gen_operation; + using this_class = vm_impl; using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&); continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override; + void gen_block_prologue(jit_holder& jh) override; + void gen_block_epilogue(jit_holder& jh) override; inline const char *name(size_t index){return traits::reg_aliases.at(index);} + void gen_instr_prologue(jit_holder& jh, addr_t pc); + void gen_instr_epilogue(jit_holder& jh); + inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause); + template::type> inline S sext(U from) { auto mask = (1ULL< - private: /**************************************************************************** * start opcode definitions @@ -326,7 +341,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)((int32_t)imm)); } } @@ -370,7 +385,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)(PC+(int32_t)imm)); } } @@ -418,12 +433,12 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)(PC+ 4)); } auto PC_val_v = (uint32_t)(PC+(int32_t)sext<21>(imm)); cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } } auto returnValue = BRANCH; @@ -486,12 +501,12 @@ private: cc.bind(label_else); { if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)(PC+ 4)); } auto PC_val_v = new_pc; cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } cc.bind(label_merge); } @@ -547,7 +562,7 @@ private: else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } } cc.bind(label_merge); @@ -604,7 +619,7 @@ private: else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } } cc.bind(label_merge); @@ -663,7 +678,7 @@ private: else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } } cc.bind(label_merge); @@ -722,7 +737,7 @@ private: else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } } cc.bind(label_merge); @@ -779,7 +794,7 @@ private: else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } } cc.bind(label_merge); @@ -836,7 +851,7 @@ private: else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } } cc.bind(label_merge); @@ -888,7 +903,7 @@ private: auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 1), 8, false); if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, res, 32, true)); } @@ -940,7 +955,7 @@ private: auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 2), 16, false); if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, res, 32, true)); } @@ -992,7 +1007,7 @@ private: auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 4), 32, false); if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, res, 32, true)); } @@ -1043,7 +1058,7 @@ private: ), 32, true); auto res = gen_read_mem(jh, traits::MEM, load_address, 1); if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, res, 32, false)); } @@ -1094,7 +1109,7 @@ private: ), 32, true); auto res = gen_read_mem(jh, traits::MEM, load_address, 2); if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, res, 32, false)); } @@ -1281,7 +1296,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true)) @@ -1341,7 +1356,7 @@ private: cc.bind(label_then); cc.mov(tmp_reg, 1); cc.bind(label_merge); - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, tmp_reg , 32, false) ); @@ -1400,7 +1415,7 @@ private: cc.bind(label_then); cc.mov(tmp_reg, 1); cc.bind(label_merge); - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, tmp_reg , 32, false) ); @@ -1448,7 +1463,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) ); @@ -1495,7 +1510,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) ); @@ -1542,7 +1557,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) ); @@ -1589,7 +1604,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, shamt, 32, false)) ); @@ -1636,7 +1651,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, shamt, 32, false)) ); @@ -1683,7 +1698,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, sar, gen_ext(jh, @@ -1732,7 +1747,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false)) @@ -1780,7 +1795,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, sub, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false)) @@ -1828,7 +1843,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, gen_operation(jh, shl, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), (gen_operation(jh, band, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false), (static_cast(traits::XLEN)- 1)) @@ -1890,7 +1905,7 @@ private: cc.bind(label_then); cc.mov(tmp_reg, 1); cc.bind(label_merge); - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, tmp_reg , 32, false) ); @@ -1949,7 +1964,7 @@ private: cc.bind(label_then); cc.mov(tmp_reg, 1); cc.bind(label_merge); - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, tmp_reg , 32, false) ); @@ -1997,7 +2012,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ); @@ -2044,7 +2059,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, gen_operation(jh, shr, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), (gen_operation(jh, band, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false), (static_cast(traits::XLEN)- 1)) @@ -2093,7 +2108,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_ext(jh, gen_operation(jh, sar, gen_ext(jh, gen_ext(jh, @@ -2144,7 +2159,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ); @@ -2191,7 +2206,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ); @@ -2412,7 +2427,7 @@ private: if(rd!= 0){ auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); gen_write_mem(jh, traits::CSR, csr, xrs1, 4); - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), xrd); } else{ @@ -2467,7 +2482,7 @@ private: , 4); } if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), xrd); } } @@ -2519,7 +2534,7 @@ private: , 4); } if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), xrd); } } @@ -2566,7 +2581,7 @@ private: auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); gen_write_mem(jh, traits::CSR, csr, (uint32_t)zimm, 4); if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), xrd); } } @@ -2617,7 +2632,7 @@ private: , 4); } if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), xrd); } } @@ -2668,7 +2683,7 @@ private: , 4); } if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), xrd); } } @@ -2758,7 +2773,7 @@ private: load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true), 128, true)) ), 64, true); if(rd!=0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, res, 32, true)); } @@ -2812,7 +2827,7 @@ private: load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true), 128, true)) ), 64, true); if(rd!=0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, sar, res, gen_ext(jh, static_cast(traits::XLEN), 64, false)) @@ -2867,7 +2882,7 @@ private: load_reg_from_mem(jh, traits::X0 + rs2), 64, false), 128, false)) ), 64, true); if(rd!=0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, sar, res, gen_ext(jh, static_cast(traits::XLEN), 64, false)) @@ -2921,7 +2936,7 @@ private: load_reg_from_mem(jh, traits::X0 + rs2), 64, false), 128, false)) ), 64, false); if(rd!=0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, shr, res, gen_ext(jh, static_cast(traits::XLEN), 64, false)) @@ -2992,13 +3007,13 @@ private: auto label_else = cc.newLabel(); cc.je(label_else); { - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), MMIN); } cc.jmp(label_merge); cc.bind(label_else); { - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, idiv, gen_ext(jh, dividend, 64, true), gen_ext(jh, divisor, 64, true)) @@ -3009,7 +3024,7 @@ private: cc.jmp(label_merge); cc.bind(label_else); { - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)- 1); } cc.bind(label_merge); @@ -3063,7 +3078,7 @@ private: cc.je(label_else); { if(rd!=0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, div, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) @@ -3074,7 +3089,7 @@ private: cc.bind(label_else); { if(rd!=0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)- 1); } } @@ -3141,7 +3156,7 @@ private: cc.je(label_else); { if(rd!=0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, 0, 32, false) ); } @@ -3150,7 +3165,7 @@ private: cc.bind(label_else); { if(rd!=0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, srem, gen_ext(jh, @@ -3165,7 +3180,7 @@ private: cc.bind(label_else); { if(rd!=0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), load_reg_from_mem(jh, traits::X0 + rs1)); } } @@ -3219,7 +3234,7 @@ private: cc.je(label_else); { if(rd!=0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, urem, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ); @@ -3229,7 +3244,7 @@ private: cc.bind(label_else); { if(rd!=0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), load_reg_from_mem(jh, traits::X0 + rs1)); } } @@ -3271,7 +3286,7 @@ private: cc.comment("\n//behavior:"); /*generate behavior*/ if(imm){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), gen_ext(jh, (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, imm, 64, false)) @@ -3320,7 +3335,7 @@ private: (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1+ 8), 64, false), gen_ext(jh, uimm, 64, false)) ), 32, false); - cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), gen_ext(jh, gen_ext(jh, gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true)); @@ -3406,7 +3421,7 @@ private: } else{ if(rs1!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rs1), + cc.mov(get_ptr_for(jh, traits::X0+ rs1), gen_ext(jh, (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int8_t)sext<6>(imm), 64, true)) @@ -3480,11 +3495,11 @@ private: gen_instr_prologue(jh, pc.val); cc.comment("\n//behavior:"); /*generate behavior*/ - cc.mov(get_reg_ptr(jh, traits::X0+ 1), + cc.mov(get_ptr_for(jh, traits::X0+ 1), (uint32_t)(PC+ 2)); auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); auto returnValue = BRANCH; gen_instr_epilogue(jh); @@ -3525,7 +3540,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)((int8_t)sext<6>(imm))); } } @@ -3568,7 +3583,7 @@ private: gen_raise(jh, 0, 2); } if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)((int32_t)sext<18>(imm))); } auto returnValue = CONT; @@ -3606,7 +3621,7 @@ private: cc.comment("\n//behavior:"); /*generate behavior*/ if(nzimm){ - cc.mov(get_reg_ptr(jh, traits::X0+ 2), + cc.mov(get_ptr_for(jh, traits::X0+ 2), gen_ext(jh, (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, (int16_t)sext<10>(nzimm), 64, true)) @@ -3684,7 +3699,7 @@ private: gen_instr_prologue(jh, pc.val); cc.comment("\n//behavior:"); /*generate behavior*/ - cc.mov(get_reg_ptr(jh, traits::X0+ rs1+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1+ 8), gen_ext(jh, shamt, 32, false)) ); @@ -3724,7 +3739,7 @@ private: cc.comment("\n//behavior:"); /*generate behavior*/ if(shamt){ - cc.mov(get_reg_ptr(jh, traits::X0+ rs1+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), gen_ext(jh, (gen_operation(jh, sar, (gen_ext(jh, @@ -3733,7 +3748,7 @@ private: } else{ if(static_cast(traits::XLEN)== 128){ - cc.mov(get_reg_ptr(jh, traits::X0+ rs1+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), gen_ext(jh, (gen_operation(jh, sar, (gen_ext(jh, @@ -3776,7 +3791,7 @@ private: gen_instr_prologue(jh, pc.val); cc.comment("\n//behavior:"); /*generate behavior*/ - cc.mov(get_reg_ptr(jh, traits::X0+ rs1+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), gen_ext(jh, (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1+ 8), gen_ext(jh, (int8_t)sext<6>(imm), 32, true)) @@ -3816,7 +3831,7 @@ private: gen_instr_prologue(jh, pc.val); cc.comment("\n//behavior:"); /*generate behavior*/ - cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), gen_ext(jh, (gen_operation(jh, sub, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rd+ 8), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2+ 8), 64, false)) @@ -3856,7 +3871,7 @@ private: gen_instr_prologue(jh, pc.val); cc.comment("\n//behavior:"); /*generate behavior*/ - cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) ); @@ -3895,7 +3910,7 @@ private: gen_instr_prologue(jh, pc.val); cc.comment("\n//behavior:"); /*generate behavior*/ - cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) ); @@ -3934,7 +3949,7 @@ private: gen_instr_prologue(jh, pc.val); cc.comment("\n//behavior:"); /*generate behavior*/ - cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) ); @@ -3974,7 +3989,7 @@ private: /*generate behavior*/ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); auto returnValue = BRANCH; gen_instr_epilogue(jh); @@ -4018,7 +4033,7 @@ private: { auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm)); cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } cc.bind(label_merge); auto returnValue = BRANCH; @@ -4064,7 +4079,7 @@ private: { auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm)); cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } cc.bind(label_merge); auto returnValue = BRANCH; @@ -4107,7 +4122,7 @@ private: } else{ if(rs1!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rs1), + cc.mov(get_ptr_for(jh, traits::X0+ rs1), gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, nzuimm, 32, false)) ); @@ -4156,7 +4171,7 @@ private: (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, uimm, 64, false)) ), 32, false); - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, gen_ext(jh, gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true)); @@ -4201,7 +4216,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), load_reg_from_mem(jh, traits::X0 + rs2)); } } @@ -4244,7 +4259,7 @@ private: load_reg_from_mem(jh, traits::X0 + rs1%static_cast(traits::RFS)), gen_ext(jh, ~ 0x1, 32, false)) ; cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } else{ gen_raise(jh, 0, 2); @@ -4322,7 +4337,7 @@ private: } else{ if(rd!= 0){ - cc.mov(get_reg_ptr(jh, traits::X0+ rd), + cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, add, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rd), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false)) @@ -4368,13 +4383,13 @@ private: } else{ auto new_pc = load_reg_from_mem(jh, traits::X0 + rs1); - cc.mov(get_reg_ptr(jh, traits::X0+ 1), + cc.mov(get_ptr_for(jh, traits::X0+ 1), (uint32_t)(PC+ 2)); auto PC_val_v = gen_operation(jh, band, new_pc, gen_ext(jh, ~ 0x1, 32, false)) ; cc.mov(jh.next_pc, PC_val_v); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); } auto returnValue = BRANCH; @@ -4556,11 +4571,6 @@ private: } }; -template void debug_fn(CODE_WORD instr) { - volatile CODE_WORD x = instr; - instr = 2 * x; -} - template vm_impl::vm_impl() { this(new ARCH()); } template @@ -4574,8 +4584,7 @@ vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) } template -continuation_e -vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) { +continuation_e vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) { enum {TRAP_ID=1<<16}; code_word_t instr = 0; phys_addr_t paddr(pc); @@ -4593,6 +4602,96 @@ vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, f = &this_class::illegal_intruction; return (this->*f)(pc, instr, jh); } +template +void vm_impl::gen_instr_prologue(jit_holder& jh, addr_t pc) { + auto& cc = jh.cc; + cc.mov(jh.pc, pc); + + cc.comment("\n//(*icount)++;"); + cc.inc(get_ptr_for(jh, traits::ICOUNT)); + + cc.comment("\n//*pc=*next_pc;"); + cc.mov(get_ptr_for(jh, traits::PC), jh.next_pc); + + cc.comment("\n//*trap_state=*pending_trap;"); + x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); + cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + cc.mov(get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state); + + cc.comment("\n//increment *next_pc"); + cc.mov(jh.next_pc, pc); +} +template +void vm_impl::gen_instr_epilogue(jit_holder& jh) { + auto& cc = jh.cc; + + cc.comment("\n//if(*trap_state!=0) goto trap_entry;"); + x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); + cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + cc.cmp(current_trap_state, 0); + cc.jne(jh.trap_entry); + + // TODO: Does not need to be done for every instruction, only when needed (by plugin) + cc.comment("\n//write back regs to mem"); + write_reg_to_mem(jh, jh.pc, traits::PC); + write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); +} +template +void vm_impl::gen_block_prologue(jit_holder& jh){ + + jh.pc = load_reg_from_mem(jh, traits::PC); + jh.next_pc = load_reg_from_mem(jh, traits::NEXT_PC); +} +template +void vm_impl::gen_block_epilogue(jit_holder& jh){ + x86::Compiler& cc = jh.cc; + cc.comment("\n//return *next_pc;"); + cc.ret(jh.next_pc); + + cc.bind(jh.trap_entry); + cc.comment("\n//Prepare for enter_trap;"); + // Make sure cached values are written back + cc.comment("\n//write back regs to mem"); + write_reg_to_mem(jh, jh.pc, traits::PC); + write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); + this->gen_sync(jh, POST_SYNC, -1); + + x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); + cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + + x86::Gp current_pc = get_reg_for(jh, traits::PC); + cc.mov(current_pc, get_ptr_for(jh, traits::PC)); + + x86::Gp instr = cc.newInt32("instr"); + cc.mov(instr, 0); // this is not correct + cc.comment("\n//enter trap call;"); + InvokeNode* call_enter_trap; + cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT()); + call_enter_trap->setArg(0, jh.arch_if_ptr); + call_enter_trap->setArg(1, current_trap_state); + call_enter_trap->setArg(2, current_pc); + call_enter_trap->setArg(3, instr); + + x86::Gp current_next_pc = get_reg_for(jh, traits::NEXT_PC); + cc.mov(current_next_pc, get_ptr_for(jh, traits::NEXT_PC)); + cc.mov(jh.next_pc, current_next_pc); + + cc.comment("\n//*last_branch = std::numeric_limits::max();"); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), std::numeric_limits::max()); + cc.comment("\n//return *next_pc;"); + cc.ret(jh.next_pc); +} +template +inline void vm_impl:: gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) { + auto& cc = jh.cc; + cc.comment("//gen_raise"); + auto tmp1 = get_reg_for(jh, traits::TRAP_STATE); + cc.mov(tmp1, 0x80ULL << 24 | (cause << 16) | trap_id); + cc.mov(get_ptr_for(jh, traits::TRAP_STATE), tmp1); + auto tmp2 = get_reg_for(jh, traits::NEXT_PC); + cc.mov(tmp2, std::numeric_limits::max()); + cc.mov(get_ptr_for(jh, traits::NEXT_PC), tmp2); +} From ad79a287054726c26769d7c3456a39e646f621a1 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Tue, 30 Apr 2024 19:21:27 +0200 Subject: [PATCH 16/33] wip checkin --- gen_input/templates/asmjit/CORENAME.cpp.gtl | 125 +- src/main.cpp | 2 +- src/vm/asmjit/helper_func.h | 539 -------- src/vm/asmjit/vm_tgc5c.cpp | 1373 ++++++++++--------- 4 files changed, 837 insertions(+), 1202 deletions(-) delete mode 100644 src/vm/asmjit/helper_func.h diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 00e86e9..cb0a2b5 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -79,21 +79,36 @@ public: } protected: - using vm_base::get_reg_ptr; + using super::get_ptr_for; +using super::get_reg; + using super::get_reg_for; + using super::load_reg_from_mem; + using super::write_reg_to_mem; + using super::gen_ext; + using super::gen_read_mem; + using super::gen_write_mem; + using super::gen_wait; + using super::gen_leave; + using super::gen_operation; + using this_class = vm_impl; using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&); continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override; + void gen_block_prologue(jit_holder& jh) override; + void gen_block_epilogue(jit_holder& jh) override; inline const char *name(size_t index){return traits::reg_aliases.at(index);} + void gen_instr_prologue(jit_holder& jh); + void gen_instr_epilogue(jit_holder& jh); + inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause); + template::type> inline S sext(U from) { auto mask = (1ULL< - private: /**************************************************************************** * start opcode definitions @@ -139,12 +154,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\\n${instr.name}_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("${instr.name}_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, ${idx}); - pc=pc+ ${instr.length/8}; - - gen_instr_prologue(jh, pc.val); - cc.comment("\\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+${instr.length/8}; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ <%instr.behavior.eachLine{%>${it} <%}%> @@ -214,11 +231,6 @@ private: } }; -template void debug_fn(CODE_WORD instr) { - volatile CODE_WORD x = instr; - instr = 2 * x; -} - template vm_impl::vm_impl() { this(new ARCH()); } template @@ -232,8 +244,7 @@ vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) } template -continuation_e -vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) { +continuation_e vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) { enum {TRAP_ID=1<<16}; code_word_t instr = 0; phys_addr_t paddr(pc); @@ -251,10 +262,90 @@ vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, f = &this_class::illegal_intruction; return (this->*f)(pc, instr, jh); } +template +void vm_impl::gen_instr_prologue(jit_holder& jh) { + auto& cc = jh.cc; + cc.comment("//(*icount)++;"); + cc.inc(get_ptr_for(jh, traits::ICOUNT)); + cc.comment("//*trap_state=*pending_trap;"); + x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); + cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + cc.mov(get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state); -} // namespace ${coreDef.name.toLowerCase()} +} +template +void vm_impl::gen_instr_epilogue(jit_holder& jh) { + auto& cc = jh.cc; + + cc.comment("//if(*trap_state!=0) goto trap_entry;"); + x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); + cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + cc.cmp(current_trap_state, 0); + cc.jne(jh.trap_entry); + + // TODO: Does not need to be done for every instruction, only when needed (by plugin) + cc.comment("//write back regs to mem"); + write_reg_to_mem(jh, jh.pc, traits::PC); + write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); +} +template +void vm_impl::gen_block_prologue(jit_holder& jh){ + + jh.pc = load_reg_from_mem(jh, traits::PC); + jh.next_pc = load_reg_from_mem(jh, traits::NEXT_PC); +} +template +void vm_impl::gen_block_epilogue(jit_holder& jh){ + x86::Compiler& cc = jh.cc; + cc.comment("//return *next_pc;"); + cc.ret(jh.next_pc); + + cc.bind(jh.trap_entry); + cc.comment("//Prepare for enter_trap;"); + // Make sure cached values are written back + cc.comment("//write back regs to mem"); + write_reg_to_mem(jh, jh.pc, traits::PC); + write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); + this->gen_sync(jh, POST_SYNC, -1); + + x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); + cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); + + x86::Gp current_pc = get_reg_for(jh, traits::PC); + cc.mov(current_pc, get_ptr_for(jh, traits::PC)); + + x86::Gp instr = cc.newInt32("instr"); + cc.mov(instr, 0); // this is not correct + cc.comment("//enter trap call;"); + InvokeNode* call_enter_trap; + cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT()); + call_enter_trap->setArg(0, jh.arch_if_ptr); + call_enter_trap->setArg(1, current_trap_state); + call_enter_trap->setArg(2, current_pc); + call_enter_trap->setArg(3, instr); + + x86::Gp current_next_pc = get_reg_for(jh, traits::NEXT_PC); + cc.mov(current_next_pc, get_ptr_for(jh, traits::NEXT_PC)); + cc.mov(jh.next_pc, current_next_pc); + + cc.comment("//*last_branch = std::numeric_limits::max();"); + cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), std::numeric_limits::max()); + cc.comment("//return *next_pc;"); + cc.ret(jh.next_pc); +} +template +inline void vm_impl:: gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) { + auto& cc = jh.cc; + cc.comment("//gen_raise"); + auto tmp1 = get_reg_for(jh, traits::TRAP_STATE); + cc.mov(tmp1, 0x80ULL << 24 | (cause << 16) | trap_id); + cc.mov(get_ptr_for(jh, traits::TRAP_STATE), tmp1); + cc.mov(jh.next_pc, std::numeric_limits::max()); +} + +} // namespace tgc5c template <> std::unique_ptr create(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) { @@ -265,9 +356,9 @@ std::unique_ptr create(arch::${coreD } // namespace asmjit } // namespace iss -#include #include #include +#include namespace iss { namespace { volatile std::array dummy = { diff --git a/src/main.cpp b/src/main.cpp index 839bbbc..e4ad4c3 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -75,7 +75,7 @@ int main(int argc, char* argv[]) { ("elf,f", po::value>(), "ELF file(s) to load") ("mem,m", po::value(), "the memory input file") ("plugin,p", po::value>(), "plugin to activate") - ("backend", po::value()->default_value("interp"), "the ISS backend to use, options are: interp, tcc") + ("backend", po::value()->default_value("interp"), "the ISS backend to use, options are: interp, llvm, tcc, asmjit") ("isa", po::value()->default_value("tgc5c"), "core or isa name to use for simulation, use '?' to get list"); // clang-format on auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run(); diff --git a/src/vm/asmjit/helper_func.h b/src/vm/asmjit/helper_func.h deleted file mode 100644 index 88aceba..0000000 --- a/src/vm/asmjit/helper_func.h +++ /dev/null @@ -1,539 +0,0 @@ -#include -#include - -x86::Mem get_reg_ptr(jit_holder& jh, unsigned idx) { - - x86::Gp tmp_ptr = jh.cc.newUIntPtr("tmp_ptr"); - jh.cc.mov(tmp_ptr, jh.regs_base_ptr); - jh.cc.add(tmp_ptr, traits::reg_byte_offsets[idx]); - switch(traits::reg_bit_widths[idx]) { - case 8: - return x86::ptr_8(tmp_ptr); - case 16: - return x86::ptr_16(tmp_ptr); - case 32: - return x86::ptr_32(tmp_ptr); - case 64: - return x86::ptr_64(tmp_ptr); - default: - throw std::runtime_error("Invalid reg size in get_reg_ptr"); - } -} -x86::Gp get_reg_for(jit_holder& jh, unsigned idx) { - // TODO can check for regs in jh and return them instead of creating new ones - switch(traits::reg_bit_widths[idx]) { - case 8: - return jh.cc.newInt8(); - case 16: - return jh.cc.newInt16(); - case 32: - return jh.cc.newInt32(); - case 64: - return jh.cc.newInt64(); - default: - throw std::runtime_error("Invalid reg size in get_reg_ptr"); - } -} -x86::Gp get_reg_for(jit_holder& jh, unsigned size, bool is_signed) { - if(is_signed) - switch(size) { - case 8: - return jh.cc.newInt8(); - case 16: - return jh.cc.newInt16(); - case 32: - return jh.cc.newInt32(); - case 64: - return jh.cc.newInt64(); - default: - throw std::runtime_error("Invalid reg size in get_reg_ptr"); - } - else - switch(size) { - case 8: - return jh.cc.newUInt8(); - case 16: - return jh.cc.newUInt16(); - case 32: - return jh.cc.newUInt32(); - case 64: - return jh.cc.newUInt64(); - default: - throw std::runtime_error("Invalid reg size in get_reg_ptr"); - } -} -inline x86::Gp load_reg_from_mem(jit_holder& jh, unsigned idx) { - auto ptr = get_reg_ptr(jh, idx); - auto reg = get_reg_for(jh, idx); - jh.cc.mov(reg, ptr); - return reg; -} -inline void write_reg_to_mem(jit_holder& jh, x86::Gp reg, unsigned idx) { - auto ptr = get_reg_ptr(jh, idx); - jh.cc.mov(ptr, reg); -} - -void gen_instr_prologue(jit_holder& jh, addr_t pc) { - auto& cc = jh.cc; - cc.mov(jh.pc, pc); - - cc.comment("\n//(*icount)++;"); - cc.inc(get_reg_ptr(jh, traits::ICOUNT)); - - cc.comment("\n//*pc=*next_pc;"); - cc.mov(get_reg_ptr(jh, traits::PC), jh.next_pc); - - cc.comment("\n//*trap_state=*pending_trap;"); - x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); - cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE)); - cc.mov(get_reg_ptr(jh, traits::PENDING_TRAP), current_trap_state); - - cc.comment("\n//increment *next_pc"); - cc.mov(jh.next_pc, pc); -} -void gen_instr_epilogue(jit_holder& jh) { - auto& cc = jh.cc; - - cc.comment("\n//if(*trap_state!=0) goto trap_entry;"); - x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); - cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE)); - cc.cmp(current_trap_state, 0); - cc.jne(jh.trap_entry); - - // TODO: Does not need to be done for every instruction, only when needed - cc.comment("\n//write back regs to mem"); - write_reg_to_mem(jh, jh.pc, traits::PC); - write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); -} -void gen_block_prologue(jit_holder& jh) override { - - jh.pc = load_reg_from_mem(jh, traits::PC); - jh.next_pc = load_reg_from_mem(jh, traits::NEXT_PC); -} -void gen_block_epilogue(jit_holder& jh) override { - x86::Compiler& cc = jh.cc; - cc.comment("\n//return *next_pc;"); - cc.ret(jh.next_pc); - - cc.bind(jh.trap_entry); - cc.comment("\n//Prepare for enter_trap;"); - // Make sure cached values are written back - cc.comment("\n//write back regs to mem"); - write_reg_to_mem(jh, jh.pc, traits::PC); - write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); - this->gen_sync(jh, POST_SYNC, -1); - - x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); - cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE)); - - x86::Gp current_pc = get_reg_for(jh, traits::PC); - cc.mov(current_pc, get_reg_ptr(jh, traits::PC)); - - x86::Gp instr = cc.newInt32("instr"); - cc.mov(instr, 0); // this is not correct - cc.comment("\n//enter trap call;"); - InvokeNode* call_enter_trap; - cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT()); - call_enter_trap->setArg(0, jh.arch_if_ptr); - call_enter_trap->setArg(1, current_trap_state); - call_enter_trap->setArg(2, current_pc); - call_enter_trap->setArg(3, instr); - - x86::Gp current_next_pc = get_reg_for(jh, traits::NEXT_PC); - cc.mov(current_next_pc, get_reg_ptr(jh, traits::NEXT_PC)); - cc.mov(jh.next_pc, current_next_pc); - - cc.comment("\n//*last_branch = std::numeric_limits::max();"); - cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), std::numeric_limits::max()); - cc.comment("\n//return *next_pc;"); - cc.ret(jh.next_pc); -} -/* - inline void raise(uint16_t trap_id, uint16_t cause){ - auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id; - this->core.reg.trap_state = trap_val; - this->template get_reg(traits::NEXT_PC) = std::numeric_limits::max(); - } -*/ -inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) { - auto& cc = jh.cc; - cc.comment("//gen_raise"); - auto tmp1 = get_reg_for(jh, traits::TRAP_STATE); - cc.mov(tmp1, 0x80ULL << 24 | (cause << 16) | trap_id); - cc.mov(get_reg_ptr(jh, traits::TRAP_STATE), tmp1); - auto tmp2 = get_reg_for(jh, traits::NEXT_PC); - cc.mov(tmp2, std::numeric_limits::max()); - cc.mov(get_reg_ptr(jh, traits::NEXT_PC), tmp2); -} -inline void gen_wait(jit_holder& jh, unsigned type) { jh.cc.comment("//gen_wait"); } -inline void gen_leave(jit_holder& jh, unsigned lvl) { jh.cc.comment("//gen_leave"); } - -enum operation { add, sub, band, bor, bxor, shl, sar, shr }; - -template ::value || std::is_same::value>> -x86::Gp gen_operation(jit_holder& jh, operation op, x86::Gp a, T b) { - x86::Compiler& cc = jh.cc; - switch(op) { - case add: { - cc.add(a, b); - break; - } - case sub: { - cc.sub(a, b); - break; - } - case band: { - cc.and_(a, b); - break; - } - case bor: { - cc.or_(a, b); - break; - } - case bxor: { - cc.xor_(a, b); - break; - } - case shl: { - cc.shl(a, b); - break; - } - case sar: { - cc.sar(a, b); - break; - } - case shr: { - cc.shr(a, b); - break; - } - default: - throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (operation)", op)); - } - return a; -} - -enum three_operand_operation { imul, mul, idiv, div, srem, urem }; - -x86::Gp gen_operation(jit_holder& jh, three_operand_operation op, x86::Gp a, x86::Gp b) { - x86::Compiler& cc = jh.cc; - switch(op) { - case imul: { - x86::Gp dummy = cc.newInt64(); - cc.imul(dummy, a.r64(), b.r64()); - return a; - } - case mul: { - x86::Gp dummy = cc.newInt64(); - cc.mul(dummy, a.r64(), b.r64()); - return a; - } - case idiv: { - x86::Gp dummy = cc.newInt64(); - cc.mov(dummy, 0); - cc.idiv(dummy, a.r64(), b.r64()); - return a; - } - case div: { - x86::Gp dummy = cc.newInt64(); - cc.mov(dummy, 0); - cc.div(dummy, a.r64(), b.r64()); - return a; - } - case srem: { - x86::Gp rem = cc.newInt32(); - cc.mov(rem, 0); - auto a_reg = cc.newInt32(); - cc.mov(a_reg, a.r32()); - cc.idiv(rem, a_reg, b.r32()); - return rem; - } - case urem: { - x86::Gp rem = cc.newInt32(); - cc.mov(rem, 0); - auto a_reg = cc.newInt32(); - cc.mov(a_reg, a.r32()); - cc.div(rem, a_reg, b.r32()); - return rem; - } - - default: - throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (three_operand)", op)); - } - return a; -} -template ::value>> -x86::Gp gen_operation(jit_holder& jh, three_operand_operation op, x86::Gp a, T b) { - x86::Gp b_reg = jh.cc.newInt32(); - /* switch(a.size()){ - case 1: b_reg = jh.cc.newInt8(); break; - case 2: b_reg = jh.cc.newInt16(); break; - case 4: b_reg = jh.cc.newInt32(); break; - case 8: b_reg = jh.cc.newInt64(); break; - default: throw std::runtime_error(fmt::format("Invalid size ({}) in gen operation", a.size())); - } */ - jh.cc.mov(b_reg, b); - return gen_operation(jh, op, a, b_reg); -} -enum comparison_operation { land, lor, eq, ne, lt, ltu, gt, gtu, lte, lteu, gte, gteu }; - -template ::value || std::is_same::value>> -x86::Gp gen_operation(jit_holder& jh, comparison_operation op, x86::Gp a, T b) { - x86::Compiler& cc = jh.cc; - x86::Gp tmp = cc.newInt8(); - cc.mov(tmp, 1); - Label label_then = cc.newLabel(); - cc.cmp(a, b); - switch(op) { - case eq: - cc.je(label_then); - break; - case ne: - cc.jne(label_then); - break; - case lt: - cc.jl(label_then); - break; - case ltu: - cc.jb(label_then); - break; - case gt: - cc.jg(label_then); - break; - case gtu: - cc.ja(label_then); - break; - case lte: - cc.jle(label_then); - break; - case lteu: - cc.jbe(label_then); - break; - case gte: - cc.jge(label_then); - break; - case gteu: - cc.jae(label_then); - break; - case land: { - Label label_false = cc.newLabel(); - cc.cmp(a, 0); - cc.je(label_false); - auto b_reg = cc.newInt8(); - cc.mov(b_reg, b); - cc.cmp(b_reg, 0); - cc.je(label_false); - cc.jmp(label_then); - cc.bind(label_false); - break; - } - case lor: { - cc.cmp(a, 0); - cc.jne(label_then); - auto b_reg = cc.newInt8(); - cc.mov(b_reg, b); - cc.cmp(b_reg, 0); - cc.jne(label_then); - break; - } - default: - throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (comparison)", op)); - } - cc.mov(tmp, 0); - cc.bind(label_then); - return tmp; -} -enum binary_operation { lnot, inc, dec, bnot, neg }; - -x86::Gp gen_operation(jit_holder& jh, binary_operation op, x86::Gp a) { - x86::Compiler& cc = jh.cc; - switch(op) { - case lnot: - throw std::runtime_error("Current operation not supported in gen_operation(lnot)"); - case inc: { - cc.inc(a); - break; - } - case dec: { - cc.dec(a); - break; - } - case bnot: { - cc.not_(a); - break; - } - case neg: { - cc.neg(a); - break; - } - default: - throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (unary)", op)); - } - return a; -} - -template ::value>> -inline x86::Gp gen_ext(jit_holder& jh, T val, unsigned size, bool is_signed) { - auto val_reg = get_reg_for(jh, sizeof(val) * 8, is_signed); - jh.cc.mov(val_reg, val); - return gen_ext(jh, val_reg, size, is_signed); -} -inline x86::Gp gen_ext(jit_holder& jh, x86::Gp val, unsigned size, bool is_signed) { - auto& cc = jh.cc; - if(is_signed) { - switch(val.size()) { - case 1: - cc.cbw(val); - break; - case 2: - cc.cwde(val); - break; - case 4: - cc.cdqe(val); - break; - case 8: - break; - default: - throw std::runtime_error("Invalid register size in gen_ext"); - } - } - switch(size) { - case 8: - cc.and_(val, std::numeric_limits::max()); - return val.r8(); - case 16: - cc.and_(val, std::numeric_limits::max()); - return val.r16(); - case 32: - cc.and_(val, std::numeric_limits::max()); - return val.r32(); - case 64: - cc.and_(val, std::numeric_limits::max()); - return val.r64(); - case 128: - return val.r64(); - default: - throw std::runtime_error("Invalid size in gen_ext"); - } -} -inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, uint32_t length) { - x86::Compiler& cc = jh.cc; - auto ret_reg = cc.newInt32(); - - auto mem_type_reg = cc.newInt32(); - cc.mov(mem_type_reg, type); - - auto space_reg = cc.newInt32(); - cc.mov(space_reg, static_cast(iss::address_type::VIRTUAL)); - - auto val_ptr = cc.newUIntPtr(); - cc.mov(val_ptr, read_mem_buf); - - InvokeNode* invokeNode; - uint64_t mask = 0; - x86::Gp val_reg = cc.newInt64(); - - switch(length) { - case 1: { - cc.invoke(&invokeNode, &read_mem1, FuncSignatureT()); - mask = std::numeric_limits::max(); - break; - } - case 2: { - cc.invoke(&invokeNode, &read_mem2, FuncSignatureT()); - mask = std::numeric_limits::max(); - break; - } - case 4: { - cc.invoke(&invokeNode, &read_mem4, FuncSignatureT()); - mask = std::numeric_limits::max(); - break; - } - case 8: { - cc.invoke(&invokeNode, &read_mem8, FuncSignatureT()); - mask = std::numeric_limits::max(); - break; - } - default: - throw std::runtime_error(fmt::format("Invalid length ({}) in gen_read_mem", length)); - } - - invokeNode->setRet(0, ret_reg); - invokeNode->setArg(0, jh.arch_if_ptr); - invokeNode->setArg(1, space_reg); - invokeNode->setArg(2, mem_type_reg); - invokeNode->setArg(3, addr); - invokeNode->setArg(4, val_ptr); - cc.cmp(ret_reg, 0); - cc.jne(jh.trap_entry); - - cc.mov(val_reg, x86::ptr_64(val_ptr)); - cc.and_(val_reg, mask); - return val_reg; -} -inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, x86::Gp length) { - throw std::runtime_error("Invalid gen_read_mem"); -} -inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, uint64_t addr, x86::Gp length) { - throw std::runtime_error("Invalid gen_read_mem"); -} -inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, uint64_t addr, uint32_t length) { - auto addr_reg = jh.cc.newInt64(); - jh.cc.mov(addr_reg, addr); - - return gen_read_mem(jh, type, addr_reg, length); -} -inline void gen_write_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, int64_t val, uint32_t length) { - auto val_reg = get_reg_for(jh, length * 8, true); - jh.cc.mov(val_reg, val); - gen_write_mem(jh, type, addr, val_reg, length); -} -inline void gen_write_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, x86::Gp val, uint32_t length) { - x86::Compiler& cc = jh.cc; - assert(val.size() == length); - auto mem_type_reg = cc.newInt32(); - jh.cc.mov(mem_type_reg, type); - auto space_reg = cc.newInt32(); - jh.cc.mov(space_reg, static_cast(iss::address_type::VIRTUAL)); - auto ret_reg = cc.newInt32(); - InvokeNode* invokeNode; - switch(length) { - case 1: - cc.invoke(&invokeNode, &write_mem1, FuncSignatureT()); - - break; - case 2: - cc.invoke(&invokeNode, &write_mem2, FuncSignatureT()); - break; - case 4: - cc.invoke(&invokeNode, &write_mem4, FuncSignatureT()); - break; - case 8: - cc.invoke(&invokeNode, &write_mem8, FuncSignatureT()); - - break; - default: - throw std::runtime_error("Invalid register size in gen_ext"); - } - invokeNode->setRet(0, ret_reg); - invokeNode->setArg(0, jh.arch_if_ptr); - invokeNode->setArg(1, space_reg); - invokeNode->setArg(2, mem_type_reg); - invokeNode->setArg(3, addr); - invokeNode->setArg(4, val); - - cc.cmp(ret_reg, 0); - cc.jne(jh.trap_entry); -} -inline void gen_write_mem(jit_holder& jh, mem_type_e type, uint64_t addr, x86::Gp val, uint32_t length) { - auto addr_reg = jh.cc.newUInt64(); - jh.cc.mov(addr_reg, addr); - gen_write_mem(jh, type, addr_reg, val, length); -} -inline void gen_write_mem(jit_holder& jh, mem_type_e type, uint64_t addr, int64_t val, uint32_t length) { - auto val_reg = get_reg_for(jh, length * 8, true); - jh.cc.mov(val_reg, val); - - auto addr_reg = jh.cc.newUInt64(); - jh.cc.mov(addr_reg, addr); - gen_write_mem(jh, type, addr_reg, val_reg, length); -} diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index 1669219..8e4f72b 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -80,7 +80,7 @@ public: protected: using super::get_ptr_for; - using super::get_reg; +using super::get_reg; using super::get_reg_for; using super::load_reg_from_mem; using super::write_reg_to_mem; @@ -99,7 +99,7 @@ protected: void gen_block_epilogue(jit_holder& jh) override; inline const char *name(size_t index){return traits::reg_aliases.at(index);} - void gen_instr_prologue(jit_holder& jh, addr_t pc); + void gen_instr_prologue(jit_holder& jh); void gen_instr_epilogue(jit_holder& jh); inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause); @@ -329,12 +329,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nLUI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("LUI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 0); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -373,12 +375,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nAUIPC_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("AUIPC_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 1); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -417,12 +421,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nJAL_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("JAL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 2); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -470,12 +476,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nJALR_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("JALR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 3); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -483,14 +491,11 @@ private: else{ auto addr_mask = (uint32_t)- 2; auto new_pc = gen_ext(jh, - (gen_operation(jh, band, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true)) - ), gen_ext(jh, addr_mask, 64, false)) + (gen_operation(jh, band, (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) + ), addr_mask) ), 32, true); auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, urem, - new_pc, static_cast(traits::INSTR_ALIGNMENT)) + cc.cmp(gen_operation(jh, urem, new_pc, static_cast(traits::INSTR_ALIGNMENT)) ,0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -539,20 +544,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nBEQ_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("BEQ_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 4); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, eq, - load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + cc.cmp(gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ,0); cc.je(label_merge); { @@ -596,20 +602,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nBNE_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("BNE_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 5); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ne, - load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ,0); cc.je(label_merge); { @@ -653,22 +660,23 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nBLT_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("BLT_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 6); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, lt, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs2), 32, false)) + cc.cmp(gen_operation(jh, lt, gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs2), 32, false)) ,0); cc.je(label_merge); { @@ -712,22 +720,23 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nBGE_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("BGE_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 7); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, gte, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs2), 32, false)) + cc.cmp(gen_operation(jh, gte, gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs2), 32, false)) ,0); cc.je(label_merge); { @@ -771,20 +780,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nBLTU_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("BLTU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 8); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ltu, - load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + cc.cmp(gen_operation(jh, ltu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ,0); cc.je(label_merge); { @@ -828,20 +838,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nBGEU_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("BGEU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 9); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, gteu, - load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + cc.cmp(gen_operation(jh, gteu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ,0); cc.je(label_merge); { @@ -885,20 +896,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nLB_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("LB_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 10); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto load_address = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) ), 32, true); auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 1), 8, false); @@ -937,20 +949,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nLH_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("LH_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 11); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto load_address = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) ), 32, true); auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 2), 16, false); @@ -989,20 +1002,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nLW_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("LW_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 12); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto load_address = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) ), 32, true); auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 4), 32, false); @@ -1041,20 +1055,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nLBU_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("LBU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 13); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto load_address = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) ), 32, true); auto res = gen_read_mem(jh, traits::MEM, load_address, 1); if(rd!= 0){ @@ -1092,20 +1107,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nLHU_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("LHU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 14); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto load_address = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) ), 32, true); auto res = gen_read_mem(jh, traits::MEM, load_address, 2); if(rd!= 0){ @@ -1143,20 +1159,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSB_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SB_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 15); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto store_address = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) ), 32, true); gen_write_mem(jh, traits::MEM, store_address, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 8, false), 1); @@ -1190,20 +1207,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSH_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SH_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 16); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto store_address = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) ), 32, true); gen_write_mem(jh, traits::MEM, store_address, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 16, false), 2); @@ -1237,20 +1255,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSW_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SW_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 17); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto store_address = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) ), 32, true); gen_write_mem(jh, traits::MEM, store_address, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, false), 4); @@ -1284,12 +1303,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nADDI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("ADDI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 18); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1298,8 +1319,7 @@ private: if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) ), 32, true)); } } @@ -1332,12 +1352,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSLTI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SLTI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 19); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1392,12 +1414,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSLTIU_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SLTIU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 20); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1451,12 +1475,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nXORI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("XORI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 21); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1464,8 +1490,7 @@ private: else{ if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, bxor, - load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) + gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) ); } } @@ -1498,12 +1523,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nORI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("ORI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 22); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1511,8 +1538,7 @@ private: else{ if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, bor, - load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) + gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) ); } } @@ -1545,12 +1571,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nANDI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("ANDI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 23); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1558,8 +1586,7 @@ private: else{ if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, band, - load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) + gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) ); } } @@ -1592,12 +1619,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSLLI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SLLI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 24); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1605,8 +1634,7 @@ private: else{ if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, shl, - load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, shamt, 32, false)) + gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), shamt) ); } } @@ -1639,12 +1667,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSRLI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SRLI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 25); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1652,8 +1682,7 @@ private: else{ if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, shr, - load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, shamt, 32, false)) + gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), shamt) ); } } @@ -1686,12 +1715,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSRAI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SRAI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 26); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1700,9 +1731,8 @@ private: if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_operation(jh, sar, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh, shamt, 32, false)) + (gen_operation(jh, sar, gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, true), shamt) ), 32, true)); } } @@ -1735,12 +1765,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nADD_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("ADD_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 27); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1749,8 +1781,7 @@ private: if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ), 32, false)); } } @@ -1783,12 +1814,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSUB_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SUB_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 28); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1797,8 +1830,7 @@ private: if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_operation(jh, sub, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false)) + (gen_operation(jh, sub, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ), 32, true)); } } @@ -1831,12 +1863,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSLL_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SLL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 29); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1844,10 +1878,8 @@ private: else{ if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, gen_operation(jh, shl, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), (gen_operation(jh, band, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false), (static_cast(traits::XLEN)- 1)) - )) + gen_ext(jh, gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)- 1)) + )) , 32, false)); } } @@ -1880,12 +1912,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSLT_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SLT_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 30); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -1941,12 +1975,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSLTU_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SLTU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 31); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2000,12 +2036,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nXOR_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("XOR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 32); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2013,8 +2051,7 @@ private: else{ if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, bxor, - load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ); } } @@ -2047,12 +2084,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSRL_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SRL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 33); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2060,10 +2099,8 @@ private: else{ if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, gen_operation(jh, shr, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), (gen_operation(jh, band, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false), (static_cast(traits::XLEN)- 1)) - )) + gen_ext(jh, gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)- 1)) + )) , 32, false)); } } @@ -2096,12 +2133,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nSRA_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("SRA_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 34); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2110,11 +2149,9 @@ private: if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_ext(jh, gen_operation(jh, sar, - gen_ext(jh, gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), (gen_operation(jh, band, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false), (static_cast(traits::XLEN)- 1)) - )) + (gen_ext(jh, gen_operation(jh, sar, gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, true), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)- 1)) + )) , 32, true)), 32, true)); } } @@ -2147,12 +2184,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nOR_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("OR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 35); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2160,8 +2199,7 @@ private: else{ if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, bor, - load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ); } } @@ -2194,12 +2232,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nAND_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("AND_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 36); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2207,8 +2247,7 @@ private: else{ if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, band, - load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ); } } @@ -2243,12 +2282,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nFENCE_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("FENCE_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 37); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ gen_write_mem(jh, traits::FENCE, static_cast(traits::fence), (uint8_t)pred<< 4|succ, 4); auto returnValue = CONT; @@ -2276,12 +2317,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nECALL_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("ECALL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 38); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ gen_raise(jh, 0, 11); auto returnValue = TRAP; @@ -2309,12 +2352,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nEBREAK_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("EBREAK_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 39); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ gen_raise(jh, 0, 3); auto returnValue = TRAP; @@ -2342,12 +2387,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nMRET_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("MRET_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 40); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ gen_leave(jh, 3); auto returnValue = TRAP; @@ -2375,12 +2422,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nWFI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("WFI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 41); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ gen_wait(jh, 1); auto returnValue = CONT; @@ -2412,12 +2461,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nCSRRW_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("CSRRW_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 42); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2463,12 +2514,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nCSRRS_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("CSRRS_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 43); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2477,8 +2530,7 @@ private: auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1); if(rs1!= 0){ - gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, - xrd, xrs1) + gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, xrd, xrs1) , 4); } if(rd!= 0){ @@ -2515,12 +2567,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nCSRRC_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("CSRRC_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 44); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2529,8 +2583,7 @@ private: auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1); if(rs1!= 0){ - gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, - xrd, gen_operation(jh, bnot, xrs1)) + gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, xrd, gen_operation(jh, bnot, xrs1)) , 4); } if(rd!= 0){ @@ -2567,12 +2620,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nCSRRWI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("CSRRWI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 45); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2614,12 +2669,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nCSRRSI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("CSRRSI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 46); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2627,8 +2684,7 @@ private: else{ auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); if(zimm!= 0){ - gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, - xrd, (uint32_t)zimm) + gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, xrd, (uint32_t)zimm) , 4); } if(rd!= 0){ @@ -2665,12 +2721,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nCSRRCI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("CSRRCI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 47); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2678,8 +2736,7 @@ private: else{ auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); if(zimm!= 0){ - gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, - xrd, ~ ((uint32_t)zimm)) + gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, xrd, ~ ((uint32_t)zimm)) , 4); } if(rd!= 0){ @@ -2716,12 +2773,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nFENCE_I_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("FENCE_I_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 48); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ gen_write_mem(jh, traits::FENCE, static_cast(traits::fencei), imm, 4); auto returnValue = CONT; @@ -2753,24 +2812,25 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nMUL_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("MUL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 49); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto res = gen_ext(jh, - (gen_operation(jh, imul, - gen_ext(jh, gen_ext(jh, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), 128, true), gen_ext(jh, gen_ext(jh, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true), 128, true)) + (gen_operation(jh, imul, gen_ext(jh, + gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh, + gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true)) ), 64, true); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), @@ -2807,30 +2867,30 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nMULH_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("MULH_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 50); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto res = gen_ext(jh, - (gen_operation(jh, imul, - gen_ext(jh, gen_ext(jh, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), 128, true), gen_ext(jh, gen_ext(jh, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true), 128, true)) + (gen_operation(jh, imul, gen_ext(jh, + gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh, + gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true)) ), 64, true); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_operation(jh, sar, - res, gen_ext(jh, static_cast(traits::XLEN), 64, false)) + (gen_operation(jh, sar, res, static_cast(traits::XLEN)) ), 32, true)); } } @@ -2863,29 +2923,29 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nMULHSU_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("MULHSU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 51); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto res = gen_ext(jh, - (gen_operation(jh, imul, - gen_ext(jh, gen_ext(jh, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), 128, true), gen_ext(jh, gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs2), 64, false), 128, false)) + (gen_operation(jh, imul, gen_ext(jh, + gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs2), 64, false)) ), 64, true); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_operation(jh, sar, - res, gen_ext(jh, static_cast(traits::XLEN), 64, false)) + (gen_operation(jh, sar, res, static_cast(traits::XLEN)) ), 32, true)); } } @@ -2918,28 +2978,28 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nMULHU_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("MULHU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 52); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto res = gen_ext(jh, - (gen_operation(jh, mul, - gen_ext(jh, gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 64, false), 128, false), gen_ext(jh, gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs2), 64, false), 128, false)) + (gen_operation(jh, mul, gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs2), 64, false)) ), 64, false); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_operation(jh, shr, - res, gen_ext(jh, static_cast(traits::XLEN), 64, false)) + (gen_operation(jh, shr, res, static_cast(traits::XLEN)) ), 32, false)); } } @@ -2972,12 +3032,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nDIV_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("DIV_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 53); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -2989,20 +3051,16 @@ private: load_reg_from_mem(jh, traits::X0 + rs2), 32, false); if(rd!= 0){ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ne, - divisor, gen_ext(jh, 0, 32, false)) + cc.cmp(gen_operation(jh, ne, divisor, 0) ,0); auto label_else = cc.newLabel(); cc.je(label_else); { auto MMIN = ((uint32_t)1)<<(static_cast(traits::XLEN)-1); auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, land, - gen_operation(jh, eq, - load_reg_from_mem(jh, traits::X0 + rs1), MMIN) - , gen_operation(jh, eq, - divisor, gen_ext(jh, - 1, 32, true)) - ) + cc.cmp(gen_operation(jh, land, gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN) + , gen_operation(jh, eq, divisor, - 1) + ) ,0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -3015,8 +3073,7 @@ private: { cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_operation(jh, idiv, - gen_ext(jh, dividend, 64, true), gen_ext(jh, divisor, 64, true)) + (gen_operation(jh, idiv, dividend, divisor) ), 32, true)); } cc.bind(label_merge); @@ -3059,20 +3116,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nDIVU_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("DIVU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 54); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ne, - load_reg_from_mem(jh, traits::X0 + rs2), gen_ext(jh, 0, 32, false)) + cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0) ,0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -3080,8 +3138,7 @@ private: if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_operation(jh, div, - load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + (gen_operation(jh, div, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ), 32, false)); } } @@ -3124,33 +3181,31 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nREM_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("REM_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 55); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ne, - load_reg_from_mem(jh, traits::X0 + rs2), gen_ext(jh, 0, 32, false)) + cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0) ,0); auto label_else = cc.newLabel(); cc.je(label_else); { auto MMIN = (uint32_t)1<<(static_cast(traits::XLEN)-1); auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, land, - gen_operation(jh, eq, - load_reg_from_mem(jh, traits::X0 + rs1), MMIN) - , gen_operation(jh, eq, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs2), 32, false), gen_ext(jh, - 1, 32, true)) - ) + cc.cmp(gen_operation(jh, land, gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN) + , gen_operation(jh, eq, gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs2), 32, false), - 1) + ) ,0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -3167,10 +3222,9 @@ private: if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_operation(jh, srem, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs2), 32, false)) + (gen_operation(jh, srem, gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs2), 32, false)) ), 32, true)); } } @@ -3215,28 +3269,28 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nREMU_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("REMU_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 56); - pc=pc+ 4; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+4; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ne, - load_reg_from_mem(jh, traits::X0 + rs2), gen_ext(jh, 0, 32, false)) + cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0) ,0); auto label_else = cc.newLabel(); cc.je(label_else); { if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_operation(jh, urem, - load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) + gen_operation(jh, urem, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ); } } @@ -3278,18 +3332,19 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__ADDI4SPN_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__ADDI4SPN_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 57); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(imm){ cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, imm, 64, false)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), imm) ), 32, false)); } else{ @@ -3324,16 +3379,17 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__LW_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__LW_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 58); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ auto offs = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1+ 8), 64, false), gen_ext(jh, uimm, 64, false)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1+ 8), uimm) ), 32, false); cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), gen_ext(jh, @@ -3368,16 +3424,17 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__SW_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__SW_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 59); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ auto offs = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1+ 8), 64, false), gen_ext(jh, uimm, 64, false)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1+ 8), uimm) ), 32, false); gen_write_mem(jh, traits::MEM, offs, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2+ 8), 32, false), 4); @@ -3409,12 +3466,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__ADDI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__ADDI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 60); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -3423,8 +3482,7 @@ private: if(rs1!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rs1), gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int8_t)sext<6>(imm), 64, true)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int8_t)sext<6>(imm)) ), 32, true)); } } @@ -3454,12 +3512,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__NOP_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__NOP_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 61); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ auto returnValue = CONT; @@ -3488,12 +3548,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__JAL_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__JAL_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 62); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ 1), (uint32_t)(PC+ 2)); @@ -3528,12 +3590,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__LI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__LI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 63); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -3572,12 +3636,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__LUI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__LUI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 64); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(imm== 0||rd>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -3613,18 +3679,19 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__ADDI16SP_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__ADDI16SP_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 65); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(nzimm){ cc.mov(get_ptr_for(jh, traits::X0+ 2), gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, (int16_t)sext<10>(nzimm), 64, true)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), (int16_t)sext<10>(nzimm)) ), 32, true)); } else{ @@ -3656,12 +3723,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\n__reserved_clui_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("__reserved_clui_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 66); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ gen_raise(jh, 0, 2); auto returnValue = CONT; @@ -3692,16 +3761,17 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__SRLI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__SRLI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 67); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), - gen_operation(jh, shr, - load_reg_from_mem(jh, traits::X0 + rs1+ 8), gen_ext(jh, shamt, 32, false)) + gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1+ 8), shamt) ); auto returnValue = CONT; @@ -3731,28 +3801,28 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__SRAI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__SRAI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 68); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(shamt){ cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), gen_ext(jh, - (gen_operation(jh, sar, - (gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1+ 8), 32, false)), gen_ext(jh, shamt, 32, false)) + (gen_operation(jh, sar, (gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1+ 8), 32, false)), shamt) ), 32, true)); } else{ if(static_cast(traits::XLEN)== 128){ cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), gen_ext(jh, - (gen_operation(jh, sar, - (gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1+ 8), 32, false)), gen_ext(jh, 64, 32, false)) + (gen_operation(jh, sar, (gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1+ 8), 32, false)), 64) ), 32, true)); } } @@ -3784,17 +3854,18 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__ANDI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__ANDI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 69); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), gen_ext(jh, - (gen_operation(jh, band, - load_reg_from_mem(jh, traits::X0 + rs1+ 8), gen_ext(jh, (int8_t)sext<6>(imm), 32, true)) + (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1+ 8), (int8_t)sext<6>(imm)) ), 32, true)); auto returnValue = CONT; @@ -3824,17 +3895,18 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__SUB_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__SUB_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 70); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), gen_ext(jh, - (gen_operation(jh, sub, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rd+ 8), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2+ 8), 64, false)) + (gen_operation(jh, sub, load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) ), 32, true)); auto returnValue = CONT; @@ -3864,16 +3936,17 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__XOR_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__XOR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 71); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), - gen_operation(jh, bxor, - load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) + gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) ); auto returnValue = CONT; @@ -3903,16 +3976,17 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__OR_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__OR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 72); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), - gen_operation(jh, bor, - load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) + gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) ); auto returnValue = CONT; @@ -3942,16 +4016,17 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__AND_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__AND_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 73); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), - gen_operation(jh, band, - load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) + gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) ); auto returnValue = CONT; @@ -3980,12 +4055,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__J_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__J_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 74); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); cc.mov(jh.next_pc, PC_val_v); @@ -4018,16 +4095,17 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__BEQZ_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__BEQZ_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 75); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, eq, - load_reg_from_mem(jh, traits::X0 + rs1+ 8), gen_ext(jh, 0, 32, false)) + cc.cmp(gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1+ 8), 0) ,0); cc.je(label_merge); { @@ -4064,16 +4142,17 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__BNEZ_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__BNEZ_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 76); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ne, - load_reg_from_mem(jh, traits::X0 + rs1+ 8), gen_ext(jh, 0, 32, false)) + cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs1+ 8), 0) ,0); cc.je(label_merge); { @@ -4110,12 +4189,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__SLLI_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__SLLI_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 77); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -4123,8 +4204,7 @@ private: else{ if(rs1!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rs1), - gen_operation(jh, shl, - load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, nzuimm, 32, false)) + gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), nzuimm) ); } } @@ -4156,20 +4236,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__LWSP_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__LWSP_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 78); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rd== 0){ gen_raise(jh, 0, 2); } else{ auto offs = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, uimm, 64, false)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), uimm) ), 32, false); cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, @@ -4204,12 +4285,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__MV_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__MV_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 79); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -4247,16 +4330,17 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__JR_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__JR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 80); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs1&&rs1(traits::RFS)){ - auto PC_val_v = gen_operation(jh, band, - load_reg_from_mem(jh, traits::X0 + rs1%static_cast(traits::RFS)), gen_ext(jh, ~ 0x1, 32, false)) + auto PC_val_v = gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1%static_cast(traits::RFS)), ~ 0x1) ; cc.mov(jh.next_pc, PC_val_v); cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); @@ -4289,12 +4373,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\n__reserved_cmv_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("__reserved_cmv_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 81); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ gen_raise(jh, 0, 2); auto returnValue = CONT; @@ -4325,12 +4411,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__ADD_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__ADD_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 82); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -4339,8 +4427,7 @@ private: if(rd!= 0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rd), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rd), load_reg_from_mem(jh, traits::X0 + rs2)) ), 32, false)); } } @@ -4371,12 +4458,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__JALR_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__JALR_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 83); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs1>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); @@ -4385,8 +4474,7 @@ private: auto new_pc = load_reg_from_mem(jh, traits::X0 + rs1); cc.mov(get_ptr_for(jh, traits::X0+ 1), (uint32_t)(PC+ 2)); - auto PC_val_v = gen_operation(jh, band, - new_pc, gen_ext(jh, ~ 0x1, 32, false)) + auto PC_val_v = gen_operation(jh, band, new_pc, ~ 0x1) ; cc.mov(jh.next_pc, PC_val_v); cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); @@ -4416,12 +4504,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__EBREAK_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__EBREAK_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 84); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ gen_raise(jh, 0, 3); auto returnValue = CONT; @@ -4452,20 +4542,21 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nC__SWSP_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("C__SWSP_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 85); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)){ gen_raise(jh, 0, 2); } else{ auto offs = gen_ext(jh, - (gen_operation(jh, add, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, uimm, 64, false)) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), uimm) ), 32, false); gen_write_mem(jh, traits::MEM, offs, gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, false), 4); @@ -4495,12 +4586,14 @@ private: } x86::Compiler& cc = jh.cc; - cc.comment(fmt::format("\nDII_{:#x}:",pc.val).c_str()); + cc.comment(fmt::format("DII_{:#x}:",pc.val).c_str()); this->gen_sync(jh, PRE_SYNC, 86); - pc=pc+ 2; - - gen_instr_prologue(jh, pc.val); - cc.comment("\n//behavior:"); + cc.mov(jh.pc, pc.val); + pc = pc+2; + cc.mov(jh.next_pc, pc.val); + + gen_instr_prologue(jh); + cc.comment("//behavior:"); /*generate behavior*/ gen_raise(jh, 0, 2); auto returnValue = CONT; @@ -4603,36 +4696,30 @@ continuation_e vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned return (this->*f)(pc, instr, jh); } template -void vm_impl::gen_instr_prologue(jit_holder& jh, addr_t pc) { +void vm_impl::gen_instr_prologue(jit_holder& jh) { auto& cc = jh.cc; - cc.mov(jh.pc, pc); - cc.comment("\n//(*icount)++;"); + cc.comment("//(*icount)++;"); cc.inc(get_ptr_for(jh, traits::ICOUNT)); - cc.comment("\n//*pc=*next_pc;"); - cc.mov(get_ptr_for(jh, traits::PC), jh.next_pc); - - cc.comment("\n//*trap_state=*pending_trap;"); + cc.comment("//*trap_state=*pending_trap;"); x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); cc.mov(get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state); - cc.comment("\n//increment *next_pc"); - cc.mov(jh.next_pc, pc); } template void vm_impl::gen_instr_epilogue(jit_holder& jh) { auto& cc = jh.cc; - cc.comment("\n//if(*trap_state!=0) goto trap_entry;"); + cc.comment("//if(*trap_state!=0) goto trap_entry;"); x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); cc.cmp(current_trap_state, 0); cc.jne(jh.trap_entry); // TODO: Does not need to be done for every instruction, only when needed (by plugin) - cc.comment("\n//write back regs to mem"); + cc.comment("//write back regs to mem"); write_reg_to_mem(jh, jh.pc, traits::PC); write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); } @@ -4645,13 +4732,13 @@ void vm_impl::gen_block_prologue(jit_holder& jh){ template void vm_impl::gen_block_epilogue(jit_holder& jh){ x86::Compiler& cc = jh.cc; - cc.comment("\n//return *next_pc;"); + cc.comment("//return *next_pc;"); cc.ret(jh.next_pc); cc.bind(jh.trap_entry); - cc.comment("\n//Prepare for enter_trap;"); + cc.comment("//Prepare for enter_trap;"); // Make sure cached values are written back - cc.comment("\n//write back regs to mem"); + cc.comment("//write back regs to mem"); write_reg_to_mem(jh, jh.pc, traits::PC); write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); this->gen_sync(jh, POST_SYNC, -1); @@ -4664,7 +4751,7 @@ void vm_impl::gen_block_epilogue(jit_holder& jh){ x86::Gp instr = cc.newInt32("instr"); cc.mov(instr, 0); // this is not correct - cc.comment("\n//enter trap call;"); + cc.comment("//enter trap call;"); InvokeNode* call_enter_trap; cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT()); call_enter_trap->setArg(0, jh.arch_if_ptr); @@ -4676,9 +4763,9 @@ void vm_impl::gen_block_epilogue(jit_holder& jh){ cc.mov(current_next_pc, get_ptr_for(jh, traits::NEXT_PC)); cc.mov(jh.next_pc, current_next_pc); - cc.comment("\n//*last_branch = std::numeric_limits::max();"); + cc.comment("//*last_branch = std::numeric_limits::max();"); cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), std::numeric_limits::max()); - cc.comment("\n//return *next_pc;"); + cc.comment("//return *next_pc;"); cc.ret(jh.next_pc); } template @@ -4688,13 +4775,9 @@ inline void vm_impl:: gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t auto tmp1 = get_reg_for(jh, traits::TRAP_STATE); cc.mov(tmp1, 0x80ULL << 24 | (cause << 16) | trap_id); cc.mov(get_ptr_for(jh, traits::TRAP_STATE), tmp1); - auto tmp2 = get_reg_for(jh, traits::NEXT_PC); - cc.mov(tmp2, std::numeric_limits::max()); - cc.mov(get_ptr_for(jh, traits::NEXT_PC), tmp2); + cc.mov(jh.next_pc, std::numeric_limits::max()); } - - } // namespace tgc5c template <> From 3422c7cd5ccb4440f0bbc5611deab243d5c174d5 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Wed, 8 May 2024 15:18:38 +0200 Subject: [PATCH 17/33] optimizes writebacks --- gen_input/templates/asmjit/CORENAME.cpp.gtl | 10 +-------- src/vm/asmjit/vm_tgc5c.cpp | 24 +++++++-------------- 2 files changed, 9 insertions(+), 25 deletions(-) diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index cb0a2b5..981950c 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -284,11 +284,6 @@ void vm_impl::gen_instr_epilogue(jit_holder& jh) { cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); cc.cmp(current_trap_state, 0); cc.jne(jh.trap_entry); - - // TODO: Does not need to be done for every instruction, only when needed (by plugin) - cc.comment("//write back regs to mem"); - write_reg_to_mem(jh, jh.pc, traits::PC); - write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); } template void vm_impl::gen_block_prologue(jit_holder& jh){ @@ -304,10 +299,7 @@ void vm_impl::gen_block_epilogue(jit_holder& jh){ cc.bind(jh.trap_entry); cc.comment("//Prepare for enter_trap;"); - // Make sure cached values are written back - cc.comment("//write back regs to mem"); - write_reg_to_mem(jh, jh.pc, traits::PC); - write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); + this->write_back(jh); this->gen_sync(jh, POST_SYNC, -1); x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index 8e4f72b..5073c53 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -2826,12 +2826,12 @@ private: } else{ auto res = gen_ext(jh, - (gen_operation(jh, imul, gen_ext(jh, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh, - gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true)) - ), 64, true); + (gen_operation(jh, imul, + gen_ext(jh, + gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), + gen_ext(jh, + gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true)) + ), 64, true); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, @@ -4717,11 +4717,6 @@ void vm_impl::gen_instr_epilogue(jit_holder& jh) { cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); cc.cmp(current_trap_state, 0); cc.jne(jh.trap_entry); - - // TODO: Does not need to be done for every instruction, only when needed (by plugin) - cc.comment("//write back regs to mem"); - write_reg_to_mem(jh, jh.pc, traits::PC); - write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); } template void vm_impl::gen_block_prologue(jit_holder& jh){ @@ -4737,10 +4732,7 @@ void vm_impl::gen_block_epilogue(jit_holder& jh){ cc.bind(jh.trap_entry); cc.comment("//Prepare for enter_trap;"); - // Make sure cached values are written back - cc.comment("//write back regs to mem"); - write_reg_to_mem(jh, jh.pc, traits::PC); - write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC); + this->write_back(jh); this->gen_sync(jh, POST_SYNC, -1); x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); @@ -4750,7 +4742,7 @@ void vm_impl::gen_block_epilogue(jit_holder& jh){ cc.mov(current_pc, get_ptr_for(jh, traits::PC)); x86::Gp instr = cc.newInt32("instr"); - cc.mov(instr, 0); // this is not correct + cc.mov(instr, 0); // FIXME:this is not correct cc.comment("//enter trap call;"); InvokeNode* call_enter_trap; cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT()); From f0a004be9d875049dfaa6850a7cfa3bb295ce5c8 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Thu, 9 May 2024 13:42:16 +0200 Subject: [PATCH 18/33] adds information for debugging --- src/iss/arch/tgc5c.h | 46 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index cff086d..06d74de 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -76,7 +76,53 @@ template <> struct traits { static constexpr std::array reg_byte_offsets{ {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}}; +/* +For easy lookup: +X0 (zero): 0x0000 +X1 (ra) : 0x0004 +X2 (sp) : 0x0008 +X3 (gp) : 0x000c +X4 (tp) : 0x0010 +X5 (t0) : 0x0014 +X6 (t1) : 0x0018 +X7 (t2) : 0x001c +X8 (s0/fp): 0x0020 +X9 (s1) : 0x0024 +X10 (a0) : 0x0028 +X11 (a1) : 0x002c +X12 (a2) : 0x0030 +X13 (a3) : 0x0034 +X14 (a4) : 0x0038 +X15 (a5) : 0x003c +X16 (a6) : 0x0040 +X17 (a7) : 0x0044 +X18 (s2) : 0x0048 +X19 (s3) : 0x004c +X20 (s4) : 0x0050 +X21 (s5) : 0x0054 +X22 (s6) : 0x0058 +X23 (s7) : 0x005c +X24 (s8) : 0x0060 +X25 (s9) : 0x0064 +X26 (s10) : 0x0068 +X27 (s11) : 0x006c +X28 (t3) : 0x0070 +X29 (t4) : 0x0074 +X30 (t5) : 0x0078 +X31 (t6) : 0x007c +PC : 0x0080 +NEXT_PC : 0x0084 +PRIV : 0x0085 +DPC : 0x0089 +trap_state : 0x008d +pending_trap : 0x0091 +icount : 0x0095 +cycle : 0x009d +instret : 0x00a5 +instruction : 0x00ad +last_branch : 0x00b1 +*/ static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); enum sreg_flag_e { FLAGS }; From 2e27b025cc1a75a4a0ed5a0d911a65c422ecfe23 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Thu, 9 May 2024 13:47:36 +0200 Subject: [PATCH 19/33] improves dump-ir comments --- gen_input/templates/asmjit/CORENAME.cpp.gtl | 12 ++++-------- src/vm/asmjit/vm_tgc5c.cpp | 10 +++------- 2 files changed, 7 insertions(+), 15 deletions(-) diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 981950c..47167ed 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -266,10 +266,9 @@ template void vm_impl::gen_instr_prologue(jit_holder& jh) { auto& cc = jh.cc; - cc.comment("//(*icount)++;"); + cc.comment("//gen_instr_prologue"); cc.inc(get_ptr_for(jh, traits::ICOUNT)); - cc.comment("//*trap_state=*pending_trap;"); x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); cc.mov(get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state); @@ -279,7 +278,7 @@ template void vm_impl::gen_instr_epilogue(jit_holder& jh) { auto& cc = jh.cc; - cc.comment("//if(*trap_state!=0) goto trap_entry;"); + cc.comment("//gen_instr_epilogue"); x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); cc.cmp(current_trap_state, 0); @@ -294,11 +293,10 @@ void vm_impl::gen_block_prologue(jit_holder& jh){ template void vm_impl::gen_block_epilogue(jit_holder& jh){ x86::Compiler& cc = jh.cc; - cc.comment("//return *next_pc;"); + cc.comment("//gen_block_epilogue"); cc.ret(jh.next_pc); cc.bind(jh.trap_entry); - cc.comment("//Prepare for enter_trap;"); this->write_back(jh); this->gen_sync(jh, POST_SYNC, -1); @@ -309,7 +307,7 @@ void vm_impl::gen_block_epilogue(jit_holder& jh){ cc.mov(current_pc, get_ptr_for(jh, traits::PC)); x86::Gp instr = cc.newInt32("instr"); - cc.mov(instr, 0); // this is not correct + cc.mov(instr, 0); // FIXME:this is not correct cc.comment("//enter trap call;"); InvokeNode* call_enter_trap; cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT()); @@ -322,9 +320,7 @@ void vm_impl::gen_block_epilogue(jit_holder& jh){ cc.mov(current_next_pc, get_ptr_for(jh, traits::NEXT_PC)); cc.mov(jh.next_pc, current_next_pc); - cc.comment("//*last_branch = std::numeric_limits::max();"); cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), std::numeric_limits::max()); - cc.comment("//return *next_pc;"); cc.ret(jh.next_pc); } template diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index 5073c53..5b35db0 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -4699,10 +4699,9 @@ template void vm_impl::gen_instr_prologue(jit_holder& jh) { auto& cc = jh.cc; - cc.comment("//(*icount)++;"); + cc.comment("//gen_instr_prologue"); cc.inc(get_ptr_for(jh, traits::ICOUNT)); - cc.comment("//*trap_state=*pending_trap;"); x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); cc.mov(get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state); @@ -4712,7 +4711,7 @@ template void vm_impl::gen_instr_epilogue(jit_holder& jh) { auto& cc = jh.cc; - cc.comment("//if(*trap_state!=0) goto trap_entry;"); + cc.comment("//gen_instr_epilogue"); x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE); cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE)); cc.cmp(current_trap_state, 0); @@ -4727,11 +4726,10 @@ void vm_impl::gen_block_prologue(jit_holder& jh){ template void vm_impl::gen_block_epilogue(jit_holder& jh){ x86::Compiler& cc = jh.cc; - cc.comment("//return *next_pc;"); + cc.comment("//gen_block_epilogue"); cc.ret(jh.next_pc); cc.bind(jh.trap_entry); - cc.comment("//Prepare for enter_trap;"); this->write_back(jh); this->gen_sync(jh, POST_SYNC, -1); @@ -4755,9 +4753,7 @@ void vm_impl::gen_block_epilogue(jit_holder& jh){ cc.mov(current_next_pc, get_ptr_for(jh, traits::NEXT_PC)); cc.mov(jh.next_pc, current_next_pc); - cc.comment("//*last_branch = std::numeric_limits::max();"); cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), std::numeric_limits::max()); - cc.comment("//return *next_pc;"); cc.ret(jh.next_pc); } template From ee6a11dae6ae62c9d7f71cc02c661d7b169c0e0b Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Thu, 9 May 2024 20:54:30 +0200 Subject: [PATCH 20/33] fixes typo --- gen_input/templates/asmjit/CORENAME.cpp.gtl | 2 +- src/vm/asmjit/vm_tgc5c.cpp | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 47167ed..081d9de 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -324,7 +324,7 @@ void vm_impl::gen_block_epilogue(jit_holder& jh){ cc.ret(jh.next_pc); } template -inline void vm_impl:: gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) { +inline void vm_impl::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) { auto& cc = jh.cc; cc.comment("//gen_raise"); auto tmp1 = get_reg_for(jh, traits::TRAP_STATE); diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index 5b35db0..8955a24 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -80,7 +80,7 @@ public: protected: using super::get_ptr_for; -using super::get_reg; + using super::get_reg; using super::get_reg_for; using super::load_reg_from_mem; using super::write_reg_to_mem; @@ -4757,7 +4757,7 @@ void vm_impl::gen_block_epilogue(jit_holder& jh){ cc.ret(jh.next_pc); } template -inline void vm_impl:: gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) { +inline void vm_impl::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) { auto& cc = jh.cc; cc.comment("//gen_raise"); auto tmp1 = get_reg_for(jh, traits::TRAP_STATE); From 001c6349f78fd38c929562c942f30d002df8afb0 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Sat, 11 May 2024 15:16:46 +0200 Subject: [PATCH 21/33] removes tcc sim stop when writing to tohost --- src/iss/arch/riscv_hart_m_p.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 90a7d5f..f6d2222 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -1126,7 +1126,7 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned le this->reg.trap_state = std::numeric_limits::max(); this->interrupt_sim = hostvar; #ifndef WITH_TCC - throw(iss::simulation_stopped(hostvar)); + // throw(iss::simulation_stopped(hostvar)); #endif break; case 0x0101: { From b76c5bf0d65b0d3a93e24d4c71dbf8ed220c6366 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Sat, 11 May 2024 15:25:49 +0200 Subject: [PATCH 22/33] adds flush to fence_i --- src/vm/asmjit/vm_tgc5c.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index 8955a24..ac2681c 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -2783,7 +2783,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ gen_write_mem(jh, traits::FENCE, static_cast(traits::fencei), imm, 4); - auto returnValue = CONT; + auto returnValue = FLUSH; gen_instr_epilogue(jh); this->gen_sync(jh, POST_SYNC, 48); From fb330cddea6d780b50d0af02db92d88e45e0a137 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Sat, 18 May 2024 19:33:57 +0200 Subject: [PATCH 23/33] llvm passes act --- gen_input/templates/llvm/CORENAME.cpp.gtl | 35 +- src/vm/llvm/vm_tgc5c.cpp | 744 +++++++++++++--------- 2 files changed, 479 insertions(+), 300 deletions(-) diff --git a/gen_input/templates/llvm/CORENAME.cpp.gtl b/gen_input/templates/llvm/CORENAME.cpp.gtl index b6bef39..1b13101 100644 --- a/gen_input/templates/llvm/CORENAME.cpp.gtl +++ b/gen_input/templates/llvm/CORENAME.cpp.gtl @@ -99,16 +99,11 @@ protected: std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override; void gen_leave_behavior(BasicBlock *leave_blk) override; - void gen_raise_trap(uint16_t trap_id, uint16_t cause); - void gen_leave_trap(unsigned lvl); - void gen_wait(unsigned type); - void gen_trap_behavior(BasicBlock *) override; - - void gen_trap_check(BasicBlock *bb); + void gen_instr_epilogue(BasicBlock *bb); inline Value *gen_reg_load(unsigned i, unsigned level = 0) { return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false); @@ -162,20 +157,22 @@ private: /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %> /* instruction ${idx}: ${instr.name} */ std::tuple __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,${idx}); uint64_t PC = pc.val; <%instr.fields.eachLine{%>${it} <%}%>if(this->disass_enabled){ /* generate console output when executing the command */<%instr.disass.eachLine{%> ${it}<%}%> } + bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,${idx}); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ ${instr.length/8}; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ <%instr.behavior.eachLine{%>${it} <%}%> - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, ${idx}); this->builder.CreateBr(bb); return returnValue; @@ -195,7 +192,7 @@ private: pc = pc + ((instr & 3) == 3 ? 4 : 2); this->gen_raise_trap(0, 2); // illegal instruction trap this->gen_sync(iss::POST_SYNC, instr_descr.size()); - this->gen_trap_check(this->leave_blk); + this->gen_instr_epilogue(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } //decoding functionality @@ -301,18 +298,21 @@ vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, return (this->*f)(pc, instr, this_block); } -template void vm_impl::gen_leave_behavior(BasicBlock *leave_blk) { +template +void vm_impl::gen_leave_behavior(BasicBlock *leave_blk) { this->builder.SetInsertPoint(leave_blk); this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false)); } -template void vm_impl::gen_raise_trap(uint16_t trap_id, uint16_t cause) { +template +void vm_impl::gen_raise_trap(uint16_t trap_id, uint16_t cause) { auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id); this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } -template void vm_impl::gen_leave_trap(unsigned lvl) { +template +void vm_impl::gen_leave_trap(unsigned lvl) { std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) }; this->builder.CreateCall(this->mod->getFunction("leave_trap"), args); auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8); @@ -320,12 +320,14 @@ template void vm_impl::gen_leave_trap(unsigned lvl) { this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } -template void vm_impl::gen_wait(unsigned type) { +template +void vm_impl::gen_wait(unsigned type) { std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) }; this->builder.CreateCall(this->mod->getFunction("wait"), args); } -template void vm_impl::gen_trap_behavior(BasicBlock *trap_blk) { +template +void vm_impl::gen_trap_behavior(BasicBlock *trap_blk) { this->builder.SetInsertPoint(trap_blk); this->gen_sync(POST_SYNC, -1); //TODO get right InstrId auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); @@ -338,7 +340,8 @@ template void vm_impl::gen_trap_behavior(BasicBlock *trap_ this->builder.CreateRet(trap_addr_val); } -template inline void vm_impl::gen_trap_check(BasicBlock *bb) { +template +void vm_impl::gen_instr_epilogue(BasicBlock *bb) { auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb); auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); this->gen_cond_branch(this->builder.CreateICmp( diff --git a/src/vm/llvm/vm_tgc5c.cpp b/src/vm/llvm/vm_tgc5c.cpp index fe03630..58e3c2c 100644 --- a/src/vm/llvm/vm_tgc5c.cpp +++ b/src/vm/llvm/vm_tgc5c.cpp @@ -99,16 +99,11 @@ protected: std::tuple gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override; void gen_leave_behavior(BasicBlock *leave_blk) override; - void gen_raise_trap(uint16_t trap_id, uint16_t cause); - void gen_leave_trap(unsigned lvl); - void gen_wait(unsigned type); - void gen_trap_behavior(BasicBlock *) override; - - void gen_trap_check(BasicBlock *bb); + void gen_instr_epilogue(BasicBlock *bb); inline Value *gen_reg_load(unsigned i, unsigned level = 0) { return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false); @@ -334,8 +329,6 @@ private: /* instruction definitions */ /* instruction 0: LUI */ std::tuple __lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("LUI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,0); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint32_t imm = ((bit_sub<12,20>(instr) << 12)); @@ -351,9 +344,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("LUI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,0); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -367,7 +364,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 0); this->builder.CreateBr(bb); return returnValue; @@ -375,8 +372,6 @@ private: /* instruction 1: AUIPC */ std::tuple __auipc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("AUIPC_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,1); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint32_t imm = ((bit_sub<12,20>(instr) << 12)); @@ -392,9 +387,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("AUIPC_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,1); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -408,7 +407,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 1); this->builder.CreateBr(bb); return returnValue; @@ -416,8 +415,6 @@ private: /* instruction 2: JAL */ std::tuple __jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("JAL_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,2); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); @@ -433,9 +430,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("JAL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,2); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -456,7 +457,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 2); this->builder.CreateBr(bb); return returnValue; @@ -464,8 +465,6 @@ private: /* instruction 3: JALR */ std::tuple __jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("JALR_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,3); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -482,9 +481,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("JALR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,3); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -528,7 +531,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 3); this->builder.CreateBr(bb); return returnValue; @@ -536,8 +539,6 @@ private: /* instruction 4: BEQ */ std::tuple __beq(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("BEQ_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,4); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -554,9 +555,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("BEQ_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,4); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -583,7 +588,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 4); this->builder.CreateBr(bb); return returnValue; @@ -591,8 +596,6 @@ private: /* instruction 5: BNE */ std::tuple __bne(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("BNE_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,5); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -609,9 +612,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("BNE_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,5); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -638,7 +645,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 5); this->builder.CreateBr(bb); return returnValue; @@ -646,8 +653,6 @@ private: /* instruction 6: BLT */ std::tuple __blt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("BLT_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,6); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -664,9 +669,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("BLT_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,6); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -697,7 +706,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 6); this->builder.CreateBr(bb); return returnValue; @@ -705,8 +714,6 @@ private: /* instruction 7: BGE */ std::tuple __bge(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("BGE_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,7); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -723,9 +730,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("BGE_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,7); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -756,7 +767,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 7); this->builder.CreateBr(bb); return returnValue; @@ -764,8 +775,6 @@ private: /* instruction 8: BLTU */ std::tuple __bltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("BLTU_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,8); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -782,9 +791,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("BLTU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,8); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -811,7 +824,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 8); this->builder.CreateBr(bb); return returnValue; @@ -819,8 +832,6 @@ private: /* instruction 9: BGEU */ std::tuple __bgeu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("BGEU_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,9); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -837,9 +848,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("BGEU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,9); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -866,7 +881,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 9); this->builder.CreateBr(bb); return returnValue; @@ -874,8 +889,6 @@ private: /* instruction 10: LB */ std::tuple __lb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("LB_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,10); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -892,9 +905,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("LB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,10); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -919,7 +936,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 10); this->builder.CreateBr(bb); return returnValue; @@ -927,8 +944,6 @@ private: /* instruction 11: LH */ std::tuple __lh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("LH_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,11); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -945,9 +960,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("LH_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,11); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -972,7 +991,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 11); this->builder.CreateBr(bb); return returnValue; @@ -980,8 +999,6 @@ private: /* instruction 12: LW */ std::tuple __lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("LW_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,12); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -998,9 +1015,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("LW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,12); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1025,7 +1046,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 12); this->builder.CreateBr(bb); return returnValue; @@ -1033,8 +1054,6 @@ private: /* instruction 13: LBU */ std::tuple __lbu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("LBU_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,13); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1051,9 +1070,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("LBU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,13); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1076,7 +1099,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 13); this->builder.CreateBr(bb); return returnValue; @@ -1084,8 +1107,6 @@ private: /* instruction 14: LHU */ std::tuple __lhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("LHU_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,14); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1102,9 +1123,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("LHU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,14); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1127,7 +1152,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 14); this->builder.CreateBr(bb); return returnValue; @@ -1135,8 +1160,6 @@ private: /* instruction 15: SB */ std::tuple __sb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SB_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,15); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1153,9 +1176,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,15); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1175,7 +1202,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 15); this->builder.CreateBr(bb); return returnValue; @@ -1183,8 +1210,6 @@ private: /* instruction 16: SH */ std::tuple __sh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SH_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,16); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1201,9 +1226,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SH_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,16); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1223,7 +1252,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 16); this->builder.CreateBr(bb); return returnValue; @@ -1231,8 +1260,6 @@ private: /* instruction 17: SW */ std::tuple __sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SW_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,17); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1249,9 +1276,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,17); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1271,7 +1302,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 17); this->builder.CreateBr(bb); return returnValue; @@ -1279,8 +1310,6 @@ private: /* instruction 18: ADDI */ std::tuple __addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("ADDI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,18); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1297,9 +1326,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("ADDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,18); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1318,7 +1351,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 18); this->builder.CreateBr(bb); return returnValue; @@ -1326,8 +1359,6 @@ private: /* instruction 19: SLTI */ std::tuple __slti(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SLTI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,19); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1344,9 +1375,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SLTI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,19); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1367,7 +1402,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 19); this->builder.CreateBr(bb); return returnValue; @@ -1375,8 +1410,6 @@ private: /* instruction 20: SLTIU */ std::tuple __sltiu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SLTIU_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,20); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1393,9 +1426,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SLTIU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,20); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1415,7 +1452,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 20); this->builder.CreateBr(bb); return returnValue; @@ -1423,8 +1460,6 @@ private: /* instruction 21: XORI */ std::tuple __xori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("XORI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,21); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1441,9 +1476,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("XORI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,21); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1460,7 +1499,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 21); this->builder.CreateBr(bb); return returnValue; @@ -1468,8 +1507,6 @@ private: /* instruction 22: ORI */ std::tuple __ori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("ORI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,22); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1486,9 +1523,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("ORI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,22); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1505,7 +1546,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 22); this->builder.CreateBr(bb); return returnValue; @@ -1513,8 +1554,6 @@ private: /* instruction 23: ANDI */ std::tuple __andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("ANDI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,23); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1531,9 +1570,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("ANDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,23); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1550,7 +1593,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 23); this->builder.CreateBr(bb); return returnValue; @@ -1558,8 +1601,6 @@ private: /* instruction 24: SLLI */ std::tuple __slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SLLI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,24); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1576,9 +1617,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SLLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,24); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1595,7 +1640,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 24); this->builder.CreateBr(bb); return returnValue; @@ -1603,8 +1648,6 @@ private: /* instruction 25: SRLI */ std::tuple __srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SRLI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,25); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1621,9 +1664,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SRLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,25); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1640,7 +1687,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 25); this->builder.CreateBr(bb); return returnValue; @@ -1648,8 +1695,6 @@ private: /* instruction 26: SRAI */ std::tuple __srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SRAI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,26); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1666,9 +1711,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SRAI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,26); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1688,7 +1737,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 26); this->builder.CreateBr(bb); return returnValue; @@ -1696,8 +1745,6 @@ private: /* instruction 27: ADD */ std::tuple __add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("ADD_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,27); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1714,9 +1761,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("ADD_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,27); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1735,7 +1786,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 27); this->builder.CreateBr(bb); return returnValue; @@ -1743,8 +1794,6 @@ private: /* instruction 28: SUB */ std::tuple __sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SUB_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,28); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1761,9 +1810,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SUB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,28); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1782,7 +1835,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 28); this->builder.CreateBr(bb); return returnValue; @@ -1790,8 +1843,6 @@ private: /* instruction 29: SLL */ std::tuple __sll(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SLL_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,29); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1808,9 +1859,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SLL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,29); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1830,7 +1885,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 29); this->builder.CreateBr(bb); return returnValue; @@ -1838,8 +1893,6 @@ private: /* instruction 30: SLT */ std::tuple __slt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SLT_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,30); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1856,9 +1909,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SLT_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,30); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1880,7 +1937,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 30); this->builder.CreateBr(bb); return returnValue; @@ -1888,8 +1945,6 @@ private: /* instruction 31: SLTU */ std::tuple __sltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SLTU_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,31); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1906,9 +1961,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SLTU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,31); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1928,7 +1987,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 31); this->builder.CreateBr(bb); return returnValue; @@ -1936,8 +1995,6 @@ private: /* instruction 32: XOR */ std::tuple __xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("XOR_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,32); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1954,9 +2011,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("XOR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,32); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -1973,7 +2034,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 32); this->builder.CreateBr(bb); return returnValue; @@ -1981,8 +2042,6 @@ private: /* instruction 33: SRL */ std::tuple __srl(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SRL_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,33); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -1999,9 +2058,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SRL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,33); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2021,7 +2084,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 33); this->builder.CreateBr(bb); return returnValue; @@ -2029,8 +2092,6 @@ private: /* instruction 34: SRA */ std::tuple __sra(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("SRA_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,34); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2047,9 +2108,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("SRA_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,34); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2072,7 +2137,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 34); this->builder.CreateBr(bb); return returnValue; @@ -2080,8 +2145,6 @@ private: /* instruction 35: OR */ std::tuple __or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("OR_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,35); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2098,9 +2161,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("OR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,35); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2117,7 +2184,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 35); this->builder.CreateBr(bb); return returnValue; @@ -2125,8 +2192,6 @@ private: /* instruction 36: AND */ std::tuple __and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("AND_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,36); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2143,9 +2208,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("AND_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,36); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2162,7 +2231,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 36); this->builder.CreateBr(bb); return returnValue; @@ -2170,8 +2239,6 @@ private: /* instruction 37: FENCE */ std::tuple __fence(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("FENCE_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,37); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2190,16 +2257,20 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("FENCE_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,37); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->gen_write_mem(traits::FENCE, static_cast(traits::fence), this->gen_const(8,(uint8_t)pred<< 4|succ)); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 37); this->builder.CreateBr(bb); return returnValue; @@ -2207,21 +2278,23 @@ private: /* instruction 38: ECALL */ std::tuple __ecall(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("ECALL_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,38); uint64_t PC = pc.val; if(this->disass_enabled){ /* generate console output when executing the command */ //This disass is not yet implemented } + bb->setName(fmt::format("ECALL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,38); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->gen_raise_trap(0, 11); bb = this->leave_blk; auto returnValue = std::make_tuple(TRAP,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 38); this->builder.CreateBr(bb); return returnValue; @@ -2229,21 +2302,23 @@ private: /* instruction 39: EBREAK */ std::tuple __ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("EBREAK_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,39); uint64_t PC = pc.val; if(this->disass_enabled){ /* generate console output when executing the command */ //This disass is not yet implemented } + bb->setName(fmt::format("EBREAK_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,39); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->gen_raise_trap(0, 3); bb = this->leave_blk; auto returnValue = std::make_tuple(TRAP,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 39); this->builder.CreateBr(bb); return returnValue; @@ -2251,21 +2326,23 @@ private: /* instruction 40: MRET */ std::tuple __mret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("MRET_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,40); uint64_t PC = pc.val; if(this->disass_enabled){ /* generate console output when executing the command */ //This disass is not yet implemented } + bb->setName(fmt::format("MRET_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,40); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->gen_leave_trap(3); bb = this->leave_blk; auto returnValue = std::make_tuple(TRAP,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 40); this->builder.CreateBr(bb); return returnValue; @@ -2273,21 +2350,23 @@ private: /* instruction 41: WFI */ std::tuple __wfi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("WFI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,41); uint64_t PC = pc.val; if(this->disass_enabled){ /* generate console output when executing the command */ //This disass is not yet implemented } + bb->setName(fmt::format("WFI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,41); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->gen_wait(1); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 41); this->builder.CreateBr(bb); return returnValue; @@ -2295,8 +2374,6 @@ private: /* instruction 42: CSRRW */ std::tuple __csrrw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("CSRRW_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,42); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2313,9 +2390,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("CSRRW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,42); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2338,7 +2419,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 42); this->builder.CreateBr(bb); return returnValue; @@ -2346,8 +2427,6 @@ private: /* instruction 43: CSRRS */ std::tuple __csrrs(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("CSRRS_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,43); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2364,9 +2443,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("CSRRS_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,43); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2390,7 +2473,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 43); this->builder.CreateBr(bb); return returnValue; @@ -2398,8 +2481,6 @@ private: /* instruction 44: CSRRC */ std::tuple __csrrc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("CSRRC_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,44); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2416,9 +2497,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("CSRRC_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,44); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2442,7 +2527,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 44); this->builder.CreateBr(bb); return returnValue; @@ -2450,8 +2535,6 @@ private: /* instruction 45: CSRRWI */ std::tuple __csrrwi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("CSRRWI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,45); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); @@ -2468,9 +2551,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("CSRRWI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,45); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2488,7 +2575,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 45); this->builder.CreateBr(bb); return returnValue; @@ -2496,8 +2583,6 @@ private: /* instruction 46: CSRRSI */ std::tuple __csrrsi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("CSRRSI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,46); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); @@ -2514,9 +2599,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("CSRRSI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,46); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2539,7 +2628,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 46); this->builder.CreateBr(bb); return returnValue; @@ -2547,8 +2636,6 @@ private: /* instruction 47: CSRRCI */ std::tuple __csrrci(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("CSRRCI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,47); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t zimm = ((bit_sub<15,5>(instr))); @@ -2565,9 +2652,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("CSRRCI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,47); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2590,7 +2681,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 47); this->builder.CreateBr(bb); return returnValue; @@ -2598,8 +2689,6 @@ private: /* instruction 48: FENCE_I */ std::tuple __fence_i(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("FENCE_I_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,48); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2616,16 +2705,20 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("FENCE_I_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,48); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->gen_write_mem(traits::FENCE, static_cast(traits::fencei), this->gen_const(16,imm)); - bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); - auto returnValue = std::make_tuple(CONT,bb); + bb = this->leave_blk; + auto returnValue = std::make_tuple(FLUSH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 48); this->builder.CreateBr(bb); return returnValue; @@ -2633,8 +2726,6 @@ private: /* instruction 49: MUL */ std::tuple __mul(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("MUL_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,49); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2651,9 +2742,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("MUL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,49); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2681,7 +2776,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 49); this->builder.CreateBr(bb); return returnValue; @@ -2689,8 +2784,6 @@ private: /* instruction 50: MULH */ std::tuple __mulh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("MULH_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,50); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2707,9 +2800,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("MULH_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,50); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2740,7 +2837,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 50); this->builder.CreateBr(bb); return returnValue; @@ -2748,8 +2845,6 @@ private: /* instruction 51: MULHSU */ std::tuple __mulhsu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("MULHSU_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,51); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2766,9 +2861,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("MULHSU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,51); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2798,7 +2897,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 51); this->builder.CreateBr(bb); return returnValue; @@ -2806,8 +2905,6 @@ private: /* instruction 52: MULHU */ std::tuple __mulhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("MULHU_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,52); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2824,9 +2921,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("MULHU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,52); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2855,7 +2956,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 52); this->builder.CreateBr(bb); return returnValue; @@ -2863,8 +2964,6 @@ private: /* instruction 53: DIV */ std::tuple __div(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("DIV_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,53); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2881,9 +2980,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("DIV_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,53); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -2952,7 +3055,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 53); this->builder.CreateBr(bb); return returnValue; @@ -2960,8 +3063,6 @@ private: /* instruction 54: DIVU */ std::tuple __divu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("DIVU_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,54); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -2978,9 +3079,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("DIVU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,54); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -3020,7 +3125,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 54); this->builder.CreateBr(bb); return returnValue; @@ -3028,8 +3133,6 @@ private: /* instruction 55: REM */ std::tuple __rem(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("REM_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,55); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -3046,9 +3149,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("REM_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,55); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -3122,7 +3229,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 55); this->builder.CreateBr(bb); return returnValue; @@ -3130,8 +3237,6 @@ private: /* instruction 56: REMU */ std::tuple __remu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("REMU_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,56); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -3148,9 +3253,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("REMU_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,56); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 4; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -3188,7 +3297,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 56); this->builder.CreateBr(bb); return returnValue; @@ -3196,8 +3305,6 @@ private: /* instruction 57: C__ADDI4SPN */ std::tuple __c__addi4spn(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__ADDI4SPN_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,57); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<2,3>(instr))); uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); @@ -3213,9 +3320,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__ADDI4SPN_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,57); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(imm) { this->builder.CreateStore( this->gen_ext( @@ -3232,7 +3343,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 57); this->builder.CreateBr(bb); return returnValue; @@ -3240,8 +3351,6 @@ private: /* instruction 58: C__LW */ std::tuple __c__lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__LW_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,58); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); @@ -3258,9 +3367,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__LW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,58); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ auto offs =this->gen_ext( (this->builder.CreateAdd( this->gen_ext(this->gen_reg_load(rs1+ 8+ traits::X0, 0), 64,false), @@ -3277,7 +3390,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 58); this->builder.CreateBr(bb); return returnValue; @@ -3285,8 +3398,6 @@ private: /* instruction 59: C__SW */ std::tuple __c__sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__SW_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,59); uint64_t PC = pc.val; uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); @@ -3303,9 +3414,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__SW_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,59); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ auto offs =this->gen_ext( (this->builder.CreateAdd( this->gen_ext(this->gen_reg_load(rs1+ 8+ traits::X0, 0), 64,false), @@ -3320,7 +3435,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 59); this->builder.CreateBr(bb); return returnValue; @@ -3328,8 +3443,6 @@ private: /* instruction 60: C__ADDI */ std::tuple __c__addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__ADDI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,60); uint64_t PC = pc.val; uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,5>(instr))); @@ -3345,9 +3458,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__ADDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,60); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -3366,7 +3483,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 60); this->builder.CreateBr(bb); return returnValue; @@ -3374,21 +3491,23 @@ private: /* instruction 61: C__NOP */ std::tuple __c__nop(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__NOP_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,61); uint64_t PC = pc.val; uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); if(this->disass_enabled){ /* generate console output when executing the command */ //This disass is not yet implemented } + bb->setName(fmt::format("C__NOP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,61); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 61); this->builder.CreateBr(bb); return returnValue; @@ -3396,8 +3515,6 @@ private: /* instruction 62: C__JAL */ std::tuple __c__jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__JAL_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,62); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ @@ -3412,9 +3529,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__JAL_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,62); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->builder.CreateStore( this->gen_const(32,(uint32_t)(PC+ 2)), get_reg_ptr(1 + traits::X0), false); @@ -3424,7 +3545,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 62); this->builder.CreateBr(bb); return returnValue; @@ -3432,8 +3553,6 @@ private: /* instruction 63: C__LI */ std::tuple __c__li(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__LI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,63); uint64_t PC = pc.val; uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); @@ -3449,9 +3568,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__LI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,63); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -3465,7 +3588,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 63); this->builder.CreateBr(bb); return returnValue; @@ -3473,8 +3596,6 @@ private: /* instruction 64: C__LUI */ std::tuple __c__lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__LUI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,64); uint64_t PC = pc.val; uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); uint8_t rd = ((bit_sub<7,5>(instr))); @@ -3490,9 +3611,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__LUI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,64); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(imm== 0||rd>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -3504,7 +3629,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 64); this->builder.CreateBr(bb); return returnValue; @@ -3512,8 +3637,6 @@ private: /* instruction 65: C__ADDI16SP */ std::tuple __c__addi16sp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__ADDI16SP_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,65); uint64_t PC = pc.val; uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); if(this->disass_enabled){ @@ -3528,9 +3651,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__ADDI16SP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,65); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(nzimm) { this->builder.CreateStore( this->gen_ext( @@ -3547,7 +3674,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 65); this->builder.CreateBr(bb); return returnValue; @@ -3555,22 +3682,24 @@ private: /* instruction 66: __reserved_clui */ std::tuple ____reserved_clui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("__reserved_clui_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,66); uint64_t PC = pc.val; uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ //This disass is not yet implemented } + bb->setName(fmt::format("__reserved_clui_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,66); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->gen_raise_trap(0, 2); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 66); this->builder.CreateBr(bb); return returnValue; @@ -3578,8 +3707,6 @@ private: /* instruction 67: C__SRLI */ std::tuple __c__srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__SRLI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,67); uint64_t PC = pc.val; uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -3595,9 +3722,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__SRLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,67); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->builder.CreateStore( this->builder.CreateLShr( this->gen_reg_load(rs1+ 8+ traits::X0, 0), @@ -3607,7 +3738,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 67); this->builder.CreateBr(bb); return returnValue; @@ -3615,8 +3746,6 @@ private: /* instruction 68: C__SRAI */ std::tuple __c__srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__SRAI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,68); uint64_t PC = pc.val; uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -3632,9 +3761,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__SRAI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,68); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(shamt){ this->builder.CreateStore( this->gen_ext( (this->builder.CreateAShr( @@ -3662,7 +3795,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 68); this->builder.CreateBr(bb); return returnValue; @@ -3670,8 +3803,6 @@ private: /* instruction 69: C__ANDI */ std::tuple __c__andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__ANDI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,69); uint64_t PC = pc.val; uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -3687,9 +3818,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__ANDI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,69); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->builder.CreateStore( this->gen_ext( (this->builder.CreateAnd( @@ -3701,7 +3836,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 69); this->builder.CreateBr(bb); return returnValue; @@ -3709,8 +3844,6 @@ private: /* instruction 70: C__SUB */ std::tuple __c__sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__SUB_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,70); uint64_t PC = pc.val; uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); @@ -3726,9 +3859,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__SUB_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,70); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->builder.CreateStore( this->gen_ext( (this->builder.CreateSub( @@ -3740,7 +3877,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 70); this->builder.CreateBr(bb); return returnValue; @@ -3748,8 +3885,6 @@ private: /* instruction 71: C__XOR */ std::tuple __c__xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__XOR_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,71); uint64_t PC = pc.val; uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); @@ -3765,9 +3900,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__XOR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,71); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->builder.CreateStore( this->builder.CreateXor( this->gen_reg_load(rd+ 8+ traits::X0, 0), @@ -3777,7 +3916,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 71); this->builder.CreateBr(bb); return returnValue; @@ -3785,8 +3924,6 @@ private: /* instruction 72: C__OR */ std::tuple __c__or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__OR_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,72); uint64_t PC = pc.val; uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); @@ -3802,9 +3939,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__OR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,72); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->builder.CreateStore( this->builder.CreateOr( this->gen_reg_load(rd+ 8+ traits::X0, 0), @@ -3814,7 +3955,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 72); this->builder.CreateBr(bb); return returnValue; @@ -3822,8 +3963,6 @@ private: /* instruction 73: C__AND */ std::tuple __c__and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__AND_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,73); uint64_t PC = pc.val; uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); @@ -3839,9 +3978,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__AND_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,73); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->builder.CreateStore( this->builder.CreateAnd( this->gen_reg_load(rd+ 8+ traits::X0, 0), @@ -3851,7 +3994,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 73); this->builder.CreateBr(bb); return returnValue; @@ -3859,8 +4002,6 @@ private: /* instruction 74: C__J */ std::tuple __c__j(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__J_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,74); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ @@ -3875,16 +4016,20 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__J_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,74); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 74); this->builder.CreateBr(bb); return returnValue; @@ -3892,8 +4037,6 @@ private: /* instruction 75: C__BEQZ */ std::tuple __c__beqz(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__BEQZ_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,75); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -3909,9 +4052,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__BEQZ_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,75); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, @@ -3929,7 +4076,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 75); this->builder.CreateBr(bb); return returnValue; @@ -3937,8 +4084,6 @@ private: /* instruction 76: C__BNEZ */ std::tuple __c__bnez(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__BNEZ_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,76); uint64_t PC = pc.val; uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -3954,9 +4099,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__BNEZ_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,76); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, @@ -3974,7 +4123,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 76); this->builder.CreateBr(bb); return returnValue; @@ -3982,8 +4131,6 @@ private: /* instruction 77: C__SLLI */ std::tuple __c__slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__SLLI_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,77); uint64_t PC = pc.val; uint8_t nzuimm = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,5>(instr))); @@ -3999,9 +4146,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__SLLI_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,77); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -4018,7 +4169,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 77); this->builder.CreateBr(bb); return returnValue; @@ -4026,8 +4177,6 @@ private: /* instruction 78: C__LWSP */ std::tuple __c__lwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__LWSP_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,78); uint64_t PC = pc.val; uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); @@ -4043,9 +4192,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__LWSP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,78); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rd== 0) { this->gen_raise_trap(0, 2); } @@ -4067,7 +4220,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 78); this->builder.CreateBr(bb); return returnValue; @@ -4075,8 +4228,6 @@ private: /* instruction 79: C__MV */ std::tuple __c__mv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__MV_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,79); uint64_t PC = pc.val; uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr))); @@ -4092,9 +4243,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__MV_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,79); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -4108,7 +4263,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 79); this->builder.CreateBr(bb); return returnValue; @@ -4116,8 +4271,6 @@ private: /* instruction 80: C__JR */ std::tuple __c__jr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__JR_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,80); uint64_t PC = pc.val; uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -4132,16 +4285,20 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__JR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,80); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); - if(rs1&&rs1(traits::RFS)) { - auto PC_val_v = this->builder.CreateAnd( - this->gen_reg_load(rs1%static_cast(traits::RFS)+ traits::X0, 0), - this->gen_ext(this->gen_const(8,~ 0x1), 32,false)) - ; - this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); - this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); + + /*generate behavior*/ + if(rs1&&rs1(traits::RFS)){ auto addr_mask =this->gen_const(32,(uint32_t)- 2); + auto PC_val_v = this->builder.CreateAnd( + this->gen_reg_load(rs1%static_cast(traits::RFS)+ traits::X0, 0), + addr_mask) + ; + this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); + this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); } else{ this->gen_raise_trap(0, 2); @@ -4149,7 +4306,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 80); this->builder.CreateBr(bb); return returnValue; @@ -4157,21 +4314,23 @@ private: /* instruction 81: __reserved_cmv */ std::tuple ____reserved_cmv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("__reserved_cmv_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,81); uint64_t PC = pc.val; if(this->disass_enabled){ /* generate console output when executing the command */ //This disass is not yet implemented } + bb->setName(fmt::format("__reserved_cmv_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,81); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->gen_raise_trap(0, 2); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 81); this->builder.CreateBr(bb); return returnValue; @@ -4179,8 +4338,6 @@ private: /* instruction 82: C__ADD */ std::tuple __c__add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__ADD_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,82); uint64_t PC = pc.val; uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr))); @@ -4196,9 +4353,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__ADD_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,82); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -4217,7 +4378,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 82); this->builder.CreateBr(bb); return returnValue; @@ -4225,8 +4386,6 @@ private: /* instruction 83: C__JALR */ std::tuple __c__jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__JALR_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,83); uint64_t PC = pc.val; uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -4241,20 +4400,25 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__JALR_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,83); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs1>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } else{ + auto addr_mask =this->gen_const(32,(uint32_t)- 2); auto new_pc =this->gen_reg_load(rs1+ traits::X0, 0); this->builder.CreateStore( this->gen_const(32,(uint32_t)(PC+ 2)), get_reg_ptr(1 + traits::X0), false); auto PC_val_v = this->builder.CreateAnd( new_pc, - this->gen_ext(this->gen_const(8,~ 0x1), 32,false)) + addr_mask) ; this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); @@ -4262,7 +4426,7 @@ private: bb = this->leave_blk; auto returnValue = std::make_tuple(BRANCH,nullptr); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 83); this->builder.CreateBr(bb); return returnValue; @@ -4270,21 +4434,23 @@ private: /* instruction 84: C__EBREAK */ std::tuple __c__ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__EBREAK_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,84); uint64_t PC = pc.val; if(this->disass_enabled){ /* generate console output when executing the command */ //This disass is not yet implemented } + bb->setName(fmt::format("C__EBREAK_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,84); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->gen_raise_trap(0, 3); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 84); this->builder.CreateBr(bb); return returnValue; @@ -4292,8 +4458,6 @@ private: /* instruction 85: C__SWSP */ std::tuple __c__swsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("C__SWSP_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,85); uint64_t PC = pc.val; uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); @@ -4309,9 +4473,13 @@ private: }; this->builder.CreateCall(this->mod->getFunction("print_disass"), args); } + bb->setName(fmt::format("C__SWSP_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,85); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ if(rs2>=static_cast(traits::RFS)) { this->gen_raise_trap(0, 2); } @@ -4331,7 +4499,7 @@ private: bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 85); this->builder.CreateBr(bb); return returnValue; @@ -4339,21 +4507,23 @@ private: /* instruction 86: DII */ std::tuple __dii(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){ - bb->setName(fmt::format("DII_0x{:X}",pc.val)); - this->gen_sync(PRE_SYNC,86); uint64_t PC = pc.val; if(this->disass_enabled){ /* generate console output when executing the command */ //This disass is not yet implemented } + bb->setName(fmt::format("DII_0x{:X}",pc.val)); + this->gen_sync(PRE_SYNC,86); auto cur_pc_val = this->gen_const(32,pc.val); pc=pc+ 2; this->gen_set_pc(pc, traits::NEXT_PC); + + /*generate behavior*/ this->gen_raise_trap(0, 2); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); - this->gen_trap_check(bb); + this->gen_instr_epilogue(bb); this->gen_sync(POST_SYNC, 86); this->builder.CreateBr(bb); return returnValue; @@ -4373,7 +4543,7 @@ private: pc = pc + ((instr & 3) == 3 ? 4 : 2); this->gen_raise_trap(0, 2); // illegal instruction trap this->gen_sync(iss::POST_SYNC, instr_descr.size()); - this->gen_trap_check(this->leave_blk); + this->gen_instr_epilogue(this->leave_blk); return std::make_tuple(BRANCH, nullptr); } //decoding functionality @@ -4479,18 +4649,21 @@ vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, return (this->*f)(pc, instr, this_block); } -template void vm_impl::gen_leave_behavior(BasicBlock *leave_blk) { +template +void vm_impl::gen_leave_behavior(BasicBlock *leave_blk) { this->builder.SetInsertPoint(leave_blk); this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false)); } -template void vm_impl::gen_raise_trap(uint16_t trap_id, uint16_t cause) { +template +void vm_impl::gen_raise_trap(uint16_t trap_id, uint16_t cause) { auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id); this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true); this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } -template void vm_impl::gen_leave_trap(unsigned lvl) { +template +void vm_impl::gen_leave_trap(unsigned lvl) { std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) }; this->builder.CreateCall(this->mod->getFunction("leave_trap"), args); auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8); @@ -4498,12 +4671,14 @@ template void vm_impl::gen_leave_trap(unsigned lvl) { this->builder.CreateStore(this->gen_const(32U, std::numeric_limits::max()), get_reg_ptr(traits::LAST_BRANCH), false); } -template void vm_impl::gen_wait(unsigned type) { +template +void vm_impl::gen_wait(unsigned type) { std::vector args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) }; this->builder.CreateCall(this->mod->getFunction("wait"), args); } -template void vm_impl::gen_trap_behavior(BasicBlock *trap_blk) { +template +void vm_impl::gen_trap_behavior(BasicBlock *trap_blk) { this->builder.SetInsertPoint(trap_blk); this->gen_sync(POST_SYNC, -1); //TODO get right InstrId auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); @@ -4516,7 +4691,8 @@ template void vm_impl::gen_trap_behavior(BasicBlock *trap_ this->builder.CreateRet(trap_addr_val); } -template inline void vm_impl::gen_trap_check(BasicBlock *bb) { +template +void vm_impl::gen_instr_epilogue(BasicBlock *bb) { auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb); auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true); this->gen_cond_branch(this->builder.CreateICmp( From a27850f841ad139484664f8e5a8530ac5104673f Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Sat, 18 May 2024 21:00:21 +0200 Subject: [PATCH 24/33] adds verilog literal and illegal_instr to asmjit --- gen_input/templates/asmjit/CORENAME.cpp.gtl | 12 +- src/vm/asmjit/vm_tgc5c.cpp | 361 ++++++++++---------- 2 files changed, 194 insertions(+), 179 deletions(-) diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl index 081d9de..b671123 100644 --- a/gen_input/templates/asmjit/CORENAME.cpp.gtl +++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl @@ -174,9 +174,17 @@ private: * end opcode definitions ****************************************************************************/ continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) { - + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("illegal_intruction{:#x}:",pc.val).c_str()); + this->gen_sync(jh, PRE_SYNC, instr_descr.size()); + pc = pc + ((instr & 3) == 3 ? 4 : 2); + gen_instr_prologue(jh); + cc.comment("//behavior:"); + gen_instr_epilogue(jh); + this->gen_sync(jh, POST_SYNC, instr_descr.size()); return BRANCH; - } + } + //decoding functionality void populate_decoding_tree(decoding_tree_node* root){ diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index ac2681c..7d72232 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -80,7 +80,7 @@ public: protected: using super::get_ptr_for; - using super::get_reg; +using super::get_reg; using super::get_reg_for; using super::load_reg_from_mem; using super::write_reg_to_mem; @@ -339,10 +339,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)((int32_t)imm)); } @@ -385,10 +385,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)(PC+(int32_t)imm)); } @@ -431,16 +431,16 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ if(imm%static_cast(traits::INSTR_ALIGNMENT)){ - gen_raise(jh, 0, 0); + gen_raise(jh, 0, 0); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - (uint32_t)(PC+ 4)); + (uint32_t)(PC+4)); } auto PC_val_v = (uint32_t)(PC+(int32_t)sext<21>(imm)); cc.mov(jh.next_pc, PC_val_v); @@ -486,7 +486,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto addr_mask = (uint32_t)- 2; @@ -500,14 +500,14 @@ private: auto label_else = cc.newLabel(); cc.je(label_else); { - gen_raise(jh, 0, 0); + gen_raise(jh, 0, 0); } cc.jmp(label_merge); cc.bind(label_else); { - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - (uint32_t)(PC+ 4)); + (uint32_t)(PC+4)); } auto PC_val_v = new_pc; cc.mov(jh.next_pc, PC_val_v); @@ -554,7 +554,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); @@ -563,7 +563,7 @@ private: cc.je(label_merge); { if(imm%static_cast(traits::INSTR_ALIGNMENT)){ - gen_raise(jh, 0, 0); + gen_raise(jh, 0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -612,7 +612,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); @@ -621,7 +621,7 @@ private: cc.je(label_merge); { if(imm%static_cast(traits::INSTR_ALIGNMENT)){ - gen_raise(jh, 0, 0); + gen_raise(jh, 0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -670,7 +670,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); @@ -681,7 +681,7 @@ private: cc.je(label_merge); { if(imm%static_cast(traits::INSTR_ALIGNMENT)){ - gen_raise(jh, 0, 0); + gen_raise(jh, 0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -730,7 +730,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); @@ -741,7 +741,7 @@ private: cc.je(label_merge); { if(imm%static_cast(traits::INSTR_ALIGNMENT)){ - gen_raise(jh, 0, 0); + gen_raise(jh, 0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -790,7 +790,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); @@ -799,7 +799,7 @@ private: cc.je(label_merge); { if(imm%static_cast(traits::INSTR_ALIGNMENT)){ - gen_raise(jh, 0, 0); + gen_raise(jh, 0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -848,7 +848,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); @@ -857,7 +857,7 @@ private: cc.je(label_merge); { if(imm%static_cast(traits::INSTR_ALIGNMENT)){ - gen_raise(jh, 0, 0); + gen_raise(jh, 0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -906,7 +906,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto load_address = gen_ext(jh, @@ -914,7 +914,7 @@ private: ), 32, true); auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 1), 8, false); - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, res, 32, true)); @@ -959,7 +959,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto load_address = gen_ext(jh, @@ -967,7 +967,7 @@ private: ), 32, true); auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 2), 16, false); - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, res, 32, true)); @@ -1012,7 +1012,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto load_address = gen_ext(jh, @@ -1020,7 +1020,7 @@ private: ), 32, true); auto res = gen_ext(jh, gen_read_mem(jh, traits::MEM, load_address, 4), 32, false); - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, res, 32, true)); @@ -1065,14 +1065,14 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto load_address = gen_ext(jh, (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) ), 32, true); auto res = gen_read_mem(jh, traits::MEM, load_address, 1); - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, res, 32, false)); @@ -1117,14 +1117,14 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto load_address = gen_ext(jh, (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) ), 32, true); auto res = gen_read_mem(jh, traits::MEM, load_address, 2); - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, res, 32, false)); @@ -1169,7 +1169,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto store_address = gen_ext(jh, @@ -1217,7 +1217,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto store_address = gen_ext(jh, @@ -1265,7 +1265,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto store_address = gen_ext(jh, @@ -1313,10 +1313,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm)) @@ -1362,10 +1362,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ { auto label_then = cc.newLabel(); auto label_merge = cc.newLabel(); @@ -1373,10 +1373,10 @@ private: cc.cmp(gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), (int16_t)sext<12>(imm)); cc.jl(label_then); - cc.mov(tmp_reg, 0); + cc.mov(tmp_reg,0); cc.jmp(label_merge); cc.bind(label_then); - cc.mov(tmp_reg, 1); + cc.mov(tmp_reg,1); cc.bind(label_merge); cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, tmp_reg @@ -1424,20 +1424,20 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ { auto label_then = cc.newLabel(); auto label_merge = cc.newLabel(); auto tmp_reg = get_reg_for(jh, 1); cc.cmp(load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))); cc.jb(label_then); - cc.mov(tmp_reg, 0); + cc.mov(tmp_reg,0); cc.jmp(label_merge); cc.bind(label_then); - cc.mov(tmp_reg, 1); + cc.mov(tmp_reg,1); cc.bind(label_merge); cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, tmp_reg @@ -1485,10 +1485,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) ); @@ -1533,10 +1533,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) ); @@ -1581,10 +1581,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm))) ); @@ -1629,10 +1629,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), shamt) ); @@ -1677,10 +1677,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), shamt) ); @@ -1725,10 +1725,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, sar, gen_ext(jh, @@ -1775,10 +1775,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) @@ -1824,10 +1824,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, sub, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) @@ -1873,12 +1873,12 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)- 1)) + gen_ext(jh, gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1)) )) , 32, false)); } @@ -1922,10 +1922,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ { auto label_then = cc.newLabel(); auto label_merge = cc.newLabel(); @@ -1934,10 +1934,10 @@ private: load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, true)); cc.jl(label_then); - cc.mov(tmp_reg, 0); + cc.mov(tmp_reg,0); cc.jmp(label_merge); cc.bind(label_then); - cc.mov(tmp_reg, 1); + cc.mov(tmp_reg,1); cc.bind(label_merge); cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, tmp_reg @@ -1985,20 +1985,20 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ { auto label_then = cc.newLabel(); auto label_merge = cc.newLabel(); auto tmp_reg = get_reg_for(jh, 1); cc.cmp(load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)); cc.jb(label_then); - cc.mov(tmp_reg, 0); + cc.mov(tmp_reg,0); cc.jmp(label_merge); cc.bind(label_then); - cc.mov(tmp_reg, 1); + cc.mov(tmp_reg,1); cc.bind(label_merge); cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, tmp_reg @@ -2046,10 +2046,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ); @@ -2094,12 +2094,12 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)- 1)) + gen_ext(jh, gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1)) )) , 32, false)); } @@ -2143,14 +2143,14 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_ext(jh, gen_operation(jh, sar, gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1), 32, true), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)- 1)) + load_reg_from_mem(jh, traits::X0 + rs1), 32, true), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast(traits::XLEN)-1)) )) , 32, true)), 32, true)); } @@ -2194,10 +2194,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ); @@ -2242,10 +2242,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2)) ); @@ -2291,7 +2291,7 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - gen_write_mem(jh, traits::FENCE, static_cast(traits::fence), (uint8_t)pred<< 4|succ, 4); + gen_write_mem(jh, traits::FENCE, static_cast(traits::fence), (uint8_t)pred<<4|succ, 4); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -2326,7 +2326,7 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - gen_raise(jh, 0, 11); + gen_raise(jh, 0, 11); auto returnValue = TRAP; gen_instr_epilogue(jh); @@ -2361,7 +2361,7 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - gen_raise(jh, 0, 3); + gen_raise(jh, 0, 3); auto returnValue = TRAP; gen_instr_epilogue(jh); @@ -2471,11 +2471,11 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1); - if(rd!= 0){ + if(rd!=0){ auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); gen_write_mem(jh, traits::CSR, csr, xrs1, 4); cc.mov(get_ptr_for(jh, traits::X0+ rd), @@ -2524,16 +2524,16 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1); - if(rs1!= 0){ + if(rs1!=0){ gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, xrd, xrs1) , 4); } - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), xrd); } @@ -2577,16 +2577,16 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1); - if(rs1!= 0){ + if(rs1!=0){ gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, xrd, gen_operation(jh, bnot, xrs1)) , 4); } - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), xrd); } @@ -2630,12 +2630,12 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); gen_write_mem(jh, traits::CSR, csr, (uint32_t)zimm, 4); - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), xrd); } @@ -2679,15 +2679,15 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); - if(zimm!= 0){ + if(zimm!=0){ gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, xrd, (uint32_t)zimm) , 4); } - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), xrd); } @@ -2731,15 +2731,15 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto xrd = gen_read_mem(jh, traits::CSR, csr, 4); - if(zimm!= 0){ + if(zimm!=0){ gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, xrd, ~ ((uint32_t)zimm)) , 4); } - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), xrd); } @@ -2822,16 +2822,16 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto res = gen_ext(jh, - (gen_operation(jh, imul, - gen_ext(jh, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), - gen_ext(jh, - gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true)) - ), 64, true); + (gen_operation(jh, imul, gen_ext(jh, + gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh, + gen_ext(jh, + load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true)) + ), 64, true); if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, @@ -2877,7 +2877,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto res = gen_ext(jh, @@ -2933,7 +2933,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto res = gen_ext(jh, @@ -2988,7 +2988,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto res = gen_ext(jh, @@ -3042,16 +3042,16 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto dividend = gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, false); auto divisor = gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, false); - if(rd!= 0){ + if(rd!=0){ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ne, divisor, 0) + cc.cmp(gen_operation(jh, ne, divisor, 0) ,0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -3126,11 +3126,11 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0) + cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0) ,0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -3191,11 +3191,11 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0) + cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0) ,0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -3212,7 +3212,7 @@ private: { if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), - gen_ext(jh, 0, 32, false) + gen_ext(jh, 0, 32, false) ); } } @@ -3279,11 +3279,11 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0) + cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0) ,0); auto label_else = cc.newLabel(); cc.je(label_else); @@ -3342,13 +3342,13 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(imm){ - cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rd+8), gen_ext(jh, (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), imm) ), 32, false)); } else{ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } auto returnValue = CONT; @@ -3389,9 +3389,9 @@ private: cc.comment("//behavior:"); /*generate behavior*/ auto offs = gen_ext(jh, - (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1+ 8), uimm) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1+8), uimm) ), 32, false); - cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rd+8), gen_ext(jh, gen_ext(jh, gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true)); @@ -3434,10 +3434,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ auto offs = gen_ext(jh, - (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1+ 8), uimm) + (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1+8), uimm) ), 32, false); gen_write_mem(jh, traits::MEM, offs, gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs2+ 8), 32, false), 4); + load_reg_from_mem(jh, traits::X0 + rs2+8), 32, false), 4); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -3476,10 +3476,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rs1!= 0){ + if(rs1!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rs1), gen_ext(jh, (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int8_t)sext<6>(imm)) @@ -3558,7 +3558,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ cc.mov(get_ptr_for(jh, traits::X0+ 1), - (uint32_t)(PC+ 2)); + (uint32_t)(PC+2)); auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); cc.mov(jh.next_pc, PC_val_v); cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); @@ -3600,10 +3600,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)((int8_t)sext<6>(imm))); } @@ -3645,10 +3645,10 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - if(imm== 0||rd>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + if(imm==0||rd>=static_cast(traits::RFS)){ + gen_raise(jh, 0, 2); } - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), (uint32_t)((int32_t)sext<18>(imm))); } @@ -3695,7 +3695,7 @@ private: ), 32, true)); } else{ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } auto returnValue = CONT; @@ -3732,7 +3732,7 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -3770,8 +3770,8 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), - gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1+ 8), shamt) + cc.mov(get_ptr_for(jh, traits::X0+ rs1+8), + gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1+8), shamt) ); auto returnValue = CONT; @@ -3811,18 +3811,18 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(shamt){ - cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rs1+8), gen_ext(jh, (gen_operation(jh, sar, (gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1+ 8), 32, false)), shamt) + load_reg_from_mem(jh, traits::X0 + rs1+8), 32, false)), shamt) ), 32, true)); } else{ - if(static_cast(traits::XLEN)== 128){ - cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), + if(static_cast(traits::XLEN)==128){ + cc.mov(get_ptr_for(jh, traits::X0+ rs1+8), gen_ext(jh, (gen_operation(jh, sar, (gen_ext(jh, - load_reg_from_mem(jh, traits::X0 + rs1+ 8), 32, false)), 64) + load_reg_from_mem(jh, traits::X0 + rs1+8), 32, false)), 64) ), 32, true)); } } @@ -3863,9 +3863,9 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - cc.mov(get_ptr_for(jh, traits::X0+ rs1+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rs1+8), gen_ext(jh, - (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1+ 8), (int8_t)sext<6>(imm)) + (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1+8), (int8_t)sext<6>(imm)) ), 32, true)); auto returnValue = CONT; @@ -3904,9 +3904,9 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), + cc.mov(get_ptr_for(jh, traits::X0+ rd+8), gen_ext(jh, - (gen_operation(jh, sub, load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) + (gen_operation(jh, sub, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) ), 32, true)); auto returnValue = CONT; @@ -3945,8 +3945,8 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), - gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) + cc.mov(get_ptr_for(jh, traits::X0+ rd+8), + gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) ); auto returnValue = CONT; @@ -3985,8 +3985,8 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), - gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) + cc.mov(get_ptr_for(jh, traits::X0+ rd+8), + gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) ); auto returnValue = CONT; @@ -4025,8 +4025,8 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - cc.mov(get_ptr_for(jh, traits::X0+ rd+ 8), - gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8)) + cc.mov(get_ptr_for(jh, traits::X0+ rd+8), + gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8)) ); auto returnValue = CONT; @@ -4105,7 +4105,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1+ 8), 0) + cc.cmp(gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1+8), 0) ,0); cc.je(label_merge); { @@ -4152,7 +4152,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ auto label_merge = cc.newLabel(); - cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs1+ 8), 0) + cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs1+8), 0) ,0); cc.je(label_merge); { @@ -4199,10 +4199,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rs1!= 0){ + if(rs1!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rs1), gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), nzuimm) ); @@ -4245,8 +4245,8 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - if(rd>=static_cast(traits::RFS)||rd== 0){ - gen_raise(jh, 0, 2); + if(rd>=static_cast(traits::RFS)||rd==0){ + gen_raise(jh, 0, 2); } else{ auto offs = gen_ext(jh, @@ -4295,10 +4295,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), load_reg_from_mem(jh, traits::X0 + rs2)); } @@ -4340,7 +4340,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs1&&rs1(traits::RFS)){ - auto PC_val_v = gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1%static_cast(traits::RFS)), ~ 0x1) + auto PC_val_v = gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1%static_cast(traits::RFS)), ~ 1) ; cc.mov(jh.next_pc, PC_val_v); cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); @@ -4421,10 +4421,10 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rd>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ - if(rd!= 0){ + if(rd!=0){ cc.mov(get_ptr_for(jh, traits::X0+ rd), gen_ext(jh, (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rd), load_reg_from_mem(jh, traits::X0 + rs2)) @@ -4468,13 +4468,13 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs1>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto new_pc = load_reg_from_mem(jh, traits::X0 + rs1); cc.mov(get_ptr_for(jh, traits::X0+ 1), - (uint32_t)(PC+ 2)); - auto PC_val_v = gen_operation(jh, band, new_pc, ~ 0x1) + (uint32_t)(PC+2)); + auto PC_val_v = gen_operation(jh, band, new_pc, ~ 1) ; cc.mov(jh.next_pc, PC_val_v); cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); @@ -4513,7 +4513,7 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - gen_raise(jh, 0, 3); + gen_raise(jh, 0, 3); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -4552,7 +4552,7 @@ private: cc.comment("//behavior:"); /*generate behavior*/ if(rs2>=static_cast(traits::RFS)){ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); } else{ auto offs = gen_ext(jh, @@ -4595,7 +4595,7 @@ private: gen_instr_prologue(jh); cc.comment("//behavior:"); /*generate behavior*/ - gen_raise(jh, 0, 2); + gen_raise(jh, 0, 2); auto returnValue = CONT; gen_instr_epilogue(jh); @@ -4607,7 +4607,14 @@ private: * end opcode definitions ****************************************************************************/ continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) { - + x86::Compiler& cc = jh.cc; + cc.comment(fmt::format("illegal_intruction{:#x}:",pc.val).c_str()); + this->gen_sync(jh, PRE_SYNC, instr_descr.size()); + pc = pc + ((instr & 3) == 3 ? 4 : 2); + gen_instr_prologue(jh); + cc.comment("//behavior:"); + gen_instr_epilogue(jh); + this->gen_sync(jh, POST_SYNC, instr_descr.size()); return BRANCH; } //decoding functionality From 3cc8bd085469219d9fbcd77948a3ffc062d9dc43 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Sat, 18 May 2024 21:00:54 +0200 Subject: [PATCH 25/33] adds reformat bc of verilog literals --- src/vm/llvm/vm_tgc5c.cpp | 356 +++++++++++++++++++-------------------- src/vm/tcc/vm_tgc5c.cpp | 353 +++++++++++++++++++------------------- 2 files changed, 353 insertions(+), 356 deletions(-) diff --git a/src/vm/llvm/vm_tgc5c.cpp b/src/vm/llvm/vm_tgc5c.cpp index 58e3c2c..1212037 100644 --- a/src/vm/llvm/vm_tgc5c.cpp +++ b/src/vm/llvm/vm_tgc5c.cpp @@ -352,10 +352,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_const(32,(uint32_t)((int32_t)imm)), get_reg_ptr(rd + traits::X0), false); @@ -395,10 +395,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_const(32,(uint32_t)(PC+(int32_t)imm)), get_reg_ptr(rd + traits::X0), false); @@ -438,15 +438,15 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( - this->gen_const(32,(uint32_t)(PC+ 4)), + this->gen_const(32,(uint32_t)(PC+4)), get_reg_ptr(rd + traits::X0), false); } auto PC_val_v = (uint32_t)(PC+(int32_t)sext<21>(imm)); @@ -489,7 +489,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto addr_mask =this->gen_const(32,(uint32_t)- 2); @@ -511,14 +511,14 @@ private: , 1), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); { - this->gen_raise_trap(0, 0); + this->gen_raise_trap(0, 0); } this->builder.CreateBr(bb_merge); this->builder.SetInsertPoint(bb_else); { - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( - this->gen_const(32,(uint32_t)(PC+ 4)), + this->gen_const(32,(uint32_t)(PC+4)), get_reg_ptr(rd + traits::X0), false); } auto PC_val_v = new_pc; @@ -563,7 +563,7 @@ private: /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); @@ -574,7 +574,7 @@ private: , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -620,7 +620,7 @@ private: /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); @@ -631,7 +631,7 @@ private: , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -677,7 +677,7 @@ private: /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); @@ -692,7 +692,7 @@ private: , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -738,7 +738,7 @@ private: /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); @@ -753,7 +753,7 @@ private: , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -799,7 +799,7 @@ private: /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); @@ -810,7 +810,7 @@ private: , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -856,7 +856,7 @@ private: /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); @@ -867,7 +867,7 @@ private: , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { - if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); + if(imm%static_cast(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0); } else{ auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm)); @@ -913,7 +913,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto load_address =this->gen_ext( @@ -925,7 +925,7 @@ private: auto res =this->gen_ext( this->gen_read_mem(traits::MEM, load_address, 1), 8, false); - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext( res, @@ -968,7 +968,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto load_address =this->gen_ext( @@ -980,7 +980,7 @@ private: auto res =this->gen_ext( this->gen_read_mem(traits::MEM, load_address, 2), 16, false); - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext( res, @@ -1023,7 +1023,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto load_address =this->gen_ext( @@ -1035,7 +1035,7 @@ private: auto res =this->gen_ext( this->gen_read_mem(traits::MEM, load_address, 4), 32, false); - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext( res, @@ -1078,7 +1078,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto load_address =this->gen_ext( @@ -1088,7 +1088,7 @@ private: ), 32, true); auto res =this->gen_read_mem(traits::MEM, load_address, 1); - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext( res, @@ -1131,7 +1131,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto load_address =this->gen_ext( @@ -1141,7 +1141,7 @@ private: ), 32, true); auto res =this->gen_read_mem(traits::MEM, load_address, 2); - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext( res, @@ -1184,7 +1184,7 @@ private: /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto store_address =this->gen_ext( @@ -1234,7 +1234,7 @@ private: /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto store_address =this->gen_ext( @@ -1284,7 +1284,7 @@ private: /*generate behavior*/ if(rs2>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto store_address =this->gen_ext( @@ -1334,10 +1334,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext( (this->builder.CreateAdd( @@ -1383,18 +1383,18 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext(this->gen_choose((this->builder.CreateICmp(ICmpInst::ICMP_SLT, this->gen_ext( this->gen_reg_load(rs1+ traits::X0, 0), 32,true), this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 32,true)) ), - this->gen_const(8, 1), - this->gen_const(8, 0), + this->gen_const(8,1), + this->gen_const(8,0), 1), 32), get_reg_ptr(rd + traits::X0), false); } @@ -1434,17 +1434,17 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext(this->gen_choose((this->builder.CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(rs1+ traits::X0, 0), this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm)))) ), - this->gen_const(8, 1), - this->gen_const(8, 0), + this->gen_const(8,1), + this->gen_const(8,0), 1), 32), get_reg_ptr(rd + traits::X0), false); } @@ -1484,10 +1484,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->builder.CreateXor( this->gen_reg_load(rs1+ traits::X0, 0), @@ -1531,10 +1531,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->builder.CreateOr( this->gen_reg_load(rs1+ traits::X0, 0), @@ -1578,10 +1578,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->builder.CreateAnd( this->gen_reg_load(rs1+ traits::X0, 0), @@ -1625,10 +1625,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->builder.CreateShl( this->gen_reg_load(rs1+ traits::X0, 0), @@ -1672,10 +1672,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->builder.CreateLShr( this->gen_reg_load(rs1+ traits::X0, 0), @@ -1719,10 +1719,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext( (this->builder.CreateAShr( @@ -1769,10 +1769,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext( (this->builder.CreateAdd( @@ -1818,10 +1818,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext( (this->builder.CreateSub( @@ -1867,16 +1867,16 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext(this->builder.CreateShl( this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), (this->builder.CreateAnd( this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false), - this->gen_const(64,(static_cast(traits::XLEN)- 1))) + this->gen_const(64,(static_cast(traits::XLEN)-1))) )) , 32, false), get_reg_ptr(rd + traits::X0), false); @@ -1917,10 +1917,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext(this->gen_choose(this->builder.CreateICmp(ICmpInst::ICMP_SLT, this->gen_ext( @@ -1928,8 +1928,8 @@ private: this->gen_ext( this->gen_reg_load(rs2+ traits::X0, 0), 32,true)) , - this->gen_const(8, 1), - this->gen_const(8, 0), + this->gen_const(8,1), + this->gen_const(8,0), 1), 32), get_reg_ptr(rd + traits::X0), false); } @@ -1969,17 +1969,17 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext(this->gen_choose(this->builder.CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(rs1+ traits::X0, 0), this->gen_reg_load(rs2+ traits::X0, 0)) , - this->gen_const(8, 1), - this->gen_const(8, 0), + this->gen_const(8,1), + this->gen_const(8,0), 1), 32), get_reg_ptr(rd + traits::X0), false); } @@ -2019,10 +2019,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->builder.CreateXor( this->gen_reg_load(rs1+ traits::X0, 0), @@ -2066,16 +2066,16 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext(this->builder.CreateLShr( this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false), (this->builder.CreateAnd( this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false), - this->gen_const(64,(static_cast(traits::XLEN)- 1))) + this->gen_const(64,(static_cast(traits::XLEN)-1))) )) , 32, false), get_reg_ptr(rd + traits::X0), false); @@ -2116,10 +2116,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext( (this->gen_ext(this->builder.CreateAShr( @@ -2127,7 +2127,7 @@ private: this->gen_reg_load(rs1+ traits::X0, 0), 32,true), 64,true), (this->builder.CreateAnd( this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false), - this->gen_const(64,(static_cast(traits::XLEN)- 1))) + this->gen_const(64,(static_cast(traits::XLEN)-1))) )) , 32, true)), 32, true), @@ -2169,10 +2169,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->builder.CreateOr( this->gen_reg_load(rs1+ traits::X0, 0), @@ -2216,10 +2216,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->builder.CreateAnd( this->gen_reg_load(rs1+ traits::X0, 0), @@ -2266,7 +2266,7 @@ private: /*generate behavior*/ this->gen_write_mem(traits::FENCE, static_cast(traits::fence), - this->gen_const(8,(uint8_t)pred<< 4|succ)); + this->gen_const(8,(uint8_t)pred<<4|succ)); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -2290,7 +2290,7 @@ private: this->gen_set_pc(pc, traits::NEXT_PC); /*generate behavior*/ - this->gen_raise_trap(0, 11); + this->gen_raise_trap(0, 11); bb = this->leave_blk; auto returnValue = std::make_tuple(TRAP,nullptr); @@ -2314,7 +2314,7 @@ private: this->gen_set_pc(pc, traits::NEXT_PC); /*generate behavior*/ - this->gen_raise_trap(0, 3); + this->gen_raise_trap(0, 3); bb = this->leave_blk; auto returnValue = std::make_tuple(TRAP,nullptr); @@ -2398,11 +2398,11 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0); - if(rd!= 0){ auto xrd =this->gen_read_mem(traits::CSR, csr, 4); + if(rd!=0){ auto xrd =this->gen_read_mem(traits::CSR, csr, 4); this->gen_write_mem(traits::CSR, csr, xrs1); @@ -2451,12 +2451,12 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto xrd =this->gen_read_mem(traits::CSR, csr, 4); auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0); - if(rs1!= 0) { + if(rs1!=0) { this->gen_write_mem(traits::CSR, csr, this->builder.CreateOr( @@ -2464,7 +2464,7 @@ private: xrs1) ); } - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( xrd, get_reg_ptr(rd + traits::X0), false); @@ -2505,12 +2505,12 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto xrd =this->gen_read_mem(traits::CSR, csr, 4); auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0); - if(rs1!= 0) { + if(rs1!=0) { this->gen_write_mem(traits::CSR, csr, this->builder.CreateAnd( @@ -2518,7 +2518,7 @@ private: this->builder.CreateNeg(xrs1)) ); } - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( xrd, get_reg_ptr(rd + traits::X0), false); @@ -2559,14 +2559,14 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto xrd =this->gen_read_mem(traits::CSR, csr, 4); this->gen_write_mem(traits::CSR, csr, this->gen_const(32,(uint32_t)zimm)); - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( xrd, get_reg_ptr(rd + traits::X0), false); @@ -2607,11 +2607,11 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto xrd =this->gen_read_mem(traits::CSR, csr, 4); - if(zimm!= 0) { + if(zimm!=0) { this->gen_write_mem(traits::CSR, csr, this->builder.CreateOr( @@ -2619,7 +2619,7 @@ private: this->gen_const(32,(uint32_t)zimm)) ); } - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( xrd, get_reg_ptr(rd + traits::X0), false); @@ -2660,11 +2660,11 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto xrd =this->gen_read_mem(traits::CSR, csr, 4); - if(zimm!= 0) { + if(zimm!=0) { this->gen_write_mem(traits::CSR, csr, this->builder.CreateAnd( @@ -2672,7 +2672,7 @@ private: this->gen_const(32,~ ((uint32_t)zimm))) ); } - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( xrd, get_reg_ptr(rd + traits::X0), false); @@ -2750,7 +2750,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto res =this->gen_ext( @@ -2808,7 +2808,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto res =this->gen_ext( @@ -2869,7 +2869,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto res =this->gen_ext( @@ -2929,7 +2929,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto res =this->gen_ext( @@ -2988,7 +2988,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto dividend =this->gen_ext( @@ -2997,12 +2997,12 @@ private: auto divisor =this->gen_ext( this->gen_reg_load(rs2+ traits::X0, 0), 32, false); - if(rd!= 0){ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); + if(rd!=0){ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, divisor, - this->gen_ext(this->gen_const(8, 0), 32,false)) + this->gen_ext(this->gen_const(8,0), 32,false)) , 1), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); { @@ -3087,7 +3087,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); @@ -3095,7 +3095,7 @@ private: auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2+ traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32,false)) + this->gen_ext(this->gen_const(8,0), 32,false)) , 1), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); { @@ -3157,7 +3157,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); @@ -3165,7 +3165,7 @@ private: auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2+ traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32,false)) + this->gen_ext(this->gen_const(8,0), 32,false)) , 1), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); { @@ -3189,7 +3189,7 @@ private: { if(rd!=0) { this->builder.CreateStore( - this->gen_ext(this->gen_const(8, 0), 32), + this->gen_ext(this->gen_const(8,0), 32), get_reg_ptr(rd + traits::X0), false); } } @@ -3261,7 +3261,7 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)||rs1>=static_cast(traits::RFS)||rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); @@ -3269,7 +3269,7 @@ private: auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge); this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2+ traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32,false)) + this->gen_ext(this->gen_const(8,0), 32,false)) , 1), bb_then, bb_else); this->builder.SetInsertPoint(bb_then); { @@ -3335,10 +3335,10 @@ private: this->gen_ext(this->gen_const(16,imm), 64,false)) ), 32, false), - get_reg_ptr(rd+ 8 + traits::X0), false); + get_reg_ptr(rd+8 + traits::X0), false); } else{ - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -3376,7 +3376,7 @@ private: /*generate behavior*/ auto offs =this->gen_ext( (this->builder.CreateAdd( - this->gen_ext(this->gen_reg_load(rs1+ 8+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_reg_load(rs1+8+ traits::X0, 0), 64,false), this->gen_ext(this->gen_const(8,uimm), 64,false)) ), 32, false); @@ -3386,7 +3386,7 @@ private: this->gen_read_mem(traits::MEM, offs, 4), 32, false), 32, true), - get_reg_ptr(rd+ 8 + traits::X0), false); + get_reg_ptr(rd+8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -3423,14 +3423,14 @@ private: /*generate behavior*/ auto offs =this->gen_ext( (this->builder.CreateAdd( - this->gen_ext(this->gen_reg_load(rs1+ 8+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_reg_load(rs1+8+ traits::X0, 0), 64,false), this->gen_ext(this->gen_const(8,uimm), 64,false)) ), 32, false); this->gen_write_mem(traits::MEM, offs, this->gen_ext( - this->gen_reg_load(rs2+ 8+ traits::X0, 0), + this->gen_reg_load(rs2+8+ traits::X0, 0), 32, false)); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -3466,10 +3466,10 @@ private: /*generate behavior*/ if(rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rs1!= 0) { + if(rs1!=0) { this->builder.CreateStore( this->gen_ext( (this->builder.CreateAdd( @@ -3537,7 +3537,7 @@ private: /*generate behavior*/ this->builder.CreateStore( - this->gen_const(32,(uint32_t)(PC+ 2)), + this->gen_const(32,(uint32_t)(PC+2)), get_reg_ptr(1 + traits::X0), false); auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm)); this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false); @@ -3576,10 +3576,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_const(32,(uint32_t)((int8_t)sext<6>(imm))), get_reg_ptr(rd + traits::X0), false); @@ -3618,10 +3618,10 @@ private: this->gen_set_pc(pc, traits::NEXT_PC); /*generate behavior*/ - if(imm== 0||rd>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + if(imm==0||rd>=static_cast(traits::RFS)) { + this->gen_raise_trap(0, 2); } - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_const(32,(uint32_t)((int32_t)sext<18>(imm))), get_reg_ptr(rd + traits::X0), false); @@ -3669,7 +3669,7 @@ private: get_reg_ptr(2 + traits::X0), false); } else{ - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -3695,7 +3695,7 @@ private: this->gen_set_pc(pc, traits::NEXT_PC); /*generate behavior*/ - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -3731,10 +3731,10 @@ private: /*generate behavior*/ this->builder.CreateStore( this->builder.CreateLShr( - this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_reg_load(rs1+8+ traits::X0, 0), this->gen_ext(this->gen_const(8,shamt), 32,false)) , - get_reg_ptr(rs1+ 8 + traits::X0), false); + get_reg_ptr(rs1+8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -3772,24 +3772,24 @@ private: this->gen_ext( (this->builder.CreateAShr( (this->gen_ext( - this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_reg_load(rs1+8+ traits::X0, 0), 32, false)), this->gen_ext(this->gen_const(8,shamt), 32,false)) ), 32, true), - get_reg_ptr(rs1+ 8 + traits::X0), false); + get_reg_ptr(rs1+8 + traits::X0), false); } else{ - if(static_cast(traits::XLEN)== 128){ this->builder.CreateStore( + if(static_cast(traits::XLEN)==128){ this->builder.CreateStore( this->gen_ext( (this->builder.CreateAShr( (this->gen_ext( - this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_reg_load(rs1+8+ traits::X0, 0), 32, false)), - this->gen_ext(this->gen_const(8, 64), 32,false)) + this->gen_ext(this->gen_const(8,64), 32,false)) ), 32, true), - get_reg_ptr(rs1+ 8 + traits::X0), false); + get_reg_ptr(rs1+8 + traits::X0), false); } } bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); @@ -3828,11 +3828,11 @@ private: this->builder.CreateStore( this->gen_ext( (this->builder.CreateAnd( - this->gen_reg_load(rs1+ 8+ traits::X0, 0), + this->gen_reg_load(rs1+8+ traits::X0, 0), this->gen_ext(this->gen_const(8,(int8_t)sext<6>(imm)), 32,true)) ), 32, true), - get_reg_ptr(rs1+ 8 + traits::X0), false); + get_reg_ptr(rs1+8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -3869,11 +3869,11 @@ private: this->builder.CreateStore( this->gen_ext( (this->builder.CreateSub( - this->gen_ext(this->gen_reg_load(rd+ 8+ traits::X0, 0), 64,false), - this->gen_ext(this->gen_reg_load(rs2+ 8+ traits::X0, 0), 64,false)) + this->gen_ext(this->gen_reg_load(rd+8+ traits::X0, 0), 64,false), + this->gen_ext(this->gen_reg_load(rs2+8+ traits::X0, 0), 64,false)) ), 32, true), - get_reg_ptr(rd+ 8 + traits::X0), false); + get_reg_ptr(rd+8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -3909,10 +3909,10 @@ private: /*generate behavior*/ this->builder.CreateStore( this->builder.CreateXor( - this->gen_reg_load(rd+ 8+ traits::X0, 0), - this->gen_reg_load(rs2+ 8+ traits::X0, 0)) + this->gen_reg_load(rd+8+ traits::X0, 0), + this->gen_reg_load(rs2+8+ traits::X0, 0)) , - get_reg_ptr(rd+ 8 + traits::X0), false); + get_reg_ptr(rd+8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -3948,10 +3948,10 @@ private: /*generate behavior*/ this->builder.CreateStore( this->builder.CreateOr( - this->gen_reg_load(rd+ 8+ traits::X0, 0), - this->gen_reg_load(rs2+ 8+ traits::X0, 0)) + this->gen_reg_load(rd+8+ traits::X0, 0), + this->gen_reg_load(rs2+8+ traits::X0, 0)) , - get_reg_ptr(rd+ 8 + traits::X0), false); + get_reg_ptr(rd+8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -3987,10 +3987,10 @@ private: /*generate behavior*/ this->builder.CreateStore( this->builder.CreateAnd( - this->gen_reg_load(rd+ 8+ traits::X0, 0), - this->gen_reg_load(rs2+ 8+ traits::X0, 0)) + this->gen_reg_load(rd+8+ traits::X0, 0), + this->gen_reg_load(rs2+8+ traits::X0, 0)) , - get_reg_ptr(rd+ 8 + traits::X0), false); + get_reg_ptr(rd+8 + traits::X0), false); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -4062,8 +4062,8 @@ private: auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, - this->gen_reg_load(rs1+ 8+ traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32,false)) + this->gen_reg_load(rs1+8+ traits::X0, 0), + this->gen_ext(this->gen_const(8,0), 32,false)) , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { @@ -4109,8 +4109,8 @@ private: auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk); auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge); this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, - this->gen_reg_load(rs1+ 8+ traits::X0, 0), - this->gen_ext(this->gen_const(8, 0), 32,false)) + this->gen_reg_load(rs1+8+ traits::X0, 0), + this->gen_ext(this->gen_const(8,0), 32,false)) , 1), bb_then, bb_merge); this->builder.SetInsertPoint(bb_then); { @@ -4154,10 +4154,10 @@ private: /*generate behavior*/ if(rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rs1!= 0) { + if(rs1!=0) { this->builder.CreateStore( this->builder.CreateShl( this->gen_reg_load(rs1+ traits::X0, 0), @@ -4199,8 +4199,8 @@ private: this->gen_set_pc(pc, traits::NEXT_PC); /*generate behavior*/ - if(rd>=static_cast(traits::RFS)||rd== 0) { - this->gen_raise_trap(0, 2); + if(rd>=static_cast(traits::RFS)||rd==0) { + this->gen_raise_trap(0, 2); } else{ auto offs =this->gen_ext( @@ -4251,10 +4251,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_reg_load(rs2+ traits::X0, 0), get_reg_ptr(rd + traits::X0), false); @@ -4292,10 +4292,9 @@ private: this->gen_set_pc(pc, traits::NEXT_PC); /*generate behavior*/ - if(rs1&&rs1(traits::RFS)){ auto addr_mask =this->gen_const(32,(uint32_t)- 2); - auto PC_val_v = this->builder.CreateAnd( + if(rs1&&rs1(traits::RFS)){ auto PC_val_v = this->builder.CreateAnd( this->gen_reg_load(rs1%static_cast(traits::RFS)+ traits::X0, 0), - addr_mask) + this->gen_const(32,~ 1)) ; this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); @@ -4361,10 +4360,10 @@ private: /*generate behavior*/ if(rd>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { this->builder.CreateStore( this->gen_ext( (this->builder.CreateAdd( @@ -4408,17 +4407,16 @@ private: /*generate behavior*/ if(rs1>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ - auto addr_mask =this->gen_const(32,(uint32_t)- 2); auto new_pc =this->gen_reg_load(rs1+ traits::X0, 0); this->builder.CreateStore( - this->gen_const(32,(uint32_t)(PC+ 2)), + this->gen_const(32,(uint32_t)(PC+2)), get_reg_ptr(1 + traits::X0), false); auto PC_val_v = this->builder.CreateAnd( new_pc, - addr_mask) + this->gen_const(32,~ 1)) ; this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false); this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false); @@ -4446,7 +4444,7 @@ private: this->gen_set_pc(pc, traits::NEXT_PC); /*generate behavior*/ - this->gen_raise_trap(0, 3); + this->gen_raise_trap(0, 3); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); @@ -4481,7 +4479,7 @@ private: /*generate behavior*/ if(rs2>=static_cast(traits::RFS)) { - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); } else{ auto offs =this->gen_ext( @@ -4519,7 +4517,7 @@ private: this->gen_set_pc(pc, traits::NEXT_PC); /*generate behavior*/ - this->gen_raise_trap(0, 2); + this->gen_raise_trap(0, 2); bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk); auto returnValue = std::make_tuple(CONT,bb); diff --git a/src/vm/tcc/vm_tgc5c.cpp b/src/vm/tcc/vm_tgc5c.cpp index 9015757..88c7e9d 100644 --- a/src/vm/tcc/vm_tgc5c.cpp +++ b/src/vm/tcc/vm_tgc5c.cpp @@ -346,10 +346,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)imm),32)); } @@ -381,10 +381,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.constant((uint32_t)(PC+(int32_t)imm),32)); } @@ -416,15 +416,15 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, - tu.constant((uint32_t)(PC+ 4),32)); + tu.constant((uint32_t)(PC+4),32)); } auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int32_t)sext<21>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); @@ -459,7 +459,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto addr_mask = tu.assignment(tu.constant((uint32_t)- 2,32),32); @@ -471,11 +471,11 @@ private: tu.open_if(tu.urem( new_pc, tu.constant(static_cast(traits:: INSTR_ALIGNMENT),32))); - this->gen_raise_trap(tu, 0, 0); + this->gen_raise_trap(tu, 0, 0); tu.open_else(); - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, - tu.constant((uint32_t)(PC+ 4),32)); + tu.constant((uint32_t)(PC+4),32)); } auto PC_val_v = tu.assignment("PC_val", new_pc,32); tu.store(traits::NEXT_PC, PC_val_v); @@ -510,13 +510,13 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1+ traits::X0, 0), tu.load(rs2+ traits::X0, 0))); - if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); } else{ auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); @@ -553,13 +553,13 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs1+ traits::X0, 0), tu.load(rs2+ traits::X0, 0))); - if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); } else{ auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); @@ -596,13 +596,13 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ tu.open_if(tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1+ traits::X0, 0),32,true), tu.ext(tu.load(rs2+ traits::X0, 0),32,true))); - if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); } else{ auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); @@ -639,13 +639,13 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ tu.open_if(tu.icmp(ICmpInst::ICMP_SGE, tu.ext(tu.load(rs1+ traits::X0, 0),32,true), tu.ext(tu.load(rs2+ traits::X0, 0),32,true))); - if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); } else{ auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); @@ -682,13 +682,13 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ tu.open_if(tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1+ traits::X0, 0), tu.load(rs2+ traits::X0, 0))); - if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); } else{ auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); @@ -725,13 +725,13 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ tu.open_if(tu.icmp(ICmpInst::ICMP_UGE, tu.load(rs1+ traits::X0, 0), tu.load(rs2+ traits::X0, 0))); - if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); + if(imm%static_cast(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0); } else{ auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32); @@ -768,14 +768,14 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto load_address = tu.assignment(tu.ext((tu.add( tu.load(rs1+ traits::X0, 0), tu.constant((int16_t)sext<12>(imm),16))),32,false),32); auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 8),8,true),8); - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.ext(res,32,false)); } @@ -808,14 +808,14 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto load_address = tu.assignment(tu.ext((tu.add( tu.load(rs1+ traits::X0, 0), tu.constant((int16_t)sext<12>(imm),16))),32,false),32); auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 16),16,true),16); - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.ext(res,32,false)); } @@ -848,14 +848,14 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto load_address = tu.assignment(tu.ext((tu.add( tu.load(rs1+ traits::X0, 0), tu.constant((int16_t)sext<12>(imm),16))),32,false),32); auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 32),32,true),32); - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.ext(res,32,false)); } @@ -888,14 +888,14 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto load_address = tu.assignment(tu.ext((tu.add( tu.load(rs1+ traits::X0, 0), tu.constant((int16_t)sext<12>(imm),16))),32,false),32); auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 8),8); - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.ext(res,32,false)); } @@ -928,14 +928,14 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto load_address = tu.assignment(tu.ext((tu.add( tu.load(rs1+ traits::X0, 0), tu.constant((int16_t)sext<12>(imm),16))),32,false),32); auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 16),16); - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.ext(res,32,false)); } @@ -968,7 +968,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto store_address = tu.assignment(tu.ext((tu.add( @@ -1004,7 +1004,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto store_address = tu.assignment(tu.ext((tu.add( @@ -1040,7 +1040,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs2>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto store_address = tu.assignment(tu.ext((tu.add( @@ -1076,10 +1076,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.ext((tu.add( tu.load(rs1+ traits::X0, 0), @@ -1114,14 +1114,14 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1+ traits::X0, 0),32,true), - tu.constant((int16_t)sext<12>(imm),16))), tu.constant( 1,8),tu.constant( 0,8))); + tu.constant((int16_t)sext<12>(imm),16))), tu.constant(1,8),tu.constant(0,8))); } } auto returnValue = std::make_tuple(CONT); @@ -1152,14 +1152,14 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1+ traits::X0, 0), - tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))), tu.constant( 1,8),tu.constant( 0,8))); + tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))), tu.constant(1,8),tu.constant(0,8))); } } auto returnValue = std::make_tuple(CONT); @@ -1190,10 +1190,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.bitwise_xor( tu.load(rs1+ traits::X0, 0), @@ -1228,10 +1228,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.bitwise_or( tu.load(rs1+ traits::X0, 0), @@ -1266,10 +1266,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.bitwise_and( tu.load(rs1+ traits::X0, 0), @@ -1304,10 +1304,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.shl( tu.load(rs1+ traits::X0, 0), @@ -1342,10 +1342,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.lshr( tu.load(rs1+ traits::X0, 0), @@ -1380,10 +1380,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.ext((tu.ashr( tu.ext(tu.load(rs1+ traits::X0, 0),32,true), @@ -1418,10 +1418,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.ext((tu.add( tu.load(rs1+ traits::X0, 0), @@ -1456,10 +1456,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.ext((tu.sub( tu.load(rs1+ traits::X0, 0), @@ -1494,16 +1494,16 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.shl( tu.load(rs1+ traits::X0, 0), (tu.bitwise_and( tu.load(rs2+ traits::X0, 0), - tu.constant((static_cast(traits:: XLEN)- 1),64))))); + tu.constant((static_cast(traits:: XLEN)-1),64))))); } } auto returnValue = std::make_tuple(CONT); @@ -1534,14 +1534,14 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1+ traits::X0, 0),32,true), - tu.ext(tu.load(rs2+ traits::X0, 0),32,true)), tu.constant( 1,8),tu.constant( 0,8))); + tu.ext(tu.load(rs2+ traits::X0, 0),32,true)), tu.constant(1,8),tu.constant(0,8))); } } auto returnValue = std::make_tuple(CONT); @@ -1572,14 +1572,14 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1+ traits::X0, 0), - tu.load(rs2+ traits::X0, 0)), tu.constant( 1,8),tu.constant( 0,8))); + tu.load(rs2+ traits::X0, 0)), tu.constant(1,8),tu.constant(0,8))); } } auto returnValue = std::make_tuple(CONT); @@ -1610,10 +1610,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.bitwise_xor( tu.load(rs1+ traits::X0, 0), @@ -1648,16 +1648,16 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.lshr( tu.load(rs1+ traits::X0, 0), (tu.bitwise_and( tu.load(rs2+ traits::X0, 0), - tu.constant((static_cast(traits:: XLEN)- 1),64))))); + tu.constant((static_cast(traits:: XLEN)-1),64))))); } } auto returnValue = std::make_tuple(CONT); @@ -1688,16 +1688,16 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.ext((tu.ashr( tu.ext(tu.load(rs1+ traits::X0, 0),32,true), (tu.bitwise_and( tu.load(rs2+ traits::X0, 0), - tu.constant((static_cast(traits:: XLEN)- 1),64))))),32,false)); + tu.constant((static_cast(traits:: XLEN)-1),64))))),32,false)); } } auto returnValue = std::make_tuple(CONT); @@ -1728,10 +1728,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.bitwise_or( tu.load(rs1+ traits::X0, 0), @@ -1766,10 +1766,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.bitwise_and( tu.load(rs1+ traits::X0, 0), @@ -1805,7 +1805,7 @@ private: pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.write_mem(traits::FENCE, static_cast(traits:: fence), tu.constant((uint8_t)pred<< 4|succ,8)); + tu.write_mem(traits::FENCE, static_cast(traits:: fence), tu.constant((uint8_t)pred<<4|succ,8)); auto returnValue = std::make_tuple(CONT); tu.close_scope(); @@ -1827,7 +1827,7 @@ private: pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 11); + this->gen_raise_trap(tu, 0, 11); auto returnValue = std::make_tuple(TRAP); tu.close_scope(); @@ -1849,7 +1849,7 @@ private: pc=pc+ 4; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 3); + this->gen_raise_trap(tu, 0, 3); auto returnValue = std::make_tuple(TRAP); tu.close_scope(); @@ -1922,11 +1922,11 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32); - if(rd!= 0){ auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); + if(rd!=0){ auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); tu.write_mem(traits::CSR, csr, xrs1); tu.store(rd + traits::X0, xrd); @@ -1963,17 +1963,17 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32); - if(rs1!= 0) { + if(rs1!=0) { tu.write_mem(traits::CSR, csr, tu.bitwise_or( xrd, xrs1)); } - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, xrd); } @@ -2006,17 +2006,17 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32); - if(rs1!= 0) { + if(rs1!=0) { tu.write_mem(traits::CSR, csr, tu.bitwise_and( xrd, tu.logical_neg(xrs1))); } - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, xrd); } @@ -2049,12 +2049,12 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); tu.write_mem(traits::CSR, csr, tu.constant((uint32_t)zimm,32)); - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, xrd); } @@ -2087,16 +2087,16 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); - if(zimm!= 0) { + if(zimm!=0) { tu.write_mem(traits::CSR, csr, tu.bitwise_or( xrd, tu.constant((uint32_t)zimm,32))); } - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, xrd); } @@ -2129,16 +2129,16 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32); - if(zimm!= 0) { + if(zimm!=0) { tu.write_mem(traits::CSR, csr, tu.bitwise_and( xrd, tu.constant(~ ((uint32_t)zimm),32))); } - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, xrd); } @@ -2171,7 +2171,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); tu.write_mem(traits::FENCE, static_cast(traits:: fencei), tu.constant(imm,16)); - auto returnValue = std::make_tuple(CONT); + auto returnValue = std::make_tuple(FLUSH); tu.close_scope(); gen_trap_check(tu); @@ -2199,7 +2199,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto res = tu.assignment(tu.ext((tu.mul( @@ -2238,7 +2238,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto res = tu.assignment(tu.ext((tu.mul( @@ -2279,7 +2279,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto res = tu.assignment(tu.ext((tu.mul( @@ -2320,7 +2320,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto res = tu.assignment(tu.ext((tu.mul( @@ -2361,14 +2361,14 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto dividend = tu.assignment(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),32); auto divisor = tu.assignment(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),32); - if(rd!= 0){ tu.open_if(tu.icmp(ICmpInst::ICMP_NE, + if(rd!=0){ tu.open_if(tu.icmp(ICmpInst::ICMP_NE, divisor, - tu.constant( 0,8))); + tu.constant(0,8))); auto MMIN = tu.assignment(tu.constant(((uint32_t)1)<<(static_cast(traits:: XLEN)-1),32),32); tu.open_if(tu.logical_and( tu.icmp(ICmpInst::ICMP_EQ, @@ -2419,12 +2419,12 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2+ traits::X0, 0), - tu.constant( 0,8))); + tu.constant(0,8))); if(rd!=0) { tu.store(rd + traits::X0, tu.ext((tu.udiv( @@ -2466,12 +2466,12 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2+ traits::X0, 0), - tu.constant( 0,8))); + tu.constant(0,8))); auto MMIN = tu.assignment(tu.constant((uint32_t)1<<(static_cast(traits:: XLEN)-1),32),32); tu.open_if(tu.logical_and( tu.icmp(ICmpInst::ICMP_EQ, @@ -2482,7 +2482,7 @@ private: tu.constant(- 1,8)))); if(rd!=0) { tu.store(rd + traits::X0, - tu.constant( 0,8)); + tu.constant(0,8)); } tu.open_else(); if(rd!=0) { @@ -2527,12 +2527,12 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)||rs1>=static_cast(traits:: RFS)||rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2+ traits::X0, 0), - tu.constant( 0,8))); + tu.constant(0,8))); if(rd!=0) { tu.store(rd + traits::X0, tu.urem( @@ -2573,13 +2573,13 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(imm) { - tu.store(rd+ 8 + traits::X0, + tu.store(rd+8 + traits::X0, tu.ext((tu.add( tu.load(2+ traits::X0, 0), tu.constant(imm,16))),32,false)); } else{ - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } auto returnValue = std::make_tuple(CONT); @@ -2609,9 +2609,9 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); auto offs = tu.assignment(tu.ext((tu.add( - tu.load(rs1+ 8+ traits::X0, 0), + tu.load(rs1+8+ traits::X0, 0), tu.constant(uimm,8))),32,false),32); - tu.store(rd+ 8 + traits::X0, + tu.store(rd+8 + traits::X0, tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false)); auto returnValue = std::make_tuple(CONT); @@ -2641,9 +2641,9 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); auto offs = tu.assignment(tu.ext((tu.add( - tu.load(rs1+ 8+ traits::X0, 0), + tu.load(rs1+8+ traits::X0, 0), tu.constant(uimm,8))),32,false),32); - tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2+ 8+ traits::X0, 0),32,false)); + tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2+8+ traits::X0, 0),32,false)); auto returnValue = std::make_tuple(CONT); tu.close_scope(); @@ -2671,10 +2671,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rs1!= 0) { + if(rs1!=0) { tu.store(rs1 + traits::X0, tu.ext((tu.add( tu.load(rs1+ traits::X0, 0), @@ -2729,7 +2729,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); tu.store(1 + traits::X0, - tu.constant((uint32_t)(PC+ 2),32)); + tu.constant((uint32_t)(PC+2),32)); auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<12>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); @@ -2760,10 +2760,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.constant((uint32_t)((int8_t)sext<6>(imm)),32)); } @@ -2794,10 +2794,10 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(imm== 0||rd>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + if(imm==0||rd>=static_cast(traits:: RFS)) { + this->gen_raise_trap(tu, 0, 2); } - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)sext<18>(imm)),32)); } @@ -2833,7 +2833,7 @@ private: tu.constant((int16_t)sext<10>(nzimm),16))),32,false)); } else{ - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } auto returnValue = std::make_tuple(CONT); @@ -2857,7 +2857,7 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); auto returnValue = std::make_tuple(CONT); tu.close_scope(); @@ -2884,9 +2884,9 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rs1+ 8 + traits::X0, + tu.store(rs1+8 + traits::X0, tu.lshr( - tu.load(rs1+ 8+ traits::X0, 0), + tu.load(rs1+8+ traits::X0, 0), tu.constant(shamt,8))); auto returnValue = std::make_tuple(CONT); @@ -2914,16 +2914,16 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(shamt){ tu.store(rs1+ 8 + traits::X0, + if(shamt){ tu.store(rs1+8 + traits::X0, tu.ext((tu.ashr( - (tu.ext(tu.load(rs1+ 8+ traits::X0, 0),32,true)), + (tu.ext(tu.load(rs1+8+ traits::X0, 0),32,true)), tu.constant(shamt,8))),32,false)); } else{ - if(static_cast(traits:: XLEN)== 128){ tu.store(rs1+ 8 + traits::X0, + if(static_cast(traits:: XLEN)==128){ tu.store(rs1+8 + traits::X0, tu.ext((tu.ashr( - (tu.ext(tu.load(rs1+ 8+ traits::X0, 0),32,true)), - tu.constant( 64,8))),32,false)); + (tu.ext(tu.load(rs1+8+ traits::X0, 0),32,true)), + tu.constant(64,8))),32,false)); } } auto returnValue = std::make_tuple(CONT); @@ -2952,9 +2952,9 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rs1+ 8 + traits::X0, + tu.store(rs1+8 + traits::X0, tu.ext((tu.bitwise_and( - tu.load(rs1+ 8+ traits::X0, 0), + tu.load(rs1+8+ traits::X0, 0), tu.constant((int8_t)sext<6>(imm),8))),32,false)); auto returnValue = std::make_tuple(CONT); @@ -2982,10 +2982,10 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd+ 8 + traits::X0, + tu.store(rd+8 + traits::X0, tu.ext((tu.sub( - tu.load(rd+ 8+ traits::X0, 0), - tu.load(rs2+ 8+ traits::X0, 0))),32,false)); + tu.load(rd+8+ traits::X0, 0), + tu.load(rs2+8+ traits::X0, 0))),32,false)); auto returnValue = std::make_tuple(CONT); tu.close_scope(); @@ -3012,10 +3012,10 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd+ 8 + traits::X0, + tu.store(rd+8 + traits::X0, tu.bitwise_xor( - tu.load(rd+ 8+ traits::X0, 0), - tu.load(rs2+ 8+ traits::X0, 0))); + tu.load(rd+8+ traits::X0, 0), + tu.load(rs2+8+ traits::X0, 0))); auto returnValue = std::make_tuple(CONT); tu.close_scope(); @@ -3042,10 +3042,10 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd+ 8 + traits::X0, + tu.store(rd+8 + traits::X0, tu.bitwise_or( - tu.load(rd+ 8+ traits::X0, 0), - tu.load(rs2+ 8+ traits::X0, 0))); + tu.load(rd+8+ traits::X0, 0), + tu.load(rs2+8+ traits::X0, 0))); auto returnValue = std::make_tuple(CONT); tu.close_scope(); @@ -3072,10 +3072,10 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - tu.store(rd+ 8 + traits::X0, + tu.store(rd+8 + traits::X0, tu.bitwise_and( - tu.load(rd+ 8+ traits::X0, 0), - tu.load(rs2+ 8+ traits::X0, 0))); + tu.load(rd+8+ traits::X0, 0), + tu.load(rs2+8+ traits::X0, 0))); auto returnValue = std::make_tuple(CONT); tu.close_scope(); @@ -3131,8 +3131,8 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, - tu.load(rs1+ 8+ traits::X0, 0), - tu.constant( 0,8))); + tu.load(rs1+8+ traits::X0, 0), + tu.constant(0,8))); auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); @@ -3164,8 +3164,8 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); tu.open_if(tu.icmp(ICmpInst::ICMP_NE, - tu.load(rs1+ 8+ traits::X0, 0), - tu.constant( 0,8))); + tu.load(rs1+8+ traits::X0, 0), + tu.constant(0,8))); auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); @@ -3197,10 +3197,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rs1!= 0) { + if(rs1!=0) { tu.store(rs1 + traits::X0, tu.shl( tu.load(rs1+ traits::X0, 0), @@ -3233,8 +3233,8 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rd>=static_cast(traits:: RFS)||rd== 0) { - this->gen_raise_trap(tu, 0, 2); + if(rd>=static_cast(traits:: RFS)||rd==0) { + this->gen_raise_trap(tu, 0, 2); } else{ auto offs = tu.assignment(tu.ext((tu.add( @@ -3270,10 +3270,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.load(rs2+ traits::X0, 0)); } @@ -3303,12 +3303,11 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - if(rs1&&rs1(traits:: RFS)) { - auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and( - tu.load(rs1%static_cast(traits:: RFS)+ traits::X0, 0), - tu.constant(~ 0x1,8)),32); - tu.store(traits::NEXT_PC, PC_val_v); - tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); + if(rs1&&rs1(traits:: RFS)){ auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and( + tu.load(rs1%static_cast(traits:: RFS)+ traits::X0, 0), + tu.constant(~ 1,32)),32); + tu.store(traits::NEXT_PC, PC_val_v); + tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); } else{ this->gen_raise_trap(tu, 0, 2); @@ -3362,10 +3361,10 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rd>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ - if(rd!= 0) { + if(rd!=0) { tu.store(rd + traits::X0, tu.ext((tu.add( tu.load(rd+ traits::X0, 0), @@ -3398,15 +3397,15 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs1>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto new_pc = tu.assignment(tu.load(rs1+ traits::X0, 0),32); tu.store(1 + traits::X0, - tu.constant((uint32_t)(PC+ 2),32)); + tu.constant((uint32_t)(PC+2),32)); auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and( new_pc, - tu.constant(~ 0x1,8)),32); + tu.constant(~ 1,32)),32); tu.store(traits::NEXT_PC, PC_val_v); tu.store(traits::LAST_BRANCH, tu.constant(2U, 2)); } @@ -3431,7 +3430,7 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 3); + this->gen_raise_trap(tu, 0, 3); auto returnValue = std::make_tuple(CONT); tu.close_scope(); @@ -3459,7 +3458,7 @@ private: gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); if(rs2>=static_cast(traits:: RFS)) { - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); } else{ auto offs = tu.assignment(tu.ext((tu.add( @@ -3488,7 +3487,7 @@ private: pc=pc+ 2; gen_set_pc(tu, pc, traits::NEXT_PC); tu.open_scope(); - this->gen_raise_trap(tu, 0, 2); + this->gen_raise_trap(tu, 0, 2); auto returnValue = std::make_tuple(CONT); tu.close_scope(); From 58fb815f329b92fc8cb71ebaa9ccbc0db8e23620 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Mon, 20 May 2024 10:34:23 +0200 Subject: [PATCH 26/33] fixes gen_raise in tcc --- gen_input/templates/tcc/CORENAME.cpp.gtl | 2 +- src/vm/tcc/vm_tgc5c.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gen_input/templates/tcc/CORENAME.cpp.gtl b/gen_input/templates/tcc/CORENAME.cpp.gtl index e378bb6..f9ee677 100644 --- a/gen_input/templates/tcc/CORENAME.cpp.gtl +++ b/gen_input/templates/tcc/CORENAME.cpp.gtl @@ -292,7 +292,7 @@ vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, template void vm_impl::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) { tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id); - tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits::max(), 32)); + tu.store(traits::NEXT_PC, tu.constant(std::numeric_limits::max(), 32)); } template void vm_impl::gen_leave_trap(tu_builder& tu, unsigned lvl) { diff --git a/src/vm/tcc/vm_tgc5c.cpp b/src/vm/tcc/vm_tgc5c.cpp index 88c7e9d..77033cd 100644 --- a/src/vm/tcc/vm_tgc5c.cpp +++ b/src/vm/tcc/vm_tgc5c.cpp @@ -3611,7 +3611,7 @@ vm_impl::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, template void vm_impl::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) { tu(" *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id); - tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits::max(), 32)); + tu.store(traits::NEXT_PC, tu.constant(std::numeric_limits::max(), 32)); } template void vm_impl::gen_leave_trap(tu_builder& tu, unsigned lvl) { From ed793471bbae48f3fa4aa485670f3e658226f02f Mon Sep 17 00:00:00 2001 From: gabriel Date: Fri, 31 May 2024 07:27:47 +0200 Subject: [PATCH 27/33] adding semhosting --- src/iss/arch/riscv_hart_m_p.h | 6 +- src/iss/arch/riscv_hart_mu_p.h | 6 +- src/iss/semihosting/semihosting.cpp | 210 +++- src/iss/semihosting/semihosting.h | 9 +- src/main.cpp | 3 +- src/vm/asmjit/vm_tgc5c.cpp | 4 +- src/vm/interp/vm_tgc5c.cpp | 4 +- src/vm/tcc/vm_tgc5c.cpp | 4 +- src_test/iss/arch/tgc5a.cpp | 70 ++ src_test/iss/arch/tgc5a.h | 209 ++++ src_test/iss/arch/tgc5b.cpp | 70 ++ src_test/iss/arch/tgc5b.h | 225 ++++ src_test/vm/interp/vm_tgc5a.cpp | 1776 +++++++++++++++++++++++++++ src_test/vm/interp/vm_tgc5b.cpp | 1776 +++++++++++++++++++++++++++ 14 files changed, 4335 insertions(+), 37 deletions(-) create mode 100644 src_test/iss/arch/tgc5a.cpp create mode 100644 src_test/iss/arch/tgc5a.h create mode 100644 src_test/iss/arch/tgc5b.cpp create mode 100644 src_test/iss/arch/tgc5b.h create mode 100644 src_test/vm/interp/vm_tgc5a.cpp create mode 100644 src_test/vm/interp/vm_tgc5b.cpp diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 99a7f06..c487f2b 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -292,7 +292,7 @@ public: void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); } - void set_semihosting_callback(std::function& cb) { semihosting_cb = cb; }; + void set_semihosting_callback(semihosting_cb_t cb) { semihosting_cb = cb; }; protected: struct riscv_instrumentation_if : public iss::instrumentation_if { @@ -351,7 +351,7 @@ protected: bool tohost_lower_written = false; riscv_instrumentation_if instr_if; - std::function semihosting_cb; + semihosting_cb_t semihosting_cb; using mem_type = util::sparse_array; using csr_type = util::sparse_array::reg_t, 1ULL << 12, 12>; @@ -1283,7 +1283,7 @@ template uint64_t riscv_hart_m_p::e #endif CLOG(INFO, disass) << "Semihosting call at address " << buffer.data() << " occurred "; - semihosting_callback(this, this->reg.X10 /*a0*/, this->reg.X11 /*a1*/); + semihosting_cb(this, &(this->reg.X10) /*a0*/, &(this->reg.X11) /*a1*/); return this->reg.NEXT_PC; } } diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 362fece..1f6051f 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -319,7 +319,7 @@ public: void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); } - void set_semihosting_callback(std::function& cb) { semihosting_cb = cb; }; + void set_semihosting_callback(semihosting_cb_t cb) { semihosting_cb = cb; }; protected: struct riscv_instrumentation_if : public iss::instrumentation_if { @@ -378,7 +378,7 @@ protected: bool tohost_lower_written = false; riscv_instrumentation_if instr_if; - std::function semihosting_cb; + semihosting_cb_t semihosting_cb; using mem_type = util::sparse_array; using csr_type = util::sparse_array::reg_t, 1ULL << 12, 12>; @@ -1505,7 +1505,7 @@ template uint64_t riscv_hart_mu_p:: #endif CLOG(INFO, disass) << "Semihosting call at address " << buffer.data() << " occurred "; - semihosting_callback(this, this->reg.X10 /*a0*/, this->reg.X11 /*a1*/); + semihosting_cb(this, &(this->reg.X10) /*a0*/, &(this->reg.X11) /*a1*/); return this->reg.NEXT_PC; } } diff --git a/src/iss/semihosting/semihosting.cpp b/src/iss/semihosting/semihosting.cpp index 00124fb..af7006e 100644 --- a/src/iss/semihosting/semihosting.cpp +++ b/src/iss/semihosting/semihosting.cpp @@ -1,16 +1,61 @@ #include "semihosting.h" #include +#include #include #include +#include // explanation of syscalls can be found at https://github.com/SpinalHDL/openocd_riscv/blob/riscv_spinal/src/target/semihosting_common.h -template void semihosting_callback(iss::arch_if* arch_if_ptr, T call_number, T parameter) { - switch(static_cast(call_number)) { + +const char *SYS_OPEN_MODES_STRS[] = { "r", "rb", "r+", "r+b", "w", "wb", "w+", "w+b", "a", "ab", "a+", "a+b" }; + +template T sh_read_field(iss::arch_if* arch_if_ptr, T addr, int len=4) { + uint8_t bytes[4]; + auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr, 4, &bytes[0]); + //auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character); + + if(res != iss::Ok){ + return 0; //TODO THROW ERROR + } else return static_cast(bytes[0]) | (static_cast(bytes[1]) << 8) | (static_cast(bytes[2]) << 16) | (static_cast(bytes[3]) << 24); +} + +template std::string sh_read_string(iss::arch_if* arch_if_ptr, T addr, T str_len){ + std::vector buffer(str_len); + for (int i = 0; i < str_len; i++ ) { + buffer[i] = sh_read_field(arch_if_ptr, addr + i, 1); + } + std::string str(buffer.begin(), buffer.end()); + return str; +} + + +template void semihosting_callback::operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter) { + static std::map openFiles; + static T file_count = 3; + static T semihostingErrno; + + switch(static_cast(*call_number)) { case semihosting_syscalls::SYS_CLOCK: { - throw std::runtime_error("Semihosting Call not Implemented"); + auto end = std::chrono::high_resolution_clock::now(); // end measurement + auto elapsed = end - timeVar; + auto millis = std::chrono::duration_cast(elapsed).count(); + *call_number = millis; //TODO get time now break; } case semihosting_syscalls::SYS_CLOSE: { - throw std::runtime_error("Semihosting Call not Implemented"); + T file_handle = *parameter; + if (openFiles.size() <= file_handle && file_handle < 0) { + semihostingErrno = EBADF; + return; + } + auto file = openFiles[file_handle]; + openFiles.erase(file_handle); + if (!(file == stdin || file == stdout || file == stderr)) { + int i = fclose(file); + *call_number = i; + } else { + *call_number = -1; + semihostingErrno = EINTR; + } break; } case semihosting_syscalls::SYS_ELAPSED: { @@ -18,7 +63,7 @@ template void semihosting_callback(iss::arch_if* arch_if_ptr, T cal break; } case semihosting_syscalls::SYS_ERRNO: { - throw std::runtime_error("Semihosting Call not Implemented"); + *call_number = semihostingErrno; break; } case semihosting_syscalls::SYS_EXIT: { @@ -31,7 +76,15 @@ template void semihosting_callback(iss::arch_if* arch_if_ptr, T cal break; } case semihosting_syscalls::SYS_FLEN: { - throw std::runtime_error("Semihosting Call not Implemented"); + T file_handle = *parameter; + auto file = openFiles[file_handle]; + + size_t currentPos = ftell(file); + if (currentPos < 0) throw std::runtime_error("SYS_FLEN negative value"); + fseek(file, 0, SEEK_END); + size_t length = ftell(file); + fseek(file, currentPos, SEEK_SET); + *call_number = (T)length; break; } case semihosting_syscalls::SYS_GET_CMDLINE: { @@ -43,39 +96,127 @@ template void semihosting_callback(iss::arch_if* arch_if_ptr, T cal break; } case semihosting_syscalls::SYS_ISERROR: { - throw std::runtime_error("Semihosting Call not Implemented"); + T value = *parameter; + *call_number = (value != 0); break; } case semihosting_syscalls::SYS_ISTTY: { - throw std::runtime_error("Semihosting Call not Implemented"); + T file_handle = *parameter; + *call_number = (file_handle == 0 || file_handle == 1 || file_handle == 2); break; } case semihosting_syscalls::SYS_OPEN: { - throw std::runtime_error("Semihosting Call not Implemented"); + T path_str_addr = sh_read_field(arch_if_ptr, *parameter); + T mode = sh_read_field(arch_if_ptr, 4+(*parameter)); + T path_len = sh_read_field(arch_if_ptr, 8+(*parameter)); + + std::string path_str = sh_read_string(arch_if_ptr, path_str_addr, path_len); + + //TODO LOG INFO + + if (mode >= 12) { + //TODO throw ERROR + return; + } + + FILE *file = nullptr; + if(path_str == ":tt") { + if (mode < 4) + file = stdin; + else if (mode < 8) + file = stdout; + else + file = stderr; + } else { + file = fopen(path_str.c_str(), SYS_OPEN_MODES_STRS[mode]); + if (file == nullptr) { + //TODO throw error + return; + } + } + T file_handle = file_count++; + openFiles[file_handle] = file; + *call_number = file_handle; break; + } case semihosting_syscalls::SYS_READ: { - throw std::runtime_error("Semihosting Call not Implemented"); + T file_handle = sh_read_field(arch_if_ptr, (*parameter)+4); + T addr = sh_read_field(arch_if_ptr, *parameter); + T count = sh_read_field(arch_if_ptr, (*parameter)+8); + + auto file = openFiles[file_handle]; + + std::vector buffer(count); + size_t num_read = 0; + if (file == stdin) + { + // when reading from stdin: mimic behaviour from read syscall + // and return on newline. + while (num_read < count) + { + char c = fgetc(file); + buffer[num_read] = c; + num_read++; + if (c == '\n') + break; + } + } else { + num_read = fread(buffer.data(), 1, count, file); + } + buffer.resize(num_read); + for(int i = 0; iwrite(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr+i, 1, &buffer[i]); + if(res != iss::Ok) + return; + } + *call_number = count - num_read; break; + } case semihosting_syscalls::SYS_READC: { - throw std::runtime_error("Semihosting Call not Implemented"); + uint8_t character = getchar(); + //character = getchar(); + /*if(character != iss::Ok) + std::cout << "Not OK"; + return;*/ + *call_number = character; break; } case semihosting_syscalls::SYS_REMOVE: { - throw std::runtime_error("Semihosting Call not Implemented"); + T path_str_addr = sh_read_field(arch_if_ptr, *parameter); + T path_len = sh_read_field(arch_if_ptr, (*parameter)+4); + std::string path_str = sh_read_string(arch_if_ptr, path_str_addr, path_len); + + if(remove(path_str.c_str())<0) *call_number = -1; break; } case semihosting_syscalls::SYS_RENAME: { - throw std::runtime_error("Semihosting Call not Implemented"); + T path_str_addr_old = sh_read_field(arch_if_ptr, *parameter); + T path_len_old = sh_read_field(arch_if_ptr, (*parameter)+4); + T path_str_addr_new = sh_read_field(arch_if_ptr, (*parameter)+8); + T path_len_new = sh_read_field(arch_if_ptr, (*parameter)+12); + + std::string path_str_old = sh_read_string(arch_if_ptr, path_str_addr_old, path_len_old); + std::string path_str_new = sh_read_string(arch_if_ptr, path_str_addr_new, path_len_new); + rename(path_str_old.c_str(), path_str_new.c_str()); break; } case semihosting_syscalls::SYS_SEEK: { - throw std::runtime_error("Semihosting Call not Implemented"); + T file_handle = sh_read_field(arch_if_ptr, *parameter); + T pos = sh_read_field(arch_if_ptr, (*parameter)+1); + auto file = openFiles[file_handle]; + + int retval = fseek(file, pos, SEEK_SET); + if(retval<0) throw std::runtime_error("SYS_SEEK negative return value"); + break; } case semihosting_syscalls::SYS_SYSTEM: { - throw std::runtime_error("Semihosting Call not Implemented"); + T cmd_addr = sh_read_field(arch_if_ptr, *parameter); + T cmd_len = sh_read_field(arch_if_ptr, (*parameter)+1); + std::string cmd = sh_read_string(arch_if_ptr, cmd_addr, cmd_len); + system(cmd.c_str()); break; } case semihosting_syscalls::SYS_TICKFREQ: { @@ -83,20 +224,43 @@ template void semihosting_callback(iss::arch_if* arch_if_ptr, T cal break; } case semihosting_syscalls::SYS_TIME: { - throw std::runtime_error("Semihosting Call not Implemented"); + //returns time in seconds scince 01.01.1970 00:00 + *call_number = time(NULL); break; } case semihosting_syscalls::SYS_TMPNAM: { - throw std::runtime_error("Semihosting Call not Implemented"); + T buffer_addr = sh_read_field(arch_if_ptr, *parameter); + T identifier = sh_read_field(arch_if_ptr, (*parameter)+1); + T buffer_len = sh_read_field(arch_if_ptr, (*parameter)+2); + + if (identifier > 255) { + *call_number = -1; + return; + } + std::stringstream ss; + ss << "tmp/file-" << std::setfill('0') << std::setw(3) << identifier; + std::string filename = ss.str(); + + for(int i = 0; i < buffer_len; i++) { + uint8_t character = filename[i]; + auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, (*parameter)+i, 1, &character); + if(res != iss::Ok) return; + } break; } case semihosting_syscalls::SYS_WRITE: { - throw std::runtime_error("Semihosting Call not Implemented"); + T file_handle = sh_read_field(arch_if_ptr, (*parameter)+4); + T addr = sh_read_field(arch_if_ptr, *parameter); + T count = sh_read_field(arch_if_ptr, (*parameter)+8); + + auto file = openFiles[file_handle]; + std::string str = sh_read_string(arch_if_ptr, addr, count); + fwrite(&str[0], 1, count, file); break; } case semihosting_syscalls::SYS_WRITEC: { uint8_t character; - auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, parameter, 1, &character); + auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character); if(res != iss::Ok) return; putchar(character); @@ -105,13 +269,13 @@ template void semihosting_callback(iss::arch_if* arch_if_ptr, T cal case semihosting_syscalls::SYS_WRITE0: { uint8_t character; while(1) { - auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, parameter, 1, &character); + auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character); if(res != iss::Ok) return; if(character == 0) break; putchar(character); - parameter++; + (*parameter)++; } break; } @@ -128,5 +292,5 @@ template void semihosting_callback(iss::arch_if* arch_if_ptr, T cal break; } } -template void semihosting_callback(iss::arch_if* arch_if_ptr, uint32_t call_number, uint32_t parameter); -template void semihosting_callback(iss::arch_if* arch_if_ptr, uint64_t call_number, uint64_t parameter); +template class semihosting_callback; +template class semihosting_callback; diff --git a/src/iss/semihosting/semihosting.h b/src/iss/semihosting/semihosting.h index e551f78..295c4d4 100644 --- a/src/iss/semihosting/semihosting.h +++ b/src/iss/semihosting/semihosting.h @@ -1,6 +1,8 @@ #ifndef _SEMIHOSTING_H_ #define _SEMIHOSTING_H_ #include +#include +#include /* * According to: * "Semihosting for AArch32 and AArch64, Release 2.0" @@ -48,6 +50,11 @@ enum class semihosting_syscalls { USER_CMD_0x1FF = 0x1FF, }; -template void semihosting_callback(iss::arch_if* arch_if_ptr, T call_number, T parameter); +template struct semihosting_callback{ + std::chrono::high_resolution_clock::time_point timeVar; + semihosting_callback(): timeVar(std::chrono::high_resolution_clock::now()) {} + void operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter); +}; +template using semihosting_cb_t = std::function; #endif \ No newline at end of file diff --git a/src/main.cpp b/src/main.cpp index aad92da..950a685 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -117,7 +117,8 @@ int main(int argc, char* argv[]) { // instantiate the simulator iss::vm_ptr vm{nullptr}; iss::cpu_ptr cpu{nullptr}; - std::function semihosting_cb = &semihosting_callback; + semihosting_callback cb{}; + semihosting_cb_t semihosting_cb = [&cb](iss::arch_if* i, uint32_t* a0, uint32_t* a1) {cb(i,a0,a1);}; std::string isa_opt(clim["isa"].as()); if(isa_opt.size() == 0 || isa_opt == "?") { auto list = f.get_names(); diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp index 497cc1e..5b5d779 100644 --- a/src/vm/asmjit/vm_tgc5c.cpp +++ b/src/vm/asmjit/vm_tgc5c.cpp @@ -3757,7 +3757,7 @@ volatile std::array dummy = { auto vm = new asmjit::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; @@ -3767,7 +3767,7 @@ volatile std::array dummy = { auto vm = new asmjit::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index 10b6296..6b80f2e 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -2700,7 +2700,7 @@ volatile std::array dummy = { auto vm = new interp::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; @@ -2710,7 +2710,7 @@ volatile std::array dummy = { auto vm = new interp::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; diff --git a/src/vm/tcc/vm_tgc5c.cpp b/src/vm/tcc/vm_tgc5c.cpp index 9015757..b58d1cb 100644 --- a/src/vm/tcc/vm_tgc5c.cpp +++ b/src/vm/tcc/vm_tgc5c.cpp @@ -3654,7 +3654,7 @@ volatile std::array dummy = { auto vm = new tcc::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; @@ -3664,7 +3664,7 @@ volatile std::array dummy = { auto vm = new tcc::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; diff --git a/src_test/iss/arch/tgc5a.cpp b/src_test/iss/arch/tgc5a.cpp new file mode 100644 index 0000000..0f4f6ad --- /dev/null +++ b/src_test/iss/arch/tgc5a.cpp @@ -0,0 +1,70 @@ +/******************************************************************************* + * Copyright (C) 2017 - 2020 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +// clang-format off +#include "tgc5a.h" +#include "util/ities.h" +#include +#include +#include +#include + +using namespace iss::arch; + +constexpr std::array iss::arch::traits::reg_names; +constexpr std::array iss::arch::traits::reg_aliases; +constexpr std::array iss::arch::traits::reg_bit_widths; +constexpr std::array iss::arch::traits::reg_byte_offsets; + +tgc5a::tgc5a() = default; + +tgc5a::~tgc5a() = default; + +void tgc5a::reset(uint64_t address) { + auto base_ptr = reinterpret_cast::reg_t*>(get_regs_base_ptr()); + for(size_t i=0; i::NUM_REGS; ++i) + *(base_ptr+i)=0; + reg.PC=address; + reg.NEXT_PC=reg.PC; + reg.PRIV=0x3; + reg.trap_state=0; + reg.icount=0; +} + +uint8_t *tgc5a::get_regs_base_ptr() { + return reinterpret_cast(®); +} + +tgc5a::phys_addr_t tgc5a::virt2phys(const iss::addr_t &addr) { + return phys_addr_t(addr.access, addr.space, addr.val&traits::addr_mask); +} +// clang-format on diff --git a/src_test/iss/arch/tgc5a.h b/src_test/iss/arch/tgc5a.h new file mode 100644 index 0000000..4389f3f --- /dev/null +++ b/src_test/iss/arch/tgc5a.h @@ -0,0 +1,209 @@ +/******************************************************************************* + * Copyright (C) 2017 - 2021 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +#ifndef _TGC5A_H_ +#define _TGC5A_H_ +// clang-format off +#include +#include +#include +#include + +namespace iss { +namespace arch { + +struct tgc5a; + +template <> struct traits { + + constexpr static char const* const core_type = "TGC5A"; + + static constexpr std::array reg_names{ + {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "pc", "next_pc", "priv", "dpc"}}; + + static constexpr std::array reg_aliases{ + {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "pc", "next_pc", "priv", "dpc"}}; + + enum constants {MISA_VAL=1073741840ULL, MARCHID_VAL=2147483649ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=4ULL, RFS=16ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL}; + + constexpr static unsigned FP_REGS_SIZE = 0; + + enum reg_e { + X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH + }; + + using reg_t = uint32_t; + + using addr_t = uint32_t; + + using code_word_t = uint32_t; //TODO: check removal + + using virt_addr_t = iss::typed_addr_t; + + using phys_addr_t = iss::typed_addr_t; + + static constexpr std::array reg_bit_widths{ + {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}}; + + static constexpr std::array reg_byte_offsets{ + {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,73,77,81,85,93,101,109,113}}; + + static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); + + enum sreg_flag_e { FLAGS }; + + enum mem_type_e { MEM, FENCE, RES, CSR }; + + enum class opcode_e { + LUI = 0, + AUIPC = 1, + JAL = 2, + JALR = 3, + BEQ = 4, + BNE = 5, + BLT = 6, + BGE = 7, + BLTU = 8, + BGEU = 9, + LB = 10, + LH = 11, + LW = 12, + LBU = 13, + LHU = 14, + SB = 15, + SH = 16, + SW = 17, + ADDI = 18, + SLTI = 19, + SLTIU = 20, + XORI = 21, + ORI = 22, + ANDI = 23, + SLLI = 24, + SRLI = 25, + SRAI = 26, + ADD = 27, + SUB = 28, + SLL = 29, + SLT = 30, + SLTU = 31, + XOR = 32, + SRL = 33, + SRA = 34, + OR = 35, + AND = 36, + FENCE = 37, + ECALL = 38, + EBREAK = 39, + MRET = 40, + WFI = 41, + CSRRW = 42, + CSRRS = 43, + CSRRC = 44, + CSRRWI = 45, + CSRRSI = 46, + CSRRCI = 47, + FENCE_I = 48, + MAX_OPCODE + }; +}; + +struct tgc5a: public arch_if { + + using virt_addr_t = typename traits::virt_addr_t; + using phys_addr_t = typename traits::phys_addr_t; + using reg_t = typename traits::reg_t; + using addr_t = typename traits::addr_t; + + tgc5a(); + ~tgc5a(); + + void reset(uint64_t address=0) override; + + uint8_t* get_regs_base_ptr() override; + + inline uint64_t get_icount() { return reg.icount; } + + inline bool should_stop() { return interrupt_sim; } + + inline uint64_t stop_code() { return interrupt_sim; } + + virtual phys_addr_t virt2phys(const iss::addr_t& addr); + + virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } + + inline uint32_t get_last_branch() { return reg.last_branch; } + + +#pragma pack(push, 1) + struct TGC5A_regs { + uint32_t X0 = 0; + uint32_t X1 = 0; + uint32_t X2 = 0; + uint32_t X3 = 0; + uint32_t X4 = 0; + uint32_t X5 = 0; + uint32_t X6 = 0; + uint32_t X7 = 0; + uint32_t X8 = 0; + uint32_t X9 = 0; + uint32_t X10 = 0; + uint32_t X11 = 0; + uint32_t X12 = 0; + uint32_t X13 = 0; + uint32_t X14 = 0; + uint32_t X15 = 0; + uint32_t PC = 0; + uint32_t NEXT_PC = 0; + uint8_t PRIV = 0; + uint32_t DPC = 0; + uint32_t trap_state = 0, pending_trap = 0; + uint64_t icount = 0; + uint64_t cycle = 0; + uint64_t instret = 0; + uint32_t instruction = 0; + uint32_t last_branch = 0; + } reg; +#pragma pack(pop) + std::array addr_mode; + + uint64_t interrupt_sim=0; + + uint32_t get_fcsr(){return 0;} + void set_fcsr(uint32_t val){} + +}; + +} +} +#endif /* _TGC5A_H_ */ +// clang-format on diff --git a/src_test/iss/arch/tgc5b.cpp b/src_test/iss/arch/tgc5b.cpp new file mode 100644 index 0000000..3b80493 --- /dev/null +++ b/src_test/iss/arch/tgc5b.cpp @@ -0,0 +1,70 @@ +/******************************************************************************* + * Copyright (C) 2017 - 2020 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +// clang-format off +#include "tgc5b.h" +#include "util/ities.h" +#include +#include +#include +#include + +using namespace iss::arch; + +constexpr std::array iss::arch::traits::reg_names; +constexpr std::array iss::arch::traits::reg_aliases; +constexpr std::array iss::arch::traits::reg_bit_widths; +constexpr std::array iss::arch::traits::reg_byte_offsets; + +tgc5b::tgc5b() = default; + +tgc5b::~tgc5b() = default; + +void tgc5b::reset(uint64_t address) { + auto base_ptr = reinterpret_cast::reg_t*>(get_regs_base_ptr()); + for(size_t i=0; i::NUM_REGS; ++i) + *(base_ptr+i)=0; + reg.PC=address; + reg.NEXT_PC=reg.PC; + reg.PRIV=0x3; + reg.trap_state=0; + reg.icount=0; +} + +uint8_t *tgc5b::get_regs_base_ptr() { + return reinterpret_cast(®); +} + +tgc5b::phys_addr_t tgc5b::virt2phys(const iss::addr_t &addr) { + return phys_addr_t(addr.access, addr.space, addr.val&traits::addr_mask); +} +// clang-format on diff --git a/src_test/iss/arch/tgc5b.h b/src_test/iss/arch/tgc5b.h new file mode 100644 index 0000000..7e407c5 --- /dev/null +++ b/src_test/iss/arch/tgc5b.h @@ -0,0 +1,225 @@ +/******************************************************************************* + * Copyright (C) 2017 - 2021 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +#ifndef _TGC5B_H_ +#define _TGC5B_H_ +// clang-format off +#include +#include +#include +#include + +namespace iss { +namespace arch { + +struct tgc5b; + +template <> struct traits { + + constexpr static char const* const core_type = "TGC5B"; + + static constexpr std::array reg_names{ + {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}}; + + static constexpr std::array reg_aliases{ + {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}}; + + enum constants {MISA_VAL=1073742080ULL, MARCHID_VAL=2147483650ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=4ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL}; + + constexpr static unsigned FP_REGS_SIZE = 0; + + enum reg_e { + X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH + }; + + using reg_t = uint32_t; + + using addr_t = uint32_t; + + using code_word_t = uint32_t; //TODO: check removal + + using virt_addr_t = iss::typed_addr_t; + + using phys_addr_t = iss::typed_addr_t; + + static constexpr std::array reg_bit_widths{ + {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}}; + + static constexpr std::array reg_byte_offsets{ + {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}}; + + static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); + + enum sreg_flag_e { FLAGS }; + + enum mem_type_e { MEM, FENCE, RES, CSR }; + + enum class opcode_e { + LUI = 0, + AUIPC = 1, + JAL = 2, + JALR = 3, + BEQ = 4, + BNE = 5, + BLT = 6, + BGE = 7, + BLTU = 8, + BGEU = 9, + LB = 10, + LH = 11, + LW = 12, + LBU = 13, + LHU = 14, + SB = 15, + SH = 16, + SW = 17, + ADDI = 18, + SLTI = 19, + SLTIU = 20, + XORI = 21, + ORI = 22, + ANDI = 23, + SLLI = 24, + SRLI = 25, + SRAI = 26, + ADD = 27, + SUB = 28, + SLL = 29, + SLT = 30, + SLTU = 31, + XOR = 32, + SRL = 33, + SRA = 34, + OR = 35, + AND = 36, + FENCE = 37, + ECALL = 38, + EBREAK = 39, + MRET = 40, + WFI = 41, + CSRRW = 42, + CSRRS = 43, + CSRRC = 44, + CSRRWI = 45, + CSRRSI = 46, + CSRRCI = 47, + FENCE_I = 48, + MAX_OPCODE + }; +}; + +struct tgc5b: public arch_if { + + using virt_addr_t = typename traits::virt_addr_t; + using phys_addr_t = typename traits::phys_addr_t; + using reg_t = typename traits::reg_t; + using addr_t = typename traits::addr_t; + + tgc5b(); + ~tgc5b(); + + void reset(uint64_t address=0) override; + + uint8_t* get_regs_base_ptr() override; + + inline uint64_t get_icount() { return reg.icount; } + + inline bool should_stop() { return interrupt_sim; } + + inline uint64_t stop_code() { return interrupt_sim; } + + virtual phys_addr_t virt2phys(const iss::addr_t& addr); + + virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } + + inline uint32_t get_last_branch() { return reg.last_branch; } + + +#pragma pack(push, 1) + struct TGC5B_regs { + uint32_t X0 = 0; + uint32_t X1 = 0; + uint32_t X2 = 0; + uint32_t X3 = 0; + uint32_t X4 = 0; + uint32_t X5 = 0; + uint32_t X6 = 0; + uint32_t X7 = 0; + uint32_t X8 = 0; + uint32_t X9 = 0; + uint32_t X10 = 0; + uint32_t X11 = 0; + uint32_t X12 = 0; + uint32_t X13 = 0; + uint32_t X14 = 0; + uint32_t X15 = 0; + uint32_t X16 = 0; + uint32_t X17 = 0; + uint32_t X18 = 0; + uint32_t X19 = 0; + uint32_t X20 = 0; + uint32_t X21 = 0; + uint32_t X22 = 0; + uint32_t X23 = 0; + uint32_t X24 = 0; + uint32_t X25 = 0; + uint32_t X26 = 0; + uint32_t X27 = 0; + uint32_t X28 = 0; + uint32_t X29 = 0; + uint32_t X30 = 0; + uint32_t X31 = 0; + uint32_t PC = 0; + uint32_t NEXT_PC = 0; + uint8_t PRIV = 0; + uint32_t DPC = 0; + uint32_t trap_state = 0, pending_trap = 0; + uint64_t icount = 0; + uint64_t cycle = 0; + uint64_t instret = 0; + uint32_t instruction = 0; + uint32_t last_branch = 0; + } reg; +#pragma pack(pop) + std::array addr_mode; + + uint64_t interrupt_sim=0; + + uint32_t get_fcsr(){return 0;} + void set_fcsr(uint32_t val){} + +}; + +} +} +#endif /* _TGC5B_H_ */ +// clang-format on diff --git a/src_test/vm/interp/vm_tgc5a.cpp b/src_test/vm/interp/vm_tgc5a.cpp new file mode 100644 index 0000000..875e5a7 --- /dev/null +++ b/src_test/vm/interp/vm_tgc5a.cpp @@ -0,0 +1,1776 @@ +/******************************************************************************* + * Copyright (C) 2021 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +// clang-format off +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef FMT_HEADER_ONLY +#define FMT_HEADER_ONLY +#endif +#include + +#include +#include + +namespace iss { +namespace interp { +namespace tgc5a { +using namespace iss::arch; +using namespace iss::debugger; +using namespace std::placeholders; + +struct memory_access_exception : public std::exception{ + memory_access_exception(){} +}; + +template class vm_impl : public iss::interp::vm_base { +public: + using traits = arch::traits; + using super = typename iss::interp::vm_base; + using virt_addr_t = typename super::virt_addr_t; + using phys_addr_t = typename super::phys_addr_t; + using code_word_t = typename super::code_word_t; + using addr_t = typename super::addr_t; + using reg_t = typename traits::reg_t; + using mem_type_e = typename traits::mem_type_e; + using opcode_e = typename traits::opcode_e; + + vm_impl(); + + vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); + + void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } + + target_adapter_if *accquire_target_adapter(server_if *srv) override { + debugger_if::dbg_enabled = true; + if (super::tgt_adapter == nullptr) + super::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); + return super::tgt_adapter; + } + +protected: + using this_class = vm_impl; + using compile_ret_t = virt_addr_t; + using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr); + + inline const char *name(size_t index){return indexcore.reg.trap_state = trap_val; + this->template get_reg(traits::NEXT_PC) = std::numeric_limits::max(); + } + + inline void leave(unsigned lvl){ + this->core.leave_trap(lvl); + } + + inline void wait(unsigned type){ + this->core.wait_until(type); + } + + using yield_t = boost::coroutines2::coroutine::push_type; + using coro_t = boost::coroutines2::coroutine::pull_type; + std::vector spawn_blocks; + + template::type> + inline S sext(U from) { + auto mask = (1ULL<::opcode_e op; + }; + struct decoding_tree_node{ + std::vector instrs; + std::vector children; + uint32_t submask = std::numeric_limits::max(); + uint32_t value; + decoding_tree_node(uint32_t value) : value(value){} + }; + + decoding_tree_node* root {nullptr}; + const std::array instr_descr = {{ + /* entries are: size, valid value, valid mask, function ptr */ + {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits::opcode_e::LUI}, + {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits::opcode_e::AUIPC}, + {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, arch::traits::opcode_e::JAL}, + {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::JALR}, + {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BEQ}, + {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BNE}, + {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLT}, + {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGE}, + {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLTU}, + {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGEU}, + {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LB}, + {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LH}, + {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LW}, + {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LBU}, + {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LHU}, + {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SB}, + {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SH}, + {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SW}, + {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ADDI}, + {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTI}, + {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTIU}, + {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::XORI}, + {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ORI}, + {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ANDI}, + {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLLI}, + {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRLI}, + {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRAI}, + {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::ADD}, + {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SUB}, + {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLL}, + {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLT}, + {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLTU}, + {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::XOR}, + {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRL}, + {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRA}, + {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::OR}, + {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::AND}, + {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE}, + {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::ECALL}, + {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::EBREAK}, + {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::MRET}, + {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::WFI}, + {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRW}, + {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRS}, + {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRC}, + {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRWI}, + {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRSI}, + {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRCI}, + {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE_I}, + }}; + + iss::status fetch_ins(virt_addr_t pc, uint8_t * data){ + if(this->core.has_mmu()) { + auto phys_pc = this->core.virt2phys(pc); +// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary +// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err; +// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction +// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) +// return iss::Err; +// } else { + if (this->core.read(phys_pc, 4, data) != iss::Ok) + return iss::Err; +// } + } else { + if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok) + return iss::Err; + + } + return iss::Ok; + } + + void populate_decoding_tree(decoding_tree_node* root){ + //create submask + for(auto instr: root->instrs){ + root->submask &= instr.mask; + } + //put each instr according to submask&encoding into children + for(auto instr: root->instrs){ + bool foundMatch = false; + for(auto child: root->children){ + //use value as identifying trait + if(child->value == (instr.value&root->submask)){ + child->instrs.push_back(instr); + foundMatch = true; + } + } + if(!foundMatch){ + decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask); + child->instrs.push_back(instr); + root->children.push_back(child); + } + } + root->instrs.clear(); + //call populate_decoding_tree for all children + if(root->children.size() >1) + for(auto child: root->children){ + populate_decoding_tree(child); + } + else{ + //sort instrs by value of the mask, this works bc we want to have the least restrictive one last + std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { + return instr1.mask > instr2.mask; + }); + } + } + typename arch::traits::opcode_e decode_instr(decoding_tree_node* node, code_word_t word){ + if(!node->children.size()){ + if(node->instrs.size() == 1) return node->instrs[0].op; + for(auto instr : node->instrs){ + if((instr.mask&word) == instr.value) return instr.op; + } + } + else{ + for(auto child : node->children){ + if (child->value == (node->submask&word)){ + return decode_instr(child, word); + } + } + } + return arch::traits::opcode_e::MAX_OPCODE; + } +}; + +template void debug_fn(CODE_WORD insn) { + volatile CODE_WORD x = insn; + insn = 2 * x; +} + +template vm_impl::vm_impl() { this(new ARCH()); } + +// according to +// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation +#ifdef __GCC__ +constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); } +#elif __cplusplus < 201402L +constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); } +constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; } +#else +constexpr size_t bit_count(uint32_t u) { + size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); + return ((uCount + (uCount >> 3)) & 030707070707) % 63; +} +#endif + +template +vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) +: vm_base(core, core_id, cluster_id) { + root = new decoding_tree_node(std::numeric_limits::max()); + for(auto instr:instr_descr){ + root->instrs.push_back(instr); + } + populate_decoding_tree(root); +} + +inline bool is_count_limit_enabled(finish_cond_e cond){ + return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT; +} + +inline bool is_jump_to_self_enabled(finish_cond_e cond){ + return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF; +} + +template +typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){ + auto pc=start; + auto* PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::PC]); + auto* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); + auto& trap_state = this->core.reg.trap_state; + auto& icount = this->core.reg.icount; + auto& cycle = this->core.reg.cycle; + auto& instret = this->core.reg.instret; + auto& instr = this->core.reg.instruction; + // we fetch at max 4 byte, alignment is 2 + auto *const data = reinterpret_cast(&instr); + + while(!this->core.should_stop() && + !(is_count_limit_enabled(cond) && icount >= icount_limit)){ + if(fetch_ins(pc, data)!=iss::Ok){ + this->do_sync(POST_SYNC, std::numeric_limits::max()); + pc.val = super::core.enter_trap(std::numeric_limits::max(), pc.val, 0); + } else { + if (is_jump_to_self_enabled(cond) && + (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' + auto inst_id = decode_instr(root, instr); + // pre execution stuff + this->core.reg.last_branch = 0; + if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast(inst_id)); + try{ + switch(inst_id){ + case arch::traits::opcode_e::LUI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((int32_t)imm); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AUIPC: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*PC + (int32_t)imm); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::JAL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*PC + 4); + } + *NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm)); + this->core.reg.last_branch = 1; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::JALR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t addr_mask = (uint32_t)- 2; + uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & addr_mask); + if(new_pc % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*PC + 4); + } + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BEQ: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(*(X+rs1) == *(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BNE: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(*(X+rs1) != *(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BLT: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BGE: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BLTU: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(*(X+rs1) < *(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BGEU: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(*(X+rs1) >= *(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LB: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + int8_t res_23 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int8_t res = (int8_t)res_23; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LH: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + int16_t res_24 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int16_t res = (int16_t)res_24; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + int32_t res_25 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int32_t res = (int32_t)res_25; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LBU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint8_t res_26 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint8_t res = res_26; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LHU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint16_t res_27 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint16_t res = res_27; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SB: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + super::template write_mem(traits::MEM, store_address, (uint8_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SH: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + super::template write_mem(traits::MEM, store_address, (uint16_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SW: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + super::template write_mem(traits::MEM, store_address, (uint32_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ADDI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTIU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::XORI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) ^ (uint32_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ORI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) | (uint32_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ANDI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) & (uint32_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) << shamt; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) >> shamt; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRAI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ADD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SUB: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLT: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::XOR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) ^ *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRA: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::OR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) | *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AND: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) & *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FENCE: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); + uint8_t fm = ((bit_sub<28,4>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), + fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + super::template write_mem(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ECALL: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + this->core.disass_output(pc.val, "ecall"); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + raise(0, 11); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::EBREAK: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + this->core.disass_output(pc.val, "ebreak"); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + raise(0, 3); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MRET: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + this->core.disass_output(pc.val, "mret"); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + leave(3); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::WFI: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + this->core.disass_output(pc.val, "wfi"); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + wait(1); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t xrs1 = *(X+rs1); + if(rd != 0) { + uint32_t res_28 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_28; + super::template write_mem(traits::CSR, csr, xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = xrd; + } + else { + super::template write_mem(traits::CSR, csr, xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRS: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t res_29 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_29; + uint32_t xrs1 = *(X+rs1); + if(rs1 != 0) { + super::template write_mem(traits::CSR, csr, xrd | xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRC: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t res_30 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_30; + uint32_t xrs1 = *(X+rs1); + if(rs1 != 0) { + super::template write_mem(traits::CSR, csr, xrd & ~ xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRWI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t res_31 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_31; + super::template write_mem(traits::CSR, csr, (uint32_t)zimm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRSI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t res_32 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_32; + if(zimm != 0) { + super::template write_mem(traits::CSR, csr, xrd | (uint32_t)zimm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRCI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t res_33 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_33; + if(zimm != 0) { + super::template write_mem(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FENCE_I: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), + fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + super::template write_mem(traits::FENCE, traits::fencei, imm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + default: { + *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2); + raise(0, 2); + } + } + }catch(memory_access_exception& e){} + // post execution stuff + process_spawn_blocks(); + if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast(inst_id)); + // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt + // this->core.reg.trap_state = this->core.reg.pending_trap; + // trap check + if(trap_state!=0){ + super::core.enter_trap(trap_state, pc.val, instr); + } else { + icount++; + instret++; + } + cycle++; + pc.val=*NEXT_PC; + this->core.reg.PC = this->core.reg.NEXT_PC; + this->core.reg.trap_state = this->core.reg.pending_trap; + } + } + return pc; +} + +} // namespace tgc5a + +template <> +std::unique_ptr create(arch::tgc5a *core, unsigned short port, bool dump) { + auto ret = new tgc5a::vm_impl(*core, dump); + if (port != 0) debugger::server::run_server(ret, port); + return std::unique_ptr(ret); +} +} // namespace interp +} // namespace iss + +#include +#include +#include +namespace iss { +namespace { +volatile std::array dummy = { + core_factory::instance().register_creator("tgc5a|m_p|interp", [](unsigned port, void*) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_m_p(); + auto vm = new interp::tgc5a::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("tgc5a|mu_p|interp", [](unsigned port, void*) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_mu_p(); + auto vm = new interp::tgc5a::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }) +}; +} +} +// clang-format on \ No newline at end of file diff --git a/src_test/vm/interp/vm_tgc5b.cpp b/src_test/vm/interp/vm_tgc5b.cpp new file mode 100644 index 0000000..98fb681 --- /dev/null +++ b/src_test/vm/interp/vm_tgc5b.cpp @@ -0,0 +1,1776 @@ +/******************************************************************************* + * Copyright (C) 2021 MINRES Technologies GmbH + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ + +// clang-format off +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef FMT_HEADER_ONLY +#define FMT_HEADER_ONLY +#endif +#include + +#include +#include + +namespace iss { +namespace interp { +namespace tgc5b { +using namespace iss::arch; +using namespace iss::debugger; +using namespace std::placeholders; + +struct memory_access_exception : public std::exception{ + memory_access_exception(){} +}; + +template class vm_impl : public iss::interp::vm_base { +public: + using traits = arch::traits; + using super = typename iss::interp::vm_base; + using virt_addr_t = typename super::virt_addr_t; + using phys_addr_t = typename super::phys_addr_t; + using code_word_t = typename super::code_word_t; + using addr_t = typename super::addr_t; + using reg_t = typename traits::reg_t; + using mem_type_e = typename traits::mem_type_e; + using opcode_e = typename traits::opcode_e; + + vm_impl(); + + vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); + + void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } + + target_adapter_if *accquire_target_adapter(server_if *srv) override { + debugger_if::dbg_enabled = true; + if (super::tgt_adapter == nullptr) + super::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); + return super::tgt_adapter; + } + +protected: + using this_class = vm_impl; + using compile_ret_t = virt_addr_t; + using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr); + + inline const char *name(size_t index){return indexcore.reg.trap_state = trap_val; + this->template get_reg(traits::NEXT_PC) = std::numeric_limits::max(); + } + + inline void leave(unsigned lvl){ + this->core.leave_trap(lvl); + } + + inline void wait(unsigned type){ + this->core.wait_until(type); + } + + using yield_t = boost::coroutines2::coroutine::push_type; + using coro_t = boost::coroutines2::coroutine::pull_type; + std::vector spawn_blocks; + + template::type> + inline S sext(U from) { + auto mask = (1ULL<::opcode_e op; + }; + struct decoding_tree_node{ + std::vector instrs; + std::vector children; + uint32_t submask = std::numeric_limits::max(); + uint32_t value; + decoding_tree_node(uint32_t value) : value(value){} + }; + + decoding_tree_node* root {nullptr}; + const std::array instr_descr = {{ + /* entries are: size, valid value, valid mask, function ptr */ + {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits::opcode_e::LUI}, + {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits::opcode_e::AUIPC}, + {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, arch::traits::opcode_e::JAL}, + {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::JALR}, + {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BEQ}, + {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BNE}, + {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLT}, + {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGE}, + {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLTU}, + {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGEU}, + {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LB}, + {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LH}, + {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LW}, + {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LBU}, + {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LHU}, + {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SB}, + {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SH}, + {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SW}, + {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ADDI}, + {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTI}, + {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTIU}, + {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::XORI}, + {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ORI}, + {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ANDI}, + {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLLI}, + {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRLI}, + {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRAI}, + {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::ADD}, + {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SUB}, + {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLL}, + {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLT}, + {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLTU}, + {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::XOR}, + {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRL}, + {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRA}, + {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::OR}, + {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::AND}, + {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE}, + {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::ECALL}, + {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::EBREAK}, + {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::MRET}, + {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::WFI}, + {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRW}, + {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRS}, + {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRC}, + {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRWI}, + {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRSI}, + {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRCI}, + {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE_I}, + }}; + + iss::status fetch_ins(virt_addr_t pc, uint8_t * data){ + if(this->core.has_mmu()) { + auto phys_pc = this->core.virt2phys(pc); +// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary +// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err; +// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction +// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) +// return iss::Err; +// } else { + if (this->core.read(phys_pc, 4, data) != iss::Ok) + return iss::Err; +// } + } else { + if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok) + return iss::Err; + + } + return iss::Ok; + } + + void populate_decoding_tree(decoding_tree_node* root){ + //create submask + for(auto instr: root->instrs){ + root->submask &= instr.mask; + } + //put each instr according to submask&encoding into children + for(auto instr: root->instrs){ + bool foundMatch = false; + for(auto child: root->children){ + //use value as identifying trait + if(child->value == (instr.value&root->submask)){ + child->instrs.push_back(instr); + foundMatch = true; + } + } + if(!foundMatch){ + decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask); + child->instrs.push_back(instr); + root->children.push_back(child); + } + } + root->instrs.clear(); + //call populate_decoding_tree for all children + if(root->children.size() >1) + for(auto child: root->children){ + populate_decoding_tree(child); + } + else{ + //sort instrs by value of the mask, this works bc we want to have the least restrictive one last + std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { + return instr1.mask > instr2.mask; + }); + } + } + typename arch::traits::opcode_e decode_instr(decoding_tree_node* node, code_word_t word){ + if(!node->children.size()){ + if(node->instrs.size() == 1) return node->instrs[0].op; + for(auto instr : node->instrs){ + if((instr.mask&word) == instr.value) return instr.op; + } + } + else{ + for(auto child : node->children){ + if (child->value == (node->submask&word)){ + return decode_instr(child, word); + } + } + } + return arch::traits::opcode_e::MAX_OPCODE; + } +}; + +template void debug_fn(CODE_WORD insn) { + volatile CODE_WORD x = insn; + insn = 2 * x; +} + +template vm_impl::vm_impl() { this(new ARCH()); } + +// according to +// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation +#ifdef __GCC__ +constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); } +#elif __cplusplus < 201402L +constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); } +constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; } +#else +constexpr size_t bit_count(uint32_t u) { + size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); + return ((uCount + (uCount >> 3)) & 030707070707) % 63; +} +#endif + +template +vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) +: vm_base(core, core_id, cluster_id) { + root = new decoding_tree_node(std::numeric_limits::max()); + for(auto instr:instr_descr){ + root->instrs.push_back(instr); + } + populate_decoding_tree(root); +} + +inline bool is_count_limit_enabled(finish_cond_e cond){ + return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT; +} + +inline bool is_jump_to_self_enabled(finish_cond_e cond){ + return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF; +} + +template +typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){ + auto pc=start; + auto* PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::PC]); + auto* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); + auto& trap_state = this->core.reg.trap_state; + auto& icount = this->core.reg.icount; + auto& cycle = this->core.reg.cycle; + auto& instret = this->core.reg.instret; + auto& instr = this->core.reg.instruction; + // we fetch at max 4 byte, alignment is 2 + auto *const data = reinterpret_cast(&instr); + + while(!this->core.should_stop() && + !(is_count_limit_enabled(cond) && icount >= icount_limit)){ + if(fetch_ins(pc, data)!=iss::Ok){ + this->do_sync(POST_SYNC, std::numeric_limits::max()); + pc.val = super::core.enter_trap(std::numeric_limits::max(), pc.val, 0); + } else { + if (is_jump_to_self_enabled(cond) && + (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' + auto inst_id = decode_instr(root, instr); + // pre execution stuff + this->core.reg.last_branch = 0; + if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast(inst_id)); + try{ + switch(inst_id){ + case arch::traits::opcode_e::LUI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((int32_t)imm); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AUIPC: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*PC + (int32_t)imm); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::JAL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*PC + 4); + } + *NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm)); + this->core.reg.last_branch = 1; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::JALR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t addr_mask = (uint32_t)- 2; + uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & addr_mask); + if(new_pc % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*PC + 4); + } + *NEXT_PC = new_pc; + this->core.reg.last_branch = 1; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BEQ: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(*(X+rs1) == *(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BNE: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(*(X+rs1) != *(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BLT: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BGE: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BLTU: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(*(X+rs1) < *(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::BGEU: { + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), + fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(*(X+rs1) >= *(X+rs2)) { + if(imm % traits::INSTR_ALIGNMENT) { + raise(0, 0); + } + else { + *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); + this->core.reg.last_branch = 1; + } + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LB: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + int8_t res_23 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int8_t res = (int8_t)res_23; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LH: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + int16_t res_24 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int16_t res = (int16_t)res_24; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + int32_t res_25 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + int32_t res = (int32_t)res_25; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LBU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint8_t res_26 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint8_t res = res_26; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::LHU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), + fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + uint16_t res_27 = super::template read_mem(traits::MEM, load_address); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint16_t res = res_27; + if(rd != 0) { + *(X+rd) = (uint32_t)res; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SB: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + super::template write_mem(traits::MEM, store_address, (uint8_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SH: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + super::template write_mem(traits::MEM, store_address, (uint16_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SW: { + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), + fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rs2 >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + super::template write_mem(traits::MEM, store_address, (uint32_t)*(X+rs2)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ADDI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTIU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::XORI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) ^ (uint32_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ORI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) | (uint32_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ANDI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) & (uint32_t)((int16_t)sext<12>(imm)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) << shamt; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRLI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) >> shamt; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRAI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ADD: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SUB: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLT: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SLTU: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::XOR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) ^ *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRL: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::SRA: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1))); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::OR: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) | *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::AND: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t rs2 = ((bit_sub<20,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { + raise(0, 2); + } + else { + if(rd != 0) { + *(X+rd) = *(X+rs1) & *(X+rs2); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FENCE: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t succ = ((bit_sub<20,4>(instr))); + uint8_t pred = ((bit_sub<24,4>(instr))); + uint8_t fm = ((bit_sub<28,4>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), + fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + super::template write_mem(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::ECALL: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + this->core.disass_output(pc.val, "ecall"); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + raise(0, 11); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::EBREAK: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + this->core.disass_output(pc.val, "ebreak"); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + raise(0, 3); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::MRET: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + this->core.disass_output(pc.val, "mret"); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + leave(3); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::WFI: { + if(this->disass_enabled){ + /* generate console output when executing the command */ + this->core.disass_output(pc.val, "wfi"); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + wait(1); + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRW: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t xrs1 = *(X+rs1); + if(rd != 0) { + uint32_t res_28 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_28; + super::template write_mem(traits::CSR, csr, xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + *(X+rd) = xrd; + } + else { + super::template write_mem(traits::CSR, csr, xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRS: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t res_29 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_29; + uint32_t xrs1 = *(X+rs1); + if(rs1 != 0) { + super::template write_mem(traits::CSR, csr, xrd | xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRC: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS || rs1 >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t res_30 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_30; + uint32_t xrs1 = *(X+rs1); + if(rs1 != 0) { + super::template write_mem(traits::CSR, csr, xrd & ~ xrs1); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRWI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t res_31 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_31; + super::template write_mem(traits::CSR, csr, (uint32_t)zimm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRSI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t res_32 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_32; + if(zimm != 0) { + super::template write_mem(traits::CSR, csr, xrd | (uint32_t)zimm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::CSRRCI: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t zimm = ((bit_sub<15,5>(instr))); + uint16_t csr = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), + fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers + auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + if(rd >= traits::RFS) { + raise(0, 2); + } + else { + uint32_t res_33 = super::template read_mem(traits::CSR, csr); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + uint32_t xrd = res_33; + if(zimm != 0) { + super::template write_mem(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + if(rd != 0) { + *(X+rd) = xrd; + } + } + } + break; + }// @suppress("No break at end of case") + case arch::traits::opcode_e::FENCE_I: { + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), + fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); + this->core.disass_output(pc.val, mnemonic); + } + // used registers// calculate next pc value + *NEXT_PC = *PC + 4; + // execute instruction + { + super::template write_mem(traits::FENCE, traits::fencei, imm); + if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); + } + break; + }// @suppress("No break at end of case") + default: { + *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2); + raise(0, 2); + } + } + }catch(memory_access_exception& e){} + // post execution stuff + process_spawn_blocks(); + if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast(inst_id)); + // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt + // this->core.reg.trap_state = this->core.reg.pending_trap; + // trap check + if(trap_state!=0){ + super::core.enter_trap(trap_state, pc.val, instr); + } else { + icount++; + instret++; + } + cycle++; + pc.val=*NEXT_PC; + this->core.reg.PC = this->core.reg.NEXT_PC; + this->core.reg.trap_state = this->core.reg.pending_trap; + } + } + return pc; +} + +} // namespace tgc5b + +template <> +std::unique_ptr create(arch::tgc5b *core, unsigned short port, bool dump) { + auto ret = new tgc5b::vm_impl(*core, dump); + if (port != 0) debugger::server::run_server(ret, port); + return std::unique_ptr(ret); +} +} // namespace interp +} // namespace iss + +#include +#include +#include +namespace iss { +namespace { +volatile std::array dummy = { + core_factory::instance().register_creator("tgc5b|m_p|interp", [](unsigned port, void*) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_m_p(); + auto vm = new interp::tgc5b::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }), + core_factory::instance().register_creator("tgc5b|mu_p|interp", [](unsigned port, void*) -> std::tuple{ + auto* cpu = new iss::arch::riscv_hart_mu_p(); + auto vm = new interp::tgc5b::vm_impl(*cpu, false); + if (port != 0) debugger::server::run_server(vm, port); + return {cpu_ptr{cpu}, vm_ptr{vm}}; + }) +}; +} +} +// clang-format on \ No newline at end of file From 1e30b68507d1a0a1be398289da78e4b24ffbf56c Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Fri, 31 May 2024 09:37:19 +0200 Subject: [PATCH 28/33] updates min cmake version --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 994aff2..2a46f47 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.12) +cmake_minimum_required(VERSION 3.18) list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake) # ############################################################################## From 41051f8f3445c6617c092019d6adb362b31d2f83 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Fri, 31 May 2024 10:43:38 +0200 Subject: [PATCH 29/33] fixes tohost handling --- src/iss/arch/riscv_hart_m_p.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 3b17016..dfbef36 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -293,7 +293,7 @@ public: void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); } - void set_semihosting_callback(semihosting_cb_t cb) { semihosting_cb = cb; }; + void set_semihosting_callback(semihosting_cb_t cb) { semihosting_cb = cb; }; protected: struct riscv_instrumentation_if : public iss::instrumentation_if { @@ -354,7 +354,7 @@ protected: bool tohost_lower_written = false; riscv_instrumentation_if instr_if; - semihosting_cb_t semihosting_cb; + semihosting_cb_t semihosting_cb; using mem_type = util::sparse_array; using csr_type = util::sparse_array::reg_t, 1ULL << 12, 12>; @@ -1125,9 +1125,6 @@ iss::status riscv_hart_m_p::write_mem(phys_addr_t paddr, unsigned le } this->reg.trap_state = std::numeric_limits::max(); this->interrupt_sim = hostvar; -#ifndef WITH_TCC - // throw(iss::simulation_stopped(hostvar)); -#endif break; case 0x0101: { char c = static_cast(hostvar & 0xff); From e2da306eee8b1fd581ec124aebab153889460144 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Fri, 31 May 2024 10:45:28 +0200 Subject: [PATCH 30/33] fixes semihosting cb registration --- gen_input/templates/llvm/CORENAME.cpp.gtl | 4 ++-- src/vm/llvm/vm_tgc5c.cpp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gen_input/templates/llvm/CORENAME.cpp.gtl b/gen_input/templates/llvm/CORENAME.cpp.gtl index 1b13101..9bbd147 100644 --- a/gen_input/templates/llvm/CORENAME.cpp.gtl +++ b/gen_input/templates/llvm/CORENAME.cpp.gtl @@ -373,7 +373,7 @@ volatile std::array dummy = { auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t*, arch::traits::reg_t*)>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; @@ -383,7 +383,7 @@ volatile std::array dummy = { auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t*, arch::traits::reg_t*)>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; diff --git a/src/vm/llvm/vm_tgc5c.cpp b/src/vm/llvm/vm_tgc5c.cpp index 1212037..aa4d9a0 100644 --- a/src/vm/llvm/vm_tgc5c.cpp +++ b/src/vm/llvm/vm_tgc5c.cpp @@ -4722,7 +4722,7 @@ volatile std::array dummy = { auto vm = new llvm::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t*, arch::traits::reg_t*)>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; @@ -4732,7 +4732,7 @@ volatile std::array dummy = { auto vm = new llvm::tgc5c::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t*, arch::traits::reg_t*)>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; From 37db31fb4b4cd9b1b633ce0834a7cd2e4d71a106 Mon Sep 17 00:00:00 2001 From: Eyck-Alexander Jentzsch Date: Fri, 31 May 2024 10:46:19 +0200 Subject: [PATCH 31/33] removes repo that should not be checked in --- src_test/iss/arch/tgc5a.cpp | 70 -- src_test/iss/arch/tgc5a.h | 209 ---- src_test/iss/arch/tgc5b.cpp | 70 -- src_test/iss/arch/tgc5b.h | 225 ---- src_test/vm/interp/vm_tgc5a.cpp | 1776 ------------------------------- src_test/vm/interp/vm_tgc5b.cpp | 1776 ------------------------------- 6 files changed, 4126 deletions(-) delete mode 100644 src_test/iss/arch/tgc5a.cpp delete mode 100644 src_test/iss/arch/tgc5a.h delete mode 100644 src_test/iss/arch/tgc5b.cpp delete mode 100644 src_test/iss/arch/tgc5b.h delete mode 100644 src_test/vm/interp/vm_tgc5a.cpp delete mode 100644 src_test/vm/interp/vm_tgc5b.cpp diff --git a/src_test/iss/arch/tgc5a.cpp b/src_test/iss/arch/tgc5a.cpp deleted file mode 100644 index 0f4f6ad..0000000 --- a/src_test/iss/arch/tgc5a.cpp +++ /dev/null @@ -1,70 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017 - 2020 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -// clang-format off -#include "tgc5a.h" -#include "util/ities.h" -#include -#include -#include -#include - -using namespace iss::arch; - -constexpr std::array iss::arch::traits::reg_names; -constexpr std::array iss::arch::traits::reg_aliases; -constexpr std::array iss::arch::traits::reg_bit_widths; -constexpr std::array iss::arch::traits::reg_byte_offsets; - -tgc5a::tgc5a() = default; - -tgc5a::~tgc5a() = default; - -void tgc5a::reset(uint64_t address) { - auto base_ptr = reinterpret_cast::reg_t*>(get_regs_base_ptr()); - for(size_t i=0; i::NUM_REGS; ++i) - *(base_ptr+i)=0; - reg.PC=address; - reg.NEXT_PC=reg.PC; - reg.PRIV=0x3; - reg.trap_state=0; - reg.icount=0; -} - -uint8_t *tgc5a::get_regs_base_ptr() { - return reinterpret_cast(®); -} - -tgc5a::phys_addr_t tgc5a::virt2phys(const iss::addr_t &addr) { - return phys_addr_t(addr.access, addr.space, addr.val&traits::addr_mask); -} -// clang-format on diff --git a/src_test/iss/arch/tgc5a.h b/src_test/iss/arch/tgc5a.h deleted file mode 100644 index 4389f3f..0000000 --- a/src_test/iss/arch/tgc5a.h +++ /dev/null @@ -1,209 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017 - 2021 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _TGC5A_H_ -#define _TGC5A_H_ -// clang-format off -#include -#include -#include -#include - -namespace iss { -namespace arch { - -struct tgc5a; - -template <> struct traits { - - constexpr static char const* const core_type = "TGC5A"; - - static constexpr std::array reg_names{ - {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "pc", "next_pc", "priv", "dpc"}}; - - static constexpr std::array reg_aliases{ - {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "pc", "next_pc", "priv", "dpc"}}; - - enum constants {MISA_VAL=1073741840ULL, MARCHID_VAL=2147483649ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=4ULL, RFS=16ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL}; - - constexpr static unsigned FP_REGS_SIZE = 0; - - enum reg_e { - X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH - }; - - using reg_t = uint32_t; - - using addr_t = uint32_t; - - using code_word_t = uint32_t; //TODO: check removal - - using virt_addr_t = iss::typed_addr_t; - - using phys_addr_t = iss::typed_addr_t; - - static constexpr std::array reg_bit_widths{ - {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}}; - - static constexpr std::array reg_byte_offsets{ - {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,73,77,81,85,93,101,109,113}}; - - static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); - - enum sreg_flag_e { FLAGS }; - - enum mem_type_e { MEM, FENCE, RES, CSR }; - - enum class opcode_e { - LUI = 0, - AUIPC = 1, - JAL = 2, - JALR = 3, - BEQ = 4, - BNE = 5, - BLT = 6, - BGE = 7, - BLTU = 8, - BGEU = 9, - LB = 10, - LH = 11, - LW = 12, - LBU = 13, - LHU = 14, - SB = 15, - SH = 16, - SW = 17, - ADDI = 18, - SLTI = 19, - SLTIU = 20, - XORI = 21, - ORI = 22, - ANDI = 23, - SLLI = 24, - SRLI = 25, - SRAI = 26, - ADD = 27, - SUB = 28, - SLL = 29, - SLT = 30, - SLTU = 31, - XOR = 32, - SRL = 33, - SRA = 34, - OR = 35, - AND = 36, - FENCE = 37, - ECALL = 38, - EBREAK = 39, - MRET = 40, - WFI = 41, - CSRRW = 42, - CSRRS = 43, - CSRRC = 44, - CSRRWI = 45, - CSRRSI = 46, - CSRRCI = 47, - FENCE_I = 48, - MAX_OPCODE - }; -}; - -struct tgc5a: public arch_if { - - using virt_addr_t = typename traits::virt_addr_t; - using phys_addr_t = typename traits::phys_addr_t; - using reg_t = typename traits::reg_t; - using addr_t = typename traits::addr_t; - - tgc5a(); - ~tgc5a(); - - void reset(uint64_t address=0) override; - - uint8_t* get_regs_base_ptr() override; - - inline uint64_t get_icount() { return reg.icount; } - - inline bool should_stop() { return interrupt_sim; } - - inline uint64_t stop_code() { return interrupt_sim; } - - virtual phys_addr_t virt2phys(const iss::addr_t& addr); - - virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - - inline uint32_t get_last_branch() { return reg.last_branch; } - - -#pragma pack(push, 1) - struct TGC5A_regs { - uint32_t X0 = 0; - uint32_t X1 = 0; - uint32_t X2 = 0; - uint32_t X3 = 0; - uint32_t X4 = 0; - uint32_t X5 = 0; - uint32_t X6 = 0; - uint32_t X7 = 0; - uint32_t X8 = 0; - uint32_t X9 = 0; - uint32_t X10 = 0; - uint32_t X11 = 0; - uint32_t X12 = 0; - uint32_t X13 = 0; - uint32_t X14 = 0; - uint32_t X15 = 0; - uint32_t PC = 0; - uint32_t NEXT_PC = 0; - uint8_t PRIV = 0; - uint32_t DPC = 0; - uint32_t trap_state = 0, pending_trap = 0; - uint64_t icount = 0; - uint64_t cycle = 0; - uint64_t instret = 0; - uint32_t instruction = 0; - uint32_t last_branch = 0; - } reg; -#pragma pack(pop) - std::array addr_mode; - - uint64_t interrupt_sim=0; - - uint32_t get_fcsr(){return 0;} - void set_fcsr(uint32_t val){} - -}; - -} -} -#endif /* _TGC5A_H_ */ -// clang-format on diff --git a/src_test/iss/arch/tgc5b.cpp b/src_test/iss/arch/tgc5b.cpp deleted file mode 100644 index 3b80493..0000000 --- a/src_test/iss/arch/tgc5b.cpp +++ /dev/null @@ -1,70 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017 - 2020 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -// clang-format off -#include "tgc5b.h" -#include "util/ities.h" -#include -#include -#include -#include - -using namespace iss::arch; - -constexpr std::array iss::arch::traits::reg_names; -constexpr std::array iss::arch::traits::reg_aliases; -constexpr std::array iss::arch::traits::reg_bit_widths; -constexpr std::array iss::arch::traits::reg_byte_offsets; - -tgc5b::tgc5b() = default; - -tgc5b::~tgc5b() = default; - -void tgc5b::reset(uint64_t address) { - auto base_ptr = reinterpret_cast::reg_t*>(get_regs_base_ptr()); - for(size_t i=0; i::NUM_REGS; ++i) - *(base_ptr+i)=0; - reg.PC=address; - reg.NEXT_PC=reg.PC; - reg.PRIV=0x3; - reg.trap_state=0; - reg.icount=0; -} - -uint8_t *tgc5b::get_regs_base_ptr() { - return reinterpret_cast(®); -} - -tgc5b::phys_addr_t tgc5b::virt2phys(const iss::addr_t &addr) { - return phys_addr_t(addr.access, addr.space, addr.val&traits::addr_mask); -} -// clang-format on diff --git a/src_test/iss/arch/tgc5b.h b/src_test/iss/arch/tgc5b.h deleted file mode 100644 index 7e407c5..0000000 --- a/src_test/iss/arch/tgc5b.h +++ /dev/null @@ -1,225 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017 - 2021 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _TGC5B_H_ -#define _TGC5B_H_ -// clang-format off -#include -#include -#include -#include - -namespace iss { -namespace arch { - -struct tgc5b; - -template <> struct traits { - - constexpr static char const* const core_type = "TGC5B"; - - static constexpr std::array reg_names{ - {"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31", "pc", "next_pc", "priv", "dpc"}}; - - static constexpr std::array reg_aliases{ - {"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc", "next_pc", "priv", "dpc"}}; - - enum constants {MISA_VAL=1073742080ULL, MARCHID_VAL=2147483650ULL, CLIC_NUM_IRQ=0ULL, XLEN=32ULL, INSTR_ALIGNMENT=4ULL, RFS=32ULL, fence=0ULL, fencei=1ULL, fencevmal=2ULL, fencevmau=3ULL, CSR_SIZE=4096ULL}; - - constexpr static unsigned FP_REGS_SIZE = 0; - - enum reg_e { - X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, TRAP_STATE=NUM_REGS, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION, LAST_BRANCH - }; - - using reg_t = uint32_t; - - using addr_t = uint32_t; - - using code_word_t = uint32_t; //TODO: check removal - - using virt_addr_t = iss::typed_addr_t; - - using phys_addr_t = iss::typed_addr_t; - - static constexpr std::array reg_bit_widths{ - {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32,32}}; - - static constexpr std::array reg_byte_offsets{ - {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}}; - - static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); - - enum sreg_flag_e { FLAGS }; - - enum mem_type_e { MEM, FENCE, RES, CSR }; - - enum class opcode_e { - LUI = 0, - AUIPC = 1, - JAL = 2, - JALR = 3, - BEQ = 4, - BNE = 5, - BLT = 6, - BGE = 7, - BLTU = 8, - BGEU = 9, - LB = 10, - LH = 11, - LW = 12, - LBU = 13, - LHU = 14, - SB = 15, - SH = 16, - SW = 17, - ADDI = 18, - SLTI = 19, - SLTIU = 20, - XORI = 21, - ORI = 22, - ANDI = 23, - SLLI = 24, - SRLI = 25, - SRAI = 26, - ADD = 27, - SUB = 28, - SLL = 29, - SLT = 30, - SLTU = 31, - XOR = 32, - SRL = 33, - SRA = 34, - OR = 35, - AND = 36, - FENCE = 37, - ECALL = 38, - EBREAK = 39, - MRET = 40, - WFI = 41, - CSRRW = 42, - CSRRS = 43, - CSRRC = 44, - CSRRWI = 45, - CSRRSI = 46, - CSRRCI = 47, - FENCE_I = 48, - MAX_OPCODE - }; -}; - -struct tgc5b: public arch_if { - - using virt_addr_t = typename traits::virt_addr_t; - using phys_addr_t = typename traits::phys_addr_t; - using reg_t = typename traits::reg_t; - using addr_t = typename traits::addr_t; - - tgc5b(); - ~tgc5b(); - - void reset(uint64_t address=0) override; - - uint8_t* get_regs_base_ptr() override; - - inline uint64_t get_icount() { return reg.icount; } - - inline bool should_stop() { return interrupt_sim; } - - inline uint64_t stop_code() { return interrupt_sim; } - - virtual phys_addr_t virt2phys(const iss::addr_t& addr); - - virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } - - inline uint32_t get_last_branch() { return reg.last_branch; } - - -#pragma pack(push, 1) - struct TGC5B_regs { - uint32_t X0 = 0; - uint32_t X1 = 0; - uint32_t X2 = 0; - uint32_t X3 = 0; - uint32_t X4 = 0; - uint32_t X5 = 0; - uint32_t X6 = 0; - uint32_t X7 = 0; - uint32_t X8 = 0; - uint32_t X9 = 0; - uint32_t X10 = 0; - uint32_t X11 = 0; - uint32_t X12 = 0; - uint32_t X13 = 0; - uint32_t X14 = 0; - uint32_t X15 = 0; - uint32_t X16 = 0; - uint32_t X17 = 0; - uint32_t X18 = 0; - uint32_t X19 = 0; - uint32_t X20 = 0; - uint32_t X21 = 0; - uint32_t X22 = 0; - uint32_t X23 = 0; - uint32_t X24 = 0; - uint32_t X25 = 0; - uint32_t X26 = 0; - uint32_t X27 = 0; - uint32_t X28 = 0; - uint32_t X29 = 0; - uint32_t X30 = 0; - uint32_t X31 = 0; - uint32_t PC = 0; - uint32_t NEXT_PC = 0; - uint8_t PRIV = 0; - uint32_t DPC = 0; - uint32_t trap_state = 0, pending_trap = 0; - uint64_t icount = 0; - uint64_t cycle = 0; - uint64_t instret = 0; - uint32_t instruction = 0; - uint32_t last_branch = 0; - } reg; -#pragma pack(pop) - std::array addr_mode; - - uint64_t interrupt_sim=0; - - uint32_t get_fcsr(){return 0;} - void set_fcsr(uint32_t val){} - -}; - -} -} -#endif /* _TGC5B_H_ */ -// clang-format on diff --git a/src_test/vm/interp/vm_tgc5a.cpp b/src_test/vm/interp/vm_tgc5a.cpp deleted file mode 100644 index 875e5a7..0000000 --- a/src_test/vm/interp/vm_tgc5a.cpp +++ /dev/null @@ -1,1776 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2021 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -// clang-format off -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef FMT_HEADER_ONLY -#define FMT_HEADER_ONLY -#endif -#include - -#include -#include - -namespace iss { -namespace interp { -namespace tgc5a { -using namespace iss::arch; -using namespace iss::debugger; -using namespace std::placeholders; - -struct memory_access_exception : public std::exception{ - memory_access_exception(){} -}; - -template class vm_impl : public iss::interp::vm_base { -public: - using traits = arch::traits; - using super = typename iss::interp::vm_base; - using virt_addr_t = typename super::virt_addr_t; - using phys_addr_t = typename super::phys_addr_t; - using code_word_t = typename super::code_word_t; - using addr_t = typename super::addr_t; - using reg_t = typename traits::reg_t; - using mem_type_e = typename traits::mem_type_e; - using opcode_e = typename traits::opcode_e; - - vm_impl(); - - vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); - - void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } - - target_adapter_if *accquire_target_adapter(server_if *srv) override { - debugger_if::dbg_enabled = true; - if (super::tgt_adapter == nullptr) - super::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); - return super::tgt_adapter; - } - -protected: - using this_class = vm_impl; - using compile_ret_t = virt_addr_t; - using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr); - - inline const char *name(size_t index){return indexcore.reg.trap_state = trap_val; - this->template get_reg(traits::NEXT_PC) = std::numeric_limits::max(); - } - - inline void leave(unsigned lvl){ - this->core.leave_trap(lvl); - } - - inline void wait(unsigned type){ - this->core.wait_until(type); - } - - using yield_t = boost::coroutines2::coroutine::push_type; - using coro_t = boost::coroutines2::coroutine::pull_type; - std::vector spawn_blocks; - - template::type> - inline S sext(U from) { - auto mask = (1ULL<::opcode_e op; - }; - struct decoding_tree_node{ - std::vector instrs; - std::vector children; - uint32_t submask = std::numeric_limits::max(); - uint32_t value; - decoding_tree_node(uint32_t value) : value(value){} - }; - - decoding_tree_node* root {nullptr}; - const std::array instr_descr = {{ - /* entries are: size, valid value, valid mask, function ptr */ - {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits::opcode_e::LUI}, - {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits::opcode_e::AUIPC}, - {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, arch::traits::opcode_e::JAL}, - {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::JALR}, - {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BEQ}, - {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BNE}, - {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLT}, - {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGE}, - {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLTU}, - {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGEU}, - {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LB}, - {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LH}, - {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LW}, - {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LBU}, - {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LHU}, - {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SB}, - {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SH}, - {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SW}, - {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ADDI}, - {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTI}, - {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTIU}, - {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::XORI}, - {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ORI}, - {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ANDI}, - {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLLI}, - {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRLI}, - {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRAI}, - {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::ADD}, - {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SUB}, - {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLL}, - {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLT}, - {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLTU}, - {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::XOR}, - {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRL}, - {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRA}, - {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::OR}, - {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::AND}, - {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE}, - {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::ECALL}, - {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::EBREAK}, - {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::MRET}, - {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::WFI}, - {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRW}, - {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRS}, - {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRC}, - {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRWI}, - {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRSI}, - {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRCI}, - {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE_I}, - }}; - - iss::status fetch_ins(virt_addr_t pc, uint8_t * data){ - if(this->core.has_mmu()) { - auto phys_pc = this->core.virt2phys(pc); -// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary -// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err; -// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction -// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) -// return iss::Err; -// } else { - if (this->core.read(phys_pc, 4, data) != iss::Ok) - return iss::Err; -// } - } else { - if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok) - return iss::Err; - - } - return iss::Ok; - } - - void populate_decoding_tree(decoding_tree_node* root){ - //create submask - for(auto instr: root->instrs){ - root->submask &= instr.mask; - } - //put each instr according to submask&encoding into children - for(auto instr: root->instrs){ - bool foundMatch = false; - for(auto child: root->children){ - //use value as identifying trait - if(child->value == (instr.value&root->submask)){ - child->instrs.push_back(instr); - foundMatch = true; - } - } - if(!foundMatch){ - decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask); - child->instrs.push_back(instr); - root->children.push_back(child); - } - } - root->instrs.clear(); - //call populate_decoding_tree for all children - if(root->children.size() >1) - for(auto child: root->children){ - populate_decoding_tree(child); - } - else{ - //sort instrs by value of the mask, this works bc we want to have the least restrictive one last - std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { - return instr1.mask > instr2.mask; - }); - } - } - typename arch::traits::opcode_e decode_instr(decoding_tree_node* node, code_word_t word){ - if(!node->children.size()){ - if(node->instrs.size() == 1) return node->instrs[0].op; - for(auto instr : node->instrs){ - if((instr.mask&word) == instr.value) return instr.op; - } - } - else{ - for(auto child : node->children){ - if (child->value == (node->submask&word)){ - return decode_instr(child, word); - } - } - } - return arch::traits::opcode_e::MAX_OPCODE; - } -}; - -template void debug_fn(CODE_WORD insn) { - volatile CODE_WORD x = insn; - insn = 2 * x; -} - -template vm_impl::vm_impl() { this(new ARCH()); } - -// according to -// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation -#ifdef __GCC__ -constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); } -#elif __cplusplus < 201402L -constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); } -constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; } -#else -constexpr size_t bit_count(uint32_t u) { - size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); - return ((uCount + (uCount >> 3)) & 030707070707) % 63; -} -#endif - -template -vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) -: vm_base(core, core_id, cluster_id) { - root = new decoding_tree_node(std::numeric_limits::max()); - for(auto instr:instr_descr){ - root->instrs.push_back(instr); - } - populate_decoding_tree(root); -} - -inline bool is_count_limit_enabled(finish_cond_e cond){ - return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT; -} - -inline bool is_jump_to_self_enabled(finish_cond_e cond){ - return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF; -} - -template -typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){ - auto pc=start; - auto* PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::PC]); - auto* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); - auto& trap_state = this->core.reg.trap_state; - auto& icount = this->core.reg.icount; - auto& cycle = this->core.reg.cycle; - auto& instret = this->core.reg.instret; - auto& instr = this->core.reg.instruction; - // we fetch at max 4 byte, alignment is 2 - auto *const data = reinterpret_cast(&instr); - - while(!this->core.should_stop() && - !(is_count_limit_enabled(cond) && icount >= icount_limit)){ - if(fetch_ins(pc, data)!=iss::Ok){ - this->do_sync(POST_SYNC, std::numeric_limits::max()); - pc.val = super::core.enter_trap(std::numeric_limits::max(), pc.val, 0); - } else { - if (is_jump_to_self_enabled(cond) && - (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' - auto inst_id = decode_instr(root, instr); - // pre execution stuff - this->core.reg.last_branch = 0; - if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast(inst_id)); - try{ - switch(inst_id){ - case arch::traits::opcode_e::LUI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint32_t imm = ((bit_sub<12,20>(instr) << 12)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)((int32_t)imm); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::AUIPC: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint32_t imm = ((bit_sub<12,20>(instr) << 12)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + (int32_t)imm); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::JAL: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + 4); - } - *NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm)); - this->core.reg.last_branch = 1; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::JALR: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t addr_mask = (uint32_t)- 2; - uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & addr_mask); - if(new_pc % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + 4); - } - *NEXT_PC = new_pc; - this->core.reg.last_branch = 1; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BEQ: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(*(X+rs1) == *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BNE: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(*(X+rs1) != *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BLT: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BGE: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BLTU: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(*(X+rs1) < *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BGEU: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(*(X+rs1) >= *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::LB: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int8_t res_23 = super::template read_mem(traits::MEM, load_address); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int8_t res = (int8_t)res_23; - if(rd != 0) { - *(X+rd) = (uint32_t)res; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::LH: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int16_t res_24 = super::template read_mem(traits::MEM, load_address); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int16_t res = (int16_t)res_24; - if(rd != 0) { - *(X+rd) = (uint32_t)res; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::LW: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int32_t res_25 = super::template read_mem(traits::MEM, load_address); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int32_t res = (int32_t)res_25; - if(rd != 0) { - *(X+rd) = (uint32_t)res; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::LBU: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - uint8_t res_26 = super::template read_mem(traits::MEM, load_address); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint8_t res = res_26; - if(rd != 0) { - *(X+rd) = (uint32_t)res; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::LHU: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - uint16_t res_27 = super::template read_mem(traits::MEM, load_address); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint16_t res = res_27; - if(rd != 0) { - *(X+rd) = (uint32_t)res; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SB: { - uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - super::template write_mem(traits::MEM, store_address, (uint8_t)*(X+rs2)); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SH: { - uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - super::template write_mem(traits::MEM, store_address, (uint16_t)*(X+rs2)); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SW: { - uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - super::template write_mem(traits::MEM, store_address, (uint32_t)*(X+rs2)); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::ADDI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLTI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLTIU: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::XORI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) ^ (uint32_t)((int16_t)sext<12>(imm)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::ORI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) | (uint32_t)((int16_t)sext<12>(imm)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::ANDI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) & (uint32_t)((int16_t)sext<12>(imm)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLLI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) << shamt; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRLI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) >> shamt; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRAI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::ADD: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SUB: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLL: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLT: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLTU: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::XOR: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) ^ *(X+rs2); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRL: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRA: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1))); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::OR: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) | *(X+rs2); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::AND: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) & *(X+rs2); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::FENCE: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t succ = ((bit_sub<20,4>(instr))); - uint8_t pred = ((bit_sub<24,4>(instr))); - uint8_t fm = ((bit_sub<28,4>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), - fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - super::template write_mem(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::ECALL: { - if(this->disass_enabled){ - /* generate console output when executing the command */ - this->core.disass_output(pc.val, "ecall"); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - raise(0, 11); - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::EBREAK: { - if(this->disass_enabled){ - /* generate console output when executing the command */ - this->core.disass_output(pc.val, "ebreak"); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - raise(0, 3); - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::MRET: { - if(this->disass_enabled){ - /* generate console output when executing the command */ - this->core.disass_output(pc.val, "mret"); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - leave(3); - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::WFI: { - if(this->disass_enabled){ - /* generate console output when executing the command */ - this->core.disass_output(pc.val, "wfi"); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - wait(1); - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRW: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t xrs1 = *(X+rs1); - if(rd != 0) { - uint32_t res_28 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_28; - super::template write_mem(traits::CSR, csr, xrs1); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - *(X+rd) = xrd; - } - else { - super::template write_mem(traits::CSR, csr, xrs1); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRS: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t res_29 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_29; - uint32_t xrs1 = *(X+rs1); - if(rs1 != 0) { - super::template write_mem(traits::CSR, csr, xrd | xrs1); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - if(rd != 0) { - *(X+rd) = xrd; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRC: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t res_30 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_30; - uint32_t xrs1 = *(X+rs1); - if(rs1 != 0) { - super::template write_mem(traits::CSR, csr, xrd & ~ xrs1); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - if(rd != 0) { - *(X+rd) = xrd; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRWI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t zimm = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t res_31 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_31; - super::template write_mem(traits::CSR, csr, (uint32_t)zimm); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - if(rd != 0) { - *(X+rd) = xrd; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRSI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t zimm = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t res_32 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_32; - if(zimm != 0) { - super::template write_mem(traits::CSR, csr, xrd | (uint32_t)zimm); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - if(rd != 0) { - *(X+rd) = xrd; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRCI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t zimm = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t res_33 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_33; - if(zimm != 0) { - super::template write_mem(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - if(rd != 0) { - *(X+rd) = xrd; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::FENCE_I: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), - fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - super::template write_mem(traits::FENCE, traits::fencei, imm); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - break; - }// @suppress("No break at end of case") - default: { - *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2); - raise(0, 2); - } - } - }catch(memory_access_exception& e){} - // post execution stuff - process_spawn_blocks(); - if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast(inst_id)); - // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt - // this->core.reg.trap_state = this->core.reg.pending_trap; - // trap check - if(trap_state!=0){ - super::core.enter_trap(trap_state, pc.val, instr); - } else { - icount++; - instret++; - } - cycle++; - pc.val=*NEXT_PC; - this->core.reg.PC = this->core.reg.NEXT_PC; - this->core.reg.trap_state = this->core.reg.pending_trap; - } - } - return pc; -} - -} // namespace tgc5a - -template <> -std::unique_ptr create(arch::tgc5a *core, unsigned short port, bool dump) { - auto ret = new tgc5a::vm_impl(*core, dump); - if (port != 0) debugger::server::run_server(ret, port); - return std::unique_ptr(ret); -} -} // namespace interp -} // namespace iss - -#include -#include -#include -namespace iss { -namespace { -volatile std::array dummy = { - core_factory::instance().register_creator("tgc5a|m_p|interp", [](unsigned port, void*) -> std::tuple{ - auto* cpu = new iss::arch::riscv_hart_m_p(); - auto vm = new interp::tgc5a::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - }), - core_factory::instance().register_creator("tgc5a|mu_p|interp", [](unsigned port, void*) -> std::tuple{ - auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto vm = new interp::tgc5a::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - }) -}; -} -} -// clang-format on \ No newline at end of file diff --git a/src_test/vm/interp/vm_tgc5b.cpp b/src_test/vm/interp/vm_tgc5b.cpp deleted file mode 100644 index 98fb681..0000000 --- a/src_test/vm/interp/vm_tgc5b.cpp +++ /dev/null @@ -1,1776 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2021 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -// clang-format off -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef FMT_HEADER_ONLY -#define FMT_HEADER_ONLY -#endif -#include - -#include -#include - -namespace iss { -namespace interp { -namespace tgc5b { -using namespace iss::arch; -using namespace iss::debugger; -using namespace std::placeholders; - -struct memory_access_exception : public std::exception{ - memory_access_exception(){} -}; - -template class vm_impl : public iss::interp::vm_base { -public: - using traits = arch::traits; - using super = typename iss::interp::vm_base; - using virt_addr_t = typename super::virt_addr_t; - using phys_addr_t = typename super::phys_addr_t; - using code_word_t = typename super::code_word_t; - using addr_t = typename super::addr_t; - using reg_t = typename traits::reg_t; - using mem_type_e = typename traits::mem_type_e; - using opcode_e = typename traits::opcode_e; - - vm_impl(); - - vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0); - - void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; } - - target_adapter_if *accquire_target_adapter(server_if *srv) override { - debugger_if::dbg_enabled = true; - if (super::tgt_adapter == nullptr) - super::tgt_adapter = new riscv_target_adapter(srv, this->get_arch()); - return super::tgt_adapter; - } - -protected: - using this_class = vm_impl; - using compile_ret_t = virt_addr_t; - using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr); - - inline const char *name(size_t index){return indexcore.reg.trap_state = trap_val; - this->template get_reg(traits::NEXT_PC) = std::numeric_limits::max(); - } - - inline void leave(unsigned lvl){ - this->core.leave_trap(lvl); - } - - inline void wait(unsigned type){ - this->core.wait_until(type); - } - - using yield_t = boost::coroutines2::coroutine::push_type; - using coro_t = boost::coroutines2::coroutine::pull_type; - std::vector spawn_blocks; - - template::type> - inline S sext(U from) { - auto mask = (1ULL<::opcode_e op; - }; - struct decoding_tree_node{ - std::vector instrs; - std::vector children; - uint32_t submask = std::numeric_limits::max(); - uint32_t value; - decoding_tree_node(uint32_t value) : value(value){} - }; - - decoding_tree_node* root {nullptr}; - const std::array instr_descr = {{ - /* entries are: size, valid value, valid mask, function ptr */ - {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits::opcode_e::LUI}, - {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits::opcode_e::AUIPC}, - {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, arch::traits::opcode_e::JAL}, - {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, arch::traits::opcode_e::JALR}, - {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BEQ}, - {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BNE}, - {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLT}, - {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGE}, - {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BLTU}, - {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::BGEU}, - {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LB}, - {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LH}, - {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LW}, - {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LBU}, - {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, arch::traits::opcode_e::LHU}, - {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SB}, - {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SH}, - {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SW}, - {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ADDI}, - {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTI}, - {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::SLTIU}, - {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::XORI}, - {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ORI}, - {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, arch::traits::opcode_e::ANDI}, - {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLLI}, - {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRLI}, - {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRAI}, - {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::ADD}, - {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SUB}, - {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLL}, - {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLT}, - {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SLTU}, - {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::XOR}, - {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRL}, - {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::SRA}, - {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::OR}, - {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, arch::traits::opcode_e::AND}, - {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE}, - {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::ECALL}, - {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::EBREAK}, - {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::MRET}, - {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, arch::traits::opcode_e::WFI}, - {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRW}, - {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRS}, - {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRC}, - {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRWI}, - {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRSI}, - {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, arch::traits::opcode_e::CSRRCI}, - {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, arch::traits::opcode_e::FENCE_I}, - }}; - - iss::status fetch_ins(virt_addr_t pc, uint8_t * data){ - if(this->core.has_mmu()) { - auto phys_pc = this->core.virt2phys(pc); -// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary -// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err; -// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction -// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) -// return iss::Err; -// } else { - if (this->core.read(phys_pc, 4, data) != iss::Ok) - return iss::Err; -// } - } else { - if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok) - return iss::Err; - - } - return iss::Ok; - } - - void populate_decoding_tree(decoding_tree_node* root){ - //create submask - for(auto instr: root->instrs){ - root->submask &= instr.mask; - } - //put each instr according to submask&encoding into children - for(auto instr: root->instrs){ - bool foundMatch = false; - for(auto child: root->children){ - //use value as identifying trait - if(child->value == (instr.value&root->submask)){ - child->instrs.push_back(instr); - foundMatch = true; - } - } - if(!foundMatch){ - decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask); - child->instrs.push_back(instr); - root->children.push_back(child); - } - } - root->instrs.clear(); - //call populate_decoding_tree for all children - if(root->children.size() >1) - for(auto child: root->children){ - populate_decoding_tree(child); - } - else{ - //sort instrs by value of the mask, this works bc we want to have the least restrictive one last - std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { - return instr1.mask > instr2.mask; - }); - } - } - typename arch::traits::opcode_e decode_instr(decoding_tree_node* node, code_word_t word){ - if(!node->children.size()){ - if(node->instrs.size() == 1) return node->instrs[0].op; - for(auto instr : node->instrs){ - if((instr.mask&word) == instr.value) return instr.op; - } - } - else{ - for(auto child : node->children){ - if (child->value == (node->submask&word)){ - return decode_instr(child, word); - } - } - } - return arch::traits::opcode_e::MAX_OPCODE; - } -}; - -template void debug_fn(CODE_WORD insn) { - volatile CODE_WORD x = insn; - insn = 2 * x; -} - -template vm_impl::vm_impl() { this(new ARCH()); } - -// according to -// https://stackoverflow.com/questions/8871204/count-number-of-1s-in-binary-representation -#ifdef __GCC__ -constexpr size_t bit_count(uint32_t u) { return __builtin_popcount(u); } -#elif __cplusplus < 201402L -constexpr size_t uCount(uint32_t u) { return u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); } -constexpr size_t bit_count(uint32_t u) { return ((uCount(u) + (uCount(u) >> 3)) & 030707070707) % 63; } -#else -constexpr size_t bit_count(uint32_t u) { - size_t uCount = u - ((u >> 1) & 033333333333) - ((u >> 2) & 011111111111); - return ((uCount + (uCount >> 3)) & 030707070707) % 63; -} -#endif - -template -vm_impl::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id) -: vm_base(core, core_id, cluster_id) { - root = new decoding_tree_node(std::numeric_limits::max()); - for(auto instr:instr_descr){ - root->instrs.push_back(instr); - } - populate_decoding_tree(root); -} - -inline bool is_count_limit_enabled(finish_cond_e cond){ - return (cond & finish_cond_e::COUNT_LIMIT) == finish_cond_e::COUNT_LIMIT; -} - -inline bool is_jump_to_self_enabled(finish_cond_e cond){ - return (cond & finish_cond_e::JUMP_TO_SELF) == finish_cond_e::JUMP_TO_SELF; -} - -template -typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){ - auto pc=start; - auto* PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::PC]); - auto* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); - auto& trap_state = this->core.reg.trap_state; - auto& icount = this->core.reg.icount; - auto& cycle = this->core.reg.cycle; - auto& instret = this->core.reg.instret; - auto& instr = this->core.reg.instruction; - // we fetch at max 4 byte, alignment is 2 - auto *const data = reinterpret_cast(&instr); - - while(!this->core.should_stop() && - !(is_count_limit_enabled(cond) && icount >= icount_limit)){ - if(fetch_ins(pc, data)!=iss::Ok){ - this->do_sync(POST_SYNC, std::numeric_limits::max()); - pc.val = super::core.enter_trap(std::numeric_limits::max(), pc.val, 0); - } else { - if (is_jump_to_self_enabled(cond) && - (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0' - auto inst_id = decode_instr(root, instr); - // pre execution stuff - this->core.reg.last_branch = 0; - if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast(inst_id)); - try{ - switch(inst_id){ - case arch::traits::opcode_e::LUI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint32_t imm = ((bit_sub<12,20>(instr) << 12)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)((int32_t)imm); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::AUIPC: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint32_t imm = ((bit_sub<12,20>(instr) << 12)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + (int32_t)imm); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::JAL: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + 4); - } - *NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm)); - this->core.reg.last_branch = 1; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::JALR: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t addr_mask = (uint32_t)- 2; - uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & addr_mask); - if(new_pc % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*PC + 4); - } - *NEXT_PC = new_pc; - this->core.reg.last_branch = 1; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BEQ: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(*(X+rs1) == *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BNE: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(*(X+rs1) != *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BLT: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BGE: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BLTU: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(*(X+rs1) < *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::BGEU: { - uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), - fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(*(X+rs1) >= *(X+rs2)) { - if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); - } - else { - *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm)); - this->core.reg.last_branch = 1; - } - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::LB: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int8_t res_23 = super::template read_mem(traits::MEM, load_address); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int8_t res = (int8_t)res_23; - if(rd != 0) { - *(X+rd) = (uint32_t)res; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::LH: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int16_t res_24 = super::template read_mem(traits::MEM, load_address); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int16_t res = (int16_t)res_24; - if(rd != 0) { - *(X+rd) = (uint32_t)res; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::LW: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - int32_t res_25 = super::template read_mem(traits::MEM, load_address); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - int32_t res = (int32_t)res_25; - if(rd != 0) { - *(X+rd) = (uint32_t)res; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::LBU: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - uint8_t res_26 = super::template read_mem(traits::MEM, load_address); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint8_t res = res_26; - if(rd != 0) { - *(X+rd) = (uint32_t)res; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::LHU: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), - fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - uint16_t res_27 = super::template read_mem(traits::MEM, load_address); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint16_t res = res_27; - if(rd != 0) { - *(X+rd) = (uint32_t)res; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SB: { - uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - super::template write_mem(traits::MEM, store_address, (uint8_t)*(X+rs2)); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SH: { - uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - super::template write_mem(traits::MEM, store_address, (uint16_t)*(X+rs2)); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SW: { - uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), - fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - super::template write_mem(traits::MEM, store_address, (uint32_t)*(X+rs2)); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::ADDI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLTI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLTIU: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::XORI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) ^ (uint32_t)((int16_t)sext<12>(imm)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::ORI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) | (uint32_t)((int16_t)sext<12>(imm)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::ANDI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) & (uint32_t)((int16_t)sext<12>(imm)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLLI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) << shamt; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRLI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) >> shamt; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRAI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::ADD: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SUB: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLL: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLT: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SLTU: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::XOR: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) ^ *(X+rs2); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRL: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::SRA: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1))); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::OR: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) | *(X+rs2); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::AND: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t rs2 = ((bit_sub<20,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), - fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); - } - else { - if(rd != 0) { - *(X+rd) = *(X+rs1) & *(X+rs2); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::FENCE: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t succ = ((bit_sub<20,4>(instr))); - uint8_t pred = ((bit_sub<24,4>(instr))); - uint8_t fm = ((bit_sub<28,4>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), - fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - super::template write_mem(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::ECALL: { - if(this->disass_enabled){ - /* generate console output when executing the command */ - this->core.disass_output(pc.val, "ecall"); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - raise(0, 11); - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::EBREAK: { - if(this->disass_enabled){ - /* generate console output when executing the command */ - this->core.disass_output(pc.val, "ebreak"); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - raise(0, 3); - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::MRET: { - if(this->disass_enabled){ - /* generate console output when executing the command */ - this->core.disass_output(pc.val, "mret"); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - leave(3); - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::WFI: { - if(this->disass_enabled){ - /* generate console output when executing the command */ - this->core.disass_output(pc.val, "wfi"); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - wait(1); - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRW: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t xrs1 = *(X+rs1); - if(rd != 0) { - uint32_t res_28 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_28; - super::template write_mem(traits::CSR, csr, xrs1); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - *(X+rd) = xrd; - } - else { - super::template write_mem(traits::CSR, csr, xrs1); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRS: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t res_29 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_29; - uint32_t xrs1 = *(X+rs1); - if(rs1 != 0) { - super::template write_mem(traits::CSR, csr, xrd | xrs1); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - if(rd != 0) { - *(X+rd) = xrd; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRC: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1))); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t res_30 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_30; - uint32_t xrs1 = *(X+rs1); - if(rs1 != 0) { - super::template write_mem(traits::CSR, csr, xrd & ~ xrs1); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - if(rd != 0) { - *(X+rd) = xrd; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRWI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t zimm = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t res_31 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_31; - super::template write_mem(traits::CSR, csr, (uint32_t)zimm); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - if(rd != 0) { - *(X+rd) = xrd; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRSI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t zimm = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t res_32 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_32; - if(zimm != 0) { - super::template write_mem(traits::CSR, csr, xrd | (uint32_t)zimm); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - if(rd != 0) { - *(X+rd) = xrd; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::CSRRCI: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t zimm = ((bit_sub<15,5>(instr))); - uint16_t csr = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), - fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers - auto* X = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::X0]);// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - if(rd >= traits::RFS) { - raise(0, 2); - } - else { - uint32_t res_33 = super::template read_mem(traits::CSR, csr); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - uint32_t xrd = res_33; - if(zimm != 0) { - super::template write_mem(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - if(rd != 0) { - *(X+rd) = xrd; - } - } - } - break; - }// @suppress("No break at end of case") - case arch::traits::opcode_e::FENCE_I: { - uint8_t rd = ((bit_sub<7,5>(instr))); - uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint16_t imm = ((bit_sub<20,12>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), - fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm)); - this->core.disass_output(pc.val, mnemonic); - } - // used registers// calculate next pc value - *NEXT_PC = *PC + 4; - // execute instruction - { - super::template write_mem(traits::FENCE, traits::fencei, imm); - if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - } - break; - }// @suppress("No break at end of case") - default: { - *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2); - raise(0, 2); - } - } - }catch(memory_access_exception& e){} - // post execution stuff - process_spawn_blocks(); - if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast(inst_id)); - // if(!this->core.reg.trap_state) // update trap state if there is a pending interrupt - // this->core.reg.trap_state = this->core.reg.pending_trap; - // trap check - if(trap_state!=0){ - super::core.enter_trap(trap_state, pc.val, instr); - } else { - icount++; - instret++; - } - cycle++; - pc.val=*NEXT_PC; - this->core.reg.PC = this->core.reg.NEXT_PC; - this->core.reg.trap_state = this->core.reg.pending_trap; - } - } - return pc; -} - -} // namespace tgc5b - -template <> -std::unique_ptr create(arch::tgc5b *core, unsigned short port, bool dump) { - auto ret = new tgc5b::vm_impl(*core, dump); - if (port != 0) debugger::server::run_server(ret, port); - return std::unique_ptr(ret); -} -} // namespace interp -} // namespace iss - -#include -#include -#include -namespace iss { -namespace { -volatile std::array dummy = { - core_factory::instance().register_creator("tgc5b|m_p|interp", [](unsigned port, void*) -> std::tuple{ - auto* cpu = new iss::arch::riscv_hart_m_p(); - auto vm = new interp::tgc5b::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - }), - core_factory::instance().register_creator("tgc5b|mu_p|interp", [](unsigned port, void*) -> std::tuple{ - auto* cpu = new iss::arch::riscv_hart_mu_p(); - auto vm = new interp::tgc5b::vm_impl(*cpu, false); - if (port != 0) debugger::server::run_server(vm, port); - return {cpu_ptr{cpu}, vm_ptr{vm}}; - }) -}; -} -} -// clang-format on \ No newline at end of file From 551822916c593dd79ee219416fa98aa077a25eb7 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Fri, 14 Jun 2024 17:43:12 +0200 Subject: [PATCH 32/33] applies clang-format --- src/iss/arch/riscv_hart_mu_p.h | 2 +- src/iss/semihosting/semihosting.cpp | 123 ++++++++++++++-------------- src/iss/semihosting/semihosting.h | 9 +- src/main.cpp | 4 +- 4 files changed, 70 insertions(+), 68 deletions(-) diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index b20f17a..5928d4e 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -380,7 +380,7 @@ protected: bool tohost_lower_written = false; riscv_instrumentation_if instr_if; - semihosting_cb_t semihosting_cb; + semihosting_cb_t semihosting_cb; using mem_type = util::sparse_array; using csr_type = util::sparse_array::reg_t, 1ULL << 12, 12>; diff --git a/src/iss/semihosting/semihosting.cpp b/src/iss/semihosting/semihosting.cpp index af7006e..ab2e2c9 100644 --- a/src/iss/semihosting/semihosting.cpp +++ b/src/iss/semihosting/semihosting.cpp @@ -1,55 +1,56 @@ #include "semihosting.h" -#include -#include -#include -#include #include +#include +#include +#include +#include // explanation of syscalls can be found at https://github.com/SpinalHDL/openocd_riscv/blob/riscv_spinal/src/target/semihosting_common.h -const char *SYS_OPEN_MODES_STRS[] = { "r", "rb", "r+", "r+b", "w", "wb", "w+", "w+b", "a", "ab", "a+", "a+b" }; +const char* SYS_OPEN_MODES_STRS[] = {"r", "rb", "r+", "r+b", "w", "wb", "w+", "w+b", "a", "ab", "a+", "a+b"}; -template T sh_read_field(iss::arch_if* arch_if_ptr, T addr, int len=4) { +template T sh_read_field(iss::arch_if* arch_if_ptr, T addr, int len = 4) { uint8_t bytes[4]; auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr, 4, &bytes[0]); - //auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character); + // auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character); - if(res != iss::Ok){ - return 0; //TODO THROW ERROR - } else return static_cast(bytes[0]) | (static_cast(bytes[1]) << 8) | (static_cast(bytes[2]) << 16) | (static_cast(bytes[3]) << 24); + if(res != iss::Ok) { + return 0; // TODO THROW ERROR + } else + return static_cast(bytes[0]) | (static_cast(bytes[1]) << 8) | (static_cast(bytes[2]) << 16) | + (static_cast(bytes[3]) << 24); } -template std::string sh_read_string(iss::arch_if* arch_if_ptr, T addr, T str_len){ +template std::string sh_read_string(iss::arch_if* arch_if_ptr, T addr, T str_len) { std::vector buffer(str_len); - for (int i = 0; i < str_len; i++ ) { + for(int i = 0; i < str_len; i++) { buffer[i] = sh_read_field(arch_if_ptr, addr + i, 1); } std::string str(buffer.begin(), buffer.end()); return str; } - template void semihosting_callback::operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter) { - static std::map openFiles; + static std::map openFiles; static T file_count = 3; static T semihostingErrno; switch(static_cast(*call_number)) { case semihosting_syscalls::SYS_CLOCK: { - auto end = std::chrono::high_resolution_clock::now(); // end measurement + auto end = std::chrono::high_resolution_clock::now(); // end measurement auto elapsed = end - timeVar; auto millis = std::chrono::duration_cast(elapsed).count(); - *call_number = millis; //TODO get time now + *call_number = millis; // TODO get time now break; } case semihosting_syscalls::SYS_CLOSE: { T file_handle = *parameter; - if (openFiles.size() <= file_handle && file_handle < 0) { + if(openFiles.size() <= file_handle && file_handle < 0) { semihostingErrno = EBADF; return; } auto file = openFiles[file_handle]; openFiles.erase(file_handle); - if (!(file == stdin || file == stdout || file == stderr)) { + if(!(file == stdin || file == stdout || file == stderr)) { int i = fclose(file); *call_number = i; } else { @@ -80,7 +81,8 @@ template void semihosting_callback::operator()(iss::arch_if* arc auto file = openFiles[file_handle]; size_t currentPos = ftell(file); - if (currentPos < 0) throw std::runtime_error("SYS_FLEN negative value"); + if(currentPos < 0) + throw std::runtime_error("SYS_FLEN negative value"); fseek(file, 0, SEEK_END); size_t length = ftell(file); fseek(file, currentPos, SEEK_SET); @@ -101,36 +103,36 @@ template void semihosting_callback::operator()(iss::arch_if* arc break; } case semihosting_syscalls::SYS_ISTTY: { - T file_handle = *parameter; + T file_handle = *parameter; *call_number = (file_handle == 0 || file_handle == 1 || file_handle == 2); break; } case semihosting_syscalls::SYS_OPEN: { T path_str_addr = sh_read_field(arch_if_ptr, *parameter); - T mode = sh_read_field(arch_if_ptr, 4+(*parameter)); - T path_len = sh_read_field(arch_if_ptr, 8+(*parameter)); + T mode = sh_read_field(arch_if_ptr, 4 + (*parameter)); + T path_len = sh_read_field(arch_if_ptr, 8 + (*parameter)); std::string path_str = sh_read_string(arch_if_ptr, path_str_addr, path_len); - //TODO LOG INFO + // TODO LOG INFO - if (mode >= 12) { - //TODO throw ERROR + if(mode >= 12) { + // TODO throw ERROR return; } - FILE *file = nullptr; + FILE* file = nullptr; if(path_str == ":tt") { - if (mode < 4) + if(mode < 4) file = stdin; - else if (mode < 8) + else if(mode < 8) file = stdout; - else + else file = stderr; } else { file = fopen(path_str.c_str(), SYS_OPEN_MODES_STRS[mode]); - if (file == nullptr) { - //TODO throw error + if(file == nullptr) { + // TODO throw error return; } } @@ -138,45 +140,41 @@ template void semihosting_callback::operator()(iss::arch_if* arc openFiles[file_handle] = file; *call_number = file_handle; break; - } case semihosting_syscalls::SYS_READ: { - T file_handle = sh_read_field(arch_if_ptr, (*parameter)+4); + T file_handle = sh_read_field(arch_if_ptr, (*parameter) + 4); T addr = sh_read_field(arch_if_ptr, *parameter); - T count = sh_read_field(arch_if_ptr, (*parameter)+8); + T count = sh_read_field(arch_if_ptr, (*parameter) + 8); auto file = openFiles[file_handle]; std::vector buffer(count); size_t num_read = 0; - if (file == stdin) - { + if(file == stdin) { // when reading from stdin: mimic behaviour from read syscall // and return on newline. - while (num_read < count) - { + while(num_read < count) { char c = fgetc(file); buffer[num_read] = c; num_read++; - if (c == '\n') + if(c == '\n') break; } } else { num_read = fread(buffer.data(), 1, count, file); } buffer.resize(num_read); - for(int i = 0; iwrite(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr+i, 1, &buffer[i]); + for(int i = 0; i < num_read; i++) { + auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr + i, 1, &buffer[i]); if(res != iss::Ok) return; } *call_number = count - num_read; break; - } case semihosting_syscalls::SYS_READC: { uint8_t character = getchar(); - //character = getchar(); + // character = getchar(); /*if(character != iss::Ok) std::cout << "Not OK"; return;*/ @@ -185,36 +183,38 @@ template void semihosting_callback::operator()(iss::arch_if* arc } case semihosting_syscalls::SYS_REMOVE: { T path_str_addr = sh_read_field(arch_if_ptr, *parameter); - T path_len = sh_read_field(arch_if_ptr, (*parameter)+4); + T path_len = sh_read_field(arch_if_ptr, (*parameter) + 4); std::string path_str = sh_read_string(arch_if_ptr, path_str_addr, path_len); - if(remove(path_str.c_str())<0) *call_number = -1; + if(remove(path_str.c_str()) < 0) + *call_number = -1; break; } case semihosting_syscalls::SYS_RENAME: { T path_str_addr_old = sh_read_field(arch_if_ptr, *parameter); - T path_len_old = sh_read_field(arch_if_ptr, (*parameter)+4); - T path_str_addr_new = sh_read_field(arch_if_ptr, (*parameter)+8); - T path_len_new = sh_read_field(arch_if_ptr, (*parameter)+12); + T path_len_old = sh_read_field(arch_if_ptr, (*parameter) + 4); + T path_str_addr_new = sh_read_field(arch_if_ptr, (*parameter) + 8); + T path_len_new = sh_read_field(arch_if_ptr, (*parameter) + 12); std::string path_str_old = sh_read_string(arch_if_ptr, path_str_addr_old, path_len_old); - std::string path_str_new = sh_read_string(arch_if_ptr, path_str_addr_new, path_len_new); - rename(path_str_old.c_str(), path_str_new.c_str()); + std::string path_str_new = sh_read_string(arch_if_ptr, path_str_addr_new, path_len_new); + rename(path_str_old.c_str(), path_str_new.c_str()); break; } case semihosting_syscalls::SYS_SEEK: { T file_handle = sh_read_field(arch_if_ptr, *parameter); - T pos = sh_read_field(arch_if_ptr, (*parameter)+1); + T pos = sh_read_field(arch_if_ptr, (*parameter) + 1); auto file = openFiles[file_handle]; int retval = fseek(file, pos, SEEK_SET); - if(retval<0) throw std::runtime_error("SYS_SEEK negative return value"); + if(retval < 0) + throw std::runtime_error("SYS_SEEK negative return value"); break; } case semihosting_syscalls::SYS_SYSTEM: { T cmd_addr = sh_read_field(arch_if_ptr, *parameter); - T cmd_len = sh_read_field(arch_if_ptr, (*parameter)+1); + T cmd_len = sh_read_field(arch_if_ptr, (*parameter) + 1); std::string cmd = sh_read_string(arch_if_ptr, cmd_addr, cmd_len); system(cmd.c_str()); break; @@ -224,16 +224,16 @@ template void semihosting_callback::operator()(iss::arch_if* arc break; } case semihosting_syscalls::SYS_TIME: { - //returns time in seconds scince 01.01.1970 00:00 + // returns time in seconds scince 01.01.1970 00:00 *call_number = time(NULL); break; } case semihosting_syscalls::SYS_TMPNAM: { T buffer_addr = sh_read_field(arch_if_ptr, *parameter); - T identifier = sh_read_field(arch_if_ptr, (*parameter)+1); - T buffer_len = sh_read_field(arch_if_ptr, (*parameter)+2); + T identifier = sh_read_field(arch_if_ptr, (*parameter) + 1); + T buffer_len = sh_read_field(arch_if_ptr, (*parameter) + 2); - if (identifier > 255) { + if(identifier > 255) { *call_number = -1; return; } @@ -243,15 +243,16 @@ template void semihosting_callback::operator()(iss::arch_if* arc for(int i = 0; i < buffer_len; i++) { uint8_t character = filename[i]; - auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, (*parameter)+i, 1, &character); - if(res != iss::Ok) return; + auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, (*parameter) + i, 1, &character); + if(res != iss::Ok) + return; } break; } case semihosting_syscalls::SYS_WRITE: { - T file_handle = sh_read_field(arch_if_ptr, (*parameter)+4); + T file_handle = sh_read_field(arch_if_ptr, (*parameter) + 4); T addr = sh_read_field(arch_if_ptr, *parameter); - T count = sh_read_field(arch_if_ptr, (*parameter)+8); + T count = sh_read_field(arch_if_ptr, (*parameter) + 8); auto file = openFiles[file_handle]; std::string str = sh_read_string(arch_if_ptr, addr, count); diff --git a/src/iss/semihosting/semihosting.h b/src/iss/semihosting/semihosting.h index 295c4d4..1e62df2 100644 --- a/src/iss/semihosting/semihosting.h +++ b/src/iss/semihosting/semihosting.h @@ -1,8 +1,8 @@ #ifndef _SEMIHOSTING_H_ #define _SEMIHOSTING_H_ -#include -#include #include +#include +#include /* * According to: * "Semihosting for AArch32 and AArch64, Release 2.0" @@ -50,9 +50,10 @@ enum class semihosting_syscalls { USER_CMD_0x1FF = 0x1FF, }; -template struct semihosting_callback{ +template struct semihosting_callback { std::chrono::high_resolution_clock::time_point timeVar; - semihosting_callback(): timeVar(std::chrono::high_resolution_clock::now()) {} + semihosting_callback() + : timeVar(std::chrono::high_resolution_clock::now()) {} void operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter); }; diff --git a/src/main.cpp b/src/main.cpp index f006ca6..940a106 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -119,8 +119,8 @@ int main(int argc, char* argv[]) { // instantiate the simulator iss::vm_ptr vm{nullptr}; iss::cpu_ptr cpu{nullptr}; - semihosting_callback cb{}; - semihosting_cb_t semihosting_cb = [&cb](iss::arch_if* i, uint32_t* a0, uint32_t* a1) {cb(i,a0,a1);}; + semihosting_callback cb{}; + semihosting_cb_t semihosting_cb = [&cb](iss::arch_if* i, uint32_t* a0, uint32_t* a1) { cb(i, a0, a1); }; std::string isa_opt(clim["isa"].as()); if(isa_opt.size() == 0 || isa_opt == "?") { auto list = f.get_names(); From 3fd51cc68c4547cb1e89d56a2010ff3af0ff5e97 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Fri, 14 Jun 2024 19:54:33 +0200 Subject: [PATCH 33/33] fixes templates --- gen_input/templates/interp/CORENAME.cpp.gtl | 4 +- src/iss/arch/tgc5c.h | 46 --- src/vm/interp/vm_tgc5c.cpp | 314 ++++++++++---------- 3 files changed, 159 insertions(+), 205 deletions(-) diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl index e8062c8..fd2bbc6 100644 --- a/gen_input/templates/interp/CORENAME.cpp.gtl +++ b/gen_input/templates/interp/CORENAME.cpp.gtl @@ -368,7 +368,7 @@ volatile std::array dummy = { auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; @@ -378,7 +378,7 @@ volatile std::array dummy = { auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl(*cpu, false); if (port != 0) debugger::server::run_server(vm, port); if(init_data){ - auto* cb = reinterpret_cast::reg_t, arch::traits::reg_t)>*>(init_data); + auto* cb = reinterpret_cast::reg_t>*>(init_data); cpu->set_semihosting_callback(*cb); } return {cpu_ptr{cpu}, vm_ptr{vm}}; diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h index 06d74de..cff086d 100644 --- a/src/iss/arch/tgc5c.h +++ b/src/iss/arch/tgc5c.h @@ -76,53 +76,7 @@ template <> struct traits { static constexpr std::array reg_byte_offsets{ {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}}; -/* -For easy lookup: -X0 (zero): 0x0000 -X1 (ra) : 0x0004 -X2 (sp) : 0x0008 -X3 (gp) : 0x000c -X4 (tp) : 0x0010 -X5 (t0) : 0x0014 -X6 (t1) : 0x0018 -X7 (t2) : 0x001c -X8 (s0/fp): 0x0020 -X9 (s1) : 0x0024 -X10 (a0) : 0x0028 -X11 (a1) : 0x002c -X12 (a2) : 0x0030 -X13 (a3) : 0x0034 -X14 (a4) : 0x0038 -X15 (a5) : 0x003c -X16 (a6) : 0x0040 -X17 (a7) : 0x0044 -X18 (s2) : 0x0048 -X19 (s3) : 0x004c -X20 (s4) : 0x0050 -X21 (s5) : 0x0054 -X22 (s6) : 0x0058 -X23 (s7) : 0x005c -X24 (s8) : 0x0060 -X25 (s9) : 0x0064 -X26 (s10) : 0x0068 -X27 (s11) : 0x006c -X28 (t3) : 0x0070 -X29 (t4) : 0x0074 -X30 (t5) : 0x0078 -X31 (t6) : 0x007c -PC : 0x0080 -NEXT_PC : 0x0084 -PRIV : 0x0085 -DPC : 0x0089 -trap_state : 0x008d -pending_trap : 0x0091 -icount : 0x0095 -cycle : 0x009d -instret : 0x00a5 -instruction : 0x00ad -last_branch : 0x00b1 -*/ static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); enum sreg_flag_e { FLAGS }; diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp index e6ebfa9..e4a816e 100644 --- a/src/vm/interp/vm_tgc5c.cpp +++ b/src/vm/interp/vm_tgc5c.cpp @@ -399,10 +399,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)((int32_t)imm); } } @@ -425,10 +425,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)imm )); } } @@ -451,15 +451,15 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { if(imm % traits::INSTR_ALIGNMENT) { - raise(0, 0); + raise(0, 0); } else { - if(rd != 0) { - *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 4 )); + if(rd != 0) { + *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(4 )); } *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)sext<21>(imm) )); this->core.reg.last_branch = 1; @@ -485,17 +485,17 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t addr_mask = (uint32_t)- 2; uint32_t new_pc = (uint32_t)(((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )) & (int64_t)(addr_mask )); if(new_pc % traits::INSTR_ALIGNMENT) { - raise(0, 0); + raise(0, 0); } else { - if(rd != 0) { - *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 4 )); + if(rd != 0) { + *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(4 )); } *NEXT_PC = new_pc; this->core.reg.last_branch = 1; @@ -521,12 +521,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { if(*(X+rs1) == *(X+rs2)) { if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { - raise(0, 0); + raise(0, 0); } else { *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); @@ -554,12 +554,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { if(*(X+rs1) != *(X+rs2)) { if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { - raise(0, 0); + raise(0, 0); } else { *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); @@ -587,12 +587,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) { if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { - raise(0, 0); + raise(0, 0); } else { *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); @@ -620,12 +620,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) { if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { - raise(0, 0); + raise(0, 0); } else { *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); @@ -653,12 +653,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { if(*(X+rs1) < *(X+rs2)) { if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { - raise(0, 0); + raise(0, 0); } else { *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); @@ -686,12 +686,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { if(*(X+rs1) >= *(X+rs2)) { if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) { - raise(0, 0); + raise(0, 0); } else { *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) )); @@ -719,14 +719,14 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); int8_t res_27 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int8_t res = (int8_t)res_27; - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)res; } } @@ -750,14 +750,14 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); int16_t res_28 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int16_t res = (int16_t)res_28; - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)res; } } @@ -781,14 +781,14 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); int32_t res_29 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); int32_t res = (int32_t)res_29; - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)res; } } @@ -812,14 +812,14 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); uint8_t res_30 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint8_t res = res_30; - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)res; } } @@ -843,14 +843,14 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); uint16_t res_31 = super::template read_mem(traits::MEM, load_address); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint16_t res = res_31; - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)res; } } @@ -874,7 +874,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); @@ -901,7 +901,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); @@ -928,7 +928,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs2 >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); @@ -955,10 +955,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )); } } @@ -982,11 +982,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { - *(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0; + if(rd != 0) { + *(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0; } } } @@ -1009,11 +1009,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { - *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0; + if(rd != 0) { + *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0; } } } @@ -1036,10 +1036,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = *(X+rs1) ^ (uint32_t)((int16_t)sext<12>(imm)); } } @@ -1063,10 +1063,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = *(X+rs1) | (uint32_t)((int16_t)sext<12>(imm)); } } @@ -1090,10 +1090,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = *(X+rs1) & (uint32_t)((int16_t)sext<12>(imm)); } } @@ -1117,10 +1117,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = *(X+rs1) << shamt; } } @@ -1144,10 +1144,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = *(X+rs1) >> shamt; } } @@ -1171,10 +1171,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt); } } @@ -1198,10 +1198,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)(*(X+rs2) )); } } @@ -1225,10 +1225,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) - (uint64_t)(*(X+rs2) )); } } @@ -1252,11 +1252,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { - *(X+rd) = *(X+rs1) << ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 ))); + if(rd != 0) { + *(X+rd) = *(X+rs1) << ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 ))); } } } @@ -1279,11 +1279,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { - *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0; + if(rd != 0) { + *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0; } } } @@ -1306,11 +1306,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { - *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0; + if(rd != 0) { + *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0; } } } @@ -1333,10 +1333,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = *(X+rs1) ^ *(X+rs2); } } @@ -1360,11 +1360,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { - *(X+rd) = *(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 ))); + if(rd != 0) { + *(X+rd) = *(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 ))); } } } @@ -1387,11 +1387,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { - *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 )))); + if(rd != 0) { + *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )))); } } } @@ -1414,10 +1414,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = *(X+rs1) | *(X+rs2); } } @@ -1441,10 +1441,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = *(X+rs1) & *(X+rs2); } } @@ -1468,7 +1468,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 4; // execute instruction { - super::template write_mem(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ); + super::template write_mem(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } break; @@ -1482,7 +1482,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 4; // execute instruction { - raise(0, 11); + raise(0, 11); } break; }// @suppress("No break at end of case") @@ -1495,7 +1495,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 4; // execute instruction { - raise(0, 3); + raise(0, 3); } break; }// @suppress("No break at end of case") @@ -1542,11 +1542,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t xrs1 = *(X+rs1); - if(rd != 0) { + if(rd != 0) { uint32_t res_32 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint32_t xrd = res_32; @@ -1579,18 +1579,18 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t res_33 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint32_t xrd = res_33; uint32_t xrs1 = *(X+rs1); - if(rs1 != 0) { + if(rs1 != 0) { super::template write_mem(traits::CSR, csr, xrd | xrs1); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } - if(rd != 0) { + if(rd != 0) { *(X+rd) = xrd; } } @@ -1614,18 +1614,18 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t res_34 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint32_t xrd = res_34; uint32_t xrs1 = *(X+rs1); - if(rs1 != 0) { + if(rs1 != 0) { super::template write_mem(traits::CSR, csr, xrd & ~ xrs1); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } - if(rd != 0) { + if(rd != 0) { *(X+rd) = xrd; } } @@ -1649,7 +1649,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t res_35 = super::template read_mem(traits::CSR, csr); @@ -1657,7 +1657,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co uint32_t xrd = res_35; super::template write_mem(traits::CSR, csr, (uint32_t)zimm); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - if(rd != 0) { + if(rd != 0) { *(X+rd) = xrd; } } @@ -1681,17 +1681,17 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t res_36 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint32_t xrd = res_36; - if(zimm != 0) { + if(zimm != 0) { super::template write_mem(traits::CSR, csr, xrd | (uint32_t)zimm); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } - if(rd != 0) { + if(rd != 0) { *(X+rd) = xrd; } } @@ -1715,17 +1715,17 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t res_37 = super::template read_mem(traits::CSR, csr); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); uint32_t xrd = res_37; - if(zimm != 0) { + if(zimm != 0) { super::template write_mem(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } - if(rd != 0) { + if(rd != 0) { *(X+rd) = xrd; } } @@ -1769,7 +1769,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) ); @@ -1797,7 +1797,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) ); @@ -1825,7 +1825,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)(*(X+rs2) ); @@ -1853,7 +1853,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint64_t res = (uint64_t)(*(X+rs1) ) * (uint64_t)(*(X+rs2) ); @@ -1881,13 +1881,13 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { int32_t dividend = (int32_t)*(X+rs1); int32_t divisor = (int32_t)*(X+rs2); - if(rd != 0) { - if(divisor != 0) { + if(rd != 0) { + if(divisor != 0) { uint32_t MMIN = ((uint32_t)1) << ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )); if(*(X+rs1) == MMIN && divisor == - 1) { *(X+rd) = MMIN; @@ -1921,10 +1921,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(*(X+rs2) != 0) { + if(*(X+rs2) != 0) { if(rd != 0) { *(X+rd) = *(X+rs1) / *(X+rs2); } @@ -1955,14 +1955,14 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(*(X+rs2) != 0) { + if(*(X+rs2) != 0) { uint32_t MMIN = (uint32_t)1 << ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )); if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) { if(rd != 0) { - *(X+rd) = 0; + *(X+rd) = 0; } } else { @@ -1997,10 +1997,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(*(X+rs2) != 0) { + if(*(X+rs2) != 0) { if(rd != 0) { *(X+rd) = *(X+rs1) % *(X+rs2); } @@ -2030,10 +2030,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(imm) { - *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(imm )); + *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(imm )); } else { - raise(0, 2); + raise(0, 2); } } break; @@ -2054,10 +2054,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm )); + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm )); int32_t res_38 = super::template read_mem(traits::MEM, offs); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); - *(X+rd + 8) = (uint32_t)(int32_t)res_38; + *(X+rd + 8) = (uint32_t)(int32_t)res_38; } break; }// @suppress("No break at end of case") @@ -2077,8 +2077,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm )); - super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2 + 8)); + uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm )); + super::template write_mem(traits::MEM, offs, (uint32_t)*(X+rs2 + 8)); if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception(); } break; @@ -2099,10 +2099,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rs1 != 0) { + if(rs1 != 0) { *(X+rs1) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int8_t)sext<6>(imm) )); } } @@ -2136,7 +2136,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 2 )); + *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(2 )); *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) )); this->core.reg.last_branch = 1; } @@ -2158,10 +2158,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)((int8_t)sext<6>(imm)); } } @@ -2183,10 +2183,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - if(imm == 0 || rd >= traits::RFS) { - raise(0, 2); + if(imm == 0 || rd >= traits::RFS) { + raise(0, 2); } - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)((int32_t)sext<18>(imm)); } } @@ -2210,7 +2210,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *(X+2) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)((int16_t)sext<10>(nzimm) )); } else { - raise(0, 2); + raise(0, 2); } } break; @@ -2225,7 +2225,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - raise(0, 2); + raise(0, 2); } break; }// @suppress("No break at end of case") @@ -2244,7 +2244,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt; + *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt; } break; }// @suppress("No break at end of case") @@ -2264,11 +2264,11 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(shamt) { - *(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> shamt); + *(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> shamt); } else { - if(traits::XLEN == 128) { - *(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> 64); + if(traits::XLEN == 128) { + *(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> 64); } } } @@ -2289,7 +2289,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (uint32_t)((int8_t)sext<6>(imm) )); + *(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (uint32_t)((int8_t)sext<6>(imm) )); } break; }// @suppress("No break at end of case") @@ -2308,7 +2308,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+rd + 8) ) - (uint64_t)(*(X+rs2 + 8) )); + *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+rd + 8) ) - (uint64_t)(*(X+rs2 + 8) )); } break; }// @suppress("No break at end of case") @@ -2327,7 +2327,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+rd + 8) = *(X+rd + 8) ^ *(X+rs2 + 8); + *(X+rd + 8) = *(X+rd + 8) ^ *(X+rs2 + 8); } break; }// @suppress("No break at end of case") @@ -2346,7 +2346,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+rd + 8) = *(X+rd + 8) | *(X+rs2 + 8); + *(X+rd + 8) = *(X+rd + 8) | *(X+rs2 + 8); } break; }// @suppress("No break at end of case") @@ -2365,7 +2365,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - *(X+rd + 8) = *(X+rd + 8) & *(X+rs2 + 8); + *(X+rd + 8) = *(X+rd + 8) & *(X+rs2 + 8); } break; }// @suppress("No break at end of case") @@ -2402,7 +2402,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - if(*(X+rs1 + 8) == 0) { + if(*(X+rs1 + 8) == 0) { *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) )); this->core.reg.last_branch = 1; } @@ -2424,7 +2424,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - if(*(X+rs1 + 8) != 0) { + if(*(X+rs1 + 8) != 0) { *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) )); this->core.reg.last_branch = 1; } @@ -2447,10 +2447,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rs1 != 0) { + if(rs1 != 0) { *(X+rs1) = *(X+rs1) << nzuimm; } } @@ -2472,8 +2472,8 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - if(rd >= traits::RFS || rd == 0) { - raise(0, 2); + if(rd >= traits::RFS || rd == 0) { + raise(0, 2); } else { uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm )); @@ -2500,10 +2500,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = *(X+rs2); } } @@ -2525,7 +2525,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs1 && rs1 < traits::RFS) { - *NEXT_PC = *(X+(uint32_t)(rs1 ) % traits::RFS) & (uint32_t)(~ 0x1 ); + *NEXT_PC = *(X+(uint32_t)(rs1 ) % traits::RFS) & (uint32_t)(~ 1 ); this->core.reg.last_branch = 1; } else { @@ -2563,10 +2563,10 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rd >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { - if(rd != 0) { + if(rd != 0) { *(X+rd) = (uint32_t)((uint64_t)(*(X+rd) ) + (uint64_t)(*(X+rs2) )); } } @@ -2588,12 +2588,12 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs1 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t new_pc = *(X+rs1); - *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 2 )); - *NEXT_PC = new_pc & (uint32_t)(~ 0x1 ); + *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(2 )); + *NEXT_PC = new_pc & (uint32_t)(~ 1 ); this->core.reg.last_branch = 1; } } @@ -2608,7 +2608,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - raise(0, 3); + raise(0, 3); } break; }// @suppress("No break at end of case") @@ -2628,7 +2628,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co // execute instruction { if(rs2 >= traits::RFS) { - raise(0, 2); + raise(0, 2); } else { uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm )); @@ -2647,7 +2647,7 @@ typename vm_base::virt_addr_t vm_impl::execute_inst(finish_cond_e co *NEXT_PC = *PC + 2; // execute instruction { - raise(0, 2); + raise(0, 2); } break; }// @suppress("No break at end of case")