diff --git a/CMakeLists.txt b/CMakeLists.txt
index 3070844..2a46f47 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,8 +1,9 @@
-cmake_minimum_required(VERSION 3.12)
+cmake_minimum_required(VERSION 3.18)
 list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake)
-###############################################################################
+
+# ##############################################################################
 #
-###############################################################################
+# ##############################################################################
 project(dbt-rise-tgc VERSION 1.0.0)
 
 include(GNUInstallDirs)
@@ -14,59 +15,69 @@ find_package(Boost COMPONENTS coroutine REQUIRED)
 
 add_subdirectory(softfloat)
 
-set(LIB_SOURCES 
+set(LIB_SOURCES
     src/iss/plugin/instruction_count.cpp
-	src/iss/arch/tgc5c.cpp
-	src/vm/interp/vm_tgc5c.cpp
-	src/vm/fp_functions.cpp
+    src/iss/arch/tgc5c.cpp
+    src/vm/interp/vm_tgc5c.cpp
+    src/vm/fp_functions.cpp
+    src/iss/semihosting/semihosting.cpp
 )
+
 if(WITH_TCC)
-	list(APPEND LIB_SOURCES
-	   src/vm/tcc/vm_tgc5c.cpp
+    list(APPEND LIB_SOURCES
+        src/vm/tcc/vm_tgc5c.cpp
     )
 endif()
+
 if(WITH_LLVM)
-	list(APPEND LIB_SOURCES
-		src/vm/llvm/vm_tgc5c.cpp
-		src/vm/llvm/fp_impl.cpp
-	)
-endif()
-if(WITH_ASMJIT)
-	list(APPEND LIB_SOURCES
-	   src/vm/asmjit/vm_tgc5c.cpp
+    list(APPEND LIB_SOURCES
+        src/vm/llvm/vm_tgc5c.cpp
+        src/vm/llvm/fp_impl.cpp
     )
 endif()
+
+if(WITH_ASMJIT)
+    list(APPEND LIB_SOURCES
+        src/vm/asmjit/vm_tgc5c.cpp
+    )
+endif()
+
 # library files
 FILE(GLOB GEN_ISS_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp)
 FILE(GLOB GEN_VM_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp)
 FILE(GLOB GEN_YAML_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/contrib/instr/*.yaml)
 list(APPEND LIB_SOURCES ${GEN_ISS_SOURCES} ${GEN_VM_SOURCES})
+
 foreach(FILEPATH ${GEN_ISS_SOURCES})
     get_filename_component(CORE ${FILEPATH} NAME_WE)
     string(TOUPPER ${CORE} CORE)
     list(APPEND LIB_DEFINES CORE_${CORE})
 endforeach()
+
 message(STATUS "Core defines are ${LIB_DEFINES}")
 
 if(WITH_LLVM)
-	FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp)
-	list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
+    FILE(GLOB LLVM_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/llvm/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${LLVM_GEN_SOURCES})
 endif()
 
 if(WITH_TCC)
-	FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp)
-	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
+    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/tcc/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
 endif()
+
 if(WITH_ASMJIT)
-	FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/asmjit/vm_*.cpp)
-	list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
+    FILE(GLOB TCC_GEN_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/asmjit/vm_*.cpp)
+    list(APPEND LIB_SOURCES ${TCC_GEN_SOURCES})
 endif()
+
 if(TARGET yaml-cpp::yaml-cpp)
-    list(APPEND LIB_SOURCES 
-    	src/iss/plugin/cycle_estimate.cpp
-	    src/iss/plugin/instruction_count.cpp
+    list(APPEND LIB_SOURCES
+        src/iss/plugin/cycle_estimate.cpp
+        src/iss/plugin/instruction_count.cpp
     )
 endif()
+
 # Define the library
 add_library(${PROJECT_NAME} SHARED ${LIB_SOURCES})
 
@@ -75,60 +86,67 @@ if("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU")
 elseif("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC")
     target_compile_options(${PROJECT_NAME} PRIVATE /wd4293)
 endif()
+
 target_include_directories(${PROJECT_NAME} PUBLIC src)
 target_include_directories(${PROJECT_NAME} PUBLIC src-gen)
 
 target_force_link_libraries(${PROJECT_NAME} PRIVATE dbt-rise-core)
+
 # only re-export the include paths
 get_target_property(DBT_CORE_INCL dbt-rise-core INTERFACE_INCLUDE_DIRECTORIES)
 target_include_directories(${PROJECT_NAME} INTERFACE ${DBT_CORE_INCL})
 get_target_property(DBT_CORE_DEFS dbt-rise-core INTERFACE_COMPILE_DEFINITIONS)
-if(NOT (DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
-	target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
+
+if(NOT(DBT_CORE_DEFS STREQUAL DBT_CORE_DEFS-NOTFOUND))
+    target_compile_definitions(${PROJECT_NAME} INTERFACE ${DBT_CORE_DEFS})
 endif()
 
 target_link_libraries(${PROJECT_NAME} PUBLIC elfio::elfio softfloat scc-util Boost::coroutine)
+
 if(TARGET yaml-cpp::yaml-cpp)
-	target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)
-	target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
+    target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_PLUGINS)
+    target_link_libraries(${PROJECT_NAME} PUBLIC yaml-cpp::yaml-cpp)
 endif()
 
 if(WITH_LLVM)
     find_package(LLVM)
-	target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
-	target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
-	if(BUILD_SHARED_LIBS)
-		target_link_libraries( ${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
-	endif()
+    target_compile_definitions(${PROJECT_NAME} PUBLIC ${LLVM_DEFINITIONS})
+    target_include_directories(${PROJECT_NAME} PUBLIC ${LLVM_INCLUDE_DIRS})
+
+    if(BUILD_SHARED_LIBS)
+        target_link_libraries(${PROJECT_NAME} PUBLIC ${LLVM_LIBRARIES})
+    endif()
 endif()
 
 set_target_properties(${PROJECT_NAME} PROPERTIES
-  VERSION ${PROJECT_VERSION}
-  FRAMEWORK FALSE
+    VERSION ${PROJECT_VERSION}
+    FRAMEWORK FALSE
 )
 install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
-  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
-  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
-  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
-  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
-  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
-  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
+    EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
+    ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
+    RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
+    LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
+    FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+    PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
+    INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
 )
 install(DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/incl/iss COMPONENT ${PROJECT_NAME}
-        DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory
-        FILES_MATCHING # install only matched files
-        PATTERN "*.h" # select header files
-        )
+    DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # target directory
+    FILES_MATCHING # install only matched files
+    PATTERN "*.h" # select header files
+)
 install(FILES ${GEN_YAML_SOURCES} DESTINATION share/tgc-vp)
-###############################################################################
+
+# ##############################################################################
 #
-###############################################################################
+# ##############################################################################
 set(CMAKE_INSTALL_RPATH $ORIGIN/../${CMAKE_INSTALL_LIBDIR})
 project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)
 
 add_executable(${PROJECT_NAME} src/main.cpp)
+
 if(TARGET ${CORE_NAME}_cpp)
     list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
 else()
@@ -140,21 +158,20 @@ else()
 endif()
 
 foreach(F IN LISTS TGC_SOURCES)
-    if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
-        string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
+    if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
+        string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
         string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
         target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
     endif()
 endforeach()
 
-#if(WITH_LLVM)
-#    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
-#    #target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-#endif()
-#if(WITH_TCC)
-#    target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
-#endif()
-
+# if(WITH_LLVM)
+# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_LLVM)
+# #target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+# endif()
+# if(WITH_TCC)
+# target_compile_definitions(${PROJECT_NAME} PRIVATE WITH_TCC)
+# endif()
 target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc fmt::fmt)
 
 if(TARGET Boost::program_options)
@@ -162,78 +179,85 @@ if(TARGET Boost::program_options)
 else()
     target_link_libraries(${PROJECT_NAME} PUBLIC ${BOOST_program_options_LIBRARY})
 endif()
+
 target_link_libraries(${PROJECT_NAME} PUBLIC ${CMAKE_DL_LIBS})
-if (Tcmalloc_FOUND)
+
+if(Tcmalloc_FOUND)
     target_link_libraries(${PROJECT_NAME} PUBLIC ${Tcmalloc_LIBRARIES})
 endif(Tcmalloc_FOUND)
 
 install(TARGETS tgc-sim
-  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
-  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
-  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
-  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
-  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME}  # headers for mac (note the different component -> different package)
-  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
+    EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
+    ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
+    RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
+    LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
+    FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+    PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} # headers for mac (note the different component -> different package)
+    INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
 )
 
 if(BUILD_TESTING)
-  	# ... CMake code to create tests ...
-	add_test(NAME tgc-sim-interp
-	         COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp)
-	if(WITH_TCC)
-	add_test(NAME tgc-sim-tcc
-	         COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc)
-	endif()
-	if(WITH_LLVM)
-	add_test(NAME tgc-sim-llvm
-	         COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm)
-	endif()
+    # ... CMake code to create tests ...
+    add_test(NAME tgc-sim-interp
+        COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend interp)
+
+    if(WITH_TCC)
+        add_test(NAME tgc-sim-tcc
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend tcc)
+    endif()
+
+    if(WITH_LLVM)
+        add_test(NAME tgc-sim-llvm
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend llvm)
+    endif()
+
     if(WITH_ASMJIT)
-	add_test(NAME tgc-sim-asmjit
-	         COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend asmjit)
-	endif()
+        add_test(NAME tgc-sim-asmjit
+            COMMAND tgc-sim -f ${CMAKE_BINARY_DIR}/../../Firmwares/hello-world/hello --backend asmjit)
+    endif()
 endif()
-###############################################################################
+
+# ##############################################################################
 #
-###############################################################################
+# ##############################################################################
 if(TARGET scc-sysc)
-	project(dbt-rise-tgc_sc VERSION 1.0.0)
-	set(LIB_SOURCES 
-    	src/sysc/core_complex.cpp
-    	src/sysc/register_tgc_c.cpp
-	)
-	FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/sysc/register_*.cpp)
-	list(APPEND LIB_SOURCES ${GEN_SC_SOURCES})
+    project(dbt-rise-tgc_sc VERSION 1.0.0)
+    set(LIB_SOURCES
+        src/sysc/core_complex.cpp
+        src/sysc/register_tgc_c.cpp
+    )
+    FILE(GLOB GEN_SC_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/sysc/register_*.cpp)
+    list(APPEND LIB_SOURCES ${GEN_SC_SOURCES})
     add_library(${PROJECT_NAME} ${LIB_SOURCES})
     target_compile_definitions(${PROJECT_NAME} PUBLIC WITH_SYSTEMC)
     target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
+
     foreach(F IN LISTS TGC_SOURCES)
-        if (${F} MATCHES ".*/arch/([^/]*)\.cpp")
-            string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
+        if(${F} MATCHES ".*/arch/([^/]*)\.cpp")
+            string(REGEX REPLACE ".*/([^/]*)\.cpp" "\\1" CORE_NAME_LC ${F})
             string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
             target_compile_definitions(${PROJECT_NAME} PRIVATE CORE_${CORE_NAME})
         endif()
     endforeach()
+
     target_link_libraries(${PROJECT_NAME} PUBLIC dbt-rise-tgc scc-sysc)
-#    if(WITH_LLVM)
-#        target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
-#    endif()
-    
-	set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
+
+    # if(WITH_LLVM)
+    # target_link_libraries(${PROJECT_NAME} PUBLIC ${llvm_libs})
+    # endif()
+    set(LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/src/sysc/core_complex.h)
     set_target_properties(${PROJECT_NAME} PROPERTIES
-      VERSION ${PROJECT_VERSION}
-      FRAMEWORK FALSE
-      PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
+        VERSION ${PROJECT_VERSION}
+        FRAMEWORK FALSE
+        PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
     )
     install(TARGETS ${PROJECT_NAME} COMPONENT ${PROJECT_NAME}
-	  EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-	  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}  # static lib
-	  RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}  # binaries
-	  LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}  # shared lib
-	  FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
-	  PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc   # headers for mac (note the different component -> different package)
-	  INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}             # headers
-	)    
+        EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
+        ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} # static lib
+        RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} # binaries
+        LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} # shared lib
+        FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} # for mac
+        PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/sysc # headers for mac (note the different component -> different package)
+        INCLUDES DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} # headers
+    )
 endif()
-
diff --git a/contrib/instr/TGC5C_instr.yaml b/contrib/instr/TGC5C_instr.yaml
index c1692e0..1663d37 100644
--- a/contrib/instr/TGC5C_instr.yaml
+++ b/contrib/instr/TGC5C_instr.yaml
@@ -349,7 +349,7 @@ Zifencei:
     size:   32
     branch:   false
     delay:   1
-RV32M: 
+RVM: 
   MUL:
     index: 49
     encoding: 0b00000010000000000000000000110011
diff --git a/gen_input/templates/CORENAME.h.gtl b/gen_input/templates/CORENAME.h.gtl
index d5ba6c4..02ecb68 100644
--- a/gen_input/templates/CORENAME.h.gtl
+++ b/gen_input/templates/CORENAME.h.gtl
@@ -109,7 +109,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { ${spaces.collect{it.name}.join(', ')} };
+    enum mem_type_e { ${spaces.collect{it.name}.join(', ')}, IMEM = MEM };
     
     enum class opcode_e {<%instructions.eachWithIndex{instr, index -> %>
         ${instr.instruction.name} = ${index},<%}%>
diff --git a/gen_input/templates/asmjit/CORENAME.cpp.gtl b/gen_input/templates/asmjit/CORENAME.cpp.gtl
index 74f54d4..b671123 100644
--- a/gen_input/templates/asmjit/CORENAME.cpp.gtl
+++ b/gen_input/templates/asmjit/CORENAME.cpp.gtl
@@ -79,21 +79,36 @@ public:
     }
 
 protected:
-    using vm_base<ARCH>::get_reg_ptr;
+    using super::get_ptr_for;
+using super::get_reg;
+    using super::get_reg_for;
+    using super::load_reg_from_mem;
+    using super::write_reg_to_mem;
+    using super::gen_ext;
+    using super::gen_read_mem;
+    using super::gen_write_mem;
+    using super::gen_wait;
+    using super::gen_leave;
+    using super::gen_operation;
+   
     using this_class = vm_impl<ARCH>;
     using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
 
     continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
+    void gen_block_prologue(jit_holder& jh) override;
+    void gen_block_epilogue(jit_holder& jh) override;
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
+    void gen_instr_prologue(jit_holder& jh);
+    void gen_instr_epilogue(jit_holder& jh);
+    inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
+
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
         auto sign_mask = 1ULL<<(W-1);
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     } 
-#include <vm/asmjit/helper_func.h>
-
 private:
     /****************************************************************************
      * start opcode definitions
@@ -127,16 +142,26 @@ private:
         <%instr.fields.eachLine{%>${it}
         <%}%>if(this->disass_enabled){
             /* generate disass */
+            <%instr.disass.eachLine{%>
+            ${it}<%}%>
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\\n${instr.name}_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("${instr.name}_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, ${idx});
-        pc=pc+ ${instr.length/8};
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+${instr.length/8};
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         <%instr.behavior.eachLine{%>${it}
         <%}%>
@@ -149,9 +174,17 @@ private:
      * end opcode definitions
      ****************************************************************************/
     continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
-
+        x86::Compiler& cc = jh.cc;
+        cc.comment(fmt::format("illegal_intruction{:#x}:",pc.val).c_str());
+        this->gen_sync(jh, PRE_SYNC, instr_descr.size());
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
+        gen_instr_epilogue(jh);
+        this->gen_sync(jh, POST_SYNC, instr_descr.size());
         return BRANCH;
-    }    
+    }
+     
     //decoding functionality
 
     void populate_decoding_tree(decoding_tree_node* root){
@@ -206,11 +239,6 @@ private:
     }
 };
 
-template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
-    volatile CODE_WORD x = instr;
-    instr = 2 * x;
-}
-
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 
 template <typename ARCH>
@@ -224,8 +252,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 }
 
 template <typename ARCH>
-continuation_e
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
+continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
     phys_addr_t paddr(pc);
@@ -243,10 +270,78 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
         f = &this_class::illegal_intruction;
     return (this->*f)(pc, instr, jh);
 }
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
+    auto& cc = jh.cc;
 
+    cc.comment("//gen_instr_prologue");
+    cc.inc(get_ptr_for(jh, traits::ICOUNT));
 
+    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
+    cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+    cc.mov(get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
 
-} // namespace ${coreDef.name.toLowerCase()}
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
+    auto& cc = jh.cc;
+
+    cc.comment("//gen_instr_epilogue");
+    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
+    cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+    cc.cmp(current_trap_state, 0);
+    cc.jne(jh.trap_entry);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
+
+    jh.pc = load_reg_from_mem(jh, traits::PC);
+    jh.next_pc = load_reg_from_mem(jh, traits::NEXT_PC);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
+    x86::Compiler& cc = jh.cc;
+    cc.comment("//gen_block_epilogue");
+    cc.ret(jh.next_pc);
+
+    cc.bind(jh.trap_entry);
+    this->write_back(jh);
+    this->gen_sync(jh, POST_SYNC, -1);
+
+    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
+    cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+
+    x86::Gp current_pc = get_reg_for(jh, traits::PC);
+    cc.mov(current_pc, get_ptr_for(jh, traits::PC));
+
+    x86::Gp instr = cc.newInt32("instr");
+    cc.mov(instr, 0); // FIXME:this is not correct
+    cc.comment("//enter trap call;");
+    InvokeNode* call_enter_trap;
+    cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
+    call_enter_trap->setArg(0, jh.arch_if_ptr);
+    call_enter_trap->setArg(1, current_trap_state);
+    call_enter_trap->setArg(2, current_pc);
+    call_enter_trap->setArg(3, instr);
+
+    x86::Gp current_next_pc = get_reg_for(jh, traits::NEXT_PC);
+    cc.mov(current_next_pc, get_ptr_for(jh, traits::NEXT_PC));
+    cc.mov(jh.next_pc, current_next_pc);
+
+    cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), std::numeric_limits<uint32_t>::max());
+    cc.ret(jh.next_pc);
+}
+template <typename ARCH>
+inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
+    auto& cc = jh.cc;
+    cc.comment("//gen_raise");
+    auto tmp1 = get_reg_for(jh, traits::TRAP_STATE);
+    cc.mov(tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
+    cc.mov(get_ptr_for(jh, traits::TRAP_STATE), tmp1);
+    cc.mov(jh.next_pc, std::numeric_limits<uint32_t>::max());
+}
+
+} // namespace tgc5c
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
@@ -257,22 +352,30 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 } // namespace asmjit
 } // namespace iss
 
-#include <iss/factory.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-            auto* vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-            auto* vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+		    auto vm = new asmjit::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl
index c2eb071..fd2bbc6 100644
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -357,22 +357,30 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 } // namespace interp
 } // namespace iss
 
-#include <iss/factory.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
diff --git a/gen_input/templates/llvm/CORENAME.cpp.gtl b/gen_input/templates/llvm/CORENAME.cpp.gtl
index 5945e35..9bbd147 100644
--- a/gen_input/templates/llvm/CORENAME.cpp.gtl
+++ b/gen_input/templates/llvm/CORENAME.cpp.gtl
@@ -99,16 +99,11 @@ protected:
     std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
 
     void gen_leave_behavior(BasicBlock *leave_blk) override;
-
     void gen_raise_trap(uint16_t trap_id, uint16_t cause);
-
     void gen_leave_trap(unsigned lvl);
-
     void gen_wait(unsigned type);
-
     void gen_trap_behavior(BasicBlock *) override;
-
-    void gen_trap_check(BasicBlock *bb);
+    void gen_instr_epilogue(BasicBlock *bb);
 
     inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
         return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false);
@@ -162,20 +157,22 @@ private:
     /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
     /* instruction ${idx}: ${instr.name} */
     std::tuple<continuation_e, BasicBlock*> __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
-        bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val));
-        this->gen_sync(PRE_SYNC,${idx});
         uint64_t PC = pc.val;
         <%instr.fields.eachLine{%>${it}
         <%}%>if(this->disass_enabled){
             /* generate console output when executing the command */<%instr.disass.eachLine{%>
             ${it}<%}%>
         }
+        bb->setName(fmt::format("${instr.name}_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,${idx});
         auto cur_pc_val = this->gen_const(32,pc.val);
         pc=pc+ ${instr.length/8};
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         <%instr.behavior.eachLine{%>${it}
         <%}%>
-        this->gen_trap_check(bb);
+        this->gen_instr_epilogue(bb);
     	this->gen_sync(POST_SYNC, ${idx});
         this->builder.CreateBr(bb);
     	return returnValue;        
@@ -195,7 +192,7 @@ private:
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
         this->gen_raise_trap(0, 2);     // illegal instruction trap
 		this->gen_sync(iss::POST_SYNC, instr_descr.size());
-        this->gen_trap_check(this->leave_blk);
+        this->gen_instr_epilogue(this->leave_blk);
         return std::make_tuple(BRANCH, nullptr);
     }    
     //decoding functionality
@@ -301,18 +298,21 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
     return (this->*f)(pc, instr, this_block);
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
+template <typename ARCH>
+void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
     this->builder.SetInsertPoint(leave_blk);
     this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false));
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
+template <typename ARCH>
+void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
     auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
     this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
     this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits::LAST_BRANCH), false);
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
+template <typename ARCH>
+void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
     std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
     this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
     auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8);
@@ -320,12 +320,14 @@ template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
     this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits::LAST_BRANCH), false);
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
+template <typename ARCH>
+void vm_impl<ARCH>::gen_wait(unsigned type) {
     std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
     this->builder.CreateCall(this->mod->getFunction("wait"), args);
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
+template <typename ARCH> 
+void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
     this->builder.SetInsertPoint(trap_blk);
     this->gen_sync(POST_SYNC, -1); //TODO get right InstrId
     auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
@@ -338,7 +340,8 @@ template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_
     this->builder.CreateRet(trap_addr_val);
 }
 
-template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock *bb) {
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
     auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb);
     auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
     this->gen_cond_branch(this->builder.CreateICmp(
@@ -359,22 +362,30 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 } // namespace llvm
 } // namespace iss
 
-#include <iss/factory.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
-            auto* vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
-            auto* vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+		    auto vm = new llvm::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t*)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
diff --git a/gen_input/templates/tcc/CORENAME.cpp.gtl b/gen_input/templates/tcc/CORENAME.cpp.gtl
index 252df3d..f9ee677 100644
--- a/gen_input/templates/tcc/CORENAME.cpp.gtl
+++ b/gen_input/templates/tcc/CORENAME.cpp.gtl
@@ -292,7 +292,7 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
     tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
-    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
+    tu.store(traits::NEXT_PC, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
@@ -323,22 +323,30 @@ std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreD
 } // namesapce tcc
 } // namespace iss
 
-#include <iss/factory.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("${coreDef.name.toLowerCase()}|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::${coreDef.name.toLowerCase()}>();
 		    auto vm = new tcc::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
diff --git a/softfloat/CMakeLists.txt b/softfloat/CMakeLists.txt
index b2ff9df..b5766c6 100644
--- a/softfloat/CMakeLists.txt
+++ b/softfloat/CMakeLists.txt
@@ -327,7 +327,7 @@ set(OTHERS
 
 set(LIB_SOURCES ${PRIMITIVES} ${SPECIALIZE} ${OTHERS})
 
-add_library(softfloat ${LIB_SOURCES})
+add_library(softfloat STATIC ${LIB_SOURCES})
 set_property(TARGET softfloat PROPERTY C_STANDARD 99)
 target_compile_definitions(softfloat PRIVATE 
 	SOFTFLOAT_ROUND_ODD 
@@ -347,7 +347,7 @@ set_target_properties(softfloat PROPERTIES
 
 install(TARGETS softfloat
   EXPORT ${PROJECT_NAME}Targets            # for downstream dependencies
-  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # static lib
+  ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}/static COMPONENT libs   # static lib
   LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs   # shared lib
   FRAMEWORK DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT libs # for mac
   PUBLIC_HEADER DESTINATION ${CMAKE_INSTALL_INCLUDEDIR} COMPONENT devel   # headers for mac (note the different component -> different package)
diff --git a/src/iss/arch/riscv_hart_common.h b/src/iss/arch/riscv_hart_common.h
index 4ac086d..829fbb1 100644
--- a/src/iss/arch/riscv_hart_common.h
+++ b/src/iss/arch/riscv_hart_common.h
@@ -35,8 +35,14 @@
 #ifndef _RISCV_HART_COMMON
 #define _RISCV_HART_COMMON
 
-#include "iss/arch_if.h"
 #include <cstdint>
+#include <elfio/elfio.hpp>
+#include <fmt/format.h>
+#include <iss/arch_if.h>
+#include <iss/log_categories.h>
+#include <string>
+#include <unordered_map>
+#include <util/logging.h>
 
 namespace iss {
 namespace arch {
@@ -296,6 +302,61 @@ inline void write_reg_uint32(uint64_t offs, uint32_t& reg, const uint8_t* const
         break;
     }
 }
+struct riscv_hart_common {
+    riscv_hart_common(){};
+    ~riscv_hart_common(){};
+    std::unordered_map<std::string, uint64_t> symbol_table;
+
+    std::unordered_map<std::string, uint64_t> get_sym_table(std::string name) {
+        if(!symbol_table.empty())
+            return symbol_table;
+        FILE* fp = fopen(name.c_str(), "r");
+        if(fp) {
+            std::array<char, 5> buf;
+            auto n = fread(buf.data(), 1, 4, fp);
+            fclose(fp);
+            if(n != 4)
+                throw std::runtime_error("input file has insufficient size");
+            buf[4] = 0;
+            if(strcmp(buf.data() + 1, "ELF") == 0) {
+                // Create elfio reader
+                ELFIO::elfio reader;
+                // Load ELF data
+                if(!reader.load(name))
+                    throw std::runtime_error("could not process elf file");
+                // check elf properties
+                if(reader.get_type() != ET_EXEC)
+                    throw std::runtime_error("wrong elf type in file");
+                if(reader.get_machine() != EM_RISCV)
+                    throw std::runtime_error("wrong elf machine in file");
+                const auto sym_sec = reader.sections[".symtab"];
+                if(SHT_SYMTAB == sym_sec->get_type() || SHT_DYNSYM == sym_sec->get_type()) {
+                    ELFIO::symbol_section_accessor symbols(reader, sym_sec);
+                    auto sym_no = symbols.get_symbols_num();
+                    std::string name;
+                    ELFIO::Elf64_Addr value = 0;
+                    ELFIO::Elf_Xword size = 0;
+                    unsigned char bind = 0;
+                    unsigned char type = 0;
+                    ELFIO::Elf_Half section = 0;
+                    unsigned char other = 0;
+                    for(auto i = 0U; i < sym_no; ++i) {
+                        symbols.get_symbol(i, name, value, size, bind, type, section, other);
+                        if(name != "") {
+                            this->symbol_table[name] = value;
+#ifndef NDEBUG
+                            CPPLOG(DEBUG) << "Found Symbol " << name;
+#endif
+                        }
+                    }
+                }
+                return symbol_table;
+            }
+            throw std::runtime_error(fmt::format("memory load file {} is not a valid elf file", name));
+        } else
+            throw std::runtime_error(fmt::format("memory load file not found, check if {} is a valid file", name));
+    };
+};
 
 } // namespace arch
 } // namespace iss
diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index e22c970..dfbef36 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -40,6 +40,7 @@
 #include "iss/log_categories.h"
 #include "iss/vm_if.h"
 #include "riscv_hart_common.h"
+#include <stdexcept>
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
 #endif
@@ -55,6 +56,8 @@
 #include <util/ities.h>
 #include <util/sparse_array.h>
 
+#include <iss/semihosting/semihosting.h>
+
 #if defined(__GNUC__)
 #define likely(x) __builtin_expect(!!(x), 1)
 #define unlikely(x) __builtin_expect(!!(x), 0)
@@ -66,7 +69,7 @@
 namespace iss {
 namespace arch {
 
-template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : public BASE {
+template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : public BASE, public riscv_hart_common {
 protected:
     const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
     const std::array<const char*, 16> trap_str = {{""
@@ -290,6 +293,8 @@ public:
 
     void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); }
 
+    void set_semihosting_callback(semihosting_cb_t<reg_t> cb) { semihosting_cb = cb; };
+
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
@@ -322,6 +327,8 @@ protected:
 
         unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
 
+        std::unordered_map<std::string, uint64_t> get_symbol_table(std::string name) override { return arch.get_sym_table(name); }
+
         riscv_hart_m_p<BASE, FEAT>& arch;
     };
 
@@ -344,9 +351,11 @@ protected:
     reg_t fault_data;
     uint64_t tohost = tohost_dflt;
     uint64_t fromhost = fromhost_dflt;
-    unsigned to_host_wr_cnt = 0;
+    bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
+    semihosting_cb_t<reg_t> semihosting_cb;
+
     using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
     using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
     using csr_page_type = typename csr_type::page_type;
@@ -419,6 +428,7 @@ protected:
     feature_config cfg;
     unsigned mcause_max_irq{(FEAT & features_e::FEAT_CLIC) ? std::max(16U, static_cast<unsigned>(traits<BASE>::CLIC_NUM_IRQ)) : 16U};
     inline bool debug_mode_active() { return this->reg.PRIV & 0x4; }
+
     std::pair<std::function<mem_read_f>, std::function<mem_write_f>> replace_mem_access(std::function<mem_read_f> rd,
                                                                                         std::function<mem_write_f> wr) {
         std::pair<std::function<mem_read_f>, std::function<mem_write_f>> ret{hart_mem_rd_delegate, hart_mem_wr_delegate};
@@ -563,6 +573,12 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
 }
 
 template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT>::load_file(std::string name, int type) {
+    get_sym_table(name);
+    try {
+        tohost = symbol_table.at("tohost");
+        fromhost = symbol_table.at("fromhost");
+    } catch(std::out_of_range& e) {
+    }
     FILE* fp = fopen(name.c_str(), "r");
     if(fp) {
         std::array<char, 5> buf;
@@ -593,31 +609,11 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
                     auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
                                            pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
                     if(res != iss::Ok)
-                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
+                        CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
                 }
             }
             for(const auto sec : reader.sections) {
-                if(sec->get_name() == ".symtab") {
-                    if(SHT_SYMTAB == sec->get_type() || SHT_DYNSYM == sec->get_type()) {
-                        ELFIO::symbol_section_accessor symbols(reader, sec);
-                        auto sym_no = symbols.get_symbols_num();
-                        std::string name;
-                        ELFIO::Elf64_Addr value = 0;
-                        ELFIO::Elf_Xword size = 0;
-                        unsigned char bind = 0;
-                        unsigned char type = 0;
-                        ELFIO::Elf_Half section = 0;
-                        unsigned char other = 0;
-                        for(auto i = 0U; i < sym_no; ++i) {
-                            symbols.get_symbol(i, name, value, size, bind, type, section, other);
-                            if(name == "tohost") {
-                                tohost = value;
-                            } else if(name == "fromhost") {
-                                fromhost = value;
-                            }
-                        }
-                    }
-                } else if(sec->get_name() == ".tohost") {
+                if(sec->get_name() == ".tohost") {
                     tohost = sec->get_address();
                     fromhost = tohost + 0x40;
                 }
@@ -647,11 +643,11 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
                                              const unsigned length, uint8_t* const data) {
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
-        LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
+        CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
     } else if(access && iss::access_type::FETCH) {
-        LOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
+        CPPLOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
     } else {
-        LOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
+        CPPLOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
     }
 #endif
     try {
@@ -733,23 +729,23 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
     case 8:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     case 4:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     case 2:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     case 1:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     default:
-        LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
     }
 #endif
     try {
@@ -784,7 +780,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
                     res = write_mem(phys_addr, length, data);
                 }
                 if(unlikely(res != iss::Ok && (access & access_type::DEBUG) == 0)) {
-                    this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
+                    this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
                     fault_data = addr;
                 }
                 return res;
@@ -801,7 +797,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
             case 0x10023000: // UART1 base, TXFIFO reg
                 uart_buf << (char)data[0];
                 if(((char)data[0]) == '\n' || data[0] == 0) {
-                    // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
+                    // CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
                     // '"<<uart_buf.str()<<"'";
                     std::cout << uart_buf.str();
                     uart_buf.str("");
@@ -1098,9 +1094,10 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned len
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
     switch(paddr.val) {
+    // TODO remove UART, Peripherals should not be part of the ISS
     case 0xFFFF0000: // UART0 base, TXFIFO reg
         if(((char)data[0]) == '\n' || data[0] == 0) {
-            LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
+            CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
             uart_buf.str("");
         } else if(((char)data[0]) != '\r')
             uart_buf << (char)data[0];
@@ -1115,36 +1112,34 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
             auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
             if(tohost_lower || tohost_upper) {
                 uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
-                if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
+                // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
+                if(tohost_upper && (tohost_lower || tohost_lower_written)) {
                     switch(hostvar >> 48) {
                     case 0:
                         if(hostvar != 0x1) {
-                            LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                       << "), stopping simulation";
+                            CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                                          << "), stopping simulation";
                         } else {
-                            LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                      << "), stopping simulation";
+                            CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                                         << "), stopping simulation";
                         }
                         this->reg.trap_state = std::numeric_limits<uint32_t>::max();
                         this->interrupt_sim = hostvar;
-#ifndef WITH_TCC
-                        throw(iss::simulation_stopped(hostvar));
-#endif
                         break;
                     case 0x0101: {
                         char c = static_cast<char>(hostvar & 0xff);
                         if(c == '\n' || c == 0) {
-                            LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
+                            CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
                             uart_buf.str("");
                         } else
                             uart_buf << c;
-                        to_host_wr_cnt = 0;
                     } break;
                     default:
                         break;
                     }
+                    tohost_lower_written = false;
                 } else if(tohost_lower)
-                    to_host_wr_cnt++;
+                    tohost_lower_written = true;
             } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                 uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
                 *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
@@ -1253,6 +1248,31 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
             } else {
                 csr[mtval] = addr;
             }
+            if(semihosting_cb) {
+                // Check for semihosting call
+                phys_addr_t p_addr(access_type::DEBUG_READ, traits<BASE>::MEM, addr - 4);
+                std::array<uint8_t, 8> data;
+                // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07
+                this->read_mem(p_addr, 4, data.data());
+                p_addr.val += 8;
+                this->read_mem(p_addr, 4, data.data() + 4);
+
+                const std::array<uint8_t, 8> ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40};
+                if(data == ref_data) {
+                    this->reg.NEXT_PC = addr + 8;
+
+                    std::array<char, 32> buffer;
+#if defined(_MSC_VER)
+                    sprintf(buffer.data(), "0x%016llx", addr);
+#else
+                    sprintf(buffer.data(), "0x%016lx", addr);
+#endif
+                    CLOG(INFO, disass) << "Semihosting call at address " << buffer.data() << " occurred ";
+
+                    semihosting_cb(this, &(this->reg.X10) /*a0*/, &(this->reg.X11) /*a1*/);
+                    return this->reg.NEXT_PC;
+                }
+            }
             break;
         case 4:
         case 6:
diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h
index 2a4bc90..1a350b8 100644
--- a/src/iss/arch/riscv_hart_msu_vp.h
+++ b/src/iss/arch/riscv_hart_msu_vp.h
@@ -55,6 +55,8 @@
 #include <util/ities.h>
 #include <util/sparse_array.h>
 
+#include <iss/semihosting/semihosting.h>
+
 #if defined(__GNUC__)
 #define likely(x) __builtin_expect(!!(x), 1)
 #define unlikely(x) __builtin_expect(!!(x), 0)
@@ -66,7 +68,7 @@
 namespace iss {
 namespace arch {
 
-template <typename BASE> class riscv_hart_msu_vp : public BASE {
+template <typename BASE> class riscv_hart_msu_vp : public BASE, public riscv_hart_common {
 protected:
     const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
     const std::array<const char*, 16> trap_str = {{""
@@ -341,6 +343,8 @@ public:
 
     void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); }
 
+    void set_semihosting_callback(std::function<void(arch_if*, reg_t, reg_t)>& cb) { semihosting_cb = cb; };
+
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
@@ -373,6 +377,8 @@ protected:
 
         unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
 
+        std::unordered_map<std::string, uint64_t> get_symbol_table(std::string name) override { return arch.get_sym_table(name); }
+
         riscv_hart_msu_vp<BASE>& arch;
     };
 
@@ -395,9 +401,11 @@ protected:
     std::array<vm_info, 2> vm;
     uint64_t tohost = tohost_dflt;
     uint64_t fromhost = fromhost_dflt;
-    unsigned to_host_wr_cnt = 0;
+    bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
+    std::function<void(arch_if*, reg_t, reg_t)> semihosting_cb;
+
     using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
     using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
     using csr_page_type = typename csr_type::page_type;
@@ -585,7 +593,7 @@ template <typename BASE> std::pair<uint64_t, bool> riscv_hart_msu_vp<BASE>::load
                     auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
                                            pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
                     if(res != iss::Ok)
-                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
+                        CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
                 }
             }
             for(const auto sec : reader.sections) {
@@ -626,11 +634,11 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
                                           const unsigned length, uint8_t* const data) {
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
-        LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
+        CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
     } else if(access && iss::access_type::FETCH) {
-        LOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
+        CPPLOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
     } else {
-        LOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
+        CPPLOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
     }
 #endif
     try {
@@ -720,23 +728,23 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
     case 8:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     case 4:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     case 2:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     case 1:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     default:
-        LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
     }
 #endif
     try {
@@ -781,7 +789,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
             case 0x10023000: // UART1 base, TXFIFO reg
                 uart_buf << (char)data[0];
                 if(((char)data[0]) == '\n' || data[0] == 0) {
-                    // LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
+                    // CPPLOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send
                     // '"<<uart_buf.str()<<"'";
                     std::cout << uart_buf.str();
                     uart_buf.str("");
@@ -1077,7 +1085,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_add
     switch(paddr.val) {
     case 0xFFFF0000: // UART0 base, TXFIFO reg
         if(((char)data[0]) == '\n' || data[0] == 0) {
-            LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
+            CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
             uart_buf.str("");
         } else if(((char)data[0]) != '\r')
             uart_buf << (char)data[0];
@@ -1092,34 +1100,37 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_add
             auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
             if(tohost_lower || tohost_upper) {
                 uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
-                if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
+                // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
+                if(tohost_upper && (tohost_lower || tohost_lower_written)) {
                     switch(hostvar >> 48) {
                     case 0:
                         if(hostvar != 0x1) {
-                            LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                       << "), stopping simulation";
+                            CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                                          << "), stopping simulation";
                         } else {
-                            LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                      << "), stopping simulation";
+                            CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                                         << "), stopping simulation";
                         }
                         this->reg.trap_state = std::numeric_limits<uint32_t>::max();
                         this->interrupt_sim = hostvar;
+#ifndef WITH_TCC
+                        throw(iss::simulation_stopped(hostvar));
+#endif
                         break;
-                        // throw(iss::simulation_stopped(hostvar));
                     case 0x0101: {
                         char c = static_cast<char>(hostvar & 0xff);
                         if(c == '\n' || c == 0) {
-                            LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
+                            CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
                             uart_buf.str("");
                         } else
                             uart_buf << c;
-                        to_host_wr_cnt = 0;
                     } break;
                     default:
                         break;
                     }
+                    tohost_lower_written = false;
                 } else if(tohost_lower)
-                    to_host_wr_cnt++;
+                    tohost_lower_written = true;
             } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                 uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
                 *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
@@ -1304,6 +1315,31 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
             // csr[dpc] = addr;
             // csr[dcsr] = (csr[dcsr] & ~0x1c3) | (1<<6) | PRIV_M; //FIXME: cause should not be 4 (stepi)
             csr[utval | (new_priv << 8)] = addr;
+            if(semihosting_cb) {
+                // Check for semihosting call
+                phys_addr_t p_addr(access_type::DEBUG_READ, traits<BASE>::MEM, addr - 4);
+                std::array<uint8_t, 8> data;
+                // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07
+                this->read_mem(p_addr, 4, data.data());
+                p_addr.val += 8;
+                this->read_mem(p_addr, 4, data.data() + 4);
+
+                const std::array<uint8_t, 8> ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40};
+                if(data == ref_data) {
+                    this->reg.NEXT_PC = addr + 8;
+
+                    std::array<char, 32> buffer;
+#if defined(_MSC_VER)
+                    sprintf(buffer.data(), "0x%016llx", addr);
+#else
+                    sprintf(buffer.data(), "0x%016lx", addr);
+#endif
+                    CLOG(INFO, disass) << "Semihosting call at address " << buffer.data() << " occurred ";
+
+                    semihosting_callback(this, this->reg.X10 /*a0*/, this->reg.X11 /*a1*/);
+                    return this->reg.NEXT_PC;
+                }
+            }
             break;
         case 4:
         case 6:
@@ -1321,7 +1357,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
         this->reg.pending_trap = 0;
     }
     size_t adr = ucause | (new_priv << 8);
-    csr[adr] = (trap_id << 31) + cause;
+    csr[adr] = (trap_id << (traits<BASE>::XLEN - 1)) + cause;
     // update mstatus
     // xPP field of mstatus is written with the active privilege mode at the time
     // of the trap; the x PIE field of mstatus
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 7aa8b21..5928d4e 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -55,6 +55,8 @@
 #include <util/ities.h>
 #include <util/sparse_array.h>
 
+#include <iss/semihosting/semihosting.h>
+
 #if defined(__GNUC__)
 #define likely(x) __builtin_expect(!!(x), 1)
 #define unlikely(x) __builtin_expect(!!(x), 0)
@@ -66,7 +68,7 @@
 namespace iss {
 namespace arch {
 
-template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : public BASE {
+template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : public BASE, public riscv_hart_common {
 protected:
     const std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
     const std::array<const char*, 16> trap_str = {{""
@@ -317,6 +319,8 @@ public:
 
     void set_irq_num(unsigned i) { mcause_max_irq = 1 << util::ilog2(i); }
 
+    void set_semihosting_callback(semihosting_cb_t<reg_t> cb) { semihosting_cb = cb; };
+
 protected:
     struct riscv_instrumentation_if : public iss::instrumentation_if {
 
@@ -349,6 +353,8 @@ protected:
 
         unsigned get_reg_size(unsigned num) override { return traits<BASE>::reg_bit_widths[num]; }
 
+        std::unordered_map<std::string, uint64_t> get_symbol_table(std::string name) override { return arch.get_sym_table(name); }
+
         riscv_hart_mu_p<BASE, FEAT>& arch;
     };
 
@@ -371,9 +377,11 @@ protected:
     reg_t fault_data;
     uint64_t tohost = tohost_dflt;
     uint64_t fromhost = fromhost_dflt;
-    unsigned to_host_wr_cnt = 0;
+    bool tohost_lower_written = false;
     riscv_instrumentation_if instr_if;
 
+    semihosting_cb_t<reg_t> semihosting_cb;
+
     using mem_type = util::sparse_array<uint8_t, 1ULL << 32>;
     using csr_type = util::sparse_array<typename traits<BASE>::reg_t, 1ULL << 12, 12>;
     using csr_page_type = typename csr_type::page_type;
@@ -672,7 +680,7 @@ template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m
                     auto res = this->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_WRITE, traits<BASE>::MEM,
                                            pseg->get_physical_address(), fsize, reinterpret_cast<const uint8_t* const>(seg_data));
                     if(res != iss::Ok)
-                        LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
+                        CPPLOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address();
                 }
             }
             for(const auto sec : reader.sections) {
@@ -812,11 +820,11 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                                               const unsigned length, uint8_t* const data) {
 #ifndef NDEBUG
     if(access && iss::access_type::DEBUG) {
-        LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
+        CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
     } else if(is_fetch(access)) {
-        LOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
+        CPPLOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
     } else {
-        LOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
+        CPPLOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
     }
 #endif
     try {
@@ -907,23 +915,23 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
     const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : "";
     switch(length) {
     case 8:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint64_t*)&data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     case 4:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint32_t*)&data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     case 2:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << *(uint16_t*)&data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     case 1:
-        LOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
-                   << std::hex << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes (0x" << std::hex << (uint16_t)data[0] << std::dec << ") @addr 0x"
+                      << std::hex << addr;
         break;
     default:
-        LOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
+        CPPLOG(TRACE) << prefix << "write of " << length << " bytes @addr " << addr;
     }
 #endif
     try {
@@ -984,7 +992,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
             case 0x10023000: // UART1 base, TXFIFO reg
                 uart_buf << (char)data[0];
                 if(((char)data[0]) == '\n' || data[0] == 0) {
-                    // LOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send
+                    // CPPLOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send
                     // '"<<uart_buf.str()<<"'";
                     std::cout << uart_buf.str();
                     uart_buf.str("");
@@ -1317,9 +1325,10 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned le
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
     switch(paddr.val) {
+    // TODO remove UART, Peripherals should not be part of the ISS
     case 0xFFFF0000: // UART0 base, TXFIFO reg
         if(((char)data[0]) == '\n' || data[0] == 0) {
-            LOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
+            CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'";
             uart_buf.str("");
         } else if(((char)data[0]) != '\r')
             uart_buf << (char)data[0];
@@ -1334,34 +1343,37 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
             auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost);
             if(tohost_lower || tohost_upper) {
                 uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask));
-                if(tohost_upper || (tohost_lower && to_host_wr_cnt > 0)) {
+                // in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write
+                if(tohost_upper && (tohost_lower || tohost_lower_written)) {
                     switch(hostvar >> 48) {
                     case 0:
                         if(hostvar != 0x1) {
-                            LOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                       << "), stopping simulation";
+                            CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                                          << "), stopping simulation";
                         } else {
-                            LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
-                                      << "), stopping simulation";
+                            CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
+                                         << "), stopping simulation";
                         }
                         this->reg.trap_state = std::numeric_limits<uint32_t>::max();
                         this->interrupt_sim = hostvar;
+#ifndef WITH_TCC
+                        throw(iss::simulation_stopped(hostvar));
+#endif
                         break;
-                        // throw(iss::simulation_stopped(hostvar));
                     case 0x0101: {
                         char c = static_cast<char>(hostvar & 0xff);
                         if(c == '\n' || c == 0) {
-                            LOG(INFO) << "tohost send '" << uart_buf.str() << "'";
+                            CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'";
                             uart_buf.str("");
                         } else
                             uart_buf << c;
-                        to_host_wr_cnt = 0;
                     } break;
                     default:
                         break;
                     }
+                    tohost_lower_written = false;
                 } else if(tohost_lower)
-                    to_host_wr_cnt++;
+                    tohost_lower_written = true;
             } else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
                 uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
                 *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
@@ -1474,6 +1486,31 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
             } else {
                 csr[utval | (new_priv << 8)] = addr;
             }
+            if(semihosting_cb) {
+                // Check for semihosting call
+                phys_addr_t p_addr(access_type::DEBUG_READ, traits<BASE>::MEM, addr - 4);
+                std::array<uint8_t, 8> data;
+                // check for SLLI_X0_X0_0X1F and SRAI_X0_X0_0X07
+                this->read_mem(p_addr, 4, data.data());
+                p_addr.val += 8;
+                this->read_mem(p_addr, 4, data.data() + 4);
+
+                const std::array<uint8_t, 8> ref_data = {0x13, 0x10, 0xf0, 0x01, 0x13, 0x50, 0x70, 0x40};
+                if(data == ref_data) {
+                    this->reg.NEXT_PC = addr + 8;
+
+                    std::array<char, 32> buffer;
+#if defined(_MSC_VER)
+                    sprintf(buffer.data(), "0x%016llx", addr);
+#else
+                    sprintf(buffer.data(), "0x%016lx", addr);
+#endif
+                    CLOG(INFO, disass) << "Semihosting call at address " << buffer.data() << " occurred ";
+
+                    semihosting_cb(this, &(this->reg.X10) /*a0*/, &(this->reg.X11) /*a1*/);
+                    return this->reg.NEXT_PC;
+                }
+            }
             break;
         case 4:
         case 6:
diff --git a/src/iss/arch/tgc5c.h b/src/iss/arch/tgc5c.h
index 7285edd..cff086d 100644
--- a/src/iss/arch/tgc5c.h
+++ b/src/iss/arch/tgc5c.h
@@ -81,7 +81,7 @@ template <> struct traits<tgc5c> {
 
     enum sreg_flag_e { FLAGS };
 
-    enum mem_type_e { MEM, FENCE, RES, CSR };
+    enum mem_type_e { MEM, FENCE, RES, CSR, IMEM = MEM };
     
     enum class opcode_e {
         LUI = 0,
diff --git a/src/iss/debugger/riscv_target_adapter.h b/src/iss/debugger/riscv_target_adapter.h
index 6a2a527..7e18339 100644
--- a/src/iss/debugger/riscv_target_adapter.h
+++ b/src/iss/debugger/riscv_target_adapter.h
@@ -174,7 +174,7 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::current_thread_query
 }
 
 template <typename ARCH> status riscv_target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
-    LOG(TRACE) << "reading target registers";
+    CPPLOG(TRACE) << "reading target registers";
     // return idx<0?:;
     data.clear();
     avail.clear();
@@ -328,9 +328,9 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::add_break(break_type
         auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
         auto eaddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr + length});
         target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val - saddr.val);
-        LOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
-                   << std::dec;
-        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+        CPPLOG(TRACE) << "Adding breakpoint with handle " << target_adapter_base::bp_count << " for addr 0x" << std::hex << saddr.val
+                      << std::dec;
+        CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Ok;
     }
     }
@@ -345,13 +345,13 @@ template <typename ARCH> status riscv_target_adapter<ARCH>::remove_break(break_t
         auto saddr = map_addr({iss::access_type::FETCH, iss::address_type::PHYSICAL, 0, addr});
         unsigned handle = target_adapter_base::bp_lut.getEntry(saddr.val);
         if(handle) {
-            LOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec;
+            CPPLOG(TRACE) << "Removing breakpoint with handle " << handle << " for addr 0x" << std::hex << saddr.val << std::dec;
             // TODO: check length of addr range
             target_adapter_base::bp_lut.removeEntry(handle);
-            LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+            CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
             return Ok;
         }
-        LOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
+        CPPLOG(TRACE) << "Now having " << target_adapter_base::bp_lut.size() << " breakpoints";
         return Err;
     }
     }
diff --git a/src/iss/plugin/cycle_estimate.cpp b/src/iss/plugin/cycle_estimate.cpp
index 69e466a..463e2fa 100644
--- a/src/iss/plugin/cycle_estimate.cpp
+++ b/src/iss/plugin/cycle_estimate.cpp
@@ -61,7 +61,7 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
             try {
                 auto root = YAML::LoadAll(is);
                 if(root.size() != 1) {
-                    LOG(ERR) << "Too many root nodes in YAML file " << config_file_name;
+                    CPPLOG(ERR) << "Too many root nodes in YAML file " << config_file_name;
                 }
                 for(auto p : root[0]) {
                     auto isa_subset = p.first;
@@ -87,11 +87,11 @@ bool iss::plugin::cycle_estimate::registration(const char* const version, vm_if&
                     }
                 }
             } catch(YAML::ParserException& e) {
-                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
                 return false;
             }
         } else {
-            LOG(ERR) << "Could not open input file " << config_file_name;
+            CPPLOG(ERR) << "Could not open input file " << config_file_name;
             return false;
         }
     }
diff --git a/src/iss/plugin/instruction_count.cpp b/src/iss/plugin/instruction_count.cpp
index bb47e53..000712f 100644
--- a/src/iss/plugin/instruction_count.cpp
+++ b/src/iss/plugin/instruction_count.cpp
@@ -47,7 +47,7 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
             try {
                 auto root = YAML::LoadAll(is);
                 if(root.size() != 1) {
-                    LOG(ERR) << "Too many rro nodes in YAML file " << config_file_name;
+                    CPPLOG(ERR) << "Too many rro nodes in YAML file " << config_file_name;
                 }
                 for(auto p : root[0]) {
                     auto isa_subset = p.first;
@@ -69,10 +69,10 @@ iss::plugin::instruction_count::instruction_count(std::string config_file_name)
                 }
                 rep_counts.resize(delays.size());
             } catch(YAML::ParserException& e) {
-                LOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
+                CPPLOG(ERR) << "Could not parse input file " << config_file_name << ", reason: " << e.what();
             }
         } else {
-            LOG(ERR) << "Could not open input file " << config_file_name;
+            CPPLOG(ERR) << "Could not open input file " << config_file_name;
         }
     }
 }
@@ -81,7 +81,7 @@ iss::plugin::instruction_count::~instruction_count() {
     size_t idx = 0;
     for(auto it : delays) {
         if(rep_counts[idx] > 0 && it.instr_name.find("__" != 0))
-            LOG(INFO) << it.instr_name << ";" << rep_counts[idx];
+            CPPLOG(INFO) << it.instr_name << ";" << rep_counts[idx];
         idx++;
     }
 }
diff --git a/src/iss/semihosting/semihosting.cpp b/src/iss/semihosting/semihosting.cpp
new file mode 100644
index 0000000..ab2e2c9
--- /dev/null
+++ b/src/iss/semihosting/semihosting.cpp
@@ -0,0 +1,297 @@
+#include "semihosting.h"
+#include <chrono>
+#include <cstdint>
+#include <iss/vm_types.h>
+#include <map>
+#include <stdexcept>
+// explanation of syscalls can be found at https://github.com/SpinalHDL/openocd_riscv/blob/riscv_spinal/src/target/semihosting_common.h
+
+const char* SYS_OPEN_MODES_STRS[] = {"r", "rb", "r+", "r+b", "w", "wb", "w+", "w+b", "a", "ab", "a+", "a+b"};
+
+template <typename T> T sh_read_field(iss::arch_if* arch_if_ptr, T addr, int len = 4) {
+    uint8_t bytes[4];
+    auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr, 4, &bytes[0]);
+    // auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+
+    if(res != iss::Ok) {
+        return 0; // TODO THROW ERROR
+    } else
+        return static_cast<T>(bytes[0]) | (static_cast<T>(bytes[1]) << 8) | (static_cast<T>(bytes[2]) << 16) |
+               (static_cast<T>(bytes[3]) << 24);
+}
+
+template <typename T> std::string sh_read_string(iss::arch_if* arch_if_ptr, T addr, T str_len) {
+    std::vector<uint8_t> buffer(str_len);
+    for(int i = 0; i < str_len; i++) {
+        buffer[i] = sh_read_field(arch_if_ptr, addr + i, 1);
+    }
+    std::string str(buffer.begin(), buffer.end());
+    return str;
+}
+
+template <typename T> void semihosting_callback<T>::operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter) {
+    static std::map<T, FILE*> openFiles;
+    static T file_count = 3;
+    static T semihostingErrno;
+
+    switch(static_cast<semihosting_syscalls>(*call_number)) {
+    case semihosting_syscalls::SYS_CLOCK: {
+        auto end = std::chrono::high_resolution_clock::now(); // end measurement
+        auto elapsed = end - timeVar;
+        auto millis = std::chrono::duration_cast<std::chrono::milliseconds>(elapsed).count();
+        *call_number = millis; // TODO get time now
+        break;
+    }
+    case semihosting_syscalls::SYS_CLOSE: {
+        T file_handle = *parameter;
+        if(openFiles.size() <= file_handle && file_handle < 0) {
+            semihostingErrno = EBADF;
+            return;
+        }
+        auto file = openFiles[file_handle];
+        openFiles.erase(file_handle);
+        if(!(file == stdin || file == stdout || file == stderr)) {
+            int i = fclose(file);
+            *call_number = i;
+        } else {
+            *call_number = -1;
+            semihostingErrno = EINTR;
+        }
+        break;
+    }
+    case semihosting_syscalls::SYS_ELAPSED: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_ERRNO: {
+        *call_number = semihostingErrno;
+        break;
+    }
+    case semihosting_syscalls::SYS_EXIT: {
+
+        throw std::runtime_error("ISS terminated by Semihost: SYS_EXIT");
+        break;
+    }
+    case semihosting_syscalls::SYS_EXIT_EXTENDED: {
+        throw std::runtime_error("ISS terminated by Semihost: SYS_EXIT_EXTENDED");
+        break;
+    }
+    case semihosting_syscalls::SYS_FLEN: {
+        T file_handle = *parameter;
+        auto file = openFiles[file_handle];
+
+        size_t currentPos = ftell(file);
+        if(currentPos < 0)
+            throw std::runtime_error("SYS_FLEN negative value");
+        fseek(file, 0, SEEK_END);
+        size_t length = ftell(file);
+        fseek(file, currentPos, SEEK_SET);
+        *call_number = (T)length;
+        break;
+    }
+    case semihosting_syscalls::SYS_GET_CMDLINE: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_HEAPINFO: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_ISERROR: {
+        T value = *parameter;
+        *call_number = (value != 0);
+        break;
+    }
+    case semihosting_syscalls::SYS_ISTTY: {
+        T file_handle = *parameter;
+        *call_number = (file_handle == 0 || file_handle == 1 || file_handle == 2);
+        break;
+    }
+    case semihosting_syscalls::SYS_OPEN: {
+        T path_str_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T mode = sh_read_field<T>(arch_if_ptr, 4 + (*parameter));
+        T path_len = sh_read_field<T>(arch_if_ptr, 8 + (*parameter));
+
+        std::string path_str = sh_read_string<T>(arch_if_ptr, path_str_addr, path_len);
+
+        // TODO LOG INFO
+
+        if(mode >= 12) {
+            // TODO throw ERROR
+            return;
+        }
+
+        FILE* file = nullptr;
+        if(path_str == ":tt") {
+            if(mode < 4)
+                file = stdin;
+            else if(mode < 8)
+                file = stdout;
+            else
+                file = stderr;
+        } else {
+            file = fopen(path_str.c_str(), SYS_OPEN_MODES_STRS[mode]);
+            if(file == nullptr) {
+                // TODO throw error
+                return;
+            }
+        }
+        T file_handle = file_count++;
+        openFiles[file_handle] = file;
+        *call_number = file_handle;
+        break;
+    }
+    case semihosting_syscalls::SYS_READ: {
+        T file_handle = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        T addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T count = sh_read_field<T>(arch_if_ptr, (*parameter) + 8);
+
+        auto file = openFiles[file_handle];
+
+        std::vector<uint8_t> buffer(count);
+        size_t num_read = 0;
+        if(file == stdin) {
+            // when reading from stdin: mimic behaviour from read syscall
+            // and return on newline.
+            while(num_read < count) {
+                char c = fgetc(file);
+                buffer[num_read] = c;
+                num_read++;
+                if(c == '\n')
+                    break;
+            }
+        } else {
+            num_read = fread(buffer.data(), 1, count, file);
+        }
+        buffer.resize(num_read);
+        for(int i = 0; i < num_read; i++) {
+            auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, addr + i, 1, &buffer[i]);
+            if(res != iss::Ok)
+                return;
+        }
+        *call_number = count - num_read;
+        break;
+    }
+    case semihosting_syscalls::SYS_READC: {
+        uint8_t character = getchar();
+        // character = getchar();
+        /*if(character != iss::Ok)
+            std::cout << "Not OK";
+            return;*/
+        *call_number = character;
+        break;
+    }
+    case semihosting_syscalls::SYS_REMOVE: {
+        T path_str_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T path_len = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        std::string path_str = sh_read_string<T>(arch_if_ptr, path_str_addr, path_len);
+
+        if(remove(path_str.c_str()) < 0)
+            *call_number = -1;
+        break;
+    }
+    case semihosting_syscalls::SYS_RENAME: {
+        T path_str_addr_old = sh_read_field<T>(arch_if_ptr, *parameter);
+        T path_len_old = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        T path_str_addr_new = sh_read_field<T>(arch_if_ptr, (*parameter) + 8);
+        T path_len_new = sh_read_field<T>(arch_if_ptr, (*parameter) + 12);
+
+        std::string path_str_old = sh_read_string<T>(arch_if_ptr, path_str_addr_old, path_len_old);
+        std::string path_str_new = sh_read_string<T>(arch_if_ptr, path_str_addr_new, path_len_new);
+        rename(path_str_old.c_str(), path_str_new.c_str());
+        break;
+    }
+    case semihosting_syscalls::SYS_SEEK: {
+        T file_handle = sh_read_field<T>(arch_if_ptr, *parameter);
+        T pos = sh_read_field<T>(arch_if_ptr, (*parameter) + 1);
+        auto file = openFiles[file_handle];
+
+        int retval = fseek(file, pos, SEEK_SET);
+        if(retval < 0)
+            throw std::runtime_error("SYS_SEEK negative return value");
+
+        break;
+    }
+    case semihosting_syscalls::SYS_SYSTEM: {
+        T cmd_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T cmd_len = sh_read_field<T>(arch_if_ptr, (*parameter) + 1);
+        std::string cmd = sh_read_string<T>(arch_if_ptr, cmd_addr, cmd_len);
+        system(cmd.c_str());
+        break;
+    }
+    case semihosting_syscalls::SYS_TICKFREQ: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::SYS_TIME: {
+        // returns time in seconds scince 01.01.1970 00:00
+        *call_number = time(NULL);
+        break;
+    }
+    case semihosting_syscalls::SYS_TMPNAM: {
+        T buffer_addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T identifier = sh_read_field<T>(arch_if_ptr, (*parameter) + 1);
+        T buffer_len = sh_read_field<T>(arch_if_ptr, (*parameter) + 2);
+
+        if(identifier > 255) {
+            *call_number = -1;
+            return;
+        }
+        std::stringstream ss;
+        ss << "tmp/file-" << std::setfill('0') << std::setw(3) << identifier;
+        std::string filename = ss.str();
+
+        for(int i = 0; i < buffer_len; i++) {
+            uint8_t character = filename[i];
+            auto res = arch_if_ptr->write(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, (*parameter) + i, 1, &character);
+            if(res != iss::Ok)
+                return;
+        }
+        break;
+    }
+    case semihosting_syscalls::SYS_WRITE: {
+        T file_handle = sh_read_field<T>(arch_if_ptr, (*parameter) + 4);
+        T addr = sh_read_field<T>(arch_if_ptr, *parameter);
+        T count = sh_read_field<T>(arch_if_ptr, (*parameter) + 8);
+
+        auto file = openFiles[file_handle];
+        std::string str = sh_read_string<T>(arch_if_ptr, addr, count);
+        fwrite(&str[0], 1, count, file);
+        break;
+    }
+    case semihosting_syscalls::SYS_WRITEC: {
+        uint8_t character;
+        auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+        if(res != iss::Ok)
+            return;
+        putchar(character);
+        break;
+    }
+    case semihosting_syscalls::SYS_WRITE0: {
+        uint8_t character;
+        while(1) {
+            auto res = arch_if_ptr->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0, *parameter, 1, &character);
+            if(res != iss::Ok)
+                return;
+            if(character == 0)
+                break;
+            putchar(character);
+            (*parameter)++;
+        }
+        break;
+    }
+    case semihosting_syscalls::USER_CMD_0x100: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    case semihosting_syscalls::USER_CMD_0x1FF: {
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+    default:
+        throw std::runtime_error("Semihosting Call not Implemented");
+        break;
+    }
+}
+template class semihosting_callback<uint32_t>;
+template class semihosting_callback<uint64_t>;
diff --git a/src/iss/semihosting/semihosting.h b/src/iss/semihosting/semihosting.h
new file mode 100644
index 0000000..1e62df2
--- /dev/null
+++ b/src/iss/semihosting/semihosting.h
@@ -0,0 +1,61 @@
+#ifndef _SEMIHOSTING_H_
+#define _SEMIHOSTING_H_
+#include <chrono>
+#include <functional>
+#include <iss/arch_if.h>
+/*
+ * According to:
+ * "Semihosting for AArch32 and AArch64, Release 2.0"
+ * https://static.docs.arm.com/100863/0200/semihosting.pdf
+ * from ARM Ltd.
+ *
+ * The available semihosting operation numbers passed in A0 are allocated
+ * as follows:
+ * - 0x00-0x31 Used by ARM.
+ * - 0x32-0xFF Reserved for future use by ARM.
+ * - 0x100-0x1FF Reserved for user applications. These are not used by ARM.
+ *   However, if you are writing your own SVC operations, you are advised
+ *   to use a different SVC number rather than using the semihosted
+ *   SVC number and these operation type numbers.
+ * - 0x200-0xFFFFFFFF Undefined and currently unused. It is recommended
+ *   that you do not use these.
+ */
+enum class semihosting_syscalls {
+
+    SYS_OPEN = 0x01,
+    SYS_CLOSE = 0x02,
+    SYS_WRITEC = 0x03,
+    SYS_WRITE0 = 0x04,
+    SYS_WRITE = 0x05,
+    SYS_READ = 0x06,
+    SYS_READC = 0x07,
+    SYS_ISERROR = 0x08,
+    SYS_ISTTY = 0x09,
+    SYS_SEEK = 0x0A,
+    SYS_FLEN = 0x0C,
+    SYS_TMPNAM = 0x0D,
+    SYS_REMOVE = 0x0E,
+    SYS_RENAME = 0x0F,
+    SYS_CLOCK = 0x10,
+    SYS_TIME = 0x11,
+    SYS_SYSTEM = 0x12,
+    SYS_ERRNO = 0x13,
+    SYS_GET_CMDLINE = 0x15,
+    SYS_HEAPINFO = 0x16,
+    SYS_EXIT = 0x18,
+    SYS_EXIT_EXTENDED = 0x20,
+    SYS_ELAPSED = 0x30,
+    SYS_TICKFREQ = 0x31,
+    USER_CMD_0x100 = 0x100,
+    USER_CMD_0x1FF = 0x1FF,
+};
+
+template <typename T> struct semihosting_callback {
+    std::chrono::high_resolution_clock::time_point timeVar;
+    semihosting_callback()
+    : timeVar(std::chrono::high_resolution_clock::now()) {}
+    void operator()(iss::arch_if* arch_if_ptr, T* call_number, T* parameter);
+};
+
+template <typename T> using semihosting_cb_t = std::function<void(iss::arch_if*, T*, T*)>;
+#endif
\ No newline at end of file
diff --git a/src/main.cpp b/src/main.cpp
index 61f3947..940a106 100644
--- a/src/main.cpp
+++ b/src/main.cpp
@@ -31,8 +31,12 @@
  *******************************************************************************/
 
 #include <array>
+#include <cstdint>
 #include <iostream>
 #include <iss/factory.h>
+#include <iss/semihosting/semihosting.h>
+#include <string>
+#include <unordered_map>
 #include <vector>
 
 #include "iss/arch/tgc_mapper.h"
@@ -52,7 +56,6 @@
 #endif
 
 namespace po = boost::program_options;
-
 int main(int argc, char* argv[]) {
     /*
      *  Define and parse the program options
@@ -72,7 +75,7 @@ int main(int argc, char* argv[]) {
         ("elf,f", po::value<std::vector<std::string>>(), "ELF file(s) to load")
         ("mem,m", po::value<std::string>(), "the memory input file")
         ("plugin,p", po::value<std::vector<std::string>>(), "plugin to activate")
-        ("backend", po::value<std::string>()->default_value("interp"), "the ISS backend to use, options are: interp, tcc")
+        ("backend", po::value<std::string>()->default_value("interp"), "the ISS backend to use, options are: interp, llvm, tcc, asmjit")
         ("isa", po::value<std::string>()->default_value("tgc5c"), "core or isa name to use for simulation, use '?' to get list");
     // clang-format on
     auto parsed = po::command_line_parser(argc, argv).options(desc).allow_unregistered().run();
@@ -116,6 +119,8 @@ int main(int argc, char* argv[]) {
         // instantiate the simulator
         iss::vm_ptr vm{nullptr};
         iss::cpu_ptr cpu{nullptr};
+        semihosting_callback<uint32_t> cb{};
+        semihosting_cb_t<uint32_t> semihosting_cb = [&cb](iss::arch_if* i, uint32_t* a0, uint32_t* a1) { cb(i, a0, a1); };
         std::string isa_opt(clim["isa"].as<std::string>());
         if(isa_opt.size() == 0 || isa_opt == "?") {
             auto list = f.get_names();
@@ -123,7 +128,8 @@ int main(int argc, char* argv[]) {
             std::cout << "Available implementations (core|platform|backend):\n  - " << util::join(list, "\n  - ") << std::endl;
             return 0;
         } else if(isa_opt.find('|') != std::string::npos) {
-            std::tie(cpu, vm) = f.create(isa_opt + "|" + clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>());
+            std::tie(cpu, vm) =
+                f.create(isa_opt + "|" + clim["backend"].as<std::string>(), clim["gdb-port"].as<unsigned>(), &semihosting_cb);
         } else {
             auto base_isa = isa_opt.substr(0, 5);
             if(base_isa == "tgc5d" || base_isa == "tgc5e") {
@@ -131,14 +137,14 @@ int main(int argc, char* argv[]) {
             } else {
                 isa_opt += "|m_p|" + clim["backend"].as<std::string>();
             }
-            std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as<unsigned>());
+            std::tie(cpu, vm) = f.create(isa_opt, clim["gdb-port"].as<unsigned>(), &semihosting_cb);
         }
         if(!cpu) {
-            LOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
+            CPPLOG(ERR) << "Could not create cpu for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
             return 127;
         }
         if(!vm) {
-            LOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
+            CPPLOG(ERR) << "Could not create vm for isa " << isa_opt << " and backend " << clim["backend"].as<std::string>() << std::endl;
             return 127;
         }
         if(clim.count("plugin")) {
@@ -174,7 +180,7 @@ int main(int argc, char* argv[]) {
                     } else
 #endif
                     {
-                        LOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
+                        CPPLOG(ERR) << "Unknown plugin name: " << plugin_name << ", valid names are 'ce', 'ic'" << std::endl;
                         return 127;
                     }
                 }
@@ -196,12 +202,12 @@ int main(int argc, char* argv[]) {
         if(clim.count("elf"))
             for(std::string input : clim["elf"].as<std::vector<std::string>>()) {
                 auto start_addr = vm->get_arch()->load_file(input);
-                if(start_addr.second)
+                if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
                     start_address = start_addr.first;
             }
         for(std::string input : args) {
             auto start_addr = vm->get_arch()->load_file(input); // treat remaining arguments as elf files
-            if(start_addr.second)
+            if(start_addr.second) // FIXME: this always evaluates to true as load file always returns <sth, true>
                 start_address = start_addr.first;
         }
         if(clim.count("reset")) {
@@ -211,11 +217,42 @@ int main(int argc, char* argv[]) {
         vm->reset(start_address);
         auto cycles = clim["instructions"].as<uint64_t>();
         res = vm->start(cycles, dump);
+
+        auto instr_if = vm->get_arch()->get_instrumentation_if();
+        // this assumes a single input file
+        std::unordered_map<std::string, uint64_t> sym_table;
+        if(args.empty())
+            sym_table = instr_if->get_symbol_table(clim["elf"].as<std::vector<std::string>>()[0]);
+        else
+            sym_table = instr_if->get_symbol_table(args[0]);
+        if(sym_table.find("begin_signature") != std::end(sym_table) && sym_table.find("end_signature") != std::end(sym_table)) {
+            auto start_addr = sym_table["begin_signature"];
+            auto end_addr = sym_table["end_signature"];
+            std::array<uint8_t, 4> data;
+            std::ofstream file;
+            std::string filename = fmt::format("{}.signature", isa_opt);
+            std::replace(std::begin(filename), std::end(filename), '|', '_');
+            // default riscof requires this filename
+            filename = "DUT-tgc.signature";
+            file.open(filename, std::ios::out);
+            if(!file.is_open()) {
+                LOG(ERR) << "Error opening file " << filename << std::endl;
+                return 1;
+            }
+            for(auto addr = start_addr; addr < end_addr; addr += data.size()) {
+                vm->get_arch()->read(iss::address_type::PHYSICAL, iss::access_type::DEBUG_READ, 0 /*MEM*/, addr, data.size(),
+                                     data.data()); // FIXME: get space from iss::arch::traits<ARCH>::mem_type_e::MEM
+
+                // TODO : obey Target endianess
+                uint32_t to_print = (data[3] << 24) + (data[2] << 16) + (data[1] << 8) + data[0];
+                file << std::hex << fmt::format("{:08x}", to_print) << std::dec << std::endl;
+            }
+        }
     } catch(std::exception& e) {
-        LOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl;
+        CPPLOG(ERR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit" << std::endl;
         res = 2;
     }
-    // cleanup to let plugins report of needed
+    // cleanup to let plugins report if needed
     for(auto* p : plugin_list) {
         delete p;
     }
diff --git a/src/vm/asmjit/helper_func.h b/src/vm/asmjit/helper_func.h
deleted file mode 100644
index f209e46..0000000
--- a/src/vm/asmjit/helper_func.h
+++ /dev/null
@@ -1,537 +0,0 @@
-
-
-x86::Mem get_reg_ptr(jit_holder& jh, unsigned idx) {
-
-    x86::Gp tmp_ptr = jh.cc.newUIntPtr("tmp_ptr");
-    jh.cc.mov(tmp_ptr, jh.regs_base_ptr);
-    jh.cc.add(tmp_ptr, traits::reg_byte_offsets[idx]);
-    switch(traits::reg_bit_widths[idx]) {
-    case 8:
-        return x86::ptr_8(tmp_ptr);
-    case 16:
-        return x86::ptr_16(tmp_ptr);
-    case 32:
-        return x86::ptr_32(tmp_ptr);
-    case 64:
-        return x86::ptr_64(tmp_ptr);
-    default:
-        throw std::runtime_error("Invalid reg size in get_reg_ptr");
-    }
-}
-x86::Gp get_reg_for(jit_holder& jh, unsigned idx) {
-    // TODO can check for regs in jh and return them instead of creating new ones
-    switch(traits::reg_bit_widths[idx]) {
-    case 8:
-        return jh.cc.newInt8();
-    case 16:
-        return jh.cc.newInt16();
-    case 32:
-        return jh.cc.newInt32();
-    case 64:
-        return jh.cc.newInt64();
-    default:
-        throw std::runtime_error("Invalid reg size in get_reg_ptr");
-    }
-}
-x86::Gp get_reg_for(jit_holder& jh, unsigned size, bool is_signed) {
-    if(is_signed)
-        switch(size) {
-        case 8:
-            return jh.cc.newInt8();
-        case 16:
-            return jh.cc.newInt16();
-        case 32:
-            return jh.cc.newInt32();
-        case 64:
-            return jh.cc.newInt64();
-        default:
-            throw std::runtime_error("Invalid reg size in get_reg_ptr");
-        }
-    else
-        switch(size) {
-        case 8:
-            return jh.cc.newUInt8();
-        case 16:
-            return jh.cc.newUInt16();
-        case 32:
-            return jh.cc.newUInt32();
-        case 64:
-            return jh.cc.newUInt64();
-        default:
-            throw std::runtime_error("Invalid reg size in get_reg_ptr");
-        }
-}
-inline x86::Gp load_reg_from_mem(jit_holder& jh, unsigned idx) {
-    auto ptr = get_reg_ptr(jh, idx);
-    auto reg = get_reg_for(jh, idx);
-    jh.cc.mov(reg, ptr);
-    return reg;
-}
-inline void write_reg_to_mem(jit_holder& jh, x86::Gp reg, unsigned idx) {
-    auto ptr = get_reg_ptr(jh, idx);
-    jh.cc.mov(ptr, reg);
-}
-
-void gen_instr_prologue(jit_holder& jh, addr_t pc) {
-    auto& cc = jh.cc;
-
-    cc.comment("\n//(*icount)++;");
-    cc.inc(get_reg_ptr(jh, traits::ICOUNT));
-
-    cc.comment("\n//*pc=*next_pc;");
-    cc.mov(get_reg_ptr(jh, traits::PC), jh.next_pc);
-
-    cc.comment("\n//*trap_state=*pending_trap;");
-    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
-    cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE));
-    cc.mov(get_reg_ptr(jh, traits::PENDING_TRAP), current_trap_state);
-
-    cc.comment("\n//increment *next_pc");
-    cc.mov(jh.next_pc, pc);
-}
-void gen_instr_epilogue(jit_holder& jh) {
-    auto& cc = jh.cc;
-
-    cc.comment("\n//if(*trap_state!=0) goto trap_entry;");
-    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
-    cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE));
-    cc.cmp(current_trap_state, 0);
-    cc.jne(jh.trap_entry);
-
-    // TODO: Does not need to be done for every instruction, only when needed
-    cc.comment("\n//write back regs to mem");
-    write_reg_to_mem(jh, jh.pc, traits::PC);
-    write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
-}
-void gen_block_prologue(jit_holder& jh) override {
-
-    jh.pc = load_reg_from_mem(jh, traits::PC);
-    jh.next_pc = load_reg_from_mem(jh, traits::NEXT_PC);
-}
-void gen_block_epilogue(jit_holder& jh) override {
-    x86::Compiler& cc = jh.cc;
-    cc.comment("\n//return *next_pc;");
-    cc.ret(jh.next_pc);
-
-    cc.bind(jh.trap_entry);
-    cc.comment("\n//Prepare for enter_trap;");
-    // Make sure cached values are written back
-    cc.comment("\n//write back regs to mem");
-    write_reg_to_mem(jh, jh.pc, traits::PC);
-    write_reg_to_mem(jh, jh.next_pc, traits::NEXT_PC);
-    this->gen_sync(jh, POST_SYNC, -1);
-
-    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
-    cc.mov(current_trap_state, get_reg_ptr(jh, traits::TRAP_STATE));
-
-    x86::Gp current_pc = get_reg_for(jh, traits::PC);
-    cc.mov(current_pc, get_reg_ptr(jh, traits::PC));
-
-    x86::Gp instr = cc.newInt32("instr");
-    cc.mov(instr, 0); // this is not correct
-    cc.comment("\n//enter trap call;");
-    InvokeNode* call_enter_trap;
-    cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
-    call_enter_trap->setArg(0, jh.arch_if_ptr);
-    call_enter_trap->setArg(1, current_trap_state);
-    call_enter_trap->setArg(2, current_pc);
-    call_enter_trap->setArg(3, instr);
-
-    x86::Gp current_next_pc = get_reg_for(jh, traits::NEXT_PC);
-    cc.mov(current_next_pc, get_reg_ptr(jh, traits::NEXT_PC));
-    cc.mov(jh.next_pc, current_next_pc);
-
-    cc.comment("\n//*last_branch = std::numeric_limits<uint32_t>::max();");
-    cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), std::numeric_limits<uint32_t>::max());
-    cc.comment("\n//return *next_pc;");
-    cc.ret(jh.next_pc);
-}
-/*
-    inline void raise(uint16_t trap_id, uint16_t cause){
-        auto trap_val =  0x80ULL << 24 | (cause << 16) | trap_id;
-        this->core.reg.trap_state = trap_val;
-        this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
-    }
-*/
-inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
-    auto& cc = jh.cc;
-    cc.comment("//gen_raise");
-    auto tmp1 = get_reg_for(jh, traits::TRAP_STATE);
-    cc.mov(tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
-    cc.mov(get_reg_ptr(jh, traits::TRAP_STATE), tmp1);
-    auto tmp2 = get_reg_for(jh, traits::NEXT_PC);
-    cc.mov(tmp2, std::numeric_limits<uint32_t>::max());
-    cc.mov(get_reg_ptr(jh, traits::NEXT_PC), tmp2);
-}
-inline void gen_wait(jit_holder& jh, unsigned type) { jh.cc.comment("//gen_wait"); }
-inline void gen_leave(jit_holder& jh, unsigned lvl) { jh.cc.comment("//gen_leave"); }
-
-enum operation { add, sub, band, bor, bxor, shl, sar, shr };
-
-template <typename T, typename = std::enable_if_t<std::is_integral<T>::value || std::is_same<T, x86::Gp>::value>>
-x86::Gp gen_operation(jit_holder& jh, operation op, x86::Gp a, T b) {
-    x86::Compiler& cc = jh.cc;
-    switch(op) {
-    case add: {
-        cc.add(a, b);
-        break;
-    }
-    case sub: {
-        cc.sub(a, b);
-        break;
-    }
-    case band: {
-        cc.and_(a, b);
-        break;
-    }
-    case bor: {
-        cc.or_(a, b);
-        break;
-    }
-    case bxor: {
-        cc.xor_(a, b);
-        break;
-    }
-    case shl: {
-        cc.shl(a, b);
-        break;
-    }
-    case sar: {
-        cc.sar(a, b);
-        break;
-    }
-    case shr: {
-        cc.shr(a, b);
-        break;
-    }
-    default:
-        throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (operation)", op));
-    }
-    return a;
-}
-
-enum three_operand_operation { imul, mul, idiv, div, srem, urem };
-
-x86::Gp gen_operation(jit_holder& jh, three_operand_operation op, x86::Gp a, x86::Gp b) {
-    x86::Compiler& cc = jh.cc;
-    switch(op) {
-    case imul: {
-        x86::Gp dummy = cc.newInt64();
-        cc.imul(dummy, a.r64(), b.r64());
-        return a;
-    }
-    case mul: {
-        x86::Gp dummy = cc.newInt64();
-        cc.mul(dummy, a.r64(), b.r64());
-        return a;
-    }
-    case idiv: {
-        x86::Gp dummy = cc.newInt64();
-        cc.mov(dummy, 0);
-        cc.idiv(dummy, a.r64(), b.r64());
-        return a;
-    }
-    case div: {
-        x86::Gp dummy = cc.newInt64();
-        cc.mov(dummy, 0);
-        cc.div(dummy, a.r64(), b.r64());
-        return a;
-    }
-    case srem: {
-        x86::Gp rem = cc.newInt32();
-        cc.mov(rem, 0);
-        auto a_reg = cc.newInt32();
-        cc.mov(a_reg, a.r32());
-        cc.idiv(rem, a_reg, b.r32());
-        return rem;
-    }
-    case urem: {
-        x86::Gp rem = cc.newInt32();
-        cc.mov(rem, 0);
-        auto a_reg = cc.newInt32();
-        cc.mov(a_reg, a.r32());
-        cc.div(rem, a_reg, b.r32());
-        return rem;
-    }
-
-    default:
-        throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (three_operand)", op));
-    }
-    return a;
-}
-template <typename T, typename = std::enable_if_t<std::is_integral<T>::value>>
-x86::Gp gen_operation(jit_holder& jh, three_operand_operation op, x86::Gp a, T b) {
-    x86::Gp b_reg = jh.cc.newInt32();
-    /*     switch(a.size()){
-            case 1: b_reg = jh.cc.newInt8(); break;
-            case 2: b_reg = jh.cc.newInt16(); break;
-            case 4: b_reg = jh.cc.newInt32(); break;
-            case 8: b_reg = jh.cc.newInt64(); break;
-            default: throw std::runtime_error(fmt::format("Invalid size ({}) in gen operation", a.size()));
-        } */
-    jh.cc.mov(b_reg, b);
-    return gen_operation(jh, op, a, b_reg);
-}
-enum comparison_operation { land, lor, eq, ne, lt, ltu, gt, gtu, lte, lteu, gte, gteu };
-
-template <typename T, typename = std::enable_if_t<std::is_integral<T>::value || std::is_same<T, x86::Gp>::value>>
-x86::Gp gen_operation(jit_holder& jh, comparison_operation op, x86::Gp a, T b) {
-    x86::Compiler& cc = jh.cc;
-    x86::Gp tmp = cc.newInt8();
-    cc.mov(tmp, 1);
-    Label label_then = cc.newLabel();
-    cc.cmp(a, b);
-    switch(op) {
-    case eq:
-        cc.je(label_then);
-        break;
-    case ne:
-        cc.jne(label_then);
-        break;
-    case lt:
-        cc.jl(label_then);
-        break;
-    case ltu:
-        cc.jb(label_then);
-        break;
-    case gt:
-        cc.jg(label_then);
-        break;
-    case gtu:
-        cc.ja(label_then);
-        break;
-    case lte:
-        cc.jle(label_then);
-        break;
-    case lteu:
-        cc.jbe(label_then);
-        break;
-    case gte:
-        cc.jge(label_then);
-        break;
-    case gteu:
-        cc.jae(label_then);
-        break;
-    case land: {
-        Label label_false = cc.newLabel();
-        cc.cmp(a, 0);
-        cc.je(label_false);
-        auto b_reg = cc.newInt8();
-        cc.mov(b_reg, b);
-        cc.cmp(b_reg, 0);
-        cc.je(label_false);
-        cc.jmp(label_then);
-        cc.bind(label_false);
-        break;
-    }
-    case lor: {
-        cc.cmp(a, 0);
-        cc.jne(label_then);
-        auto b_reg = cc.newInt8();
-        cc.mov(b_reg, b);
-        cc.cmp(b_reg, 0);
-        cc.jne(label_then);
-        break;
-    }
-    default:
-        throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (comparison)", op));
-    }
-    cc.mov(tmp, 0);
-    cc.bind(label_then);
-    return tmp;
-}
-enum binary_operation { lnot, inc, dec, bnot, neg };
-
-x86::Gp gen_operation(jit_holder& jh, binary_operation op, x86::Gp a) {
-    x86::Compiler& cc = jh.cc;
-    switch(op) {
-    case lnot:
-        throw std::runtime_error("Current operation not supported in gen_operation(lnot)");
-    case inc: {
-        cc.inc(a);
-        break;
-    }
-    case dec: {
-        cc.dec(a);
-        break;
-    }
-    case bnot: {
-        cc.not_(a);
-        break;
-    }
-    case neg: {
-        cc.neg(a);
-        break;
-    }
-    default:
-        throw std::runtime_error(fmt::format("Current operation {} not supported in gen_operation (unary)", op));
-    }
-    return a;
-}
-
-template <typename T, typename = std::enable_if_t<std::is_integral<T>::value>>
-inline x86::Gp gen_ext(jit_holder& jh, T val, unsigned size, bool is_signed) {
-    auto val_reg = get_reg_for(jh, sizeof(val) * 8, is_signed);
-    jh.cc.mov(val_reg, val);
-    return gen_ext(jh, val_reg, size, is_signed);
-}
-inline x86::Gp gen_ext(jit_holder& jh, x86::Gp val, unsigned size, bool is_signed) {
-    auto& cc = jh.cc;
-    if(is_signed) {
-        switch(val.size()) {
-        case 1:
-            cc.cbw(val);
-            break;
-        case 2:
-            cc.cwde(val);
-            break;
-        case 4:
-            cc.cdqe(val);
-            break;
-        case 8:
-            break;
-        default:
-            throw std::runtime_error("Invalid register size in gen_ext");
-        }
-    }
-    switch(size) {
-    case 8:
-        cc.and_(val, std::numeric_limits<uint8_t>::max());
-        return val.r8();
-    case 16:
-        cc.and_(val, std::numeric_limits<uint16_t>::max());
-        return val.r16();
-    case 32:
-        cc.and_(val, std::numeric_limits<uint32_t>::max());
-        return val.r32();
-    case 64:
-        cc.and_(val, std::numeric_limits<uint64_t>::max());
-        return val.r64();
-    case 128:
-        return val.r64();
-    default:
-        throw std::runtime_error("Invalid size in gen_ext");
-    }
-}
-inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, uint32_t length) {
-    x86::Compiler& cc = jh.cc;
-    auto ret_reg = cc.newInt32();
-
-    auto mem_type_reg = cc.newInt32();
-    cc.mov(mem_type_reg, type);
-
-    auto space_reg = cc.newInt32();
-    cc.mov(space_reg, static_cast<uint16_t>(iss::address_type::VIRTUAL));
-
-    auto val_ptr = cc.newUIntPtr();
-    cc.mov(val_ptr, read_mem_buf);
-
-    InvokeNode* invokeNode;
-    uint64_t mask = 0;
-    x86::Gp val_reg = cc.newInt64();
-
-    switch(length) {
-    case 1: {
-        cc.invoke(&invokeNode, &read_mem1, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
-        mask = std::numeric_limits<uint8_t>::max();
-        break;
-    }
-    case 2: {
-        cc.invoke(&invokeNode, &read_mem2, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
-        mask = std::numeric_limits<uint16_t>::max();
-        break;
-    }
-    case 4: {
-        cc.invoke(&invokeNode, &read_mem4, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
-        mask = std::numeric_limits<uint32_t>::max();
-        break;
-    }
-    case 8: {
-        cc.invoke(&invokeNode, &read_mem8, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uintptr_t>());
-        mask = std::numeric_limits<uint64_t>::max();
-        break;
-    }
-    default:
-        throw std::runtime_error(fmt::format("Invalid length ({}) in gen_read_mem", length));
-    }
-
-    invokeNode->setRet(0, ret_reg);
-    invokeNode->setArg(0, jh.arch_if_ptr);
-    invokeNode->setArg(1, space_reg);
-    invokeNode->setArg(2, mem_type_reg);
-    invokeNode->setArg(3, addr);
-    invokeNode->setArg(4, val_ptr);
-    cc.cmp(ret_reg, 0);
-    cc.jne(jh.trap_entry);
-
-    cc.mov(val_reg, x86::ptr_64(val_ptr));
-    cc.and_(val_reg, mask);
-    return val_reg;
-}
-inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, x86::Gp length) {
-    throw std::runtime_error("Invalid gen_read_mem");
-}
-inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, uint64_t addr, x86::Gp length) {
-    throw std::runtime_error("Invalid gen_read_mem");
-}
-inline x86::Gp gen_read_mem(jit_holder& jh, mem_type_e type, uint64_t addr, uint32_t length) {
-    auto addr_reg = jh.cc.newInt64();
-    jh.cc.mov(addr_reg, addr);
-
-    return gen_read_mem(jh, type, addr_reg, length);
-}
-inline void gen_write_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, int64_t val, uint32_t length) {
-    auto val_reg = get_reg_for(jh, length * 8, true);
-    jh.cc.mov(val_reg, val);
-    gen_write_mem(jh, type, addr, val_reg, length);
-}
-inline void gen_write_mem(jit_holder& jh, mem_type_e type, x86::Gp addr, x86::Gp val, uint32_t length) {
-    x86::Compiler& cc = jh.cc;
-    assert(val.size() == length);
-    auto mem_type_reg = cc.newInt32();
-    jh.cc.mov(mem_type_reg, type);
-    auto space_reg = cc.newInt32();
-    jh.cc.mov(space_reg, static_cast<uint16_t>(iss::address_type::VIRTUAL));
-    auto ret_reg = cc.newInt32();
-    InvokeNode* invokeNode;
-    switch(length) {
-    case 1:
-        cc.invoke(&invokeNode, &write_mem1, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint8_t>());
-
-        break;
-    case 2:
-        cc.invoke(&invokeNode, &write_mem2, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint16_t>());
-        break;
-    case 4:
-        cc.invoke(&invokeNode, &write_mem4, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint32_t>());
-        break;
-    case 8:
-        cc.invoke(&invokeNode, &write_mem8, FuncSignatureT<uint32_t, uint64_t, uint32_t, uint32_t, uint64_t, uint64_t>());
-
-        break;
-    default:
-        throw std::runtime_error("Invalid register size in gen_ext");
-    }
-    invokeNode->setRet(0, ret_reg);
-    invokeNode->setArg(0, jh.arch_if_ptr);
-    invokeNode->setArg(1, space_reg);
-    invokeNode->setArg(2, mem_type_reg);
-    invokeNode->setArg(3, addr);
-    invokeNode->setArg(4, val);
-
-    cc.cmp(ret_reg, 0);
-    cc.jne(jh.trap_entry);
-}
-inline void gen_write_mem(jit_holder& jh, mem_type_e type, uint64_t addr, x86::Gp val, uint32_t length) {
-    auto addr_reg = jh.cc.newUInt64();
-    jh.cc.mov(addr_reg, addr);
-    gen_write_mem(jh, type, addr_reg, val, length);
-}
-inline void gen_write_mem(jit_holder& jh, mem_type_e type, uint64_t addr, int64_t val, uint32_t length) {
-    auto val_reg = get_reg_for(jh, length * 8, true);
-    jh.cc.mov(val_reg, val);
-
-    auto addr_reg = jh.cc.newUInt64();
-    jh.cc.mov(addr_reg, addr);
-    gen_write_mem(jh, type, addr_reg, val_reg, length);
-}
\ No newline at end of file
diff --git a/src/vm/asmjit/vm_tgc5c.cpp b/src/vm/asmjit/vm_tgc5c.cpp
index c9656ae..c77b741 100644
--- a/src/vm/asmjit/vm_tgc5c.cpp
+++ b/src/vm/asmjit/vm_tgc5c.cpp
@@ -79,21 +79,36 @@ public:
     }
 
 protected:
-    using vm_base<ARCH>::get_reg_ptr;
+    using super::get_ptr_for;
+using super::get_reg;
+    using super::get_reg_for;
+    using super::load_reg_from_mem;
+    using super::write_reg_to_mem;
+    using super::gen_ext;
+    using super::gen_read_mem;
+    using super::gen_write_mem;
+    using super::gen_wait;
+    using super::gen_leave;
+    using super::gen_operation;
+   
     using this_class = vm_impl<ARCH>;
     using compile_func = continuation_e (this_class::*)(virt_addr_t&, code_word_t, jit_holder&);
 
     continuation_e gen_single_inst_behavior(virt_addr_t&, unsigned int &, jit_holder&) override;
+    void gen_block_prologue(jit_holder& jh) override;
+    void gen_block_epilogue(jit_holder& jh) override;
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
+    void gen_instr_prologue(jit_holder& jh);
+    void gen_instr_epilogue(jit_holder& jh);
+    inline void gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause);
+
     template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
     inline S sext(U from) {
         auto mask = (1ULL<<W) - 1;
         auto sign_mask = 1ULL<<(W-1);
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
     } 
-#include <vm/asmjit/helper_func.h>
-
 private:
     /****************************************************************************
      * start opcode definitions
@@ -300,23 +315,35 @@ private:
         uint32_t imm = ((bit_sub<12,20>(instr) << 12));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nLUI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("LUI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 0);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      (uint32_t)((int32_t)imm));
             }
         }
@@ -334,23 +361,35 @@ private:
         uint32_t imm = ((bit_sub<12,20>(instr) << 12));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nAUIPC_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("AUIPC_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 1);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      (uint32_t)(PC+(int32_t)imm));
             }
         }
@@ -368,32 +407,44 @@ private:
         uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nJAL_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("JAL_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 2);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){
-                gen_raise(jh, 0,  0);
+                gen_raise(jh, 0, 0);
             }
             else{
-                if(rd!= 0){
-                    cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                         (uint32_t)(PC+ 4));
+                if(rd!=0){
+                    cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                         (uint32_t)(PC+4));
                 }
                 auto PC_val_v = (uint32_t)(PC+(int32_t)sext<21>(imm));
                 cc.mov(jh.next_pc, PC_val_v);
-                cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+                cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
             }
         }
         auto returnValue = BRANCH;
@@ -411,47 +462,56 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nJALR_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("JALR_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 3);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto addr_mask = (uint32_t)- 2;
             auto new_pc = gen_ext(jh, 
-                (gen_operation(jh, band, 
-                    (gen_operation(jh, add, 
-                        gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true))
-                    ), gen_ext(jh, addr_mask, 64, false))
+                (gen_operation(jh, band, (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
+                ), addr_mask)
                 ), 32, true);
             auto label_merge = cc.newLabel();
-            cc.cmp(gen_operation(jh, urem, 
-                new_pc, static_cast<uint32_t>(traits::INSTR_ALIGNMENT))
+            cc.cmp(gen_operation(jh, urem, new_pc, static_cast<uint32_t>(traits::INSTR_ALIGNMENT))
             ,0);
             auto label_else = cc.newLabel();
             cc.je(label_else);
             {
-                gen_raise(jh, 0,  0);
+                gen_raise(jh, 0, 0);
             }
             cc.jmp(label_merge);
             cc.bind(label_else);
                 {
-                    if(rd!= 0){
-                        cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                             (uint32_t)(PC+ 4));
+                    if(rd!=0){
+                        cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                             (uint32_t)(PC+4));
                     }
                     auto PC_val_v = new_pc;
                     cc.mov(jh.next_pc, PC_val_v);
-                    cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+                    cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
                 }
             cc.bind(label_merge);
         }
@@ -470,34 +530,45 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nBEQ_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("BEQ_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 4);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto label_merge = cc.newLabel();
-            cc.cmp(gen_operation(jh, eq, 
-                load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
+            cc.cmp(gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
             ,0);
             cc.je(label_merge);
             {
                 if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){
-                    gen_raise(jh, 0,  0);
+                    gen_raise(jh, 0, 0);
                 }
                 else{
                     auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
                     cc.mov(jh.next_pc, PC_val_v);
-                    cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+                    cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
                 }
             }
             cc.bind(label_merge);
@@ -517,34 +588,45 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nBNE_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("BNE_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 5);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto label_merge = cc.newLabel();
-            cc.cmp(gen_operation(jh, ne, 
-                load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
+            cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
             ,0);
             cc.je(label_merge);
             {
                 if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){
-                    gen_raise(jh, 0,  0);
+                    gen_raise(jh, 0, 0);
                 }
                 else{
                     auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
                     cc.mov(jh.next_pc, PC_val_v);
-                    cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+                    cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
                 }
             }
             cc.bind(label_merge);
@@ -564,36 +646,47 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nBLT_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("BLT_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 6);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto label_merge = cc.newLabel();
-            cc.cmp(gen_operation(jh, lt, 
-                gen_ext(jh, 
-                    load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, 
-                    load_reg_from_mem(jh, traits::X0 + rs2), 32, false))
+            cc.cmp(gen_operation(jh, lt, gen_ext(jh, 
+                load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, 
+                load_reg_from_mem(jh, traits::X0 + rs2), 32, false))
             ,0);
             cc.je(label_merge);
             {
                 if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){
-                    gen_raise(jh, 0,  0);
+                    gen_raise(jh, 0, 0);
                 }
                 else{
                     auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
                     cc.mov(jh.next_pc, PC_val_v);
-                    cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+                    cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
                 }
             }
             cc.bind(label_merge);
@@ -613,36 +706,47 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nBGE_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("BGE_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 7);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto label_merge = cc.newLabel();
-            cc.cmp(gen_operation(jh, gte, 
-                gen_ext(jh, 
-                    load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, 
-                    load_reg_from_mem(jh, traits::X0 + rs2), 32, false))
+            cc.cmp(gen_operation(jh, gte, gen_ext(jh, 
+                load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, 
+                load_reg_from_mem(jh, traits::X0 + rs2), 32, false))
             ,0);
             cc.je(label_merge);
             {
                 if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){
-                    gen_raise(jh, 0,  0);
+                    gen_raise(jh, 0, 0);
                 }
                 else{
                     auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
                     cc.mov(jh.next_pc, PC_val_v);
-                    cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+                    cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
                 }
             }
             cc.bind(label_merge);
@@ -662,34 +766,45 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nBLTU_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("BLTU_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 8);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto label_merge = cc.newLabel();
-            cc.cmp(gen_operation(jh, ltu, 
-                load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
+            cc.cmp(gen_operation(jh, ltu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
             ,0);
             cc.je(label_merge);
             {
                 if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){
-                    gen_raise(jh, 0,  0);
+                    gen_raise(jh, 0, 0);
                 }
                 else{
                     auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
                     cc.mov(jh.next_pc, PC_val_v);
-                    cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+                    cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
                 }
             }
             cc.bind(label_merge);
@@ -709,34 +824,45 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nBGEU_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("BGEU_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 9);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto label_merge = cc.newLabel();
-            cc.cmp(gen_operation(jh, gteu, 
-                load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
+            cc.cmp(gen_operation(jh, gteu, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
             ,0);
             cc.je(label_merge);
             {
                 if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){
-                    gen_raise(jh, 0,  0);
+                    gen_raise(jh, 0, 0);
                 }
                 else{
                     auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
                     cc.mov(jh.next_pc, PC_val_v);
-                    cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+                    cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
                 }
             }
             cc.bind(label_merge);
@@ -756,29 +882,40 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nLB_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("LB_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 10);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto load_address = gen_ext(jh, 
-                (gen_operation(jh, add, 
-                    gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true))
+                (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
                 ), 32, true);
             auto res = gen_ext(jh, 
                 gen_read_mem(jh, traits::MEM, load_address, 1), 8, false);
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
                          res, 32, true));
             }
@@ -798,29 +935,40 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nLH_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("LH_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 11);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto load_address = gen_ext(jh, 
-                (gen_operation(jh, add, 
-                    gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true))
+                (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
                 ), 32, true);
             auto res = gen_ext(jh, 
                 gen_read_mem(jh, traits::MEM, load_address, 2), 16, false);
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
                          res, 32, true));
             }
@@ -840,29 +988,40 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nLW_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("LW_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 12);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto load_address = gen_ext(jh, 
-                (gen_operation(jh, add, 
-                    gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true))
+                (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
                 ), 32, true);
             auto res = gen_ext(jh, 
                 gen_read_mem(jh, traits::MEM, load_address, 4), 32, false);
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
                          res, 32, true));
             }
@@ -882,28 +1041,39 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nLBU_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("LBU_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 13);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto load_address = gen_ext(jh, 
-                (gen_operation(jh, add, 
-                    gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true))
+                (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
                 ), 32, true);
             auto res = gen_read_mem(jh, traits::MEM, load_address, 1);
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
                          res, 32, false));
             }
@@ -923,28 +1093,39 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nLHU_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("LHU_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 14);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto load_address = gen_ext(jh, 
-                (gen_operation(jh, add, 
-                    gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true))
+                (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
                 ), 32, true);
             auto res = gen_read_mem(jh, traits::MEM, load_address, 2);
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
                          res, 32, false));
             }
@@ -964,24 +1145,35 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSB_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SB_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 15);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto store_address = gen_ext(jh, 
-                (gen_operation(jh, add, 
-                    gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true))
+                (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
                 ), 32, true);
             gen_write_mem(jh, traits::MEM, store_address, gen_ext(jh, 
                 load_reg_from_mem(jh, traits::X0 + rs2), 8, false), 1);
@@ -1001,24 +1193,35 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSH_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SH_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 16);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto store_address = gen_ext(jh, 
-                (gen_operation(jh, add, 
-                    gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true))
+                (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
                 ), 32, true);
             gen_write_mem(jh, traits::MEM, store_address, gen_ext(jh, 
                 load_reg_from_mem(jh, traits::X0 + rs2), 16, false), 2);
@@ -1038,24 +1241,35 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSW_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SW_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 17);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto store_address = gen_ext(jh, 
-                (gen_operation(jh, add, 
-                    gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true))
+                (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
                 ), 32, true);
             gen_write_mem(jh, traits::MEM, store_address, gen_ext(jh, 
                 load_reg_from_mem(jh, traits::X0 + rs2), 32, false), 4);
@@ -1075,26 +1289,37 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nADDI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("ADDI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 18);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
-                         (gen_operation(jh, add, 
-                             gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int16_t)sext<12>(imm), 64, true))
+                         (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int16_t)sext<12>(imm))
                          ), 32, true));
             }
         }
@@ -1113,22 +1338,34 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSLTI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SLTI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 19);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
+            if(rd!=0){
                 {
                 auto label_then = cc.newLabel();
                 auto label_merge = cc.newLabel();
@@ -1136,12 +1373,12 @@ private:
                 cc.cmp(gen_ext(jh, 
                     load_reg_from_mem(jh, traits::X0 + rs1), 32, true), (int16_t)sext<12>(imm));
                 cc.jl(label_then);
-                cc.mov(tmp_reg, 0);
+                cc.mov(tmp_reg,0);
                 cc.jmp(label_merge);
                 cc.bind(label_then);
-                cc.mov(tmp_reg, 1);
+                cc.mov(tmp_reg,1);
                 cc.bind(label_merge);
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, tmp_reg
                      , 32, false)
                 );
@@ -1163,34 +1400,46 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSLTIU_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SLTIU_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 20);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
+            if(rd!=0){
                 {
                 auto label_then = cc.newLabel();
                 auto label_merge = cc.newLabel();
                 auto tmp_reg = get_reg_for(jh, 1);
                 cc.cmp(load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)));
                 cc.jb(label_then);
-                cc.mov(tmp_reg, 0);
+                cc.mov(tmp_reg,0);
                 cc.jmp(label_merge);
                 cc.bind(label_then);
-                cc.mov(tmp_reg, 1);
+                cc.mov(tmp_reg,1);
                 cc.bind(label_merge);
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, tmp_reg
                      , 32, false)
                 );
@@ -1212,25 +1461,36 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nXORI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("XORI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 21);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                     gen_operation(jh, bxor, 
-                         load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)))
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                     gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)))
                      );
             }
         }
@@ -1249,25 +1509,36 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nORI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("ORI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 22);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                     gen_operation(jh, bor, 
-                         load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)))
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                     gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)))
                      );
             }
         }
@@ -1286,25 +1557,36 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nANDI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("ANDI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 23);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                     gen_operation(jh, band, 
-                         load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)))
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                     gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), (uint32_t)((int16_t)sext<12>(imm)))
                      );
             }
         }
@@ -1323,25 +1605,36 @@ private:
         uint8_t shamt = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSLLI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SLLI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 24);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                     gen_operation(jh, shl, 
-                         load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, shamt, 32, false))
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                     gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), shamt)
                      );
             }
         }
@@ -1360,25 +1653,36 @@ private:
         uint8_t shamt = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSRLI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SRLI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 25);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                     gen_operation(jh, shr, 
-                         load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, shamt, 32, false))
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                     gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), shamt)
                      );
             }
         }
@@ -1397,27 +1701,38 @@ private:
         uint8_t shamt = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSRAI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SRAI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 26);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
-                         (gen_operation(jh, sar, 
-                             gen_ext(jh, 
-                                 load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh, shamt, 32, false))
+                         (gen_operation(jh, sar, gen_ext(jh, 
+                             load_reg_from_mem(jh, traits::X0 + rs1), 32, true), shamt)
                          ), 32, true));
             }
         }
@@ -1436,26 +1751,37 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nADD_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("ADD_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 27);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
-                         (gen_operation(jh, add, 
-                             gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false))
+                         (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
                          ), 32, false));
             }
         }
@@ -1474,26 +1800,37 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSUB_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SUB_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 28);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
-                         (gen_operation(jh, sub, 
-                             gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false))
+                         (gen_operation(jh, sub, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
                          ), 32, true));
             }
         }
@@ -1512,27 +1849,37 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSLL_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SLL_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 29);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                     gen_ext(jh, gen_operation(jh, shl, 
-                         gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), (gen_operation(jh, band, 
-                             gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false), (static_cast<uint32_t>(traits::XLEN)- 1))
-                         ))
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                     gen_ext(jh, gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast<uint32_t>(traits::XLEN)-1))
+                     ))
                      , 32, false));
             }
         }
@@ -1551,22 +1898,34 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSLT_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SLT_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 30);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
+            if(rd!=0){
                 {
                 auto label_then = cc.newLabel();
                 auto label_merge = cc.newLabel();
@@ -1575,12 +1934,12 @@ private:
                     load_reg_from_mem(jh, traits::X0 + rs1), 32, true), gen_ext(jh, 
                     load_reg_from_mem(jh, traits::X0 + rs2), 32, true));
                 cc.jl(label_then);
-                cc.mov(tmp_reg, 0);
+                cc.mov(tmp_reg,0);
                 cc.jmp(label_merge);
                 cc.bind(label_then);
-                cc.mov(tmp_reg, 1);
+                cc.mov(tmp_reg,1);
                 cc.bind(label_merge);
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, tmp_reg
                      , 32, false)
                 );
@@ -1602,34 +1961,46 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSLTU_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SLTU_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 31);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
+            if(rd!=0){
                 {
                 auto label_then = cc.newLabel();
                 auto label_merge = cc.newLabel();
                 auto tmp_reg = get_reg_for(jh, 1);
                 cc.cmp(load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2));
                 cc.jb(label_then);
-                cc.mov(tmp_reg, 0);
+                cc.mov(tmp_reg,0);
                 cc.jmp(label_merge);
                 cc.bind(label_then);
-                cc.mov(tmp_reg, 1);
+                cc.mov(tmp_reg,1);
                 cc.bind(label_merge);
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, tmp_reg
                      , 32, false)
                 );
@@ -1651,25 +2022,36 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nXOR_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("XOR_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 32);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                     gen_operation(jh, bxor, 
-                         load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                     gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
                      );
             }
         }
@@ -1688,27 +2070,37 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSRL_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SRL_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 33);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                     gen_ext(jh, gen_operation(jh, shr, 
-                         gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), (gen_operation(jh, band, 
-                             gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false), (static_cast<uint32_t>(traits::XLEN)- 1))
-                         ))
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                     gen_ext(jh, gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast<uint32_t>(traits::XLEN)-1))
+                     ))
                      , 32, false));
             }
         }
@@ -1727,29 +2119,39 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nSRA_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("SRA_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 34);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
-                         (gen_ext(jh, gen_operation(jh, sar, 
-                             gen_ext(jh, gen_ext(jh, 
-                                 load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), (gen_operation(jh, band, 
-                                 gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false), (static_cast<uint32_t>(traits::XLEN)- 1))
-                             ))
+                         (gen_ext(jh, gen_operation(jh, sar, gen_ext(jh, 
+                             load_reg_from_mem(jh, traits::X0 + rs1), 32, true), (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs2), (static_cast<uint32_t>(traits::XLEN)-1))
+                         ))
                          , 32, true)), 32, true));
             }
         }
@@ -1768,25 +2170,36 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nOR_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("OR_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 35);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                     gen_operation(jh, bor, 
-                         load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                     gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
                      );
             }
         }
@@ -1805,25 +2218,36 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nAND_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("AND_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 36);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                     gen_operation(jh, band, 
-                         load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                     gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
                      );
             }
         }
@@ -1844,18 +2268,30 @@ private:
         uint8_t fm = ((bit_sub<28,4>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"),
+                fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nFENCE_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("FENCE_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 37);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        gen_write_mem(jh, traits::FENCE, static_cast<uint32_t>(traits::fence), (uint8_t)pred<< 4|succ, 4);
+        gen_write_mem(jh, traits::FENCE, static_cast<uint32_t>(traits::fence), (uint8_t)pred<<4|succ, 4);
         auto returnValue = CONT;
         
         gen_instr_epilogue(jh);
@@ -1868,18 +2304,29 @@ private:
         uint64_t PC = pc.val;
         if(this->disass_enabled){
             /* generate disass */
+            
+            //This disass is not yet implemented
+            std::string mnemonic = "ecall";
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nECALL_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("ECALL_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 38);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        gen_raise(jh, 0,  11);
+        gen_raise(jh, 0, 11);
         auto returnValue = TRAP;
         
         gen_instr_epilogue(jh);
@@ -1892,18 +2339,29 @@ private:
         uint64_t PC = pc.val;
         if(this->disass_enabled){
             /* generate disass */
+            
+            //This disass is not yet implemented
+            std::string mnemonic = "ebreak";
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nEBREAK_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("EBREAK_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 39);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        gen_raise(jh, 0,  3);
+        gen_raise(jh, 0, 3);
         auto returnValue = TRAP;
         
         gen_instr_epilogue(jh);
@@ -1916,16 +2374,27 @@ private:
         uint64_t PC = pc.val;
         if(this->disass_enabled){
             /* generate disass */
+            
+            //This disass is not yet implemented
+            std::string mnemonic = "mret";
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nMRET_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("MRET_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 40);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         gen_leave(jh, 3);
         auto returnValue = TRAP;
@@ -1940,16 +2409,27 @@ private:
         uint64_t PC = pc.val;
         if(this->disass_enabled){
             /* generate disass */
+            
+            //This disass is not yet implemented
+            std::string mnemonic = "wfi";
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nWFI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("WFI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 41);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         gen_wait(jh, 1);
         auto returnValue = CONT;
@@ -1967,26 +2447,38 @@ private:
         uint16_t csr = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nCSRRW_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("CSRRW_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 42);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1);
-            if(rd!= 0){
+            if(rd!=0){
                 auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
                 gen_write_mem(jh, traits::CSR, csr, xrs1, 4);
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      xrd);
             }
             else{
@@ -2008,30 +2500,41 @@ private:
         uint16_t csr = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nCSRRS_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("CSRRS_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 43);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
             auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1);
-            if(rs1!= 0){
-                gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, 
-                    xrd, xrs1)
+            if(rs1!=0){
+                gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, xrd, xrs1)
                 , 4);
             }
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      xrd);
             }
         }
@@ -2050,30 +2553,41 @@ private:
         uint16_t csr = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nCSRRC_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("CSRRC_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 44);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
             auto xrs1 = load_reg_from_mem(jh, traits::X0 + rs1);
-            if(rs1!= 0){
-                gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, 
-                    xrd, gen_operation(jh, bnot, xrs1))
+            if(rs1!=0){
+                gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, xrd, gen_operation(jh, bnot, xrs1))
                 , 4);
             }
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      xrd);
             }
         }
@@ -2092,25 +2606,37 @@ private:
         uint16_t csr = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nCSRRWI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("CSRRWI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 45);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
             gen_write_mem(jh, traits::CSR, csr, (uint32_t)zimm, 4);
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      xrd);
             }
         }
@@ -2129,29 +2655,40 @@ private:
         uint16_t csr = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nCSRRSI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("CSRRSI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 46);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
-            if(zimm!= 0){
-                gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, 
-                    xrd, (uint32_t)zimm)
+            if(zimm!=0){
+                gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, bor, xrd, (uint32_t)zimm)
                 , 4);
             }
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      xrd);
             }
         }
@@ -2170,29 +2707,40 @@ private:
         uint16_t csr = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nCSRRCI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("CSRRCI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 47);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto xrd = gen_read_mem(jh, traits::CSR, csr, 4);
-            if(zimm!= 0){
-                gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, 
-                    xrd, ~ ((uint32_t)zimm))
+            if(zimm!=0){
+                gen_write_mem(jh, traits::CSR, csr, gen_operation(jh, band, xrd, ~ ((uint32_t)zimm))
                 , 4);
             }
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      xrd);
             }
         }
@@ -2211,19 +2759,31 @@ private:
         uint16_t imm = ((bit_sub<20,12>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nFENCE_I_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("FENCE_I_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 48);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         gen_write_mem(jh, traits::FENCE, static_cast<uint32_t>(traits::fencei), imm, 4);
-        auto returnValue = CONT;
+        auto returnValue = FLUSH;
         
         gen_instr_epilogue(jh);
         this->gen_sync(jh, POST_SYNC, 48);
@@ -2238,31 +2798,42 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nMUL_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("MUL_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 49);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto res = gen_ext(jh, 
-                (gen_operation(jh, imul, 
-                    gen_ext(jh, gen_ext(jh, 
-                        gen_ext(jh, 
-                            load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), 128, true), gen_ext(jh, gen_ext(jh, 
-                        gen_ext(jh, 
-                            load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true), 128, true))
+                (gen_operation(jh, imul, gen_ext(jh, 
+                    gen_ext(jh, 
+                        load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh, 
+                    gen_ext(jh, 
+                        load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true))
                 ), 64, true);
             if(rd!=0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
                          res, 32, true));
             }
@@ -2282,34 +2853,44 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nMULH_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("MULH_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 50);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto res = gen_ext(jh, 
-                (gen_operation(jh, imul, 
-                    gen_ext(jh, gen_ext(jh, 
-                        gen_ext(jh, 
-                            load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), 128, true), gen_ext(jh, gen_ext(jh, 
-                        gen_ext(jh, 
-                            load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true), 128, true))
+                (gen_operation(jh, imul, gen_ext(jh, 
+                    gen_ext(jh, 
+                        load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh, 
+                    gen_ext(jh, 
+                        load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true))
                 ), 64, true);
             if(rd!=0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
-                         (gen_operation(jh, sar, 
-                             res, gen_ext(jh, static_cast<uint32_t>(traits::XLEN), 64, false))
+                         (gen_operation(jh, sar, res, static_cast<uint32_t>(traits::XLEN))
                          ), 32, true));
             }
         }
@@ -2328,33 +2909,43 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nMULHSU_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("MULHSU_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 51);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto res = gen_ext(jh, 
-                (gen_operation(jh, imul, 
-                    gen_ext(jh, gen_ext(jh, 
-                        gen_ext(jh, 
-                            load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), 128, true), gen_ext(jh, gen_ext(jh, 
-                        load_reg_from_mem(jh, traits::X0 + rs2), 64, false), 128, false))
+                (gen_operation(jh, imul, gen_ext(jh, 
+                    gen_ext(jh, 
+                        load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh, 
+                    load_reg_from_mem(jh, traits::X0 + rs2), 64, false))
                 ), 64, true);
             if(rd!=0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
-                         (gen_operation(jh, sar, 
-                             res, gen_ext(jh, static_cast<uint32_t>(traits::XLEN), 64, false))
+                         (gen_operation(jh, sar, res, static_cast<uint32_t>(traits::XLEN))
                          ), 32, true));
             }
         }
@@ -2373,32 +2964,42 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nMULHU_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("MULHU_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 52);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto res = gen_ext(jh, 
-                (gen_operation(jh, mul, 
-                    gen_ext(jh, gen_ext(jh, 
-                        load_reg_from_mem(jh, traits::X0 + rs1), 64, false), 128, false), gen_ext(jh, gen_ext(jh, 
-                        load_reg_from_mem(jh, traits::X0 + rs2), 64, false), 128, false))
+                (gen_operation(jh, mul, gen_ext(jh, 
+                    load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, 
+                    load_reg_from_mem(jh, traits::X0 + rs2), 64, false))
                 ), 64, false);
             if(rd!=0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
-                         (gen_operation(jh, shr, 
-                             res, gen_ext(jh, static_cast<uint32_t>(traits::XLEN), 64, false))
+                         (gen_operation(jh, shr, res, static_cast<uint32_t>(traits::XLEN))
                          ), 32, false));
             }
         }
@@ -2417,55 +3018,62 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nDIV_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("DIV_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 53);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto dividend = gen_ext(jh, 
                 load_reg_from_mem(jh, traits::X0 + rs1), 32, false);
             auto divisor = gen_ext(jh, 
                 load_reg_from_mem(jh, traits::X0 + rs2), 32, false);
-            if(rd!= 0){
+            if(rd!=0){
                 auto label_merge = cc.newLabel();
-                cc.cmp(gen_operation(jh, ne, 
-                    divisor, gen_ext(jh,  0, 32, false))
+                cc.cmp(gen_operation(jh, ne, divisor, 0)
                 ,0);
                 auto label_else = cc.newLabel();
                 cc.je(label_else);
                 {
                     auto MMIN = ((uint32_t)1)<<(static_cast<uint32_t>(traits::XLEN)-1);
                     auto label_merge = cc.newLabel();
-                    cc.cmp(gen_operation(jh, land, 
-                        gen_operation(jh, eq, 
-                            load_reg_from_mem(jh, traits::X0 + rs1), MMIN)
-                        , gen_operation(jh, eq, 
-                            divisor, gen_ext(jh, - 1, 32, true))
-                        )
+                    cc.cmp(gen_operation(jh, land, gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN)
+                    , gen_operation(jh, eq, divisor, - 1)
+                    )
                     ,0);
                     auto label_else = cc.newLabel();
                     cc.je(label_else);
                     {
-                        cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                        cc.mov(get_ptr_for(jh, traits::X0+ rd),
                              MMIN);
                     }
                     cc.jmp(label_merge);
                     cc.bind(label_else);
                         {
-                            cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                            cc.mov(get_ptr_for(jh, traits::X0+ rd),
                                  gen_ext(jh, 
-                                     (gen_operation(jh, idiv, 
-                                         gen_ext(jh, dividend, 64, true), gen_ext(jh, divisor, 64, true))
+                                     (gen_operation(jh, idiv, dividend, divisor)
                                      ), 32, true));
                         }
                     cc.bind(label_merge);
@@ -2473,7 +3081,7 @@ private:
                 cc.jmp(label_merge);
                 cc.bind(label_else);
                     {
-                        cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                        cc.mov(get_ptr_for(jh, traits::X0+ rd),
                              (uint32_t)- 1);
                     }
                 cc.bind(label_merge);
@@ -2494,33 +3102,43 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nDIVU_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("DIVU_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 54);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto label_merge = cc.newLabel();
-            cc.cmp(gen_operation(jh, ne, 
-                load_reg_from_mem(jh, traits::X0 + rs2), gen_ext(jh,  0, 32, false))
+            cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
             ,0);
             auto label_else = cc.newLabel();
             cc.je(label_else);
             {
                 if(rd!=0){
-                    cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                    cc.mov(get_ptr_for(jh, traits::X0+ rd),
                          gen_ext(jh, 
-                             (gen_operation(jh, div, 
-                                 load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
+                             (gen_operation(jh, div, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
                              ), 32, false));
                 }
             }
@@ -2528,7 +3146,7 @@ private:
             cc.bind(label_else);
                 {
                     if(rd!=0){
-                        cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                        cc.mov(get_ptr_for(jh, traits::X0+ rd),
                              (uint32_t)- 1);
                     }
                 }
@@ -2549,44 +3167,52 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nREM_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("REM_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 55);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto label_merge = cc.newLabel();
-            cc.cmp(gen_operation(jh, ne, 
-                load_reg_from_mem(jh, traits::X0 + rs2), gen_ext(jh,  0, 32, false))
+            cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
             ,0);
             auto label_else = cc.newLabel();
             cc.je(label_else);
             {
                 auto MMIN = (uint32_t)1<<(static_cast<uint32_t>(traits::XLEN)-1);
                 auto label_merge = cc.newLabel();
-                cc.cmp(gen_operation(jh, land, 
-                    gen_operation(jh, eq, 
-                        load_reg_from_mem(jh, traits::X0 + rs1), MMIN)
-                    , gen_operation(jh, eq, 
-                        gen_ext(jh, 
-                            load_reg_from_mem(jh, traits::X0 + rs2), 32, false), gen_ext(jh, - 1, 32, true))
-                    )
+                cc.cmp(gen_operation(jh, land, gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1), MMIN)
+                , gen_operation(jh, eq, gen_ext(jh, 
+                    load_reg_from_mem(jh, traits::X0 + rs2), 32, false), - 1)
+                )
                 ,0);
                 auto label_else = cc.newLabel();
                 cc.je(label_else);
                 {
                     if(rd!=0){
-                        cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                             gen_ext(jh,  0, 32, false)
+                        cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                             gen_ext(jh, 0, 32, false)
                         );
                     }
                 }
@@ -2594,12 +3220,11 @@ private:
                 cc.bind(label_else);
                     {
                         if(rd!=0){
-                            cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                            cc.mov(get_ptr_for(jh, traits::X0+ rd),
                                  gen_ext(jh, 
-                                     (gen_operation(jh, srem, 
-                                         gen_ext(jh, 
-                                             load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, 
-                                             load_reg_from_mem(jh, traits::X0 + rs2), 32, false))
+                                     (gen_operation(jh, srem, gen_ext(jh, 
+                                         load_reg_from_mem(jh, traits::X0 + rs1), 32, false), gen_ext(jh, 
+                                         load_reg_from_mem(jh, traits::X0 + rs2), 32, false))
                                      ), 32, true));
                         }
                     }
@@ -2609,7 +3234,7 @@ private:
             cc.bind(label_else);
                 {
                     if(rd!=0){
-                        cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                        cc.mov(get_ptr_for(jh, traits::X0+ rd),
                              load_reg_from_mem(jh, traits::X0 + rs1));
                     }
                 }
@@ -2630,32 +3255,42 @@ private:
         uint8_t rs2 = ((bit_sub<20,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nREMU_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("REMU_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 56);
-        pc=pc+ 4;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+4;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto label_merge = cc.newLabel();
-            cc.cmp(gen_operation(jh, ne, 
-                load_reg_from_mem(jh, traits::X0 + rs2), gen_ext(jh,  0, 32, false))
+            cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs2), 0)
             ,0);
             auto label_else = cc.newLabel();
             cc.je(label_else);
             {
                 if(rd!=0){
-                    cc.mov(get_reg_ptr(jh, traits::X0+ rd),
-                         gen_operation(jh, urem, 
-                             load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
+                    cc.mov(get_ptr_for(jh, traits::X0+ rd),
+                         gen_operation(jh, urem, load_reg_from_mem(jh, traits::X0 + rs1), load_reg_from_mem(jh, traits::X0 + rs2))
                          );
                 }
             }
@@ -2663,7 +3298,7 @@ private:
             cc.bind(label_else);
                 {
                     if(rd!=0){
-                        cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+                        cc.mov(get_ptr_for(jh, traits::X0+ rd),
                              load_reg_from_mem(jh, traits::X0 + rs1));
                     }
                 }
@@ -2683,26 +3318,37 @@ private:
         uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__ADDI4SPN_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__ADDI4SPN_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 57);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(imm){
-            cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8),
+            cc.mov(get_ptr_for(jh, traits::X0+ rd+8),
                  gen_ext(jh, 
-                     (gen_operation(jh, add, 
-                         gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, imm, 64, false))
+                     (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), imm)
                      ), 32, false));
         }
         else{
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         auto returnValue = CONT;
         
@@ -2719,22 +3365,33 @@ private:
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__LW_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__LW_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 58);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         auto offs = gen_ext(jh, 
-            (gen_operation(jh, add, 
-                gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1+ 8), 64, false), gen_ext(jh, uimm, 64, false))
+            (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1+8), uimm)
             ), 32, false);
-        cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8),
+        cc.mov(get_ptr_for(jh, traits::X0+ rd+8),
              gen_ext(jh, 
                  gen_ext(jh, 
                      gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true));
@@ -2753,23 +3410,34 @@ private:
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"),
+                fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__SW_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__SW_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 59);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         auto offs = gen_ext(jh, 
-            (gen_operation(jh, add, 
-                gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1+ 8), 64, false), gen_ext(jh, uimm, 64, false))
+            (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1+8), uimm)
             ), 32, false);
         gen_write_mem(jh, traits::MEM, offs, gen_ext(jh, 
-            load_reg_from_mem(jh, traits::X0 + rs2+ 8), 32, false), 4);
+            load_reg_from_mem(jh, traits::X0 + rs2+8), 32, false), 4);
         auto returnValue = CONT;
         
         gen_instr_epilogue(jh);
@@ -2784,26 +3452,37 @@ private:
         uint8_t rs1 = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__ADDI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__ADDI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 60);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rs1!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rs1),
+            if(rs1!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rs1),
                      gen_ext(jh, 
-                         (gen_operation(jh, add, 
-                             gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 64, false), gen_ext(jh, (int8_t)sext<6>(imm), 64, true))
+                         (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rs1), (int8_t)sext<6>(imm))
                          ), 32, true));
             }
         }
@@ -2820,16 +3499,27 @@ private:
         uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
         if(this->disass_enabled){
             /* generate disass */
+            
+            //This disass is not yet implemented
+            std::string mnemonic = "c__nop";
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__NOP_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__NOP_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 61);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         auto returnValue = CONT;
         
@@ -2844,22 +3534,34 @@ private:
         uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"),
+                fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__JAL_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__JAL_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 62);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        cc.mov(get_reg_ptr(jh, traits::X0+ 1),
-             (uint32_t)(PC+ 2));
+        cc.mov(get_ptr_for(jh, traits::X0+ 1),
+             (uint32_t)(PC+2));
         auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm));
         cc.mov(jh.next_pc, PC_val_v);
-        cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+        cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
         auto returnValue = BRANCH;
         
         gen_instr_epilogue(jh);
@@ -2874,23 +3576,35 @@ private:
         uint8_t rd = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__LI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__LI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 63);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      (uint32_t)((int8_t)sext<6>(imm)));
             }
         }
@@ -2908,22 +3622,34 @@ private:
         uint8_t rd = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__LUI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__LUI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 64);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        if(imm== 0||rd>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+        if(imm==0||rd>=static_cast<uint32_t>(traits::RFS)){
+            gen_raise(jh, 0, 2);
         }
-        if(rd!= 0){
-            cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+        if(rd!=0){
+            cc.mov(get_ptr_for(jh, traits::X0+ rd),
                  (uint32_t)((int32_t)sext<18>(imm)));
         }
         auto returnValue = CONT;
@@ -2939,26 +3665,37 @@ private:
         uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"),
+                fmt::arg("nzimm", nzimm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__ADDI16SP_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__ADDI16SP_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 65);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(nzimm){
-            cc.mov(get_reg_ptr(jh, traits::X0+ 2),
+            cc.mov(get_ptr_for(jh, traits::X0+ 2),
                  gen_ext(jh, 
-                     (gen_operation(jh, add, 
-                         gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, (int16_t)sext<10>(nzimm), 64, true))
+                     (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), (int16_t)sext<10>(nzimm))
                      ), 32, true));
         }
         else{
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         auto returnValue = CONT;
         
@@ -2973,18 +3710,29 @@ private:
         uint8_t rd = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            //This disass is not yet implemented
+            std::string mnemonic = "__reserved_clui";
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\n__reserved_clui_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("__reserved_clui_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 66);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        gen_raise(jh, 0,  2);
+        gen_raise(jh, 0, 2);
         auto returnValue = CONT;
         
         gen_instr_epilogue(jh);
@@ -2999,20 +3747,31 @@ private:
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__SRLI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__SRLI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 67);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        cc.mov(get_reg_ptr(jh, traits::X0+ rs1+ 8),
-             gen_operation(jh, shr, 
-                 load_reg_from_mem(jh, traits::X0 + rs1+ 8), gen_ext(jh, shamt, 32, false))
+        cc.mov(get_ptr_for(jh, traits::X0+ rs1+8),
+             gen_operation(jh, shr, load_reg_from_mem(jh, traits::X0 + rs1+8), shamt)
              );
         auto returnValue = CONT;
         
@@ -3028,32 +3787,42 @@ private:
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__SRAI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__SRAI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 68);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(shamt){
-            cc.mov(get_reg_ptr(jh, traits::X0+ rs1+ 8),
+            cc.mov(get_ptr_for(jh, traits::X0+ rs1+8),
                  gen_ext(jh, 
-                     (gen_operation(jh, sar, 
-                         (gen_ext(jh, 
-                             load_reg_from_mem(jh, traits::X0 + rs1+ 8), 32, false)), gen_ext(jh, shamt, 32, false))
+                     (gen_operation(jh, sar, (gen_ext(jh, 
+                         load_reg_from_mem(jh, traits::X0 + rs1+8), 32, false)), shamt)
                      ), 32, true));
         }
         else{
-            if(static_cast<uint32_t>(traits::XLEN)== 128){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rs1+ 8),
+            if(static_cast<uint32_t>(traits::XLEN)==128){
+                cc.mov(get_ptr_for(jh, traits::X0+ rs1+8),
                      gen_ext(jh, 
-                         (gen_operation(jh, sar, 
-                             (gen_ext(jh, 
-                                 load_reg_from_mem(jh, traits::X0 + rs1+ 8), 32, false)), gen_ext(jh,  64, 32, false))
+                         (gen_operation(jh, sar, (gen_ext(jh, 
+                             load_reg_from_mem(jh, traits::X0 + rs1+8), 32, false)), 64)
                          ), 32, true));
             }
         }
@@ -3071,21 +3840,32 @@ private:
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__ANDI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__ANDI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 69);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        cc.mov(get_reg_ptr(jh, traits::X0+ rs1+ 8),
+        cc.mov(get_ptr_for(jh, traits::X0+ rs1+8),
              gen_ext(jh, 
-                 (gen_operation(jh, band, 
-                     load_reg_from_mem(jh, traits::X0 + rs1+ 8), gen_ext(jh, (int8_t)sext<6>(imm), 32, true))
+                 (gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1+8), (int8_t)sext<6>(imm))
                  ), 32, true));
         auto returnValue = CONT;
         
@@ -3101,21 +3881,32 @@ private:
         uint8_t rd = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__SUB_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__SUB_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 70);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8),
+        cc.mov(get_ptr_for(jh, traits::X0+ rd+8),
              gen_ext(jh, 
-                 (gen_operation(jh, sub, 
-                     gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rd+ 8), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2+ 8), 64, false))
+                 (gen_operation(jh, sub, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8))
                  ), 32, true));
         auto returnValue = CONT;
         
@@ -3131,20 +3922,31 @@ private:
         uint8_t rd = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__XOR_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__XOR_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 71);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8),
-             gen_operation(jh, bxor, 
-                 load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8))
+        cc.mov(get_ptr_for(jh, traits::X0+ rd+8),
+             gen_operation(jh, bxor, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8))
              );
         auto returnValue = CONT;
         
@@ -3160,20 +3962,31 @@ private:
         uint8_t rd = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__OR_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__OR_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 72);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8),
-             gen_operation(jh, bor, 
-                 load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8))
+        cc.mov(get_ptr_for(jh, traits::X0+ rd+8),
+             gen_operation(jh, bor, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8))
              );
         auto returnValue = CONT;
         
@@ -3189,20 +4002,31 @@ private:
         uint8_t rd = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__AND_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__AND_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 73);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        cc.mov(get_reg_ptr(jh, traits::X0+ rd+ 8),
-             gen_operation(jh, band, 
-                 load_reg_from_mem(jh, traits::X0 + rd+ 8), load_reg_from_mem(jh, traits::X0 + rs2+ 8))
+        cc.mov(get_ptr_for(jh, traits::X0+ rd+8),
+             gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rd+8), load_reg_from_mem(jh, traits::X0 + rs2+8))
              );
         auto returnValue = CONT;
         
@@ -3217,20 +4041,32 @@ private:
         uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"),
+                fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__J_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__J_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 74);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm));
         cc.mov(jh.next_pc, PC_val_v);
-        cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+        cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
         auto returnValue = BRANCH;
         
         gen_instr_epilogue(jh);
@@ -3245,26 +4081,37 @@ private:
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__BEQZ_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__BEQZ_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 75);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         auto label_merge = cc.newLabel();
-        cc.cmp(gen_operation(jh, eq, 
-            load_reg_from_mem(jh, traits::X0 + rs1+ 8), gen_ext(jh,  0, 32, false))
+        cc.cmp(gen_operation(jh, eq, load_reg_from_mem(jh, traits::X0 + rs1+8), 0)
         ,0);
         cc.je(label_merge);
         {
             auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm));
             cc.mov(jh.next_pc, PC_val_v);
-            cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+            cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
         }
         cc.bind(label_merge);
         auto returnValue = BRANCH;
@@ -3281,26 +4128,37 @@ private:
         uint8_t rs1 = ((bit_sub<7,3>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__BNEZ_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__BNEZ_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 76);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         auto label_merge = cc.newLabel();
-        cc.cmp(gen_operation(jh, ne, 
-            load_reg_from_mem(jh, traits::X0 + rs1+ 8), gen_ext(jh,  0, 32, false))
+        cc.cmp(gen_operation(jh, ne, load_reg_from_mem(jh, traits::X0 + rs1+8), 0)
         ,0);
         cc.je(label_merge);
         {
             auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm));
             cc.mov(jh.next_pc, PC_val_v);
-            cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+            cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
         }
         cc.bind(label_merge);
         auto returnValue = BRANCH;
@@ -3317,25 +4175,36 @@ private:
         uint8_t rs1 = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__SLLI_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__SLLI_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 77);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rs1!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rs1),
-                     gen_operation(jh, shl, 
-                         load_reg_from_mem(jh, traits::X0 + rs1), gen_ext(jh, nzuimm, 32, false))
+            if(rs1!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rs1),
+                     gen_operation(jh, shl, load_reg_from_mem(jh, traits::X0 + rs1), nzuimm)
                      );
             }
         }
@@ -3353,26 +4222,37 @@ private:
         uint8_t rd = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"),
+                fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__LWSP_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__LWSP_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 78);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        if(rd>=static_cast<uint32_t>(traits::RFS)||rd== 0){
-            gen_raise(jh, 0,  2);
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rd==0){
+            gen_raise(jh, 0, 2);
         }
         else{
             auto offs = gen_ext(jh, 
-                (gen_operation(jh, add, 
-                    gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, uimm, 64, false))
+                (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), uimm)
                 ), 32, false);
-            cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            cc.mov(get_ptr_for(jh, traits::X0+ rd),
                  gen_ext(jh, 
                      gen_ext(jh, 
                          gen_read_mem(jh, traits::MEM, offs, 4), 32, false), 32, true));
@@ -3391,23 +4271,35 @@ private:
         uint8_t rd = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__MV_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__MV_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 79);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      load_reg_from_mem(jh, traits::X0 + rs2));
             }
         }
@@ -3424,23 +4316,34 @@ private:
         uint8_t rs1 = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"),
+                fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__JR_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__JR_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 80);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs1&&rs1<static_cast<uint32_t>(traits::RFS)){
-            auto PC_val_v = gen_operation(jh, band, 
-                load_reg_from_mem(jh, traits::X0 + rs1%static_cast<uint32_t>(traits::RFS)), gen_ext(jh, ~ 0x1, 32, false))
+            auto PC_val_v = gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1%static_cast<uint32_t>(traits::RFS)), ~ 1)
             ;
             cc.mov(jh.next_pc, PC_val_v);
-            cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+            cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
         }
         else{
             gen_raise(jh, 0, 2);
@@ -3457,16 +4360,27 @@ private:
         uint64_t PC = pc.val;
         if(this->disass_enabled){
             /* generate disass */
+            
+            //This disass is not yet implemented
+            std::string mnemonic = "__reserved_cmv";
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\n__reserved_cmv_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("__reserved_cmv_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 81);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         gen_raise(jh, 0, 2);
         auto returnValue = CONT;
@@ -3483,26 +4397,37 @@ private:
         uint8_t rd = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__ADD_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__ADD_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 82);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rd>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
-            if(rd!= 0){
-                cc.mov(get_reg_ptr(jh, traits::X0+ rd),
+            if(rd!=0){
+                cc.mov(get_ptr_for(jh, traits::X0+ rd),
                      gen_ext(jh, 
-                         (gen_operation(jh, add, 
-                             gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rd), 64, false), gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 64, false))
+                         (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + rd), load_reg_from_mem(jh, traits::X0 + rs2))
                          ), 32, false));
             }
         }
@@ -3519,29 +4444,40 @@ private:
         uint8_t rs1 = ((bit_sub<7,5>(instr)));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"),
+                fmt::arg("rs1", name(rs1)));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__JALR_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__JALR_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 83);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs1>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto new_pc = load_reg_from_mem(jh, traits::X0 + rs1);
-            cc.mov(get_reg_ptr(jh, traits::X0+ 1),
-                 (uint32_t)(PC+ 2));
-            auto PC_val_v = gen_operation(jh, band, 
-                new_pc, gen_ext(jh, ~ 0x1, 32, false))
+            cc.mov(get_ptr_for(jh, traits::X0+ 1),
+                 (uint32_t)(PC+2));
+            auto PC_val_v = gen_operation(jh, band, new_pc, ~ 1)
             ;
             cc.mov(jh.next_pc, PC_val_v);
-            cc.mov(get_reg_ptr(jh, traits::LAST_BRANCH), 32U);
+            cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
         }
         auto returnValue = BRANCH;
         
@@ -3555,18 +4491,29 @@ private:
         uint64_t PC = pc.val;
         if(this->disass_enabled){
             /* generate disass */
+            
+            //This disass is not yet implemented
+            std::string mnemonic = "c__ebreak";
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__EBREAK_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__EBREAK_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 84);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        gen_raise(jh, 0,  3);
+        gen_raise(jh, 0, 3);
         auto returnValue = CONT;
         
         gen_instr_epilogue(jh);
@@ -3581,24 +4528,35 @@ private:
         uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
         if(this->disass_enabled){
             /* generate disass */
+            
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nC__SWSP_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("C__SWSP_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 85);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
         if(rs2>=static_cast<uint32_t>(traits::RFS)){
-            gen_raise(jh, 0,  2);
+            gen_raise(jh, 0, 2);
         }
         else{
             auto offs = gen_ext(jh, 
-                (gen_operation(jh, add, 
-                    gen_ext(jh, load_reg_from_mem(jh, traits::X0 + 2), 64, false), gen_ext(jh, uimm, 64, false))
+                (gen_operation(jh, add, load_reg_from_mem(jh, traits::X0 + 2), uimm)
                 ), 32, false);
             gen_write_mem(jh, traits::MEM, offs, gen_ext(jh, 
                 load_reg_from_mem(jh, traits::X0 + rs2), 32, false), 4);
@@ -3615,18 +4573,29 @@ private:
         uint64_t PC = pc.val;
         if(this->disass_enabled){
             /* generate disass */
+            
+            //This disass is not yet implemented
+            std::string mnemonic = "dii";
+            InvokeNode* call_print_disass;
+            char* mnemonic_ptr = strdup(mnemonic.c_str());
+            jh.disass_collection.push_back(mnemonic_ptr);
+            jh.cc.invoke(&call_print_disass, &print_disass, FuncSignatureT<void, void *, uint64_t, char *>());
+            call_print_disass->setArg(0, jh.arch_if_ptr);
+            call_print_disass->setArg(1, pc.val);
+            call_print_disass->setArg(2, mnemonic_ptr);
+
         }
         x86::Compiler& cc = jh.cc;
-        //ideally only do this if necessary (someone / plugin needs it)
-        cc.mov(jh.pc,PC);
-        cc.comment(fmt::format("\nDII_{:#x}:",pc.val).c_str());
+        cc.comment(fmt::format("DII_{:#x}:",pc.val).c_str());
         this->gen_sync(jh, PRE_SYNC, 86);
-        pc=pc+ 2;
-       
-        gen_instr_prologue(jh, pc.val);
-        cc.comment("\n//behavior:");
+        cc.mov(jh.pc, pc.val);
+        pc = pc+2;
+        cc.mov(jh.next_pc, pc.val);
+
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
         /*generate behavior*/
-        gen_raise(jh, 0,  2);
+        gen_raise(jh, 0, 2);
         auto returnValue = CONT;
         
         gen_instr_epilogue(jh);
@@ -3638,7 +4607,14 @@ private:
      * end opcode definitions
      ****************************************************************************/
     continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
-
+        x86::Compiler& cc = jh.cc;
+        cc.comment(fmt::format("illegal_intruction{:#x}:",pc.val).c_str());
+        this->gen_sync(jh, PRE_SYNC, instr_descr.size());
+        pc = pc + ((instr & 3) == 3 ? 4 : 2);
+        gen_instr_prologue(jh);
+        cc.comment("//behavior:");
+        gen_instr_epilogue(jh);
+        this->gen_sync(jh, POST_SYNC, instr_descr.size());
         return BRANCH;
     }    
     //decoding functionality
@@ -3695,11 +4671,6 @@ private:
     }
 };
 
-template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
-    volatile CODE_WORD x = instr;
-    instr = 2 * x;
-}
-
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 
 template <typename ARCH>
@@ -3713,8 +4684,7 @@ vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 }
 
 template <typename ARCH>
-continuation_e
-vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
+continuation_e vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, jit_holder& jh) {
     enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
     phys_addr_t paddr(pc);
@@ -3732,8 +4702,76 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
         f = &this_class::illegal_intruction;
     return (this->*f)(pc, instr, jh);
 }
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_prologue(jit_holder& jh) {
+    auto& cc = jh.cc;
 
+    cc.comment("//gen_instr_prologue");
+    cc.inc(get_ptr_for(jh, traits::ICOUNT));
 
+    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
+    cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+    cc.mov(get_ptr_for(jh, traits::PENDING_TRAP), current_trap_state);
+
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_epilogue(jit_holder& jh) {
+    auto& cc = jh.cc;
+
+    cc.comment("//gen_instr_epilogue");
+    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
+    cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+    cc.cmp(current_trap_state, 0);
+    cc.jne(jh.trap_entry);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_block_prologue(jit_holder& jh){
+
+    jh.pc = load_reg_from_mem(jh, traits::PC);
+    jh.next_pc = load_reg_from_mem(jh, traits::NEXT_PC);
+}
+template <typename ARCH>
+void vm_impl<ARCH>::gen_block_epilogue(jit_holder& jh){
+    x86::Compiler& cc = jh.cc;
+    cc.comment("//gen_block_epilogue");
+    cc.ret(jh.next_pc);
+
+    cc.bind(jh.trap_entry);
+    this->write_back(jh);
+    this->gen_sync(jh, POST_SYNC, -1);
+
+    x86::Gp current_trap_state = get_reg_for(jh, traits::TRAP_STATE);
+    cc.mov(current_trap_state, get_ptr_for(jh, traits::TRAP_STATE));
+
+    x86::Gp current_pc = get_reg_for(jh, traits::PC);
+    cc.mov(current_pc, get_ptr_for(jh, traits::PC));
+
+    x86::Gp instr = cc.newInt32("instr");
+    cc.mov(instr, 0); // FIXME:this is not correct
+    cc.comment("//enter trap call;");
+    InvokeNode* call_enter_trap;
+    cc.invoke(&call_enter_trap, &enter_trap, FuncSignatureT<uint64_t, void*, uint64_t, uint64_t, uint64_t>());
+    call_enter_trap->setArg(0, jh.arch_if_ptr);
+    call_enter_trap->setArg(1, current_trap_state);
+    call_enter_trap->setArg(2, current_pc);
+    call_enter_trap->setArg(3, instr);
+
+    x86::Gp current_next_pc = get_reg_for(jh, traits::NEXT_PC);
+    cc.mov(current_next_pc, get_ptr_for(jh, traits::NEXT_PC));
+    cc.mov(jh.next_pc, current_next_pc);
+
+    cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), std::numeric_limits<uint32_t>::max());
+    cc.ret(jh.next_pc);
+}
+template <typename ARCH>
+inline void vm_impl<ARCH>::gen_raise(jit_holder& jh, uint16_t trap_id, uint16_t cause) {
+    auto& cc = jh.cc;
+    cc.comment("//gen_raise");
+    auto tmp1 = get_reg_for(jh, traits::TRAP_STATE);
+    cc.mov(tmp1, 0x80ULL << 24 | (cause << 16) | trap_id);
+    cc.mov(get_ptr_for(jh, traits::TRAP_STATE), tmp1);
+    cc.mov(jh.next_pc, std::numeric_limits<uint32_t>::max());
+}
 
 } // namespace tgc5c
 
@@ -3746,22 +4784,30 @@ std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short por
 } // namespace asmjit
 } // namespace iss
 
-#include <iss/factory.h>
 #include <iss/arch/riscv_hart_m_p.h>
 #include <iss/arch/riscv_hart_mu_p.h>
+#include <iss/factory.h>
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("tgc5c|m_p|asmjit", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("tgc5c|m_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
-            auto* vm = new asmjit::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+		    auto vm = new asmjit::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("tgc5c|mu_p|asmjit", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
-            auto* vm = new asmjit::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
-            if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+		    auto vm = new asmjit::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
diff --git a/src/vm/interp/vm_tgc5c.cpp b/src/vm/interp/vm_tgc5c.cpp
index 99419ac..e4a816e 100644
--- a/src/vm/interp/vm_tgc5c.cpp
+++ b/src/vm/interp/vm_tgc5c.cpp
@@ -399,10 +399,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = (uint32_t)((int32_t)imm);
                                         }
                                     }
@@ -425,11 +425,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = (uint32_t)(*PC + (int32_t)imm);
+                                        if(rd != 0) {
+                                            *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)imm ));
                                         }
                                     }
                                 }
@@ -451,17 +451,17 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         if(imm % traits::INSTR_ALIGNMENT) {
-                                            raise(0,  0);
+                                            raise(0, 0);
                                         }
                                         else {
-                                            if(rd !=  0) {
-                                                *(X+rd) = (uint32_t)(*PC +  4);
+                                            if(rd != 0) {
+                                                *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(4 ));
                                             }
-                                            *NEXT_PC = (uint32_t)(*PC + (int32_t)sext<21>(imm));
+                                            *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)sext<21>(imm) ));
                                             this->core.reg.last_branch = 1;
                                         }
                                     }
@@ -485,17 +485,17 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         uint32_t addr_mask = (uint32_t)- 2;
-                                        uint32_t new_pc = (uint32_t)((*(X+rs1) + (int16_t)sext<12>(imm)) & addr_mask);
+                                        uint32_t new_pc = (uint32_t)(((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) )) & (int64_t)(addr_mask ));
                                         if(new_pc % traits::INSTR_ALIGNMENT) {
-                                            raise(0,  0);
+                                            raise(0, 0);
                                         }
                                         else {
-                                            if(rd !=  0) {
-                                                *(X+rd) = (uint32_t)(*PC +  4);
+                                            if(rd != 0) {
+                                                *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(4 ));
                                             }
                                             *NEXT_PC = new_pc;
                                             this->core.reg.last_branch = 1;
@@ -521,15 +521,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         if(*(X+rs1) == *(X+rs2)) {
-                                            if(imm % traits::INSTR_ALIGNMENT) {
-                                                raise(0,  0);
+                                            if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
+                                                raise(0, 0);
                                             }
                                             else {
-                                                *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                                *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
                                                 this->core.reg.last_branch = 1;
                                             }
                                         }
@@ -554,15 +554,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         if(*(X+rs1) != *(X+rs2)) {
-                                            if(imm % traits::INSTR_ALIGNMENT) {
-                                                raise(0,  0);
+                                            if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
+                                                raise(0, 0);
                                             }
                                             else {
-                                                *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                                *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
                                                 this->core.reg.last_branch = 1;
                                             }
                                         }
@@ -587,15 +587,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) {
-                                            if(imm % traits::INSTR_ALIGNMENT) {
-                                                raise(0,  0);
+                                            if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
+                                                raise(0, 0);
                                             }
                                             else {
-                                                *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                                *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
                                                 this->core.reg.last_branch = 1;
                                             }
                                         }
@@ -620,15 +620,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) {
-                                            if(imm % traits::INSTR_ALIGNMENT) {
-                                                raise(0,  0);
+                                            if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
+                                                raise(0, 0);
                                             }
                                             else {
-                                                *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                                *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
                                                 this->core.reg.last_branch = 1;
                                             }
                                         }
@@ -653,15 +653,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         if(*(X+rs1) < *(X+rs2)) {
-                                            if(imm % traits::INSTR_ALIGNMENT) {
-                                                raise(0,  0);
+                                            if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
+                                                raise(0, 0);
                                             }
                                             else {
-                                                *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                                *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
                                                 this->core.reg.last_branch = 1;
                                             }
                                         }
@@ -686,15 +686,15 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         if(*(X+rs1) >= *(X+rs2)) {
-                                            if(imm % traits::INSTR_ALIGNMENT) {
-                                                raise(0,  0);
+                                            if((uint32_t)(imm ) % traits::INSTR_ALIGNMENT) {
+                                                raise(0, 0);
                                             }
                                             else {
-                                                *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<13>(imm));
+                                                *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<13>(imm) ));
                                                 this->core.reg.last_branch = 1;
                                             }
                                         }
@@ -719,14 +719,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                        uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
                                         int8_t res_27 = super::template read_mem<int8_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         int8_t res = (int8_t)res_27;
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
                                     }
@@ -750,14 +750,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                        uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
                                         int16_t res_28 = super::template read_mem<int16_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         int16_t res = (int16_t)res_28;
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
                                     }
@@ -781,14 +781,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                        uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
                                         int32_t res_29 = super::template read_mem<int32_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         int32_t res = (int32_t)res_29;
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
                                     }
@@ -812,14 +812,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                        uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
                                         uint8_t res_30 = super::template read_mem<uint8_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         uint8_t res = res_30;
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
                                     }
@@ -843,14 +843,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        uint32_t load_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                        uint32_t load_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
                                         uint16_t res_31 = super::template read_mem<uint16_t>(traits::MEM, load_address);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         uint16_t res = res_31;
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
                                     }
@@ -874,10 +874,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                        uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
                                         super::template write_mem<uint8_t>(traits::MEM, store_address, (uint8_t)*(X+rs2));
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                     }
@@ -901,10 +901,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                        uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
                                         super::template write_mem<uint16_t>(traits::MEM, store_address, (uint16_t)*(X+rs2));
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                     }
@@ -928,10 +928,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs2 >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        uint32_t store_address = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                        uint32_t store_address = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
                                         super::template write_mem<uint32_t>(traits::MEM, store_address, (uint32_t)*(X+rs2));
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                     }
@@ -955,11 +955,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = (uint32_t)(*(X+rs1) + (int16_t)sext<12>(imm));
+                                        if(rd != 0) {
+                                            *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int16_t)sext<12>(imm) ));
                                         }
                                     }
                                 }
@@ -982,11 +982,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))?  1 :  0;
+                                        if(rd != 0) {
+                                            *(X+rd) = ((int32_t)*(X+rs1) < (int16_t)sext<12>(imm))? 1 : 0;
                                         }
                                     }
                                 }
@@ -1009,11 +1009,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))?  1 :  0;
+                                        if(rd != 0) {
+                                            *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))? 1 : 0;
                                         }
                                     }
                                 }
@@ -1036,10 +1036,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = *(X+rs1) ^ (uint32_t)((int16_t)sext<12>(imm));
                                         }
                                     }
@@ -1063,10 +1063,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = *(X+rs1) | (uint32_t)((int16_t)sext<12>(imm));
                                         }
                                     }
@@ -1090,10 +1090,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = *(X+rs1) & (uint32_t)((int16_t)sext<12>(imm));
                                         }
                                     }
@@ -1117,10 +1117,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = *(X+rs1) << shamt;
                                         }
                                     }
@@ -1144,10 +1144,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = *(X+rs1) >> shamt;
                                         }
                                     }
@@ -1171,10 +1171,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> shamt);
                                         }
                                     }
@@ -1198,11 +1198,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = (uint32_t)(*(X+rs1) + *(X+rs2));
+                                        if(rd != 0) {
+                                            *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)(*(X+rs2) ));
                                         }
                                     }
                                 }
@@ -1225,11 +1225,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = (uint32_t)(*(X+rs1) - *(X+rs2));
+                                        if(rd != 0) {
+                                            *(X+rd) = (uint32_t)((uint64_t)(*(X+rs1) ) - (uint64_t)(*(X+rs2) ));
                                         }
                                     }
                                 }
@@ -1252,11 +1252,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN -  1));
+                                        if(rd != 0) {
+                                            *(X+rd) = *(X+rs1) << ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )));
                                         }
                                     }
                                 }
@@ -1279,11 +1279,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)?  1 :  0;
+                                        if(rd != 0) {
+                                            *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)? 1 : 0;
                                         }
                                     }
                                 }
@@ -1306,11 +1306,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = *(X+rs1) < *(X+rs2)?  1 :  0;
+                                        if(rd != 0) {
+                                            *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0;
                                         }
                                     }
                                 }
@@ -1333,10 +1333,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = *(X+rs1) ^ *(X+rs2);
                                         }
                                     }
@@ -1360,11 +1360,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN -  1));
+                                        if(rd != 0) {
+                                            *(X+rd) = *(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )));
                                         }
                                     }
                                 }
@@ -1387,11 +1387,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN -  1)));
+                                        if(rd != 0) {
+                                            *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 ))));
                                         }
                                     }
                                 }
@@ -1414,10 +1414,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = *(X+rs1) | *(X+rs2);
                                         }
                                     }
@@ -1441,10 +1441,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = *(X+rs1) & *(X+rs2);
                                         }
                                     }
@@ -1468,7 +1468,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                                    super::template write_mem<uint32_t>(traits::FENCE, traits::fence, (uint8_t)pred <<  4 | succ);
+                                    super::template write_mem<uint32_t>(traits::FENCE, traits::fence, (uint8_t)pred << 4 | succ);
                                     if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                 }
                     break;
@@ -1482,7 +1482,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                                    raise(0,  11);
+                                    raise(0, 11);
                                 }
                     break;
                 }// @suppress("No break at end of case")
@@ -1495,7 +1495,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 4;
                     // execute instruction
                     {
-                                    raise(0,  3);
+                                    raise(0, 3);
                                 }
                     break;
                 }// @suppress("No break at end of case")
@@ -1542,11 +1542,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         uint32_t xrs1 = *(X+rs1);
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             uint32_t res_32 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                             uint32_t xrd = res_32;
@@ -1579,18 +1579,18 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         uint32_t res_33 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         uint32_t xrd = res_33;
                                         uint32_t xrs1 = *(X+rs1);
-                                        if(rs1 !=  0) {
+                                        if(rs1 != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd | xrs1);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         }
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = xrd;
                                         }
                                     }
@@ -1614,18 +1614,18 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         uint32_t res_34 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         uint32_t xrd = res_34;
                                         uint32_t xrs1 = *(X+rs1);
-                                        if(rs1 !=  0) {
+                                        if(rs1 != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ xrs1);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         }
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = xrd;
                                         }
                                     }
@@ -1649,7 +1649,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         uint32_t res_35 = super::template read_mem<uint32_t>(traits::CSR, csr);
@@ -1657,7 +1657,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                                         uint32_t xrd = res_35;
                                         super::template write_mem<uint32_t>(traits::CSR, csr, (uint32_t)zimm);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = xrd;
                                         }
                                     }
@@ -1681,17 +1681,17 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         uint32_t res_36 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         uint32_t xrd = res_36;
-                                        if(zimm !=  0) {
+                                        if(zimm != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd | (uint32_t)zimm);
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         }
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = xrd;
                                         }
                                     }
@@ -1715,17 +1715,17 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         uint32_t res_37 = super::template read_mem<uint32_t>(traits::CSR, csr);
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         uint32_t xrd = res_37;
-                                        if(zimm !=  0) {
+                                        if(zimm != 0) {
                                             super::template write_mem<uint32_t>(traits::CSR, csr, xrd & ~ ((uint32_t)zimm));
                                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                         }
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = xrd;
                                         }
                                     }
@@ -1769,10 +1769,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2));
+                                        int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) );
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)res;
                                         }
@@ -1797,10 +1797,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2));
+                                        int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)((int32_t)*(X+rs2) );
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                         }
@@ -1825,10 +1825,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        int64_t res = (int64_t)((int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2));
+                                        int64_t res = (int64_t)((int32_t)*(X+rs1) ) * (int64_t)(*(X+rs2) );
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                         }
@@ -1853,10 +1853,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        uint64_t res = (uint64_t)((uint64_t)*(X+rs1) * (uint64_t)*(X+rs2));
+                                        uint64_t res = (uint64_t)(*(X+rs1) ) * (uint64_t)(*(X+rs2) );
                                         if(rd != 0) {
                                             *(X+rd) = (uint32_t)(res >> traits::XLEN);
                                         }
@@ -1881,14 +1881,14 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         int32_t dividend = (int32_t)*(X+rs1);
                                         int32_t divisor = (int32_t)*(X+rs2);
-                                        if(rd !=  0) {
-                                            if(divisor !=  0) {
-                                                uint32_t MMIN = ((uint32_t)1) << (traits::XLEN - 1);
+                                        if(rd != 0) {
+                                            if(divisor != 0) {
+                                                uint32_t MMIN = ((uint32_t)1) << ((uint64_t)(traits::XLEN ) - (uint64_t)(1 ));
                                                 if(*(X+rs1) == MMIN && divisor == - 1) {
                                                     *(X+rd) = MMIN;
                                                 }
@@ -1921,12 +1921,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(*(X+rs2) !=  0) {
+                                        if(*(X+rs2) != 0) {
                                             if(rd != 0) {
-                                                *(X+rd) = (uint32_t)(*(X+rs1) / *(X+rs2));
+                                                *(X+rd) = *(X+rs1) / *(X+rs2);
                                             }
                                         }
                                         else {
@@ -1955,19 +1955,19 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(*(X+rs2) !=  0) {
-                                            uint32_t MMIN = (uint32_t)1 << (traits::XLEN - 1);
+                                        if(*(X+rs2) != 0) {
+                                            uint32_t MMIN = (uint32_t)1 << ((uint64_t)(traits::XLEN ) - (uint64_t)(1 ));
                                             if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) {
                                                 if(rd != 0) {
-                                                    *(X+rd) =  0;
+                                                    *(X+rd) = 0;
                                                 }
                                             }
                                             else {
                                                 if(rd != 0) {
-                                                    *(X+rd) = (uint32_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2));
+                                                    *(X+rd) = ((uint32_t)((int32_t)*(X+rs1) % (int32_t)*(X+rs2)));
                                                 }
                                             }
                                         }
@@ -1997,10 +1997,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS || rs1 >= traits::RFS || rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(*(X+rs2) !=  0) {
+                                        if(*(X+rs2) != 0) {
                                             if(rd != 0) {
                                                 *(X+rd) = *(X+rs1) % *(X+rs2);
                                             }
@@ -2030,10 +2030,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(imm) {
-                                        *(X+rd +  8) = (uint32_t)(*(X+2) + imm);
+                                        *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(imm ));
                                     }
                                     else {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                 }
                     break;
@@ -2054,10 +2054,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        uint32_t offs = (uint32_t)(*(X+rs1 +  8) + uimm);
+                        uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm ));
                         int32_t res_38 = super::template read_mem<int32_t>(traits::MEM, offs);
                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
-                        *(X+rd +  8) = (uint32_t)(int32_t)res_38;
+                        *(X+rd + 8) = (uint32_t)(int32_t)res_38;
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -2077,8 +2077,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        uint32_t offs = (uint32_t)(*(X+rs1 +  8) + uimm);
-                        super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2 +  8));
+                        uint32_t offs = (uint32_t)((uint64_t)(*(X+rs1 + 8) ) + (uint64_t)(uimm ));
+                        super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2 + 8));
                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                     }
                     break;
@@ -2099,11 +2099,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rs1 !=  0) {
-                                            *(X+rs1) = (uint32_t)(*(X+rs1) + (int8_t)sext<6>(imm));
+                                        if(rs1 != 0) {
+                                            *(X+rs1) = (uint32_t)((uint64_t)(*(X+rs1) ) + (uint64_t)((int8_t)sext<6>(imm) ));
                                         }
                                     }
                                 }
@@ -2136,8 +2136,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+1) = (uint32_t)(*PC +  2);
-                        *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm));
+                        *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(2 ));
+                        *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) ));
                         this->core.reg.last_branch = 1;
                     }
                     break;
@@ -2158,10 +2158,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = (uint32_t)((int8_t)sext<6>(imm));
                                         }
                                     }
@@ -2183,10 +2183,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        if(imm ==  0 || rd >= traits::RFS) {
-                            raise(0,  2);
+                        if(imm == 0 || rd >= traits::RFS) {
+                            raise(0, 2);
                         }
-                        if(rd !=  0) {
+                        if(rd != 0) {
                             *(X+rd) = (uint32_t)((int32_t)sext<18>(imm));
                         }
                     }
@@ -2207,10 +2207,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(nzimm) {
-                                        *(X+2) = (uint32_t)(*(X+2) + (int16_t)sext<10>(nzimm));
+                                        *(X+2) = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)((int16_t)sext<10>(nzimm) ));
                                     }
                                     else {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                 }
                     break;
@@ -2225,7 +2225,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                                    raise(0,  2);
+                                    raise(0, 2);
                                 }
                     break;
                 }// @suppress("No break at end of case")
@@ -2244,7 +2244,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rs1 +  8) = *(X+rs1 +  8) >> shamt;
+                        *(X+rs1 + 8) = *(X+rs1 + 8) >> shamt;
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -2264,11 +2264,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                         if(shamt) {
-                            *(X+rs1 +  8) = (uint32_t)(((int32_t)*(X+rs1 +  8)) >> shamt);
+                            *(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> shamt);
                         }
                         else {
-                            if(traits::XLEN ==  128) {
-                                *(X+rs1 +  8) = (uint32_t)(((int32_t)*(X+rs1 +  8)) >>  64);
+                            if(traits::XLEN == 128) {
+                                *(X+rs1 + 8) = (uint32_t)(((int32_t)*(X+rs1 + 8)) >> 64);
                             }
                         }
                     }
@@ -2289,7 +2289,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rs1 +  8) = (uint32_t)(*(X+rs1 +  8) & (int8_t)sext<6>(imm));
+                        *(X+rs1 + 8) = (uint32_t)(*(X+rs1 + 8) & (uint32_t)((int8_t)sext<6>(imm) ));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -2308,7 +2308,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rd +  8) = (uint32_t)(*(X+rd +  8) - *(X+rs2 +  8));
+                        *(X+rd + 8) = (uint32_t)((uint64_t)(*(X+rd + 8) ) - (uint64_t)(*(X+rs2 + 8) ));
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -2327,7 +2327,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rd +  8) = *(X+rd +  8) ^ *(X+rs2 +  8);
+                        *(X+rd + 8) = *(X+rd + 8) ^ *(X+rs2 + 8);
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -2346,7 +2346,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rd +  8) = *(X+rd +  8) | *(X+rs2 +  8);
+                        *(X+rd + 8) = *(X+rd + 8) | *(X+rs2 + 8);
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -2365,7 +2365,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        *(X+rd +  8) = *(X+rd +  8) & *(X+rs2 +  8);
+                        *(X+rd + 8) = *(X+rd + 8) & *(X+rs2 + 8);
                     }
                     break;
                 }// @suppress("No break at end of case")
@@ -2382,7 +2382,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                                    *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<12>(imm));
+                                    *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) ));
                                     this->core.reg.last_branch = 1;
                                 }
                     break;
@@ -2402,8 +2402,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                                    if(*(X+rs1 +  8) ==  0) {
-                                        *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm));
+                                    if(*(X+rs1 + 8) == 0) {
+                                        *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) ));
                                         this->core.reg.last_branch = 1;
                                     }
                                 }
@@ -2424,8 +2424,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                                    if(*(X+rs1 +  8) !=  0) {
-                                        *NEXT_PC = (uint32_t)(*PC + (int16_t)sext<9>(imm));
+                                    if(*(X+rs1 + 8) != 0) {
+                                        *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<9>(imm) ));
                                         this->core.reg.last_branch = 1;
                                     }
                                 }
@@ -2447,10 +2447,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rs1 !=  0) {
+                                        if(rs1 != 0) {
                                             *(X+rs1) = *(X+rs1) << nzuimm;
                                         }
                                     }
@@ -2472,11 +2472,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                        if(rd >= traits::RFS || rd ==  0) {
-                            raise(0,  2);
+                        if(rd >= traits::RFS || rd == 0) {
+                            raise(0, 2);
                         }
                         else {
-                            uint32_t offs = (uint32_t)(*(X+2) + uimm);
+                            uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
                             int32_t res_39 = super::template read_mem<int32_t>(traits::MEM, offs);
                             if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                             *(X+rd) = (uint32_t)(int32_t)res_39;
@@ -2500,10 +2500,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
+                                        if(rd != 0) {
                                             *(X+rd) = *(X+rs2);
                                         }
                                     }
@@ -2525,7 +2525,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs1 && rs1 < traits::RFS) {
-                                        *NEXT_PC = *(X+rs1 % traits::RFS) & ~ 0x1;
+                                        *NEXT_PC = *(X+(uint32_t)(rs1 ) % traits::RFS) & (uint32_t)(~ 1 );
                                         this->core.reg.last_branch = 1;
                                     }
                                     else {
@@ -2563,11 +2563,11 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rd >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        if(rd !=  0) {
-                                            *(X+rd) = (uint32_t)(*(X+rd) + *(X+rs2));
+                                        if(rd != 0) {
+                                            *(X+rd) = (uint32_t)((uint64_t)(*(X+rd) ) + (uint64_t)(*(X+rs2) ));
                                         }
                                     }
                                 }
@@ -2588,12 +2588,12 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs1 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
                                         uint32_t new_pc = *(X+rs1);
-                                        *(X+1) = (uint32_t)(*PC +  2);
-                                        *NEXT_PC = new_pc & ~ 0x1;
+                                        *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(2 ));
+                                        *NEXT_PC = new_pc & (uint32_t)(~ 1 );
                                         this->core.reg.last_branch = 1;
                                     }
                                 }
@@ -2608,7 +2608,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                                    raise(0,  3);
+                                    raise(0, 3);
                                 }
                     break;
                 }// @suppress("No break at end of case")
@@ -2628,10 +2628,10 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     // execute instruction
                     {
                                     if(rs2 >= traits::RFS) {
-                                        raise(0,  2);
+                                        raise(0, 2);
                                     }
                                     else {
-                                        uint32_t offs = (uint32_t)(*(X+2) + uimm);
+                                        uint32_t offs = (uint32_t)((uint64_t)(*(X+2) ) + (uint64_t)(uimm ));
                                         super::template write_mem<uint32_t>(traits::MEM, offs, (uint32_t)*(X+rs2));
                                         if(this->core.reg.trap_state>=0x80000000UL) throw memory_access_exception();
                                     }
@@ -2647,7 +2647,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
                     *NEXT_PC = *PC + 2;
                     // execute instruction
                     {
-                                    raise(0,  2);
+                                    raise(0, 2);
                                 }
                     break;
                 }// @suppress("No break at end of case")
@@ -2695,16 +2695,24 @@ std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short por
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-        core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
 		    auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         }),
-        core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr>{
+        core_factory::instance().register_creator("tgc5c|mu_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
             auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
 		    auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
 		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
             return {cpu_ptr{cpu}, vm_ptr{vm}};
         })
 };
diff --git a/src/vm/llvm/vm_tgc5c.cpp b/src/vm/llvm/vm_tgc5c.cpp
index 94fe033..aa4d9a0 100644
--- a/src/vm/llvm/vm_tgc5c.cpp
+++ b/src/vm/llvm/vm_tgc5c.cpp
@@ -29,7 +29,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+// clang-format off
 #include <iss/arch/tgc5c.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
@@ -48,7 +48,7 @@
 namespace iss {
 namespace llvm {
 namespace fp_impl {
-void add_fp_functions_2_module(::llvm::Module*, unsigned, unsigned);
+void add_fp_functions_2_module(::llvm::Module *, unsigned, unsigned);
 }
 
 namespace tgc5c {
@@ -67,13 +67,13 @@ public:
 
     vm_impl();
 
-    vm_impl(ARCH& core, unsigned core_id = 0, unsigned cluster_id = 0);
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
 
     void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
 
-    target_adapter_if* accquire_target_adapter(server_if* srv) override {
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
         debugger_if::dbg_enabled = true;
-        if(vm_base<ARCH>::tgt_adapter == nullptr)
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
             vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
         return vm_base<ARCH>::tgt_adapter;
     }
@@ -81,9 +81,9 @@ public:
 protected:
     using vm_base<ARCH>::get_reg_ptr;
 
-    inline const char* name(size_t index) { return traits::reg_aliases.at(index); }
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
-    template <typename T> inline ConstantInt* size(T type) {
+    template <typename T> inline ConstantInt *size(T type) {
         return ConstantInt::get(getContext(), APInt(32, type->getType()->getScalarSizeInBits()));
     }
 
@@ -92,42 +92,41 @@ protected:
         iss::llvm::fp_impl::add_fp_functions_2_module(m, traits::FP_REGS_SIZE, traits::XLEN);
     }
 
-    inline Value* gen_choose(Value* cond, Value* trueVal, Value* falseVal, unsigned size) {
+    inline Value *gen_choose(Value *cond, Value *trueVal, Value *falseVal, unsigned size) {
         return super::gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
     }
 
-    std::tuple<continuation_e, BasicBlock*> gen_single_inst_behavior(virt_addr_t&, unsigned int&, BasicBlock*) override;
-
-    void gen_leave_behavior(BasicBlock* leave_blk) override;
+    std::tuple<continuation_e, BasicBlock *> gen_single_inst_behavior(virt_addr_t &, unsigned int &, BasicBlock *) override;
 
+    void gen_leave_behavior(BasicBlock *leave_blk) override;
     void gen_raise_trap(uint16_t trap_id, uint16_t cause);
-
     void gen_leave_trap(unsigned lvl);
-
     void gen_wait(unsigned type);
+    void gen_trap_behavior(BasicBlock *) override;
+    void gen_instr_epilogue(BasicBlock *bb);
 
-    void gen_trap_behavior(BasicBlock*) override;
-
-    void gen_trap_check(BasicBlock* bb);
-
-    inline Value* gen_reg_load(unsigned i, unsigned level = 0) {
+    inline Value *gen_reg_load(unsigned i, unsigned level = 0) {
         return this->builder.CreateLoad(this->get_typeptr(i), get_reg_ptr(i), false);
     }
 
     inline void gen_set_pc(virt_addr_t pc, unsigned reg_num) {
-        Value* next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val), this->get_type(traits::XLEN));
+        Value *next_pc_v = this->builder.CreateSExtOrTrunc(this->gen_const(traits::XLEN, pc.val),
+                                                           this->get_type(traits::XLEN));
         this->builder.CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
     }
 
     // some compile time constants
 
     using this_class = vm_impl<ARCH>;
-    using compile_func = std::tuple<continuation_e, BasicBlock*> (this_class::*)(virt_addr_t& pc, code_word_t instr, BasicBlock* bb);
-    template <unsigned W, typename U, typename S = typename std::make_signed<U>::type> inline S sext(U from) {
-        auto mask = (1ULL << W) - 1;
-        auto sign_mask = 1ULL << (W - 1);
+    using compile_func = std::tuple<continuation_e, BasicBlock *> (this_class::*)(virt_addr_t &pc,
+                                                                                  code_word_t instr,
+                                                                                  BasicBlock *bb);
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    }
+    }   
 
 private:
     /****************************************************************************
@@ -139,19 +138,18 @@ private:
         uint32_t mask;
         compile_func op;
     };
-    struct decoding_tree_node {
+    struct decoding_tree_node{
         std::vector<instruction_descriptor> instrs;
         std::vector<decoding_tree_node*> children;
         uint32_t submask = std::numeric_limits<uint32_t>::max();
         uint32_t value;
-        decoding_tree_node(uint32_t value)
-        : value(value) {}
+        decoding_tree_node(uint32_t value) : value(value){}
     };
 
-    decoding_tree_node* root{nullptr};
+    decoding_tree_node* root {nullptr};
 
     const std::array<instruction_descriptor, 87> instr_descr = {{
-        /* entries are: size, valid value, valid mask, function ptr */
+         /* entries are: size, valid value, valid mask, function ptr */
         /* instruction LUI, encoding '0b00000000000000000000000000110111' */
         {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
         /* instruction AUIPC, encoding '0b00000000000000000000000000010111' */
@@ -327,3649 +325,4274 @@ private:
         /* instruction DII, encoding '0b0000000000000000' */
         {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii},
     }};
-
+ 
     /* instruction definitions */
     /* instruction 0: LUI */
-    std::tuple<continuation_e, BasicBlock*> __lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("LUI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 0);
+    std::tuple<continuation_e, BasicBlock*> __lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint32_t imm = ((bit_sub<12, 20>(instr) << 12));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint32_t imm = ((bit_sub<12,20>(instr) << 12));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic =
-                fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("LUI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,0);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
-                this->builder.CreateStore(this->gen_const(32, (uint32_t)((int32_t)imm)), get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->gen_const(32,(uint32_t)((int32_t)imm)),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 0);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 0);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 1: AUIPC */
-    std::tuple<continuation_e, BasicBlock*> __auipc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("AUIPC_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 1);
+    std::tuple<continuation_e, BasicBlock*> __auipc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint32_t imm = ((bit_sub<12, 20>(instr) << 12));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint32_t imm = ((bit_sub<12,20>(instr) << 12));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("AUIPC_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,1);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
-                this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + (int32_t)imm)), get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->gen_const(32,(uint32_t)(PC+(int32_t)imm)),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 1);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 1);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 2: JAL */
-    std::tuple<continuation_e, BasicBlock*> __jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("JAL_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 2);
+    std::tuple<continuation_e, BasicBlock*> __jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint32_t imm =
-            ((bit_sub<12, 8>(instr) << 12) | (bit_sub<20, 1>(instr) << 11) | (bit_sub<21, 10>(instr) << 1) | (bit_sub<31, 1>(instr) << 20));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic =
-                fmt::format("{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("JAL_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,2);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                this->gen_raise_trap(0, 0);
-            } else {
-                if(rd != 0) {
-                    this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 4)), get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0);
+            }
+            else{
+                if(rd!=0) {
+                    this->builder.CreateStore(
+                         this->gen_const(32,(uint32_t)(PC+4)),
+                         get_reg_ptr(rd + traits::X0), false);
                 }
-                auto PC_val_v = (uint32_t)(PC + (int32_t)sext<21>(imm));
-                this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
-                this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+                auto PC_val_v = (uint32_t)(PC+(int32_t)sext<21>(imm));
+                this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
+                this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
             }
         }
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 2);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 2);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 3: JALR */
-    std::tuple<continuation_e, BasicBlock*> __jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("JALR_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 3);
+    std::tuple<continuation_e, BasicBlock*> __jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("JALR_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,3);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto addr_mask = this->gen_const(32, (uint32_t)-2);
-            auto new_pc = this->gen_ext(
-                (this->builder.CreateAnd((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                                  this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))),
-                                         this->gen_ext(addr_mask, 64, false))),
+        }
+        else{
+            auto addr_mask =this->gen_const(32,(uint32_t)- 2);
+            auto new_pc =this->gen_ext(
+                (this->builder.CreateAnd(
+                   (this->builder.CreateAdd(
+                      this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                      this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true))
+                   ),
+                   this->gen_ext(addr_mask, 64,false))
+                ),
                 32, true);
             auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
             auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
             auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
-            this->builder.CreateCondBr(
-                this->gen_ext(this->builder.CreateURem(new_pc, this->gen_const(32, static_cast<uint32_t>(traits::INSTR_ALIGNMENT))), 1),
-                bb_then, bb_else);
+            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateURem(
+               new_pc,
+               this->gen_const(32,static_cast<uint32_t>(traits::INSTR_ALIGNMENT)))
+            , 1), bb_then, bb_else);
             this->builder.SetInsertPoint(bb_then);
-            { this->gen_raise_trap(0, 0); }
+            {
+                this->gen_raise_trap(0, 0);
+            }
             this->builder.CreateBr(bb_merge);
             this->builder.SetInsertPoint(bb_else);
             {
-                if(rd != 0) {
-                    this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 4)), get_reg_ptr(rd + traits::X0), false);
+                if(rd!=0) {
+                    this->builder.CreateStore(
+                         this->gen_const(32,(uint32_t)(PC+4)),
+                         get_reg_ptr(rd + traits::X0), false);
                 }
                 auto PC_val_v = new_pc;
-                this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false);
-                this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+                this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false);                            
+                this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
             }
             this->builder.CreateBr(bb_merge);
             this->builder.SetInsertPoint(bb_merge);
         }
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 3);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 3);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 4: BEQ */
-    std::tuple<continuation_e, BasicBlock*> __beq(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("BEQ_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 4);
+    std::tuple<continuation_e, BasicBlock*> __beq(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("BEQ_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,4);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
+        }
+        else{
             auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
             auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + traits::X0, 0),
-                                                                              this->gen_reg_load(rs2 + traits::X0, 0)),
-                                                     1),
-                                       bb_then, bb_merge);
+            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ,
+               this->gen_reg_load(rs1+ traits::X0, 0),
+               this->gen_reg_load(rs2+ traits::X0, 0))
+            , 1), bb_then,  bb_merge);
             this->builder.SetInsertPoint(bb_then);
             {
-                if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                    this->gen_raise_trap(0, 0);
-                } else {
-                    auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
-                    this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
-                    this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+                if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0);
+                }
+                else{
+                    auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
+                    this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
+                    this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
                 }
             }
             this->builder.CreateBr(bb_merge);
             this->builder.SetInsertPoint(bb_merge);
         }
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 4);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 4);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 5: BNE */
-    std::tuple<continuation_e, BasicBlock*> __bne(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("BNE_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 5);
+    std::tuple<continuation_e, BasicBlock*> __bne(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("BNE_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,5);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
+        }
+        else{
             auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
             auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs1 + traits::X0, 0),
-                                                                              this->gen_reg_load(rs2 + traits::X0, 0)),
-                                                     1),
-                                       bb_then, bb_merge);
+            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE,
+               this->gen_reg_load(rs1+ traits::X0, 0),
+               this->gen_reg_load(rs2+ traits::X0, 0))
+            , 1), bb_then,  bb_merge);
             this->builder.SetInsertPoint(bb_then);
             {
-                if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                    this->gen_raise_trap(0, 0);
-                } else {
-                    auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
-                    this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
-                    this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+                if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0);
+                }
+                else{
+                    auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
+                    this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
+                    this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
                 }
             }
             this->builder.CreateBr(bb_merge);
             this->builder.SetInsertPoint(bb_merge);
         }
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 5);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 5);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 6: BLT */
-    std::tuple<continuation_e, BasicBlock*> __blt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("BLT_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 6);
+    std::tuple<continuation_e, BasicBlock*> __blt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("BLT_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,6);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
+        }
+        else{
             auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
             auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-            this->builder.CreateCondBr(
-                this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SLT,
-                                                       this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false),
-                                                       this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false)),
-                              1),
-                bb_then, bb_merge);
+            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SLT,
+               this->gen_ext(
+                   this->gen_reg_load(rs1+ traits::X0, 0),
+                   32, false),
+               this->gen_ext(
+                   this->gen_reg_load(rs2+ traits::X0, 0),
+                   32, false))
+            , 1), bb_then,  bb_merge);
             this->builder.SetInsertPoint(bb_then);
             {
-                if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                    this->gen_raise_trap(0, 0);
-                } else {
-                    auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
-                    this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
-                    this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+                if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0);
+                }
+                else{
+                    auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
+                    this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
+                    this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
                 }
             }
             this->builder.CreateBr(bb_merge);
             this->builder.SetInsertPoint(bb_merge);
         }
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 6);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 6);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 7: BGE */
-    std::tuple<continuation_e, BasicBlock*> __bge(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("BGE_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 7);
+    std::tuple<continuation_e, BasicBlock*> __bge(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("BGE_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,7);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
+        }
+        else{
             auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
             auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-            this->builder.CreateCondBr(
-                this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SGE,
-                                                       this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false),
-                                                       this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false)),
-                              1),
-                bb_then, bb_merge);
+            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_SGE,
+               this->gen_ext(
+                   this->gen_reg_load(rs1+ traits::X0, 0),
+                   32, false),
+               this->gen_ext(
+                   this->gen_reg_load(rs2+ traits::X0, 0),
+                   32, false))
+            , 1), bb_then,  bb_merge);
             this->builder.SetInsertPoint(bb_then);
             {
-                if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                    this->gen_raise_trap(0, 0);
-                } else {
-                    auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
-                    this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
-                    this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+                if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0);
+                }
+                else{
+                    auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
+                    this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
+                    this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
                 }
             }
             this->builder.CreateBr(bb_merge);
             this->builder.SetInsertPoint(bb_merge);
         }
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 7);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 7);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 8: BLTU */
-    std::tuple<continuation_e, BasicBlock*> __bltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("BLTU_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 8);
+    std::tuple<continuation_e, BasicBlock*> __bltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("BLTU_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,8);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
+        }
+        else{
             auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
             auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(rs1 + traits::X0, 0),
-                                                                              this->gen_reg_load(rs2 + traits::X0, 0)),
-                                                     1),
-                                       bb_then, bb_merge);
+            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_ULT,
+               this->gen_reg_load(rs1+ traits::X0, 0),
+               this->gen_reg_load(rs2+ traits::X0, 0))
+            , 1), bb_then,  bb_merge);
             this->builder.SetInsertPoint(bb_then);
             {
-                if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                    this->gen_raise_trap(0, 0);
-                } else {
-                    auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
-                    this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
-                    this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+                if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0);
+                }
+                else{
+                    auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
+                    this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
+                    this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
                 }
             }
             this->builder.CreateBr(bb_merge);
             this->builder.SetInsertPoint(bb_merge);
         }
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 8);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 8);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 9: BGEU */
-    std::tuple<continuation_e, BasicBlock*> __bgeu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("BGEU_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 9);
+    std::tuple<continuation_e, BasicBlock*> __bgeu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("BGEU_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,9);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
+        }
+        else{
             auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
             auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_UGE, this->gen_reg_load(rs1 + traits::X0, 0),
-                                                                              this->gen_reg_load(rs2 + traits::X0, 0)),
-                                                     1),
-                                       bb_then, bb_merge);
+            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_UGE,
+               this->gen_reg_load(rs1+ traits::X0, 0),
+               this->gen_reg_load(rs2+ traits::X0, 0))
+            , 1), bb_then,  bb_merge);
             this->builder.SetInsertPoint(bb_then);
             {
-                if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                    this->gen_raise_trap(0, 0);
-                } else {
-                    auto PC_val_v = (uint32_t)(PC + (int16_t)sext<13>(imm));
-                    this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
-                    this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+                if(imm%static_cast<uint32_t>(traits::INSTR_ALIGNMENT)){ this->gen_raise_trap(0, 0);
+                }
+                else{
+                    auto PC_val_v = (uint32_t)(PC+(int16_t)sext<13>(imm));
+                    this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
+                    this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
                 }
             }
             this->builder.CreateBr(bb_merge);
             this->builder.SetInsertPoint(bb_merge);
         }
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 9);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 9);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 10: LB */
-    std::tuple<continuation_e, BasicBlock*> __lb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("LB_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 10);
+    std::tuple<continuation_e, BasicBlock*> __lb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("LB_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,10);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto load_address =
-                this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                       this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))),
-                              32, true);
-            auto res = this->gen_ext(this->gen_read_mem(traits::MEM, load_address, 1), 8, false);
-            if(rd != 0) {
-                this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            auto load_address =this->gen_ext(
+                (this->builder.CreateAdd(
+                   this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                   this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true))
+                ),
+                32, true);
+            auto res =this->gen_ext(
+                this->gen_read_mem(traits::MEM, load_address, 1),
+                8, false);
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->gen_ext(
+                         res,
+                         32, true),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 10);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 10);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 11: LH */
-    std::tuple<continuation_e, BasicBlock*> __lh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("LH_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 11);
+    std::tuple<continuation_e, BasicBlock*> __lh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("LH_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,11);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto load_address =
-                this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                       this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))),
-                              32, true);
-            auto res = this->gen_ext(this->gen_read_mem(traits::MEM, load_address, 2), 16, false);
-            if(rd != 0) {
-                this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            auto load_address =this->gen_ext(
+                (this->builder.CreateAdd(
+                   this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                   this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true))
+                ),
+                32, true);
+            auto res =this->gen_ext(
+                this->gen_read_mem(traits::MEM, load_address, 2),
+                16, false);
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->gen_ext(
+                         res,
+                         32, true),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 11);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 11);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 12: LW */
-    std::tuple<continuation_e, BasicBlock*> __lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("LW_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 12);
+    std::tuple<continuation_e, BasicBlock*> __lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("LW_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,12);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto load_address =
-                this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                       this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))),
-                              32, true);
-            auto res = this->gen_ext(this->gen_read_mem(traits::MEM, load_address, 4), 32, false);
-            if(rd != 0) {
-                this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            auto load_address =this->gen_ext(
+                (this->builder.CreateAdd(
+                   this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                   this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true))
+                ),
+                32, true);
+            auto res =this->gen_ext(
+                this->gen_read_mem(traits::MEM, load_address, 4),
+                32, false);
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->gen_ext(
+                         res,
+                         32, true),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 12);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 12);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 13: LBU */
-    std::tuple<continuation_e, BasicBlock*> __lbu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("LBU_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 13);
+    std::tuple<continuation_e, BasicBlock*> __lbu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("LBU_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,13);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto load_address =
-                this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                       this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))),
-                              32, true);
-            auto res = this->gen_read_mem(traits::MEM, load_address, 1);
-            if(rd != 0) {
-                this->builder.CreateStore(this->gen_ext(res, 32, false), get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            auto load_address =this->gen_ext(
+                (this->builder.CreateAdd(
+                   this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                   this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true))
+                ),
+                32, true);
+            auto res =this->gen_read_mem(traits::MEM, load_address, 1);
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->gen_ext(
+                         res,
+                         32, false),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 13);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 13);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 14: LHU */
-    std::tuple<continuation_e, BasicBlock*> __lhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("LHU_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 14);
+    std::tuple<continuation_e, BasicBlock*> __lhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("LHU_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,14);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto load_address =
-                this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                       this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))),
-                              32, true);
-            auto res = this->gen_read_mem(traits::MEM, load_address, 2);
-            if(rd != 0) {
-                this->builder.CreateStore(this->gen_ext(res, 32, false), get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            auto load_address =this->gen_ext(
+                (this->builder.CreateAdd(
+                   this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                   this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true))
+                ),
+                32, true);
+            auto res =this->gen_read_mem(traits::MEM, load_address, 2);
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->gen_ext(
+                         res,
+                         32, false),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 14);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 14);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 15: SB */
-    std::tuple<continuation_e, BasicBlock*> __sb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SB_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 15);
+    std::tuple<continuation_e, BasicBlock*> __sb(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), fmt::arg("rs2", name(rs2)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SB_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,15);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto store_address =
-                this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                       this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))),
-                              32, true);
-            this->gen_write_mem(traits::MEM, store_address, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 8, false));
+        }
+        else{
+            auto store_address =this->gen_ext(
+                (this->builder.CreateAdd(
+                   this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                   this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true))
+                ),
+                32, true);
+            this->gen_write_mem(traits::MEM,
+            store_address,
+            this->gen_ext(
+                this->gen_reg_load(rs2+ traits::X0, 0),
+                8, false));
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 15);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 15);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 16: SH */
-    std::tuple<continuation_e, BasicBlock*> __sh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SH_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 16);
+    std::tuple<continuation_e, BasicBlock*> __sh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), fmt::arg("rs2", name(rs2)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SH_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,16);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto store_address =
-                this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                       this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))),
-                              32, true);
-            this->gen_write_mem(traits::MEM, store_address, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 16, false));
+        }
+        else{
+            auto store_address =this->gen_ext(
+                (this->builder.CreateAdd(
+                   this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                   this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true))
+                ),
+                32, true);
+            this->gen_write_mem(traits::MEM,
+            store_address,
+            this->gen_ext(
+                this->gen_reg_load(rs2+ traits::X0, 0),
+                16, false));
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 16);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 16);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 17: SW */
-    std::tuple<continuation_e, BasicBlock*> __sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SW_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 17);
+    std::tuple<continuation_e, BasicBlock*> __sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), fmt::arg("rs2", name(rs2)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SW_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,17);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs2>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto store_address =
-                this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                       this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))),
-                              32, true);
-            this->gen_write_mem(traits::MEM, store_address, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false));
+        }
+        else{
+            auto store_address =this->gen_ext(
+                (this->builder.CreateAdd(
+                   this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                   this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true))
+                ),
+                32, true);
+            this->gen_write_mem(traits::MEM,
+            store_address,
+            this->gen_ext(
+                this->gen_reg_load(rs2+ traits::X0, 0),
+                32, false));
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 17);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 17);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 18: ADDI */
-    std::tuple<continuation_e, BasicBlock*> __addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("ADDI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 18);
+    std::tuple<continuation_e, BasicBlock*> __addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("ADDI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,18);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                           this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 64, true))),
-                                  32, true),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(
+                         (this->builder.CreateAdd(
+                            this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                            this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 64,true))
+                         ),
+                         32, true),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 18);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 18);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 19: SLTI */
-    std::tuple<continuation_e, BasicBlock*> __slti(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SLTI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 19);
+    std::tuple<continuation_e, BasicBlock*> __slti(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SLTI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,19);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext(this->gen_choose((this->builder.CreateICmp(
-                                                       ICmpInst::ICMP_SLT, this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true),
-                                                       this->gen_ext(this->gen_const(16, (int16_t)sext<12>(imm)), 32, true))),
-                                                   this->gen_const(8, 1), this->gen_const(8, 0), 1),
-                                  32),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(this->gen_choose((this->builder.CreateICmp(ICmpInst::ICMP_SLT,
+                        this->gen_ext(
+                            this->gen_reg_load(rs1+ traits::X0, 0), 32,true),
+                        this->gen_ext(this->gen_const(16,(int16_t)sext<12>(imm)), 32,true))
+                     ),
+                     this->gen_const(8,1),
+                     this->gen_const(8,0),
+                     1), 32),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 19);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 19);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 20: SLTIU */
-    std::tuple<continuation_e, BasicBlock*> __sltiu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SLTIU_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 20);
+    std::tuple<continuation_e, BasicBlock*> __sltiu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SLTIU_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,20);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext(this->gen_choose((this->builder.CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(rs1 + traits::X0, 0),
-                                                                             this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm))))),
-                                                   this->gen_const(8, 1), this->gen_const(8, 0), 1),
-                                  32),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(this->gen_choose((this->builder.CreateICmp(ICmpInst::ICMP_ULT,
+                        this->gen_reg_load(rs1+ traits::X0, 0),
+                        this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm))))
+                     ),
+                     this->gen_const(8,1),
+                     this->gen_const(8,0),
+                     1), 32),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 20);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 20);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 21: XORI */
-    std::tuple<continuation_e, BasicBlock*> __xori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("XORI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 21);
+    std::tuple<continuation_e, BasicBlock*> __xori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("XORI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,21);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
-                this->builder.CreateStore(this->builder.CreateXor(this->gen_reg_load(rs1 + traits::X0, 0),
-                                                                  this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm)))),
-                                          get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->builder.CreateXor(
+                        this->gen_reg_load(rs1+ traits::X0, 0),
+                        this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm))))
+                     ,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 21);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 21);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 22: ORI */
-    std::tuple<continuation_e, BasicBlock*> __ori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("ORI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 22);
+    std::tuple<continuation_e, BasicBlock*> __ori(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("ORI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,22);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
-                this->builder.CreateStore(this->builder.CreateOr(this->gen_reg_load(rs1 + traits::X0, 0),
-                                                                 this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm)))),
-                                          get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->builder.CreateOr(
+                        this->gen_reg_load(rs1+ traits::X0, 0),
+                        this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm))))
+                     ,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 22);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 22);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 23: ANDI */
-    std::tuple<continuation_e, BasicBlock*> __andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("ANDI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 23);
+    std::tuple<continuation_e, BasicBlock*> __andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("ANDI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,23);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
-                this->builder.CreateStore(this->builder.CreateAnd(this->gen_reg_load(rs1 + traits::X0, 0),
-                                                                  this->gen_const(32, (uint32_t)((int16_t)sext<12>(imm)))),
-                                          get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->builder.CreateAnd(
+                        this->gen_reg_load(rs1+ traits::X0, 0),
+                        this->gen_const(32,(uint32_t)((int16_t)sext<12>(imm))))
+                     ,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 23);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 23);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 24: SLLI */
-    std::tuple<continuation_e, BasicBlock*> __slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SLLI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 24);
+    std::tuple<continuation_e, BasicBlock*> __slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t shamt = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t shamt = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SLLI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,24);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->builder.CreateShl(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_ext(this->gen_const(8, shamt), 32, false)),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->builder.CreateShl(
+                        this->gen_reg_load(rs1+ traits::X0, 0),
+                        this->gen_ext(this->gen_const(8,shamt), 32,false))
+                     ,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 24);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 24);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 25: SRLI */
-    std::tuple<continuation_e, BasicBlock*> __srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SRLI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 25);
+    std::tuple<continuation_e, BasicBlock*> __srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t shamt = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t shamt = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SRLI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,25);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->builder.CreateLShr(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_ext(this->gen_const(8, shamt), 32, false)),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->builder.CreateLShr(
+                        this->gen_reg_load(rs1+ traits::X0, 0),
+                        this->gen_ext(this->gen_const(8,shamt), 32,false))
+                     ,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 25);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 25);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 26: SRAI */
-    std::tuple<continuation_e, BasicBlock*> __srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SRAI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 26);
+    std::tuple<continuation_e, BasicBlock*> __srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t shamt = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t shamt = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SRAI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,26);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext((this->builder.CreateAShr(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true),
-                                                            this->gen_ext(this->gen_const(8, shamt), 32, false))),
-                                  32, true),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(
+                         (this->builder.CreateAShr(
+                            this->gen_ext(
+                                this->gen_reg_load(rs1+ traits::X0, 0), 32,true),
+                            this->gen_ext(this->gen_const(8,shamt), 32,false))
+                         ),
+                         32, true),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 26);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 26);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 27: ADD */
-    std::tuple<continuation_e, BasicBlock*> __add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("ADD_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 27);
+    std::tuple<continuation_e, BasicBlock*> __add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("ADD_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,27);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                           this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false))),
-                                  32, false),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(
+                         (this->builder.CreateAdd(
+                            this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                            this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false))
+                         ),
+                         32, false),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 27);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 27);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 28: SUB */
-    std::tuple<continuation_e, BasicBlock*> __sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SUB_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 28);
+    std::tuple<continuation_e, BasicBlock*> __sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SUB_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,28);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext((this->builder.CreateSub(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                           this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false))),
-                                  32, true),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(
+                         (this->builder.CreateSub(
+                            this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                            this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false))
+                         ),
+                         32, true),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 28);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 28);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 29: SLL */
-    std::tuple<continuation_e, BasicBlock*> __sll(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SLL_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 29);
+    std::tuple<continuation_e, BasicBlock*> __sll(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SLL_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,29);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext(
-                        this->builder.CreateShl(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                (this->builder.CreateAnd(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false),
-                                                                         this->gen_const(64, (static_cast<uint32_t>(traits::XLEN) - 1))))),
-                        32, false),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(this->builder.CreateShl(
+                        this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                        (this->builder.CreateAnd(
+                           this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false),
+                           this->gen_const(64,(static_cast<uint32_t>(traits::XLEN)-1)))
+                        ))
+                     , 32, false),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 29);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 29);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 30: SLT */
-    std::tuple<continuation_e, BasicBlock*> __slt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SLT_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 30);
+    std::tuple<continuation_e, BasicBlock*> __slt(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SLT_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,30);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext(this->gen_choose(this->builder.CreateICmp(
-                                                       ICmpInst::ICMP_SLT, this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true),
-                                                       this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, true)),
-                                                   this->gen_const(8, 1), this->gen_const(8, 0), 1),
-                                  32),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(this->gen_choose(this->builder.CreateICmp(ICmpInst::ICMP_SLT,
+                        this->gen_ext(
+                            this->gen_reg_load(rs1+ traits::X0, 0), 32,true),
+                        this->gen_ext(
+                            this->gen_reg_load(rs2+ traits::X0, 0), 32,true))
+                     ,
+                     this->gen_const(8,1),
+                     this->gen_const(8,0),
+                     1), 32),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 30);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 30);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 31: SLTU */
-    std::tuple<continuation_e, BasicBlock*> __sltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SLTU_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 31);
+    std::tuple<continuation_e, BasicBlock*> __sltu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SLTU_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,31);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext(this->gen_choose(this->builder.CreateICmp(ICmpInst::ICMP_ULT, this->gen_reg_load(rs1 + traits::X0, 0),
-                                                                            this->gen_reg_load(rs2 + traits::X0, 0)),
-                                                   this->gen_const(8, 1), this->gen_const(8, 0), 1),
-                                  32),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(this->gen_choose(this->builder.CreateICmp(ICmpInst::ICMP_ULT,
+                        this->gen_reg_load(rs1+ traits::X0, 0),
+                        this->gen_reg_load(rs2+ traits::X0, 0))
+                     ,
+                     this->gen_const(8,1),
+                     this->gen_const(8,0),
+                     1), 32),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 31);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 31);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 32: XOR */
-    std::tuple<continuation_e, BasicBlock*> __xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("XOR_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 32);
+    std::tuple<continuation_e, BasicBlock*> __xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("XOR_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,32);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->builder.CreateXor(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->builder.CreateXor(
+                        this->gen_reg_load(rs1+ traits::X0, 0),
+                        this->gen_reg_load(rs2+ traits::X0, 0))
+                     ,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 32);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 32);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 33: SRL */
-    std::tuple<continuation_e, BasicBlock*> __srl(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SRL_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 33);
+    std::tuple<continuation_e, BasicBlock*> __srl(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SRL_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,33);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext(
-                        this->builder.CreateLShr(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                 (this->builder.CreateAnd(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false),
-                                                                          this->gen_const(64, (static_cast<uint32_t>(traits::XLEN) - 1))))),
-                        32, false),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(this->builder.CreateLShr(
+                        this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                        (this->builder.CreateAnd(
+                           this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false),
+                           this->gen_const(64,(static_cast<uint32_t>(traits::XLEN)-1)))
+                        ))
+                     , 32, false),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 33);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 33);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 34: SRA */
-    std::tuple<continuation_e, BasicBlock*> __sra(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("SRA_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 34);
+    std::tuple<continuation_e, BasicBlock*> __sra(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("SRA_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,34);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext(
-                        (this->gen_ext(this->builder.CreateAShr(
-                                           this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true),
-                                           (this->builder.CreateAnd(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false),
-                                                                    this->gen_const(64, (static_cast<uint32_t>(traits::XLEN) - 1))))),
-                                       32, true)),
-                        32, true),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(
+                         (this->gen_ext(this->builder.CreateAShr(
+                            this->gen_ext(this->gen_ext(
+                                this->gen_reg_load(rs1+ traits::X0, 0), 32,true), 64,true),
+                            (this->builder.CreateAnd(
+                               this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false),
+                               this->gen_const(64,(static_cast<uint32_t>(traits::XLEN)-1)))
+                            ))
+                         , 32, true)),
+                         32, true),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 34);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 34);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 35: OR */
-    std::tuple<continuation_e, BasicBlock*> __or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("OR_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 35);
+    std::tuple<continuation_e, BasicBlock*> __or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("OR_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,35);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->builder.CreateOr(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->builder.CreateOr(
+                        this->gen_reg_load(rs1+ traits::X0, 0),
+                        this->gen_reg_load(rs2+ traits::X0, 0))
+                     ,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 35);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 35);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 36: AND */
-    std::tuple<continuation_e, BasicBlock*> __and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("AND_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 36);
+    std::tuple<continuation_e, BasicBlock*> __and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("AND_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,36);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        }
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->builder.CreateAnd(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->builder.CreateAnd(
+                        this->gen_reg_load(rs1+ traits::X0, 0),
+                        this->gen_reg_load(rs2+ traits::X0, 0))
+                     ,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 36);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 36);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 37: FENCE */
-    std::tuple<continuation_e, BasicBlock*> __fence(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("FENCE_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 37);
+    std::tuple<continuation_e, BasicBlock*> __fence(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t succ = ((bit_sub<20, 4>(instr)));
-        uint8_t pred = ((bit_sub<24, 4>(instr)));
-        uint8_t fm = ((bit_sub<28, 4>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t succ = ((bit_sub<20,4>(instr)));
+        uint8_t pred = ((bit_sub<24,4>(instr)));
+        uint8_t fm = ((bit_sub<28,4>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic =
-                fmt::format("{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), fmt::arg("pred", pred),
-                            fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"),
+                fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("FENCE_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,37);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        this->gen_write_mem(traits::FENCE, static_cast<uint32_t>(traits::fence), this->gen_const(8, (uint8_t)pred << 4 | succ));
+
+        /*generate behavior*/
+        this->gen_write_mem(traits::FENCE,
+        static_cast<uint32_t>(traits::fence),
+        this->gen_const(8,(uint8_t)pred<<4|succ));
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 37);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 37);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 38: ECALL */
-    std::tuple<continuation_e, BasicBlock*> __ecall(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("ECALL_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 38);
+    std::tuple<continuation_e, BasicBlock*> __ecall(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            // This disass is not yet implemented
+            //This disass is not yet implemented
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("ECALL_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,38);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         this->gen_raise_trap(0, 11);
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(TRAP, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 38);
+        auto returnValue = std::make_tuple(TRAP,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 38);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 39: EBREAK */
-    std::tuple<continuation_e, BasicBlock*> __ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("EBREAK_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 39);
+    std::tuple<continuation_e, BasicBlock*> __ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            // This disass is not yet implemented
+            //This disass is not yet implemented
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("EBREAK_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,39);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         this->gen_raise_trap(0, 3);
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(TRAP, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 39);
+        auto returnValue = std::make_tuple(TRAP,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 39);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 40: MRET */
-    std::tuple<continuation_e, BasicBlock*> __mret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("MRET_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 40);
+    std::tuple<continuation_e, BasicBlock*> __mret(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            // This disass is not yet implemented
+            //This disass is not yet implemented
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("MRET_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,40);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         this->gen_leave_trap(3);
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(TRAP, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 40);
+        auto returnValue = std::make_tuple(TRAP,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 40);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 41: WFI */
-    std::tuple<continuation_e, BasicBlock*> __wfi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("WFI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 41);
+    std::tuple<continuation_e, BasicBlock*> __wfi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            // This disass is not yet implemented
+            //This disass is not yet implemented
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("WFI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,41);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         this->gen_wait(1);
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 41);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 41);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 42: CSRRW */
-    std::tuple<continuation_e, BasicBlock*> __csrrw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("CSRRW_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 42);
+    std::tuple<continuation_e, BasicBlock*> __csrrw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("CSRRW_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,42);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto xrs1 = this->gen_reg_load(rs1 + traits::X0, 0);
-            if(rd != 0) {
-                auto xrd = this->gen_read_mem(traits::CSR, csr, 4);
-                this->gen_write_mem(traits::CSR, csr, xrs1);
-                this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false);
-            } else {
-                this->gen_write_mem(traits::CSR, csr, xrs1);
+        }
+        else{
+            auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0);
+            if(rd!=0){ auto xrd =this->gen_read_mem(traits::CSR, csr, 4);
+            this->gen_write_mem(traits::CSR,
+            csr,
+            xrs1);
+            this->builder.CreateStore(
+                 xrd,
+                 get_reg_ptr(rd + traits::X0), false);
+            }
+            else{
+                this->gen_write_mem(traits::CSR,
+                csr,
+                xrs1);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 42);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 42);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 43: CSRRS */
-    std::tuple<continuation_e, BasicBlock*> __csrrs(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("CSRRS_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 43);
+    std::tuple<continuation_e, BasicBlock*> __csrrs(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("CSRRS_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,43);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto xrd = this->gen_read_mem(traits::CSR, csr, 4);
-            auto xrs1 = this->gen_reg_load(rs1 + traits::X0, 0);
-            if(rs1 != 0) {
-                this->gen_write_mem(traits::CSR, csr, this->builder.CreateOr(xrd, xrs1));
+        }
+        else{
+            auto xrd =this->gen_read_mem(traits::CSR, csr, 4);
+            auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0);
+            if(rs1!=0) {
+                this->gen_write_mem(traits::CSR,
+                csr,
+                this->builder.CreateOr(
+                   xrd,
+                   xrs1)
+                );
             }
-            if(rd != 0) {
-                this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false);
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     xrd,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 43);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 43);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 44: CSRRC */
-    std::tuple<continuation_e, BasicBlock*> __csrrc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("CSRRC_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 44);
+    std::tuple<continuation_e, BasicBlock*> __csrrc(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("CSRRC_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,44);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto xrd = this->gen_read_mem(traits::CSR, csr, 4);
-            auto xrs1 = this->gen_reg_load(rs1 + traits::X0, 0);
-            if(rs1 != 0) {
-                this->gen_write_mem(traits::CSR, csr, this->builder.CreateAnd(xrd, this->builder.CreateNeg(xrs1)));
+        }
+        else{
+            auto xrd =this->gen_read_mem(traits::CSR, csr, 4);
+            auto xrs1 =this->gen_reg_load(rs1+ traits::X0, 0);
+            if(rs1!=0) {
+                this->gen_write_mem(traits::CSR,
+                csr,
+                this->builder.CreateAnd(
+                   xrd,
+                   this->builder.CreateNeg(xrs1))
+                );
             }
-            if(rd != 0) {
-                this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false);
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     xrd,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 44);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 44);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 45: CSRRWI */
-    std::tuple<continuation_e, BasicBlock*> __csrrwi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("CSRRWI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 45);
+    std::tuple<continuation_e, BasicBlock*> __csrrwi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t zimm = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t zimm = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("zimm", zimm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("CSRRWI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,45);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto xrd = this->gen_read_mem(traits::CSR, csr, 4);
-            this->gen_write_mem(traits::CSR, csr, this->gen_const(32, (uint32_t)zimm));
-            if(rd != 0) {
-                this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            auto xrd =this->gen_read_mem(traits::CSR, csr, 4);
+            this->gen_write_mem(traits::CSR,
+            csr,
+            this->gen_const(32,(uint32_t)zimm));
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     xrd,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 45);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 45);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 46: CSRRSI */
-    std::tuple<continuation_e, BasicBlock*> __csrrsi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("CSRRSI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 46);
+    std::tuple<continuation_e, BasicBlock*> __csrrsi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t zimm = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t zimm = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("zimm", zimm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("CSRRSI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,46);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto xrd = this->gen_read_mem(traits::CSR, csr, 4);
-            if(zimm != 0) {
-                this->gen_write_mem(traits::CSR, csr, this->builder.CreateOr(xrd, this->gen_const(32, (uint32_t)zimm)));
+        }
+        else{
+            auto xrd =this->gen_read_mem(traits::CSR, csr, 4);
+            if(zimm!=0) {
+                this->gen_write_mem(traits::CSR,
+                csr,
+                this->builder.CreateOr(
+                   xrd,
+                   this->gen_const(32,(uint32_t)zimm))
+                );
             }
-            if(rd != 0) {
-                this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false);
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     xrd,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 46);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 46);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 47: CSRRCI */
-    std::tuple<continuation_e, BasicBlock*> __csrrci(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("CSRRCI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 47);
+    std::tuple<continuation_e, BasicBlock*> __csrrci(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t zimm = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t zimm = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("zimm", zimm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("CSRRCI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,47);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto xrd = this->gen_read_mem(traits::CSR, csr, 4);
-            if(zimm != 0) {
-                this->gen_write_mem(traits::CSR, csr, this->builder.CreateAnd(xrd, this->gen_const(32, ~((uint32_t)zimm))));
+        }
+        else{
+            auto xrd =this->gen_read_mem(traits::CSR, csr, 4);
+            if(zimm!=0) {
+                this->gen_write_mem(traits::CSR,
+                csr,
+                this->builder.CreateAnd(
+                   xrd,
+                   this->gen_const(32,~ ((uint32_t)zimm)))
+                );
             }
-            if(rd != 0) {
-                this->builder.CreateStore(xrd, get_reg_ptr(rd + traits::X0), false);
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     xrd,
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 47);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 47);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 48: FENCE_I */
-    std::tuple<continuation_e, BasicBlock*> __fence_i(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("FENCE_I_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 48);
+    std::tuple<continuation_e, BasicBlock*> __fence_i(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("FENCE_I_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,48);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        this->gen_write_mem(traits::FENCE, static_cast<uint32_t>(traits::fencei), this->gen_const(16, imm));
-        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
 
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 48);
+        /*generate behavior*/
+        this->gen_write_mem(traits::FENCE,
+        static_cast<uint32_t>(traits::fencei),
+        this->gen_const(16,imm));
+        bb = this->leave_blk;
+        auto returnValue = std::make_tuple(FLUSH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 48);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 49: MUL */
-    std::tuple<continuation_e, BasicBlock*> __mul(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("MUL_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 49);
+    std::tuple<continuation_e, BasicBlock*> __mul(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("MUL_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,49);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto res = this->gen_ext(
+        }
+        else{
+            auto res =this->gen_ext(
                 (this->builder.CreateMul(
-                    this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true), 128, true),
-                    this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, true), 64, true), 128, true))),
+                   this->gen_ext(this->gen_ext(
+                       this->gen_ext(
+                           this->gen_reg_load(rs1+ traits::X0, 0), 32,true),
+                       64, true), 128,true),
+                   this->gen_ext(this->gen_ext(
+                       this->gen_ext(
+                           this->gen_reg_load(rs2+ traits::X0, 0), 32,true),
+                       64, true), 128,true))
+                ),
                 64, true);
-            if(rd != 0) {
-                this->builder.CreateStore(this->gen_ext(res, 32, true), get_reg_ptr(rd + traits::X0), false);
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->gen_ext(
+                         res,
+                         32, true),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 49);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 49);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 50: MULH */
-    std::tuple<continuation_e, BasicBlock*> __mulh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("MULH_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 50);
+    std::tuple<continuation_e, BasicBlock*> __mulh(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("MULH_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,50);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto res = this->gen_ext(
+        }
+        else{
+            auto res =this->gen_ext(
                 (this->builder.CreateMul(
-                    this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true), 128, true),
-                    this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, true), 64, true), 128, true))),
+                   this->gen_ext(this->gen_ext(
+                       this->gen_ext(
+                           this->gen_reg_load(rs1+ traits::X0, 0), 32,true),
+                       64, true), 128,true),
+                   this->gen_ext(this->gen_ext(
+                       this->gen_ext(
+                           this->gen_reg_load(rs2+ traits::X0, 0), 32,true),
+                       64, true), 128,true))
+                ),
                 64, true);
-            if(rd != 0) {
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext(
-                        (this->builder.CreateAShr(res, this->gen_ext(this->gen_const(32, static_cast<uint32_t>(traits::XLEN)), 64, false))),
-                        32, true),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(
+                         (this->builder.CreateAShr(
+                            res,
+                            this->gen_ext(this->gen_const(32,static_cast<uint32_t>(traits::XLEN)), 64,false))
+                         ),
+                         32, true),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 50);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 50);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 51: MULHSU */
-    std::tuple<continuation_e, BasicBlock*> __mulhsu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("MULHSU_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 51);
+    std::tuple<continuation_e, BasicBlock*> __mulhsu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("MULHSU_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,51);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto res = this->gen_ext(
+        }
+        else{
+            auto res =this->gen_ext(
                 (this->builder.CreateMul(
-                    this->gen_ext(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, true), 64, true), 128, true),
-                    this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), 128, false))),
+                   this->gen_ext(this->gen_ext(
+                       this->gen_ext(
+                           this->gen_reg_load(rs1+ traits::X0, 0), 32,true),
+                       64, true), 128,true),
+                   this->gen_ext(this->gen_ext(
+                       this->gen_reg_load(rs2+ traits::X0, 0),
+                       64, false), 128,false))
+                ),
                 64, true);
-            if(rd != 0) {
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext(
-                        (this->builder.CreateAShr(res, this->gen_ext(this->gen_const(32, static_cast<uint32_t>(traits::XLEN)), 64, false))),
-                        32, true),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(
+                         (this->builder.CreateAShr(
+                            res,
+                            this->gen_ext(this->gen_const(32,static_cast<uint32_t>(traits::XLEN)), 64,false))
+                         ),
+                         32, true),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 51);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 51);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 52: MULHU */
-    std::tuple<continuation_e, BasicBlock*> __mulhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("MULHU_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 52);
+    std::tuple<continuation_e, BasicBlock*> __mulhu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("MULHU_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,52);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto res = this->gen_ext(
-                (this->builder.CreateMul(this->gen_ext(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false), 128, false),
-                                         this->gen_ext(this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false), 128, false))),
+        }
+        else{
+            auto res =this->gen_ext(
+                (this->builder.CreateMul(
+                   this->gen_ext(this->gen_ext(
+                       this->gen_reg_load(rs1+ traits::X0, 0),
+                       64, false), 128,false),
+                   this->gen_ext(this->gen_ext(
+                       this->gen_reg_load(rs2+ traits::X0, 0),
+                       64, false), 128,false))
+                ),
                 64, false);
-            if(rd != 0) {
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext(
-                        (this->builder.CreateLShr(res, this->gen_ext(this->gen_const(32, static_cast<uint32_t>(traits::XLEN)), 64, false))),
-                        32, false),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_ext(
+                         (this->builder.CreateLShr(
+                            res,
+                            this->gen_ext(this->gen_const(32,static_cast<uint32_t>(traits::XLEN)), 64,false))
+                         ),
+                         32, false),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 52);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 52);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 53: DIV */
-    std::tuple<continuation_e, BasicBlock*> __div(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("DIV_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 53);
+    std::tuple<continuation_e, BasicBlock*> __div(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
+        bb->setName(fmt::format("DIV_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,53);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto dividend = this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false);
-            auto divisor = this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false);
-            if(rd != 0) {
+        }
+        else{
+            auto dividend =this->gen_ext(
+                this->gen_reg_load(rs1+ traits::X0, 0),
+                32, false);
+            auto divisor =this->gen_ext(
+                this->gen_reg_load(rs2+ traits::X0, 0),
+                32, false);
+            if(rd!=0){ auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
+            auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
+            auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
+            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE,
+               divisor,
+               this->gen_ext(this->gen_const(8,0), 32,false))
+            , 1), bb_then, bb_else);
+            this->builder.SetInsertPoint(bb_then);
+            {
+                auto MMIN =this->gen_const(32,((uint32_t)1)<<(static_cast<uint32_t>(traits::XLEN)-1));
                 auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
                 auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
                 auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
-                this->builder.CreateCondBr(
-                    this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, divisor, this->gen_ext(this->gen_const(8, 0), 32, false)), 1),
-                    bb_then, bb_else);
+                this->builder.CreateCondBr(this->gen_ext(this->builder.CreateAnd(
+                   this->builder.CreateICmp(ICmpInst::ICMP_EQ,
+                      this->gen_reg_load(rs1+ traits::X0, 0),
+                      MMIN)
+                   ,
+                   this->builder.CreateICmp(ICmpInst::ICMP_EQ,
+                      divisor,
+                      this->gen_ext(this->gen_const(8,- 1), 32,true))
+                   )
+                , 1), bb_then, bb_else);
                 this->builder.SetInsertPoint(bb_then);
                 {
-                    auto MMIN = this->gen_const(32, ((uint32_t)1) << (static_cast<uint32_t>(traits::XLEN) - 1));
-                    auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
-                    auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-                    auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
-                    this->builder.CreateCondBr(
-                        this->gen_ext(
-                            this->builder.CreateAnd(
-                                this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + traits::X0, 0), MMIN),
-                                this->builder.CreateICmp(ICmpInst::ICMP_EQ, divisor, this->gen_ext(this->gen_const(8, -1), 32, true))),
-                            1),
-                        bb_then, bb_else);
-                    this->builder.SetInsertPoint(bb_then);
-                    { this->builder.CreateStore(MMIN, get_reg_ptr(rd + traits::X0), false); }
-                    this->builder.CreateBr(bb_merge);
-                    this->builder.SetInsertPoint(bb_else);
-                    {
-                        this->builder.CreateStore(
-                            this->gen_ext((this->builder.CreateSDiv(this->gen_ext(dividend, 64, true), this->gen_ext(divisor, 64, true))),
-                                          32, true),
-                            get_reg_ptr(rd + traits::X0), false);
-                    }
-                    this->builder.CreateBr(bb_merge);
-                    this->builder.SetInsertPoint(bb_merge);
-                }
-                this->builder.CreateBr(bb_merge);
-                this->builder.SetInsertPoint(bb_else);
-                { this->builder.CreateStore(this->gen_const(32, (uint32_t)-1), get_reg_ptr(rd + traits::X0), false); }
-                this->builder.CreateBr(bb_merge);
-                this->builder.SetInsertPoint(bb_merge);
-            }
-        }
-        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 53);
-        this->builder.CreateBr(bb);
-        return returnValue;
-    }
-
-    /* instruction 54: DIVU */
-    std::tuple<continuation_e, BasicBlock*> __divu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("DIVU_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 54);
-        uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
-                this->core_ptr,
-                this->gen_const(64, pc.val),
-                this->builder.CreateGlobalStringPtr(mnemonic),
-            };
-            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
-        }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
-        this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, 2);
-        } else {
-            auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
-            auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-            auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
-            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2 + traits::X0, 0),
-                                                                              this->gen_ext(this->gen_const(8, 0), 32, false)),
-                                                     1),
-                                       bb_then, bb_else);
-            this->builder.SetInsertPoint(bb_then);
-            {
-                if(rd != 0) {
-                    this->builder.CreateStore(this->gen_ext((this->builder.CreateUDiv(this->gen_reg_load(rs1 + traits::X0, 0),
-                                                                                      this->gen_reg_load(rs2 + traits::X0, 0))),
-                                                            32, false),
-                                              get_reg_ptr(rd + traits::X0), false);
-                }
-            }
-            this->builder.CreateBr(bb_merge);
-            this->builder.SetInsertPoint(bb_else);
-            {
-                if(rd != 0) {
-                    this->builder.CreateStore(this->gen_const(32, (uint32_t)-1), get_reg_ptr(rd + traits::X0), false);
-                }
-            }
-            this->builder.CreateBr(bb_merge);
-            this->builder.SetInsertPoint(bb_merge);
-        }
-        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 54);
-        this->builder.CreateBr(bb);
-        return returnValue;
-    }
-
-    /* instruction 55: REM */
-    std::tuple<continuation_e, BasicBlock*> __rem(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("REM_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 55);
-        uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
-                this->core_ptr,
-                this->gen_const(64, pc.val),
-                this->builder.CreateGlobalStringPtr(mnemonic),
-            };
-            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
-        }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
-        this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, 2);
-        } else {
-            auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
-            auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-            auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
-            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2 + traits::X0, 0),
-                                                                              this->gen_ext(this->gen_const(8, 0), 32, false)),
-                                                     1),
-                                       bb_then, bb_else);
-            this->builder.SetInsertPoint(bb_then);
-            {
-                auto MMIN = this->gen_const(32, (uint32_t)1 << (static_cast<uint32_t>(traits::XLEN) - 1));
-                auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
-                auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-                auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
-                this->builder.CreateCondBr(
-                    this->gen_ext(
-                        this->builder.CreateAnd(this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + traits::X0, 0), MMIN),
-                                                this->builder.CreateICmp(ICmpInst::ICMP_EQ,
-                                                                         this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false),
-                                                                         this->gen_ext(this->gen_const(8, -1), 32, true))),
-                        1),
-                    bb_then, bb_else);
-                this->builder.SetInsertPoint(bb_then);
-                {
-                    if(rd != 0) {
-                        this->builder.CreateStore(this->gen_ext(this->gen_const(8, 0), 32), get_reg_ptr(rd + traits::X0), false);
-                    }
-                }
-                this->builder.CreateBr(bb_merge);
-                this->builder.SetInsertPoint(bb_else);
-                {
-                    if(rd != 0) {
-                        this->builder.CreateStore(
-                            this->gen_ext((this->builder.CreateSRem(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 32, false),
-                                                                    this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false))),
-                                          32, true),
-                            get_reg_ptr(rd + traits::X0), false);
-                    }
-                }
-                this->builder.CreateBr(bb_merge);
-                this->builder.SetInsertPoint(bb_merge);
-            }
-            this->builder.CreateBr(bb_merge);
-            this->builder.SetInsertPoint(bb_else);
-            {
-                if(rd != 0) {
-                    this->builder.CreateStore(this->gen_reg_load(rs1 + traits::X0, 0), get_reg_ptr(rd + traits::X0), false);
-                }
-            }
-            this->builder.CreateBr(bb_merge);
-            this->builder.SetInsertPoint(bb_merge);
-        }
-        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 55);
-        this->builder.CreateBr(bb);
-        return returnValue;
-    }
-
-    /* instruction 56: REMU */
-    std::tuple<continuation_e, BasicBlock*> __remu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("REMU_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 56);
-        uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
-                this->core_ptr,
-                this->gen_const(64, pc.val),
-                this->builder.CreateGlobalStringPtr(mnemonic),
-            };
-            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
-        }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 4;
-        this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, 2);
-        } else {
-            auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
-            auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-            auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
-            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs2 + traits::X0, 0),
-                                                                              this->gen_ext(this->gen_const(8, 0), 32, false)),
-                                                     1),
-                                       bb_then, bb_else);
-            this->builder.SetInsertPoint(bb_then);
-            {
-                if(rd != 0) {
                     this->builder.CreateStore(
-                        this->builder.CreateURem(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_reg_load(rs2 + traits::X0, 0)),
-                        get_reg_ptr(rd + traits::X0), false);
+                         MMIN,
+                         get_reg_ptr(rd + traits::X0), false);
                 }
+                this->builder.CreateBr(bb_merge);
+                this->builder.SetInsertPoint(bb_else);
+                {
+                    this->builder.CreateStore(
+                         this->gen_ext(
+                             (this->builder.CreateSDiv(
+                                this->gen_ext(dividend, 64,true),
+                                this->gen_ext(divisor, 64,true))
+                             ),
+                             32, true),
+                         get_reg_ptr(rd + traits::X0), false);
+                }
+                this->builder.CreateBr(bb_merge);
+                this->builder.SetInsertPoint(bb_merge);
             }
             this->builder.CreateBr(bb_merge);
             this->builder.SetInsertPoint(bb_else);
             {
-                if(rd != 0) {
-                    this->builder.CreateStore(this->gen_reg_load(rs1 + traits::X0, 0), get_reg_ptr(rd + traits::X0), false);
-                }
+                this->builder.CreateStore(
+                     this->gen_const(32,(uint32_t)- 1),
+                     get_reg_ptr(rd + traits::X0), false);
             }
             this->builder.CreateBr(bb_merge);
             this->builder.SetInsertPoint(bb_merge);
+            }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 56);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 53);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
-    /* instruction 57: C__ADDI4SPN */
-    std::tuple<continuation_e, BasicBlock*> __c__addi4spn(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__ADDI4SPN_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 57);
+    
+    /* instruction 54: DIVU */
+    std::tuple<continuation_e, BasicBlock*> __divu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<2, 3>(instr)));
-        uint16_t imm =
-            ((bit_sub<5, 1>(instr) << 3) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<7, 4>(instr) << 6) | (bit_sub<11, 2>(instr) << 4));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"), fmt::arg("rd", name(8 + rd)),
-                                        fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("DIVU_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,54);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
+            this->gen_raise_trap(0, 2);
+        }
+        else{
+            auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
+            auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
+            auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
+            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE,
+               this->gen_reg_load(rs2+ traits::X0, 0),
+               this->gen_ext(this->gen_const(8,0), 32,false))
+            , 1), bb_then, bb_else);
+            this->builder.SetInsertPoint(bb_then);
+            {
+                if(rd!=0) {
+                    this->builder.CreateStore(
+                         this->gen_ext(
+                             (this->builder.CreateUDiv(
+                                this->gen_reg_load(rs1+ traits::X0, 0),
+                                this->gen_reg_load(rs2+ traits::X0, 0))
+                             ),
+                             32, false),
+                         get_reg_ptr(rd + traits::X0), false);
+                }
+            }
+            this->builder.CreateBr(bb_merge);
+            this->builder.SetInsertPoint(bb_else);
+            {
+                if(rd!=0) {
+                    this->builder.CreateStore(
+                         this->gen_const(32,(uint32_t)- 1),
+                         get_reg_ptr(rd + traits::X0), false);
+                }
+            }
+            this->builder.CreateBr(bb_merge);
+            this->builder.SetInsertPoint(bb_merge);
+        }
+        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 54);
+        this->builder.CreateBr(bb);
+    	return returnValue;        
+    }
+    
+    /* instruction 55: REM */
+    std::tuple<continuation_e, BasicBlock*> __rem(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        uint64_t PC = pc.val;
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
+                this->core_ptr,
+                this->gen_const(64, pc.val),
+                this->builder.CreateGlobalStringPtr(mnemonic),
+            };
+            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
+        }
+        bb->setName(fmt::format("REM_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,55);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
+        this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
+            this->gen_raise_trap(0, 2);
+        }
+        else{
+            auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
+            auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
+            auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
+            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE,
+               this->gen_reg_load(rs2+ traits::X0, 0),
+               this->gen_ext(this->gen_const(8,0), 32,false))
+            , 1), bb_then, bb_else);
+            this->builder.SetInsertPoint(bb_then);
+            {
+                auto MMIN =this->gen_const(32,(uint32_t)1<<(static_cast<uint32_t>(traits::XLEN)-1));
+                auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
+                auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
+                auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
+                this->builder.CreateCondBr(this->gen_ext(this->builder.CreateAnd(
+                   this->builder.CreateICmp(ICmpInst::ICMP_EQ,
+                      this->gen_reg_load(rs1+ traits::X0, 0),
+                      MMIN)
+                   ,
+                   this->builder.CreateICmp(ICmpInst::ICMP_EQ,
+                      this->gen_ext(
+                          this->gen_reg_load(rs2+ traits::X0, 0),
+                          32, false),
+                      this->gen_ext(this->gen_const(8,- 1), 32,true))
+                   )
+                , 1), bb_then, bb_else);
+                this->builder.SetInsertPoint(bb_then);
+                {
+                    if(rd!=0) {
+                        this->builder.CreateStore(
+                             this->gen_ext(this->gen_const(8,0), 32),
+                             get_reg_ptr(rd + traits::X0), false);
+                    }
+                }
+                this->builder.CreateBr(bb_merge);
+                this->builder.SetInsertPoint(bb_else);
+                {
+                    if(rd!=0) {
+                        this->builder.CreateStore(
+                             this->gen_ext(
+                                 (this->builder.CreateSRem(
+                                    this->gen_ext(
+                                        this->gen_reg_load(rs1+ traits::X0, 0),
+                                        32, false),
+                                    this->gen_ext(
+                                        this->gen_reg_load(rs2+ traits::X0, 0),
+                                        32, false))
+                                 ),
+                                 32, true),
+                             get_reg_ptr(rd + traits::X0), false);
+                    }
+                }
+                this->builder.CreateBr(bb_merge);
+                this->builder.SetInsertPoint(bb_merge);
+            }
+            this->builder.CreateBr(bb_merge);
+            this->builder.SetInsertPoint(bb_else);
+            {
+                if(rd!=0) {
+                    this->builder.CreateStore(
+                         this->gen_reg_load(rs1+ traits::X0, 0),
+                         get_reg_ptr(rd + traits::X0), false);
+                }
+            }
+            this->builder.CreateBr(bb_merge);
+            this->builder.SetInsertPoint(bb_merge);
+        }
+        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 55);
+        this->builder.CreateBr(bb);
+    	return returnValue;        
+    }
+    
+    /* instruction 56: REMU */
+    std::tuple<continuation_e, BasicBlock*> __remu(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        uint64_t PC = pc.val;
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
+                this->core_ptr,
+                this->gen_const(64, pc.val),
+                this->builder.CreateGlobalStringPtr(mnemonic),
+            };
+            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
+        }
+        bb->setName(fmt::format("REMU_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,56);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 4;
+        this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rs1>=static_cast<uint32_t>(traits::RFS)||rs2>=static_cast<uint32_t>(traits::RFS)) {
+            this->gen_raise_trap(0, 2);
+        }
+        else{
+            auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
+            auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
+            auto bb_else = BasicBlock::Create(this->mod->getContext(), "bb_else", this->func, bb_merge);
+            this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE,
+               this->gen_reg_load(rs2+ traits::X0, 0),
+               this->gen_ext(this->gen_const(8,0), 32,false))
+            , 1), bb_then, bb_else);
+            this->builder.SetInsertPoint(bb_then);
+            {
+                if(rd!=0) {
+                    this->builder.CreateStore(
+                         this->builder.CreateURem(
+                            this->gen_reg_load(rs1+ traits::X0, 0),
+                            this->gen_reg_load(rs2+ traits::X0, 0))
+                         ,
+                         get_reg_ptr(rd + traits::X0), false);
+                }
+            }
+            this->builder.CreateBr(bb_merge);
+            this->builder.SetInsertPoint(bb_else);
+            {
+                if(rd!=0) {
+                    this->builder.CreateStore(
+                         this->gen_reg_load(rs1+ traits::X0, 0),
+                         get_reg_ptr(rd + traits::X0), false);
+                }
+            }
+            this->builder.CreateBr(bb_merge);
+            this->builder.SetInsertPoint(bb_merge);
+        }
+        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 56);
+        this->builder.CreateBr(bb);
+    	return returnValue;        
+    }
+    
+    /* instruction 57: C__ADDI4SPN */
+    std::tuple<continuation_e, BasicBlock*> __c__addi4spn(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        uint64_t PC = pc.val;
+        uint8_t rd = ((bit_sub<2,3>(instr)));
+        uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
+                this->core_ptr,
+                this->gen_const(64, pc.val),
+                this->builder.CreateGlobalStringPtr(mnemonic),
+            };
+            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
+        }
+        bb->setName(fmt::format("C__ADDI4SPN_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,57);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
+        this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         if(imm) {
             this->builder.CreateStore(
-                this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false),
-                                                       this->gen_ext(this->gen_const(16, imm), 64, false))),
-                              32, false),
-                get_reg_ptr(rd + 8 + traits::X0), false);
-        } else {
+                 this->gen_ext(
+                     (this->builder.CreateAdd(
+                        this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false),
+                        this->gen_ext(this->gen_const(16,imm), 64,false))
+                     ),
+                     32, false),
+                 get_reg_ptr(rd+8 + traits::X0), false);
+        }
+        else{
             this->gen_raise_trap(0, 2);
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 57);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 57);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 58: C__LW */
-    std::tuple<continuation_e, BasicBlock*> __c__lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__LW_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 58);
+    std::tuple<continuation_e, BasicBlock*> __c__lw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<2, 3>(instr)));
-        uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<2,3>(instr)));
+        uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"),
-                                        fmt::arg("rd", name(8 + rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__LW_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,58);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 64, false),
-                                                           this->gen_ext(this->gen_const(8, uimm), 64, false))),
-                                  32, false);
-        this->builder.CreateStore(this->gen_ext(this->gen_ext(this->gen_read_mem(traits::MEM, offs, 4), 32, false), 32, true),
-                                  get_reg_ptr(rd + 8 + traits::X0), false);
+
+        /*generate behavior*/
+        auto offs =this->gen_ext(
+            (this->builder.CreateAdd(
+               this->gen_ext(this->gen_reg_load(rs1+8+ traits::X0, 0), 64,false),
+               this->gen_ext(this->gen_const(8,uimm), 64,false))
+            ),
+            32, false);
+        this->builder.CreateStore(
+             this->gen_ext(
+                 this->gen_ext(
+                     this->gen_read_mem(traits::MEM, offs, 4),
+                     32, false),
+                 32, true),
+             get_reg_ptr(rd+8 + traits::X0), false);
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 58);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 58);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 59: C__SW */
-    std::tuple<continuation_e, BasicBlock*> __c__sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__SW_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 59);
+    std::tuple<continuation_e, BasicBlock*> __c__sw(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 3>(instr)));
-        uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+        uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"),
-                                        fmt::arg("rs2", name(8 + rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"),
+                fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__SW_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,59);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 64, false),
-                                                           this->gen_ext(this->gen_const(8, uimm), 64, false))),
-                                  32, false);
-        this->gen_write_mem(traits::MEM, offs, this->gen_ext(this->gen_reg_load(rs2 + 8 + traits::X0, 0), 32, false));
+
+        /*generate behavior*/
+        auto offs =this->gen_ext(
+            (this->builder.CreateAdd(
+               this->gen_ext(this->gen_reg_load(rs1+8+ traits::X0, 0), 64,false),
+               this->gen_ext(this->gen_const(8,uimm), 64,false))
+            ),
+            32, false);
+        this->gen_write_mem(traits::MEM,
+        offs,
+        this->gen_ext(
+            this->gen_reg_load(rs2+8+ traits::X0, 0),
+            32, false));
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 59);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 59);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 60: C__ADDI */
-    std::tuple<continuation_e, BasicBlock*> __c__addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__ADDI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 60);
+    std::tuple<continuation_e, BasicBlock*> __c__addi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__ADDI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,60);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rs1 != 0) {
+        }
+        else{
+            if(rs1!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rs1 + traits::X0, 0), 64, false),
-                                                           this->gen_ext(this->gen_const(8, (int8_t)sext<6>(imm)), 64, true))),
-                                  32, true),
-                    get_reg_ptr(rs1 + traits::X0), false);
+                     this->gen_ext(
+                         (this->builder.CreateAdd(
+                            this->gen_ext(this->gen_reg_load(rs1+ traits::X0, 0), 64,false),
+                            this->gen_ext(this->gen_const(8,(int8_t)sext<6>(imm)), 64,true))
+                         ),
+                         32, true),
+                     get_reg_ptr(rs1 + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 60);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 60);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 61: C__NOP */
-    std::tuple<continuation_e, BasicBlock*> __c__nop(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__NOP_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 61);
+    std::tuple<continuation_e, BasicBlock*> __c__nop(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t nzimm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
-        if(this->disass_enabled) {
+        uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            // This disass is not yet implemented
+            //This disass is not yet implemented
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__NOP_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,61);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 61);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 61);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 62: C__JAL */
-    std::tuple<continuation_e, BasicBlock*> __c__jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__JAL_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 62);
+    std::tuple<continuation_e, BasicBlock*> __c__jal(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) |
-             (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"),
+                fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__JAL_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,62);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 2)), get_reg_ptr(1 + traits::X0), false);
-        auto PC_val_v = (uint32_t)(PC + (int16_t)sext<12>(imm));
-        this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
-        this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+
+        /*generate behavior*/
+        this->builder.CreateStore(
+             this->gen_const(32,(uint32_t)(PC+2)),
+             get_reg_ptr(1 + traits::X0), false);
+        auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm));
+        this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
+        this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 62);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 62);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 63: C__LI */
-    std::tuple<continuation_e, BasicBlock*> __c__li(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__LI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 63);
+    std::tuple<continuation_e, BasicBlock*> __c__li(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__LI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,63);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
-                this->builder.CreateStore(this->gen_const(32, (uint32_t)((int8_t)sext<6>(imm))), get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->gen_const(32,(uint32_t)((int8_t)sext<6>(imm))),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 63);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 63);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 64: C__LUI */
-    std::tuple<continuation_e, BasicBlock*> __c__lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__LUI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 64);
+    std::tuple<continuation_e, BasicBlock*> __c__lui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint32_t imm = ((bit_sub<2, 5>(instr) << 12) | (bit_sub<12, 1>(instr) << 17));
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__LUI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,64);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(imm == 0 || rd >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(imm==0||rd>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
         }
-        if(rd != 0) {
-            this->builder.CreateStore(this->gen_const(32, (uint32_t)((int32_t)sext<18>(imm))), get_reg_ptr(rd + traits::X0), false);
+        if(rd!=0) {
+            this->builder.CreateStore(
+                 this->gen_const(32,(uint32_t)((int32_t)sext<18>(imm))),
+                 get_reg_ptr(rd + traits::X0), false);
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 64);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 64);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 65: C__ADDI16SP */
-    std::tuple<continuation_e, BasicBlock*> __c__addi16sp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__ADDI16SP_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 65);
+    std::tuple<continuation_e, BasicBlock*> __c__addi16sp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t nzimm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 7) | (bit_sub<5, 1>(instr) << 6) |
-                          (bit_sub<6, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 9));
-        if(this->disass_enabled) {
+        uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"), fmt::arg("nzimm", nzimm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"),
+                fmt::arg("nzimm", nzimm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__ADDI16SP_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,65);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         if(nzimm) {
             this->builder.CreateStore(
-                this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false),
-                                                       this->gen_ext(this->gen_const(16, (int16_t)sext<10>(nzimm)), 64, true))),
-                              32, true),
-                get_reg_ptr(2 + traits::X0), false);
-        } else {
+                 this->gen_ext(
+                     (this->builder.CreateAdd(
+                        this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false),
+                        this->gen_ext(this->gen_const(16,(int16_t)sext<10>(nzimm)), 64,true))
+                     ),
+                     32, true),
+                 get_reg_ptr(2 + traits::X0), false);
+        }
+        else{
             this->gen_raise_trap(0, 2);
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 65);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 65);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 66: __reserved_clui */
-    std::tuple<continuation_e, BasicBlock*> ____reserved_clui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("__reserved_clui_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 66);
+    std::tuple<continuation_e, BasicBlock*> ____reserved_clui(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            // This disass is not yet implemented
+            //This disass is not yet implemented
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("__reserved_clui_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,66);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         this->gen_raise_trap(0, 2);
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 66);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 66);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 67: C__SRLI */
-    std::tuple<continuation_e, BasicBlock*> __c__srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__SRLI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 67);
+    std::tuple<continuation_e, BasicBlock*> __c__srli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t shamt = ((bit_sub<2, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t shamt = ((bit_sub<2,5>(instr)));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"), fmt::arg("rs1", name(8 + rs1)),
-                                        fmt::arg("shamt", shamt));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__SRLI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,67);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         this->builder.CreateStore(
-            this->builder.CreateLShr(this->gen_reg_load(rs1 + 8 + traits::X0, 0), this->gen_ext(this->gen_const(8, shamt), 32, false)),
-            get_reg_ptr(rs1 + 8 + traits::X0), false);
+             this->builder.CreateLShr(
+                this->gen_reg_load(rs1+8+ traits::X0, 0),
+                this->gen_ext(this->gen_const(8,shamt), 32,false))
+             ,
+             get_reg_ptr(rs1+8 + traits::X0), false);
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 67);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 67);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 68: C__SRAI */
-    std::tuple<continuation_e, BasicBlock*> __c__srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__SRAI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 68);
+    std::tuple<continuation_e, BasicBlock*> __c__srai(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t shamt = ((bit_sub<2, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t shamt = ((bit_sub<2,5>(instr)));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"), fmt::arg("rs1", name(8 + rs1)),
-                                        fmt::arg("shamt", shamt));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__SRAI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,68);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(shamt) {
-            this->builder.CreateStore(
-                this->gen_ext((this->builder.CreateAShr((this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 32, false)),
-                                                        this->gen_ext(this->gen_const(8, shamt), 32, false))),
-                              32, true),
-                get_reg_ptr(rs1 + 8 + traits::X0), false);
-        } else {
-            if(static_cast<uint32_t>(traits::XLEN) == 128) {
-                this->builder.CreateStore(
-                    this->gen_ext((this->builder.CreateAShr((this->gen_ext(this->gen_reg_load(rs1 + 8 + traits::X0, 0), 32, false)),
-                                                            this->gen_ext(this->gen_const(8, 64), 32, false))),
-                                  32, true),
-                    get_reg_ptr(rs1 + 8 + traits::X0), false);
+
+        /*generate behavior*/
+        if(shamt){ this->builder.CreateStore(
+             this->gen_ext(
+                 (this->builder.CreateAShr(
+                    (this->gen_ext(
+                        this->gen_reg_load(rs1+8+ traits::X0, 0),
+                        32, false)),
+                    this->gen_ext(this->gen_const(8,shamt), 32,false))
+                 ),
+                 32, true),
+             get_reg_ptr(rs1+8 + traits::X0), false);
+        }
+        else{
+            if(static_cast<uint32_t>(traits::XLEN)==128){ this->builder.CreateStore(
+                 this->gen_ext(
+                     (this->builder.CreateAShr(
+                        (this->gen_ext(
+                            this->gen_reg_load(rs1+8+ traits::X0, 0),
+                            32, false)),
+                        this->gen_ext(this->gen_const(8,64), 32,false))
+                     ),
+                     32, true),
+                 get_reg_ptr(rs1+8 + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 68);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 68);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 69: C__ANDI */
-    std::tuple<continuation_e, BasicBlock*> __c__andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__ANDI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 69);
+    std::tuple<continuation_e, BasicBlock*> __c__andi(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"), fmt::arg("rs1", name(8 + rs1)),
-                                        fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__ANDI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,69);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         this->builder.CreateStore(
-            this->gen_ext((this->builder.CreateAnd(this->gen_reg_load(rs1 + 8 + traits::X0, 0),
-                                                   this->gen_ext(this->gen_const(8, (int8_t)sext<6>(imm)), 32, true))),
-                          32, true),
-            get_reg_ptr(rs1 + 8 + traits::X0), false);
+             this->gen_ext(
+                 (this->builder.CreateAnd(
+                    this->gen_reg_load(rs1+8+ traits::X0, 0),
+                    this->gen_ext(this->gen_const(8,(int8_t)sext<6>(imm)), 32,true))
+                 ),
+                 32, true),
+             get_reg_ptr(rs1+8 + traits::X0), false);
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 69);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 69);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 70: C__SUB */
-    std::tuple<continuation_e, BasicBlock*> __c__sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__SUB_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 70);
+    std::tuple<continuation_e, BasicBlock*> __c__sub(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 3>(instr)));
-        uint8_t rd = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+        uint8_t rd = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"), fmt::arg("rd", name(8 + rd)),
-                                        fmt::arg("rs2", name(8 + rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__SUB_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,70);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         this->builder.CreateStore(
-            this->gen_ext((this->builder.CreateSub(this->gen_ext(this->gen_reg_load(rd + 8 + traits::X0, 0), 64, false),
-                                                   this->gen_ext(this->gen_reg_load(rs2 + 8 + traits::X0, 0), 64, false))),
-                          32, true),
-            get_reg_ptr(rd + 8 + traits::X0), false);
+             this->gen_ext(
+                 (this->builder.CreateSub(
+                    this->gen_ext(this->gen_reg_load(rd+8+ traits::X0, 0), 64,false),
+                    this->gen_ext(this->gen_reg_load(rs2+8+ traits::X0, 0), 64,false))
+                 ),
+                 32, true),
+             get_reg_ptr(rd+8 + traits::X0), false);
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 70);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 70);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 71: C__XOR */
-    std::tuple<continuation_e, BasicBlock*> __c__xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__XOR_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 71);
+    std::tuple<continuation_e, BasicBlock*> __c__xor(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 3>(instr)));
-        uint8_t rd = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+        uint8_t rd = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"), fmt::arg("rd", name(8 + rd)),
-                                        fmt::arg("rs2", name(8 + rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__XOR_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,71);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         this->builder.CreateStore(
-            this->builder.CreateXor(this->gen_reg_load(rd + 8 + traits::X0, 0), this->gen_reg_load(rs2 + 8 + traits::X0, 0)),
-            get_reg_ptr(rd + 8 + traits::X0), false);
+             this->builder.CreateXor(
+                this->gen_reg_load(rd+8+ traits::X0, 0),
+                this->gen_reg_load(rs2+8+ traits::X0, 0))
+             ,
+             get_reg_ptr(rd+8 + traits::X0), false);
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 71);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 71);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 72: C__OR */
-    std::tuple<continuation_e, BasicBlock*> __c__or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__OR_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 72);
+    std::tuple<continuation_e, BasicBlock*> __c__or(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 3>(instr)));
-        uint8_t rd = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+        uint8_t rd = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"), fmt::arg("rd", name(8 + rd)),
-                                        fmt::arg("rs2", name(8 + rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__OR_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,72);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         this->builder.CreateStore(
-            this->builder.CreateOr(this->gen_reg_load(rd + 8 + traits::X0, 0), this->gen_reg_load(rs2 + 8 + traits::X0, 0)),
-            get_reg_ptr(rd + 8 + traits::X0), false);
+             this->builder.CreateOr(
+                this->gen_reg_load(rd+8+ traits::X0, 0),
+                this->gen_reg_load(rs2+8+ traits::X0, 0))
+             ,
+             get_reg_ptr(rd+8 + traits::X0), false);
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 72);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 72);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 73: C__AND */
-    std::tuple<continuation_e, BasicBlock*> __c__and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__AND_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 73);
+    std::tuple<continuation_e, BasicBlock*> __c__and(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 3>(instr)));
-        uint8_t rd = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+        uint8_t rd = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"), fmt::arg("rd", name(8 + rd)),
-                                        fmt::arg("rs2", name(8 + rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__AND_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,73);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         this->builder.CreateStore(
-            this->builder.CreateAnd(this->gen_reg_load(rd + 8 + traits::X0, 0), this->gen_reg_load(rs2 + 8 + traits::X0, 0)),
-            get_reg_ptr(rd + 8 + traits::X0), false);
+             this->builder.CreateAnd(
+                this->gen_reg_load(rd+8+ traits::X0, 0),
+                this->gen_reg_load(rs2+8+ traits::X0, 0))
+             ,
+             get_reg_ptr(rd+8 + traits::X0), false);
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 73);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 73);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 74: C__J */
-    std::tuple<continuation_e, BasicBlock*> __c__j(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__J_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 74);
+    std::tuple<continuation_e, BasicBlock*> __c__j(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) |
-             (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"), fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"),
+                fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__J_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,74);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        auto PC_val_v = (uint32_t)(PC + (int16_t)sext<12>(imm));
-        this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
-        this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+
+        /*generate behavior*/
+        auto PC_val_v = (uint32_t)(PC+(int16_t)sext<12>(imm));
+        this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
+        this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 74);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 74);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 75: C__BEQZ */
-    std::tuple<continuation_e, BasicBlock*> __c__beqz(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__BEQZ_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 75);
+    std::tuple<continuation_e, BasicBlock*> __c__beqz(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) |
-                        (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"), fmt::arg("rs1", name(8 + rs1)),
-                                        fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__BEQZ_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,75);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
         auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-        this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ, this->gen_reg_load(rs1 + 8 + traits::X0, 0),
-                                                                          this->gen_ext(this->gen_const(8, 0), 32, false)),
-                                                 1),
-                                   bb_then, bb_merge);
+        this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_EQ,
+           this->gen_reg_load(rs1+8+ traits::X0, 0),
+           this->gen_ext(this->gen_const(8,0), 32,false))
+        , 1), bb_then,  bb_merge);
         this->builder.SetInsertPoint(bb_then);
         {
-            auto PC_val_v = (uint32_t)(PC + (int16_t)sext<9>(imm));
-            this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
-            this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+            auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm));
+            this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
+            this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
         }
         this->builder.CreateBr(bb_merge);
         this->builder.SetInsertPoint(bb_merge);
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 75);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 75);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 76: C__BNEZ */
-    std::tuple<continuation_e, BasicBlock*> __c__bnez(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__BNEZ_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 76);
+    std::tuple<continuation_e, BasicBlock*> __c__bnez(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) |
-                        (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"), fmt::arg("rs1", name(8 + rs1)),
-                                        fmt::arg("imm", imm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__BNEZ_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,76);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
         auto bb_merge = BasicBlock::Create(this->mod->getContext(), "bb_merge", this->func, this->leave_blk);
         auto bb_then = BasicBlock::Create(this->mod->getContext(), "bb_then", this->func, bb_merge);
-        this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE, this->gen_reg_load(rs1 + 8 + traits::X0, 0),
-                                                                          this->gen_ext(this->gen_const(8, 0), 32, false)),
-                                                 1),
-                                   bb_then, bb_merge);
+        this->builder.CreateCondBr(this->gen_ext(this->builder.CreateICmp(ICmpInst::ICMP_NE,
+           this->gen_reg_load(rs1+8+ traits::X0, 0),
+           this->gen_ext(this->gen_const(8,0), 32,false))
+        , 1), bb_then,  bb_merge);
         this->builder.SetInsertPoint(bb_then);
         {
-            auto PC_val_v = (uint32_t)(PC + (int16_t)sext<9>(imm));
-            this->builder.CreateStore(this->gen_const(32, PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
-            this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
+            auto PC_val_v = (uint32_t)(PC+(int16_t)sext<9>(imm));
+            this->builder.CreateStore(this->gen_const(32,PC_val_v), get_reg_ptr(traits::NEXT_PC), false);
+            this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
         }
         this->builder.CreateBr(bb_merge);
         this->builder.SetInsertPoint(bb_merge);
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 76);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 76);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 77: C__SLLI */
-    std::tuple<continuation_e, BasicBlock*> __c__slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__SLLI_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 77);
+    std::tuple<continuation_e, BasicBlock*> __c__slli(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t nzuimm = ((bit_sub<2, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t nzuimm = ((bit_sub<2,5>(instr)));
+        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("nzuimm", nzuimm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__SLLI_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,77);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs1>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            if(rs1 != 0) {
+        }
+        else{
+            if(rs1!=0) {
                 this->builder.CreateStore(
-                    this->builder.CreateShl(this->gen_reg_load(rs1 + traits::X0, 0), this->gen_ext(this->gen_const(8, nzuimm), 32, false)),
-                    get_reg_ptr(rs1 + traits::X0), false);
+                     this->builder.CreateShl(
+                        this->gen_reg_load(rs1+ traits::X0, 0),
+                        this->gen_ext(this->gen_const(8,nzuimm), 32,false))
+                     ,
+                     get_reg_ptr(rs1 + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 77);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 77);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 78: C__LWSP */
-    std::tuple<continuation_e, BasicBlock*> __c__lwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__LWSP_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 78);
+    std::tuple<continuation_e, BasicBlock*> __c__lwsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t uimm = ((bit_sub<2, 2>(instr) << 6) | (bit_sub<4, 3>(instr) << 2) | (bit_sub<12, 1>(instr) << 5));
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("uimm", uimm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"),
+                fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__LWSP_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,78);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rd == 0) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)||rd==0) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false),
-                                                               this->gen_ext(this->gen_const(8, uimm), 64, false))),
-                                      32, false);
-            this->builder.CreateStore(this->gen_ext(this->gen_ext(this->gen_read_mem(traits::MEM, offs, 4), 32, false), 32, true),
-                                      get_reg_ptr(rd + traits::X0), false);
+        }
+        else{
+            auto offs =this->gen_ext(
+                (this->builder.CreateAdd(
+                   this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false),
+                   this->gen_ext(this->gen_const(8,uimm), 64,false))
+                ),
+                32, false);
+            this->builder.CreateStore(
+                 this->gen_ext(
+                     this->gen_ext(
+                         this->gen_read_mem(traits::MEM, offs, 4),
+                         32, false),
+                     32, true),
+                 get_reg_ptr(rd + traits::X0), false);
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 78);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 78);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
+    
     /* instruction 79: C__MV */
-    std::tuple<continuation_e, BasicBlock*> __c__mv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__MV_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 79);
+    std::tuple<continuation_e, BasicBlock*> __c__mv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 5>(instr)));
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,5>(instr)));
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__MV_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,79);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
-                this->builder.CreateStore(this->gen_reg_load(rs2 + traits::X0, 0), get_reg_ptr(rd + traits::X0), false);
-            }
-        }
-        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
 
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 79);
-        this->builder.CreateBr(bb);
-        return returnValue;
-    }
-
-    /* instruction 80: C__JR */
-    std::tuple<continuation_e, BasicBlock*> __c__jr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__JR_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 80);
-        uint64_t PC = pc.val;
-        uint8_t rs1 = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
-                this->core_ptr,
-                this->gen_const(64, pc.val),
-                this->builder.CreateGlobalStringPtr(mnemonic),
-            };
-            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
-        }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
-        this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs1 && rs1 < static_cast<uint32_t>(traits::RFS)) {
-            auto addr_mask = this->gen_const(32, (uint32_t)-2);
-            auto PC_val_v =
-                this->builder.CreateAnd(this->gen_reg_load(rs1 % static_cast<uint32_t>(traits::RFS) + traits::X0, 0), addr_mask);
-            this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false);
-            this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
-        } else {
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
         }
-        bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 80);
-        this->builder.CreateBr(bb);
-        return returnValue;
-    }
-
-    /* instruction 81: __reserved_cmv */
-    std::tuple<continuation_e, BasicBlock*> ____reserved_cmv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("__reserved_cmv_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 81);
-        uint64_t PC = pc.val;
-        if(this->disass_enabled) {
-            /* generate console output when executing the command */
-            // This disass is not yet implemented
-        }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
-        this->gen_set_pc(pc, traits::NEXT_PC);
-        this->gen_raise_trap(0, 2);
-        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 81);
-        this->builder.CreateBr(bb);
-        return returnValue;
-    }
-
-    /* instruction 82: C__ADD */
-    std::tuple<continuation_e, BasicBlock*> __c__add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__ADD_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 82);
-        uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 5>(instr)));
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs2", name(rs2)));
-            std::vector<Value*> args{
-                this->core_ptr,
-                this->gen_const(64, pc.val),
-                this->builder.CreateGlobalStringPtr(mnemonic),
-            };
-            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
-        }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
-        this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
-            this->gen_raise_trap(0, 2);
-        } else {
-            if(rd != 0) {
+        else{
+            if(rd!=0) {
                 this->builder.CreateStore(
-                    this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(rd + traits::X0, 0), 64, false),
-                                                           this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 64, false))),
-                                  32, false),
-                    get_reg_ptr(rd + traits::X0), false);
+                     this->gen_reg_load(rs2+ traits::X0, 0),
+                     get_reg_ptr(rd + traits::X0), false);
             }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 82);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 79);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
-    /* instruction 83: C__JALR */
-    std::tuple<continuation_e, BasicBlock*> __c__jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__JALR_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 83);
+    
+    /* instruction 80: C__JR */
+    std::tuple<continuation_e, BasicBlock*> __c__jr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rs1 = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"), fmt::arg("rs1", name(rs1)));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"),
+                fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__JR_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,80);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs1 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rs1&&rs1<static_cast<uint32_t>(traits::RFS)){ auto PC_val_v = this->builder.CreateAnd(
+           this->gen_reg_load(rs1%static_cast<uint32_t>(traits::RFS)+ traits::X0, 0),
+           this->gen_const(32,~ 1))
+        ;
+        this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false);                            
+        this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
+        }
+        else{
             this->gen_raise_trap(0, 2);
-        } else {
-            auto addr_mask = this->gen_const(32, (uint32_t)-2);
-            auto new_pc = this->gen_reg_load(rs1 + traits::X0, 0);
-            this->builder.CreateStore(this->gen_const(32, (uint32_t)(PC + 2)), get_reg_ptr(1 + traits::X0), false);
-            auto PC_val_v = this->builder.CreateAnd(new_pc, addr_mask);
-            this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false);
-            this->builder.CreateStore(this->gen_const(32, 2U), get_reg_ptr(traits::LAST_BRANCH), false);
         }
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(BRANCH, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 83);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 80);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
-    /* instruction 84: C__EBREAK */
-    std::tuple<continuation_e, BasicBlock*> __c__ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__EBREAK_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 84);
+    
+    /* instruction 81: __reserved_cmv */
+    std::tuple<continuation_e, BasicBlock*> ____reserved_cmv(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            // This disass is not yet implemented
+            //This disass is not yet implemented
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("__reserved_cmv_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,81);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        this->gen_raise_trap(0, 3);
-        bb = this->leave_blk;
-        auto returnValue = std::make_tuple(TRAP, nullptr);
 
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 84);
+        /*generate behavior*/
+        this->gen_raise_trap(0, 2);
+        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 81);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
-    /* instruction 85: C__SWSP */
-    std::tuple<continuation_e, BasicBlock*> __c__swsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("C__SWSP_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 85);
+    
+    /* instruction 82: C__ADD */
+    std::tuple<continuation_e, BasicBlock*> __c__add(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 5>(instr)));
-        uint8_t uimm = ((bit_sub<7, 2>(instr) << 6) | (bit_sub<9, 4>(instr) << 2));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,5>(instr)));
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"), fmt::arg("rs2", name(rs2)),
-                                        fmt::arg("uimm", uimm));
-            std::vector<Value*> args{
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
+            std::vector<Value*> args {
                 this->core_ptr,
                 this->gen_const(64, pc.val),
                 this->builder.CreateGlobalStringPtr(mnemonic),
             };
             this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__ADD_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,82);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        if(rs2 >= static_cast<uint32_t>(traits::RFS)) {
+
+        /*generate behavior*/
+        if(rd>=static_cast<uint32_t>(traits::RFS)) {
             this->gen_raise_trap(0, 2);
-        } else {
-            auto offs = this->gen_ext((this->builder.CreateAdd(this->gen_ext(this->gen_reg_load(2 + traits::X0, 0), 64, false),
-                                                               this->gen_ext(this->gen_const(8, uimm), 64, false))),
-                                      32, false);
-            this->gen_write_mem(traits::MEM, offs, this->gen_ext(this->gen_reg_load(rs2 + traits::X0, 0), 32, false));
+        }
+        else{
+            if(rd!=0) {
+                this->builder.CreateStore(
+                     this->gen_ext(
+                         (this->builder.CreateAdd(
+                            this->gen_ext(this->gen_reg_load(rd+ traits::X0, 0), 64,false),
+                            this->gen_ext(this->gen_reg_load(rs2+ traits::X0, 0), 64,false))
+                         ),
+                         32, false),
+                     get_reg_ptr(rd + traits::X0), false);
+            }
         }
         bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
-        auto returnValue = std::make_tuple(CONT, bb);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 85);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 82);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
-
-    /* instruction 86: DII */
-    std::tuple<continuation_e, BasicBlock*> __dii(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        bb->setName(fmt::format("DII_0x{:X}", pc.val));
-        this->gen_sync(PRE_SYNC, 86);
+    
+    /* instruction 83: C__JALR */
+    std::tuple<continuation_e, BasicBlock*> __c__jalr(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            // This disass is not yet implemented
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"),
+                fmt::arg("rs1", name(rs1)));
+            std::vector<Value*> args {
+                this->core_ptr,
+                this->gen_const(64, pc.val),
+                this->builder.CreateGlobalStringPtr(mnemonic),
+            };
+            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
         }
-        auto cur_pc_val = this->gen_const(32, pc.val);
-        pc = pc + 2;
+        bb->setName(fmt::format("C__JALR_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,83);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
         this->gen_set_pc(pc, traits::NEXT_PC);
-        this->gen_raise_trap(0, 2);
+
+        /*generate behavior*/
+        if(rs1>=static_cast<uint32_t>(traits::RFS)) {
+            this->gen_raise_trap(0, 2);
+        }
+        else{
+            auto new_pc =this->gen_reg_load(rs1+ traits::X0, 0);
+            this->builder.CreateStore(
+                 this->gen_const(32,(uint32_t)(PC+2)),
+                 get_reg_ptr(1 + traits::X0), false);
+            auto PC_val_v = this->builder.CreateAnd(
+               new_pc,
+               this->gen_const(32,~ 1))
+            ;
+            this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false);                            
+            this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
+        }
         bb = this->leave_blk;
-        auto returnValue = std::make_tuple(TRAP, nullptr);
-
-        this->gen_trap_check(bb);
-        this->gen_sync(POST_SYNC, 86);
+        auto returnValue = std::make_tuple(BRANCH,nullptr);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 83);
         this->builder.CreateBr(bb);
-        return returnValue;
+    	return returnValue;        
     }
+    
+    /* instruction 84: C__EBREAK */
+    std::tuple<continuation_e, BasicBlock*> __c__ebreak(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        uint64_t PC = pc.val;
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            //This disass is not yet implemented
+        }
+        bb->setName(fmt::format("C__EBREAK_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,84);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
+        this->gen_set_pc(pc, traits::NEXT_PC);
 
+        /*generate behavior*/
+        this->gen_raise_trap(0, 3);
+        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 84);
+        this->builder.CreateBr(bb);
+    	return returnValue;        
+    }
+    
+    /* instruction 85: C__SWSP */
+    std::tuple<continuation_e, BasicBlock*> __c__swsp(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        uint64_t PC = pc.val;
+        uint8_t rs2 = ((bit_sub<2,5>(instr)));
+        uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
+            std::vector<Value*> args {
+                this->core_ptr,
+                this->gen_const(64, pc.val),
+                this->builder.CreateGlobalStringPtr(mnemonic),
+            };
+            this->builder.CreateCall(this->mod->getFunction("print_disass"), args);
+        }
+        bb->setName(fmt::format("C__SWSP_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,85);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
+        this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
+        if(rs2>=static_cast<uint32_t>(traits::RFS)) {
+            this->gen_raise_trap(0, 2);
+        }
+        else{
+            auto offs =this->gen_ext(
+                (this->builder.CreateAdd(
+                   this->gen_ext(this->gen_reg_load(2+ traits::X0, 0), 64,false),
+                   this->gen_ext(this->gen_const(8,uimm), 64,false))
+                ),
+                32, false);
+            this->gen_write_mem(traits::MEM,
+            offs,
+            this->gen_ext(
+                this->gen_reg_load(rs2+ traits::X0, 0),
+                32, false));
+        }
+        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 85);
+        this->builder.CreateBr(bb);
+    	return returnValue;        
+    }
+    
+    /* instruction 86: DII */
+    std::tuple<continuation_e, BasicBlock*> __dii(virt_addr_t& pc, code_word_t instr, BasicBlock* bb){
+        uint64_t PC = pc.val;
+        if(this->disass_enabled){
+            /* generate console output when executing the command */
+            //This disass is not yet implemented
+        }
+        bb->setName(fmt::format("DII_0x{:X}",pc.val));
+        this->gen_sync(PRE_SYNC,86);
+        auto cur_pc_val = this->gen_const(32,pc.val);
+        pc=pc+ 2;
+        this->gen_set_pc(pc, traits::NEXT_PC);
+
+        /*generate behavior*/
+        this->gen_raise_trap(0, 2);
+        bb = BasicBlock::Create(this->mod->getContext(), "entry", this->func, this->leave_blk);
+        auto returnValue = std::make_tuple(CONT,bb);
+        
+        this->gen_instr_epilogue(bb);
+    	this->gen_sync(POST_SYNC, 86);
+        this->builder.CreateBr(bb);
+    	return returnValue;        
+    }
+    
     /****************************************************************************
      * end opcode definitions
      ****************************************************************************/
-    std::tuple<continuation_e, BasicBlock*> illegal_intruction(virt_addr_t& pc, code_word_t instr, BasicBlock* bb) {
-        this->gen_sync(iss::PRE_SYNC, instr_descr.size());
+    std::tuple<continuation_e, BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr, BasicBlock *bb) {
+		this->gen_sync(iss::PRE_SYNC, instr_descr.size());
         this->builder.CreateStore(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), true),
-                                  get_reg_ptr(traits::PC), true);
+                                   get_reg_ptr(traits::PC), true);
         this->builder.CreateStore(
             this->builder.CreateAdd(this->builder.CreateLoad(this->get_typeptr(traits::ICOUNT), get_reg_ptr(traits::ICOUNT), true),
-                                    this->gen_const(64U, 1)),
+                                     this->gen_const(64U, 1)),
             get_reg_ptr(traits::ICOUNT), true);
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        this->gen_raise_trap(0, 2); // illegal instruction trap
-        this->gen_sync(iss::POST_SYNC, instr_descr.size());
-        this->gen_trap_check(this->leave_blk);
+        this->gen_raise_trap(0, 2);     // illegal instruction trap
+		this->gen_sync(iss::POST_SYNC, instr_descr.size());
+        this->gen_instr_epilogue(this->leave_blk);
         return std::make_tuple(BRANCH, nullptr);
-    }
-    // decoding functionality
+    }    
+    //decoding functionality
 
-    void populate_decoding_tree(decoding_tree_node* root) {
-        // create submask
-        for(auto instr : root->instrs) {
+    void populate_decoding_tree(decoding_tree_node* root){
+        //create submask
+        for(auto instr: root->instrs){
             root->submask &= instr.mask;
         }
-        // put each instr according to submask&encoding into children
-        for(auto instr : root->instrs) {
+        //put each instr according to submask&encoding into children
+        for(auto instr: root->instrs){
             bool foundMatch = false;
-            for(auto child : root->children) {
-                // use value as identifying trait
-                if(child->value == (instr.value & root->submask)) {
+            for(auto child: root->children){
+                //use value as identifying trait
+                if(child->value == (instr.value&root->submask)){
                     child->instrs.push_back(instr);
                     foundMatch = true;
                 }
             }
-            if(!foundMatch) {
-                decoding_tree_node* child = new decoding_tree_node(instr.value & root->submask);
+            if(!foundMatch){
+                decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
                 child->instrs.push_back(instr);
                 root->children.push_back(child);
             }
         }
         root->instrs.clear();
-        // call populate_decoding_tree for all children
-        if(root->children.size() > 1)
-            for(auto child : root->children) {
-                populate_decoding_tree(child);
+        //call populate_decoding_tree for all children
+        if(root->children.size() >1)
+            for(auto child: root->children){
+                populate_decoding_tree(child);      
             }
-        else {
-            // sort instrs by value of the mask, this works bc we want to have the least restrictive one last
-            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(),
-                      [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { return instr1.mask > instr2.mask; });
+        else{
+            //sort instrs by value of the mask, this works bc we want to have the least restrictive one last
+            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
+            return instr1.mask > instr2.mask;
+            }); 
         }
     }
-    compile_func decode_instr(decoding_tree_node* node, code_word_t word) {
-        if(!node->children.size()) {
-            if(node->instrs.size() == 1)
-                return node->instrs[0].op;
-            for(auto instr : node->instrs) {
-                if((instr.mask & word) == instr.value)
-                    return instr.op;
+    compile_func decode_instr(decoding_tree_node* node, code_word_t word){
+        if(!node->children.size()){
+            if(node->instrs.size() == 1) return node->instrs[0].op;
+            for(auto instr : node->instrs){
+                if((instr.mask&word) == instr.value) return instr.op;
             }
-        } else {
-            for(auto child : node->children) {
-                if(child->value == (node->submask & word)) {
+        }
+        else{
+            for(auto child : node->children){
+                if (child->value == (node->submask&word)){
                     return decode_instr(child, word);
-                }
-            }
+                }  
+            }  
         }
         return nullptr;
     }
@@ -3983,100 +4606,106 @@ template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 
 template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH& core, unsigned core_id, unsigned cluster_id)
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
     root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
-    for(auto instr : instr_descr) {
+    for(auto instr:instr_descr){
         root->instrs.push_back(instr);
     }
     populate_decoding_tree(root);
 }
 
 template <typename ARCH>
-std::tuple<continuation_e, BasicBlock*> vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt,
-                                                                                BasicBlock* this_block) {
+std::tuple<continuation_e, BasicBlock *>
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, BasicBlock *this_block) {
     // we fetch at max 4 byte, alignment is 2
-    enum { TRAP_ID = 1 << 16 };
+    enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
     // const typename traits::addr_t upper_bits = ~traits::PGMASK;
     phys_addr_t paddr(pc);
-    auto* const data = (uint8_t*)&instr;
+    auto *const data = (uint8_t *)&instr;
     if(this->core.has_mmu())
         paddr = this->core.virt2phys(pc);
-    // TODO: re-add page handling
-    //    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-    //        auto res = this->core.read(paddr, 2, data);
-    //        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-    //        if ((instr & 0x3) == 0x3) { // this is a 32bit instruction
-    //            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-    //        }
-    //    } else {
-    auto res = this->core.read(paddr, 4, data);
-    if(res != iss::Ok)
-        throw trap_access(TRAP_ID, pc.val);
-    //    }
-    if(instr == 0x0000006f || (instr & 0xffff) == 0xa001)
-        throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    //TODO: re-add page handling
+//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+//        auto res = this->core.read(paddr, 2, data);
+//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//        if ((instr & 0x3) == 0x3) { // this is a 32bit instruction
+//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+//        }
+//    } else {
+        auto res = this->core.read(paddr, 4, data);
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//    }
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
     // curr pc on stack
     ++inst_cnt;
     auto f = decode_instr(root, instr);
-    if(f == nullptr) {
+    if (f == nullptr) {
         f = &this_class::illegal_intruction;
     }
     return (this->*f)(pc, instr, this_block);
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_behavior(BasicBlock* leave_blk) {
+template <typename ARCH>
+void vm_impl<ARCH>::gen_leave_behavior(BasicBlock *leave_blk) {
     this->builder.SetInsertPoint(leave_blk);
-    this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false));
+    this->builder.CreateRet(this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC),get_reg_ptr(traits::NEXT_PC), false));
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
-    auto* TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
+template <typename ARCH>
+void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause) {
+    auto *TRAP_val = this->gen_const(32, 0x80 << 24 | (cause << 16) | trap_id);
     this->builder.CreateStore(TRAP_val, get_reg_ptr(traits::TRAP_STATE), true);
     this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits::LAST_BRANCH), false);
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
-    std::vector<Value*> args{this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl))};
+template <typename ARCH>
+void vm_impl<ARCH>::gen_leave_trap(unsigned lvl) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, lvl)) };
     this->builder.CreateCall(this->mod->getFunction("leave_trap"), args);
-    auto* PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8);
+    auto *PC_val = this->gen_read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN / 8);
     this->builder.CreateStore(PC_val, get_reg_ptr(traits::NEXT_PC), false);
     this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits::LAST_BRANCH), false);
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_wait(unsigned type) {
-    std::vector<Value*> args{this->core_ptr, ConstantInt::get(getContext(), APInt(64, type))};
+template <typename ARCH>
+void vm_impl<ARCH>::gen_wait(unsigned type) {
+    std::vector<Value *> args{ this->core_ptr, ConstantInt::get(getContext(), APInt(64, type)) };
     this->builder.CreateCall(this->mod->getFunction("wait"), args);
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(BasicBlock* trap_blk) {
+template <typename ARCH> 
+void vm_impl<ARCH>::gen_trap_behavior(BasicBlock *trap_blk) {
     this->builder.SetInsertPoint(trap_blk);
-    this->gen_sync(POST_SYNC, -1); // TODO get right InstrId
-    auto* trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
-    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()), get_reg_ptr(traits::LAST_BRANCH), false);
-    std::vector<Value*> args{this->core_ptr, this->adj_to64(trap_state_val),
-                             this->adj_to64(this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), false))};
+    this->gen_sync(POST_SYNC, -1); //TODO get right InstrId
+    auto *trap_state_val = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
+    this->builder.CreateStore(this->gen_const(32U, std::numeric_limits<uint32_t>::max()),
+                              get_reg_ptr(traits::LAST_BRANCH), false);
+    std::vector<Value *> args{this->core_ptr, this->adj_to64(trap_state_val),
+                              this->adj_to64(this->builder.CreateLoad(this->get_typeptr(traits::PC), get_reg_ptr(traits::PC), false))};
     this->builder.CreateCall(this->mod->getFunction("enter_trap"), args);
-    auto* trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false);
+    auto *trap_addr_val = this->builder.CreateLoad(this->get_typeptr(traits::NEXT_PC), get_reg_ptr(traits::NEXT_PC), false);
     this->builder.CreateRet(trap_addr_val);
 }
 
-template <typename ARCH> inline void vm_impl<ARCH>::gen_trap_check(BasicBlock* bb) {
+template <typename ARCH>
+void vm_impl<ARCH>::gen_instr_epilogue(BasicBlock *bb) {
     auto* target_bb = BasicBlock::Create(this->mod->getContext(), "", this->func, bb);
-    auto* v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
-    this->gen_cond_branch(
-        this->builder.CreateICmp(ICmpInst::ICMP_EQ, v, ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
-        target_bb, this->trap_blk, 1);
+    auto *v = this->builder.CreateLoad(this->get_typeptr(traits::TRAP_STATE), get_reg_ptr(traits::TRAP_STATE), true);
+    this->gen_cond_branch(this->builder.CreateICmp(
+                              ICmpInst::ICMP_EQ, v,
+                              ConstantInt::get(getContext(), APInt(v->getType()->getIntegerBitWidth(), 0))),
+                          target_bb, this->trap_blk, 1);
     this->builder.SetInsertPoint(target_bb);
 }
 
 } // namespace tgc5c
 
-template <> std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c* core, unsigned short port, bool dump) {
+template <>
+std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short port, bool dump) {
     auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
-    if(port != 0)
-        debugger::server<debugger::gdb_session>::run_server(ret, port);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
 } // namespace llvm
@@ -4088,20 +4717,27 @@ template <> std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c* core, unsign
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-    core_factory::instance().register_creator("tgc5c|m_p|llvm",
-                                              [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr> {
-                                                  auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
-                                                  auto* vm = new llvm::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
-                                                  if(port != 0)
-                                                      debugger::server<debugger::gdb_session>::run_server(vm, port);
-                                                  return {cpu_ptr{cpu}, vm_ptr{vm}};
-                                              }),
-    core_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr> {
-        auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
-        auto* vm = new llvm::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
-        if(port != 0)
-            debugger::server<debugger::gdb_session>::run_server(vm, port);
-        return {cpu_ptr{cpu}, vm_ptr{vm}};
-    })};
+        core_factory::instance().register_creator("tgc5c|m_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
+		    auto vm = new llvm::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t*, arch::traits<arch::tgc5c>::reg_t*)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("tgc5c|mu_p|llvm", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
+		    auto vm = new llvm::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::tgc5c>::reg_t*, arch::traits<arch::tgc5c>::reg_t*)>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
 }
-} // namespace iss
+}
+// clang-format on
\ No newline at end of file
diff --git a/src/vm/tcc/vm_tgc5c.cpp b/src/vm/tcc/vm_tgc5c.cpp
index dd767a0..cfc6375 100644
--- a/src/vm/tcc/vm_tgc5c.cpp
+++ b/src/vm/tcc/vm_tgc5c.cpp
@@ -29,14 +29,14 @@
  * POSSIBILITY OF SUCH DAMAGE.
  *
  *******************************************************************************/
-
+// clang-format off
 #include <iss/arch/tgc5c.h>
 #include <iss/debugger/gdb_session.h>
 #include <iss/debugger/server.h>
 #include <iss/iss.h>
 #include <iss/tcc/vm_base.h>
-#include <sstream>
 #include <util/logging.h>
+#include <sstream>
 
 #ifndef FMT_HEADER_ONLY
 #define FMT_HEADER_ONLY
@@ -55,23 +55,23 @@ using namespace iss::debugger;
 template <typename ARCH> class vm_impl : public iss::tcc::vm_base<ARCH> {
 public:
     using traits = arch::traits<ARCH>;
-    using super = typename iss::tcc::vm_base<ARCH>;
+    using super       = typename iss::tcc::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
     using phys_addr_t = typename super::phys_addr_t;
     using code_word_t = typename super::code_word_t;
-    using mem_type_e = typename traits::mem_type_e;
-    using addr_t = typename super::addr_t;
-    using tu_builder = typename super::tu_builder;
+    using mem_type_e  = typename traits::mem_type_e;    
+    using addr_t      = typename super::addr_t;
+    using tu_builder  = typename super::tu_builder;
 
     vm_impl();
 
-    vm_impl(ARCH& core, unsigned core_id = 0, unsigned cluster_id = 0);
+    vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
 
     void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
 
-    target_adapter_if* accquire_target_adapter(server_if* srv) override {
+    target_adapter_if *accquire_target_adapter(server_if *srv) override {
         debugger_if::dbg_enabled = true;
-        if(vm_base<ARCH>::tgt_adapter == nullptr)
+        if (vm_base<ARCH>::tgt_adapter == nullptr)
             vm_base<ARCH>::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
         return vm_base<ARCH>::tgt_adapter;
     }
@@ -81,13 +81,15 @@ protected:
 
     using this_class = vm_impl<ARCH>;
     using compile_ret_t = std::tuple<continuation_e>;
-    using compile_func = compile_ret_t (this_class::*)(virt_addr_t& pc, code_word_t instr, tu_builder&);
+    using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr, tu_builder&);
 
-    inline const char* name(size_t index) { return traits::reg_aliases.at(index); }
+    inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
-    void setup_module(std::string m) override { super::setup_module(m); }
+    void setup_module(std::string m) override {
+        super::setup_module(m);
+    }
 
-    compile_ret_t gen_single_inst_behavior(virt_addr_t&, unsigned int&, tu_builder&) override;
+    compile_ret_t gen_single_inst_behavior(virt_addr_t &, unsigned int &, tu_builder&) override;
 
     void gen_trap_behavior(tu_builder& tu) override;
 
@@ -97,10 +99,12 @@ protected:
 
     void gen_wait(tu_builder& tu, unsigned type);
 
-    inline void gen_trap_check(tu_builder& tu) { tu("if(*trap_state!=0) goto trap_entry;"); }
+    inline void gen_trap_check(tu_builder& tu) {
+        tu("if(*trap_state!=0) goto trap_entry;");
+    }
 
     inline void gen_set_pc(tu_builder& tu, virt_addr_t pc, unsigned reg_num) {
-        switch(reg_num) {
+        switch(reg_num){
         case traits::NEXT_PC:
             tu("*next_pc = {:#x};", pc.val);
             break;
@@ -108,19 +112,21 @@ protected:
             tu("*pc = {:#x};", pc.val);
             break;
         default:
-            if(!tu.defined_regs[reg_num]) {
+            if(!tu.defined_regs[reg_num]){
                 tu("reg_t* reg{:02d} = (reg_t*){:#x};", reg_num, reinterpret_cast<uintptr_t>(get_reg_ptr(reg_num)));
-                tu.defined_regs[reg_num] = true;
+            tu.defined_regs[reg_num]=true;
             }
             tu("*reg{:02d} = {:#x};", reg_num, pc.val);
         }
     }
 
-    template <unsigned W, typename U, typename S = typename std::make_signed<U>::type> inline S sext(U from) {
-        auto mask = (1ULL << W) - 1;
-        auto sign_mask = 1ULL << (W - 1);
+    
+    template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
+    inline S sext(U from) {
+        auto mask = (1ULL<<W) - 1;
+        auto sign_mask = 1ULL<<(W-1);
         return (from & mask) | ((from & sign_mask) ? ~mask : 0);
-    }
+    }    
 
 private:
     /****************************************************************************
@@ -132,19 +138,18 @@ private:
         uint32_t mask;
         compile_func op;
     };
-    struct decoding_tree_node {
+    struct decoding_tree_node{
         std::vector<instruction_descriptor> instrs;
         std::vector<decoding_tree_node*> children;
         uint32_t submask = std::numeric_limits<uint32_t>::max();
         uint32_t value;
-        decoding_tree_node(uint32_t value)
-        : value(value) {}
+        decoding_tree_node(uint32_t value) : value(value){}
     };
 
-    decoding_tree_node* root{nullptr};
+    decoding_tree_node* root {nullptr};
 
     const std::array<instruction_descriptor, 87> instr_descr = {{
-        /* entries are: size, valid value, valid mask, function ptr */
+         /* entries are: size, valid value, valid mask, function ptr */
         /* instruction LUI, encoding '0b00000000000000000000000000110111' */
         {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
         /* instruction AUIPC, encoding '0b00000000000000000000000000010111' */
@@ -320,2946 +325,3238 @@ private:
         /* instruction DII, encoding '0b0000000000000000' */
         {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii},
     }};
-
+ 
     /* instruction definitions */
     /* instruction 0: LUI */
-    compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("LUI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 0);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,0);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint32_t imm = ((bit_sub<12, 20>(instr) << 12));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint32_t imm = ((bit_sub<12,20>(instr) << 12));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic =
-                fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)imm), 32));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.constant((uint32_t)((int32_t)imm),32));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 0);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,0);
         return returnValue;
     }
-
+    
     /* instruction 1: AUIPC */
-    compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("AUIPC_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 1);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,1);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint32_t imm = ((bit_sub<12, 20>(instr) << 12));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint32_t imm = ((bit_sub<12,20>(instr) << 12));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.constant((uint32_t)(PC + (int32_t)imm), 32));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.constant((uint32_t)(PC+(int32_t)imm),32));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 1);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,1);
         return returnValue;
     }
-
+    
     /* instruction 2: JAL */
-    compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("JAL_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 2);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,2);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint32_t imm =
-            ((bit_sub<12, 8>(instr) << 12) | (bit_sub<20, 1>(instr) << 11) | (bit_sub<21, 10>(instr) << 1) | (bit_sub<31, 1>(instr) << 20));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic =
-                fmt::format("{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                this->gen_raise_trap(tu, 0, 0);
-            } else {
-                if(rd != 0) {
-                    tu.store(rd + traits::X0, tu.constant((uint32_t)(PC + 4), 32));
-                }
-                auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int32_t)sext<21>(imm)), 32);
-                tu.store(traits::NEXT_PC, PC_val_v);
-                tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
-            }
+        }
+        else{
+        	if(imm%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0);
+        	}
+        	else{
+        		if(rd!=0) {
+        		    tu.store(rd + traits::X0,
+        		          tu.constant((uint32_t)(PC+4),32));
+        		}
+        		auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int32_t)sext<21>(imm)),32);
+        		tu.store(traits::NEXT_PC, PC_val_v);
+        		tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
+        	}
         }
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 2);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,2);
         return returnValue;
     }
-
+    
     /* instruction 3: JALR */
-    compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("JALR_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 3);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,3);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto addr_mask = tu.assignment(tu.constant((uint32_t)-2, 32), 32);
-            auto new_pc = tu.assignment(
-                tu.ext((tu.bitwise_and((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), addr_mask)), 32,
-                       false),
-                32);
-            tu.open_if(tu.urem(new_pc, tu.constant(static_cast<uint32_t>(traits::INSTR_ALIGNMENT), 32)));
-            this->gen_raise_trap(tu, 0, 0);
-            tu.open_else();
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.constant((uint32_t)(PC + 4), 32));
-            }
-            auto PC_val_v = tu.assignment("PC_val", new_pc, 32);
-            tu.store(traits::NEXT_PC, PC_val_v);
-            tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
-            tu.close_scope();
+        }
+        else{
+        	auto addr_mask = tu.assignment(tu.constant((uint32_t)- 2,32),32);
+        	auto new_pc = tu.assignment(tu.ext((tu.bitwise_and(
+        	   (tu.add(
+        	      tu.load(rs1+ traits::X0, 0),
+        	      tu.constant((int16_t)sext<12>(imm),16))),
+        	   addr_mask)),32,false),32);
+        	tu.open_if(tu.urem(
+        	   new_pc,
+        	   tu.constant(static_cast<uint32_t>(traits:: INSTR_ALIGNMENT),32)));
+        	this->gen_raise_trap(tu, 0, 0);
+        	tu.open_else();
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.constant((uint32_t)(PC+4),32));
+        	}
+        	auto PC_val_v = tu.assignment("PC_val", new_pc,32);
+        	tu.store(traits::NEXT_PC, PC_val_v);
+        	tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
+        	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 3);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,3);
         return returnValue;
     }
-
+    
     /* instruction 4: BEQ */
-    compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __beq(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("BEQ_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 4);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,4);
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0)));
-            if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                this->gen_raise_trap(tu, 0, 0);
-            } else {
-                auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32);
-                tu.store(traits::NEXT_PC, PC_val_v);
-                tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
-            }
-            tu.close_scope();
+        }
+        else{
+        	tu.open_if(tu.icmp(ICmpInst::ICMP_EQ,
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.load(rs2+ traits::X0, 0)));
+        	if(imm%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0);
+        	}
+        	else{
+        		auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32);
+        		tu.store(traits::NEXT_PC, PC_val_v);
+        		tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
+        	}
+        	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 4);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,4);
         return returnValue;
     }
-
+    
     /* instruction 5: BNE */
-    compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __bne(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("BNE_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 5);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,5);
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0)));
-            if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                this->gen_raise_trap(tu, 0, 0);
-            } else {
-                auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32);
-                tu.store(traits::NEXT_PC, PC_val_v);
-                tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
-            }
-            tu.close_scope();
+        }
+        else{
+        	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.load(rs2+ traits::X0, 0)));
+        	if(imm%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0);
+        	}
+        	else{
+        		auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32);
+        		tu.store(traits::NEXT_PC, PC_val_v);
+        		tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
+        	}
+        	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 5);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,5);
         return returnValue;
     }
-
+    
     /* instruction 6: BLT */
-    compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __blt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("BLT_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 6);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,6);
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            tu.open_if(tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true),
-                               tu.ext(tu.load(rs2 + traits::X0, 0), 32, true)));
-            if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                this->gen_raise_trap(tu, 0, 0);
-            } else {
-                auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32);
-                tu.store(traits::NEXT_PC, PC_val_v);
-                tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
-            }
-            tu.close_scope();
+        }
+        else{
+        	tu.open_if(tu.icmp(ICmpInst::ICMP_SLT,
+        	   tu.ext(tu.load(rs1+ traits::X0, 0),32,true),
+        	   tu.ext(tu.load(rs2+ traits::X0, 0),32,true)));
+        	if(imm%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0);
+        	}
+        	else{
+        		auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32);
+        		tu.store(traits::NEXT_PC, PC_val_v);
+        		tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
+        	}
+        	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 6);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,6);
         return returnValue;
     }
-
+    
     /* instruction 7: BGE */
-    compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __bge(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("BGE_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 7);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,7);
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            tu.open_if(tu.icmp(ICmpInst::ICMP_SGE, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true),
-                               tu.ext(tu.load(rs2 + traits::X0, 0), 32, true)));
-            if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                this->gen_raise_trap(tu, 0, 0);
-            } else {
-                auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32);
-                tu.store(traits::NEXT_PC, PC_val_v);
-                tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
-            }
-            tu.close_scope();
+        }
+        else{
+        	tu.open_if(tu.icmp(ICmpInst::ICMP_SGE,
+        	   tu.ext(tu.load(rs1+ traits::X0, 0),32,true),
+        	   tu.ext(tu.load(rs2+ traits::X0, 0),32,true)));
+        	if(imm%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0);
+        	}
+        	else{
+        		auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32);
+        		tu.store(traits::NEXT_PC, PC_val_v);
+        		tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
+        	}
+        	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 7);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,7);
         return returnValue;
     }
-
+    
     /* instruction 8: BLTU */
-    compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("BLTU_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 8);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,8);
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            tu.open_if(tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0)));
-            if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                this->gen_raise_trap(tu, 0, 0);
-            } else {
-                auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32);
-                tu.store(traits::NEXT_PC, PC_val_v);
-                tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
-            }
-            tu.close_scope();
+        }
+        else{
+        	tu.open_if(tu.icmp(ICmpInst::ICMP_ULT,
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.load(rs2+ traits::X0, 0)));
+        	if(imm%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0);
+        	}
+        	else{
+        		auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32);
+        		tu.store(traits::NEXT_PC, PC_val_v);
+        		tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
+        	}
+        	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 8);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,8);
         return returnValue;
     }
-
+    
     /* instruction 9: BGEU */
-    compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("BGEU_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 9);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,9);
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<7, 1>(instr) << 11) | (bit_sub<8, 4>(instr) << 1) | (bit_sub<25, 6>(instr) << 5) | (bit_sub<31, 1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            tu.open_if(tu.icmp(ICmpInst::ICMP_UGE, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0)));
-            if(imm % static_cast<uint32_t>(traits::INSTR_ALIGNMENT)) {
-                this->gen_raise_trap(tu, 0, 0);
-            } else {
-                auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<13>(imm)), 32);
-                tu.store(traits::NEXT_PC, PC_val_v);
-                tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
-            }
-            tu.close_scope();
+        }
+        else{
+        	tu.open_if(tu.icmp(ICmpInst::ICMP_UGE,
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.load(rs2+ traits::X0, 0)));
+        	if(imm%static_cast<uint32_t>(traits:: INSTR_ALIGNMENT)){ this->gen_raise_trap(tu, 0, 0);
+        	}
+        	else{
+        		auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<13>(imm)),32);
+        		tu.store(traits::NEXT_PC, PC_val_v);
+        		tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
+        	}
+        	tu.close_scope();
         }
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 9);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,9);
         return returnValue;
     }
-
+    
     /* instruction 10: LB */
-    compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __lb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("LB_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 10);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,10);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto load_address =
-                tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32);
-            auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 8), 8, true), 8);
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext(res, 32, false));
-            }
+        }
+        else{
+        	auto load_address = tu.assignment(tu.ext((tu.add(
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
+        	auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 8),8,true),8);
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext(res,32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 10);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,10);
         return returnValue;
     }
-
+    
     /* instruction 11: LH */
-    compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __lh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("LH_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 11);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,11);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto load_address =
-                tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32);
-            auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 16), 16, true), 16);
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext(res, 32, false));
-            }
+        }
+        else{
+        	auto load_address = tu.assignment(tu.ext((tu.add(
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
+        	auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 16),16,true),16);
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext(res,32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 11);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,11);
         return returnValue;
     }
-
+    
     /* instruction 12: LW */
-    compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("LW_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 12);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,12);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto load_address =
-                tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32);
-            auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 32), 32, true), 32);
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext(res, 32, false));
-            }
+        }
+        else{
+        	auto load_address = tu.assignment(tu.ext((tu.add(
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
+        	auto res = tu.assignment(tu.ext(tu.read_mem(traits::MEM, load_address, 32),32,true),32);
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext(res,32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 12);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,12);
         return returnValue;
     }
-
+    
     /* instruction 13: LBU */
-    compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("LBU_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 13);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,13);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto load_address =
-                tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32);
-            auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 8), 8);
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext(res, 32, false));
-            }
+        }
+        else{
+        	auto load_address = tu.assignment(tu.ext((tu.add(
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
+        	auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 8),8);
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext(res,32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 13);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,13);
         return returnValue;
     }
-
+    
     /* instruction 14: LHU */
-    compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("LHU_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 14);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,14);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto load_address =
-                tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32);
-            auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 16), 16);
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext(res, 32, false));
-            }
+        }
+        else{
+        	auto load_address = tu.assignment(tu.ext((tu.add(
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
+        	auto res = tu.assignment(tu.read_mem(traits::MEM, load_address, 16),16);
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext(res,32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 14);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,14);
         return returnValue;
     }
-
+    
     /* instruction 15: SB */
-    compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __sb(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SB_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 15);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,15);
         uint64_t PC = pc.val;
-        uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"), fmt::arg("rs2", name(rs2)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto store_address =
-                tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32);
-            tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0), 8, false));
+        }
+        else{
+        	auto store_address = tu.assignment(tu.ext((tu.add(
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
+        	tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2+ traits::X0, 0),8,false));
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 15);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,15);
         return returnValue;
     }
-
+    
     /* instruction 16: SH */
-    compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __sh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SH_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 16);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,16);
         uint64_t PC = pc.val;
-        uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"), fmt::arg("rs2", name(rs2)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto store_address =
-                tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32);
-            tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0), 16, false));
+        }
+        else{
+        	auto store_address = tu.assignment(tu.ext((tu.add(
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
+        	tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2+ traits::X0, 0),16,false));
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 16);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,16);
         return returnValue;
     }
-
+    
     /* instruction 17: SW */
-    compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SW_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 17);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,17);
         uint64_t PC = pc.val;
-        uint16_t imm = ((bit_sub<7, 5>(instr)) | (bit_sub<25, 7>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"), fmt::arg("rs2", name(rs2)),
-                                        fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs2 >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs2>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto store_address =
-                tu.assignment(tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false), 32);
-            tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2 + traits::X0, 0), 32, false));
+        }
+        else{
+        	auto store_address = tu.assignment(tu.ext((tu.add(
+        	   tu.load(rs1+ traits::X0, 0),
+        	   tu.constant((int16_t)sext<12>(imm),16))),32,false),32);
+        	tu.write_mem(traits::MEM, store_address, tu.ext(tu.load(rs2+ traits::X0, 0),32,false));
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 17);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,17);
         return returnValue;
     }
-
+    
     /* instruction 18: ADDI */
-    compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("ADDI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 18);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,18);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0,
-                         tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int16_t)sext<12>(imm), 16))), 32, false));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext((tu.add(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.constant((int16_t)sext<12>(imm),16))),32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 18);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,18);
         return returnValue;
     }
-
+    
     /* instruction 19: SLTI */
-    compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __slti(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SLTI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 19);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,19);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0,
-                         tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true),
-                                                           tu.constant((int16_t)sext<12>(imm), 16))),
-                                                  tu.constant(1, 8), tu.constant(0, 8)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_SLT,
+        	             tu.ext(tu.load(rs1+ traits::X0, 0),32,true),
+        	             tu.constant((int16_t)sext<12>(imm),16))), tu.constant(1,8),tu.constant(0,8)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 19);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,19);
         return returnValue;
     }
-
+    
     /* instruction 20: SLTIU */
-    compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SLTIU_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 20);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,20);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1 + traits::X0, 0),
-                                                                            tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32))),
-                                                                   tu.constant(1, 8), tu.constant(0, 8)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.conditionalAssignment((tu.icmp(ICmpInst::ICMP_ULT,
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.constant((uint32_t)((int16_t)sext<12>(imm)),32))), tu.constant(1,8),tu.constant(0,8)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 20);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,20);
         return returnValue;
     }
-
+    
     /* instruction 21: XORI */
-    compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __xori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("XORI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 21);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,21);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0,
-                         tu.bitwise_xor(tu.load(rs1 + traits::X0, 0), tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.bitwise_xor(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.constant((uint32_t)((int16_t)sext<12>(imm)),32)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 21);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,21);
         return returnValue;
     }
-
+    
     /* instruction 22: ORI */
-    compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __ori(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("ORI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 22);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,22);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.bitwise_or(tu.load(rs1 + traits::X0, 0), tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.bitwise_or(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.constant((uint32_t)((int16_t)sext<12>(imm)),32)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 22);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,22);
         return returnValue;
     }
-
+    
     /* instruction 23: ANDI */
-    compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("ANDI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 23);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,23);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0,
-                         tu.bitwise_and(tu.load(rs1 + traits::X0, 0), tu.constant((uint32_t)((int16_t)sext<12>(imm)), 32)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.bitwise_and(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.constant((uint32_t)((int16_t)sext<12>(imm)),32)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 23);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,23);
         return returnValue;
     }
-
+    
     /* instruction 24: SLLI */
-    compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SLLI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 24);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,24);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t shamt = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t shamt = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.shl(tu.load(rs1 + traits::X0, 0), tu.constant(shamt, 8)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.shl(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.constant(shamt,8)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 24);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,24);
         return returnValue;
     }
-
+    
     /* instruction 25: SRLI */
-    compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SRLI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 25);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,25);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t shamt = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t shamt = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.lshr(tu.load(rs1 + traits::X0, 0), tu.constant(shamt, 8)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.lshr(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.constant(shamt,8)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 25);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,25);
         return returnValue;
     }
-
+    
     /* instruction 26: SRAI */
-    compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SRAI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 26);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,26);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t shamt = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t shamt = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0,
-                         tu.ext((tu.ashr(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), tu.constant(shamt, 8))), 32, false));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext((tu.ashr(
+        	             tu.ext(tu.load(rs1+ traits::X0, 0),32,true),
+        	             tu.constant(shamt,8))),32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 26);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,26);
         return returnValue;
     }
-
+    
     /* instruction 27: ADD */
-    compile_ret_t __add(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("ADD_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 27);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,27);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext((tu.add(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.load(rs2+ traits::X0, 0))),32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 27);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,27);
         return returnValue;
     }
-
+    
     /* instruction 28: SUB */
-    compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SUB_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 28);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,28);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext((tu.sub(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext((tu.sub(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.load(rs2+ traits::X0, 0))),32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 28);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,28);
         return returnValue;
     }
-
+    
     /* instruction 29: SLL */
-    compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __sll(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SLL_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 29);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,29);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.shl(tu.load(rs1 + traits::X0, 0),
-                                                 (tu.bitwise_and(tu.load(rs2 + traits::X0, 0),
-                                                                 tu.constant((static_cast<uint32_t>(traits::XLEN) - 1), 64)))));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.shl(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             (tu.bitwise_and(
+        	                tu.load(rs2+ traits::X0, 0),
+        	                tu.constant((static_cast<uint32_t>(traits:: XLEN)-1),64)))));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 29);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,29);
         return returnValue;
     }
-
+    
     /* instruction 30: SLT */
-    compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __slt(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SLT_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 30);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,30);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0,
-                         tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_SLT, tu.ext(tu.load(rs1 + traits::X0, 0), 32, true),
-                                                          tu.ext(tu.load(rs2 + traits::X0, 0), 32, true)),
-                                                  tu.constant(1, 8), tu.constant(0, 8)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_SLT,
+        	             tu.ext(tu.load(rs1+ traits::X0, 0),32,true),
+        	             tu.ext(tu.load(rs2+ traits::X0, 0),32,true)), tu.constant(1,8),tu.constant(0,8)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 30);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,30);
         return returnValue;
     }
-
+    
     /* instruction 31: SLTU */
-    compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SLTU_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 31);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,31);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0,
-                         tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_ULT, tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0)),
-                                                  tu.constant(1, 8), tu.constant(0, 8)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.conditionalAssignment(tu.icmp(ICmpInst::ICMP_ULT,
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.load(rs2+ traits::X0, 0)), tu.constant(1,8),tu.constant(0,8)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 31);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,31);
         return returnValue;
     }
-
+    
     /* instruction 32: XOR */
-    compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("XOR_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 32);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,32);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.bitwise_xor(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.bitwise_xor(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.load(rs2+ traits::X0, 0)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 32);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,32);
         return returnValue;
     }
-
+    
     /* instruction 33: SRL */
-    compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __srl(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SRL_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 33);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,33);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.lshr(tu.load(rs1 + traits::X0, 0),
-                                                  (tu.bitwise_and(tu.load(rs2 + traits::X0, 0),
-                                                                  tu.constant((static_cast<uint32_t>(traits::XLEN) - 1), 64)))));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.lshr(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             (tu.bitwise_and(
+        	                tu.load(rs2+ traits::X0, 0),
+        	                tu.constant((static_cast<uint32_t>(traits:: XLEN)-1),64)))));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 33);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,33);
         return returnValue;
     }
-
+    
     /* instruction 34: SRA */
-    compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __sra(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("SRA_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 34);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,34);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext((tu.ashr(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true),
-                                                          (tu.bitwise_and(tu.load(rs2 + traits::X0, 0),
-                                                                          tu.constant((static_cast<uint32_t>(traits::XLEN) - 1), 64))))),
-                                                 32, false));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext((tu.ashr(
+        	             tu.ext(tu.load(rs1+ traits::X0, 0),32,true),
+        	             (tu.bitwise_and(
+        	                tu.load(rs2+ traits::X0, 0),
+        	                tu.constant((static_cast<uint32_t>(traits:: XLEN)-1),64))))),32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 34);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,34);
         return returnValue;
     }
-
+    
     /* instruction 35: OR */
-    compile_ret_t __or(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("OR_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 35);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,35);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.bitwise_or(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.bitwise_or(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.load(rs2+ traits::X0, 0)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 35);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,35);
         return returnValue;
     }
-
+    
     /* instruction 36: AND */
-    compile_ret_t __and(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("AND_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 36);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,36);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.bitwise_and(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0)));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.bitwise_and(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.load(rs2+ traits::X0, 0)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 36);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,36);
         return returnValue;
     }
-
+    
     /* instruction 37: FENCE */
-    compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __fence(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("FENCE_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 37);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,37);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t succ = ((bit_sub<20, 4>(instr)));
-        uint8_t pred = ((bit_sub<24, 4>(instr)));
-        uint8_t fm = ((bit_sub<28, 4>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t succ = ((bit_sub<20,4>(instr)));
+        uint8_t pred = ((bit_sub<24,4>(instr)));
+        uint8_t fm = ((bit_sub<28,4>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic =
-                fmt::format("{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"), fmt::arg("pred", pred),
-                            fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"),
+                fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        tu.write_mem(traits::FENCE, static_cast<uint32_t>(traits::fence), tu.constant((uint8_t)pred << 4 | succ, 8));
+        tu.write_mem(traits::FENCE, static_cast<uint32_t>(traits:: fence), tu.constant((uint8_t)pred<<4|succ,8));
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 37);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,37);
         return returnValue;
     }
-
+    
     /* instruction 38: ECALL */
-    compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("ECALL_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 38);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,38);
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ecall");
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         this->gen_raise_trap(tu, 0, 11);
         auto returnValue = std::make_tuple(TRAP);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 38);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,38);
         return returnValue;
     }
-
+    
     /* instruction 39: EBREAK */
-    compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("EBREAK_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 39);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,39);
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "ebreak");
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         this->gen_raise_trap(tu, 0, 3);
         auto returnValue = std::make_tuple(TRAP);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 39);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,39);
         return returnValue;
     }
-
+    
     /* instruction 40: MRET */
-    compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __mret(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("MRET_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 40);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,40);
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "mret");
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         this->gen_leave_trap(tu, 3);
         auto returnValue = std::make_tuple(TRAP);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 40);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,40);
         return returnValue;
     }
-
+    
     /* instruction 41: WFI */
-    compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("WFI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 41);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,41);
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "wfi");
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         this->gen_wait(tu, 1);
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 41);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,41);
         return returnValue;
     }
-
+    
     /* instruction 42: CSRRW */
-    compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("CSRRW_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 42);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,42);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto xrs1 = tu.assignment(tu.load(rs1 + traits::X0, 0), 32);
-            if(rd != 0) {
-                auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32);
-                tu.write_mem(traits::CSR, csr, xrs1);
-                tu.store(rd + traits::X0, xrd);
-            } else {
-                tu.write_mem(traits::CSR, csr, xrs1);
-            }
+        }
+        else{
+        	auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32);
+        	if(rd!=0){ auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
+        	tu.write_mem(traits::CSR, csr, xrs1);
+        	tu.store(rd + traits::X0,
+        	      xrd);
+        	}
+        	else{
+        		tu.write_mem(traits::CSR, csr, xrs1);
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 42);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,42);
         return returnValue;
     }
-
+    
     /* instruction 43: CSRRS */
-    compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("CSRRS_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 43);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,43);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32);
-            auto xrs1 = tu.assignment(tu.load(rs1 + traits::X0, 0), 32);
-            if(rs1 != 0) {
-                tu.write_mem(traits::CSR, csr, tu.bitwise_or(xrd, xrs1));
-            }
-            if(rd != 0) {
-                tu.store(rd + traits::X0, xrd);
-            }
+        }
+        else{
+        	auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
+        	auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32);
+        	if(rs1!=0) {
+        	    tu.write_mem(traits::CSR, csr, tu.bitwise_or(
+        	       xrd,
+        	       xrs1));
+        	}
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          xrd);
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 43);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,43);
         return returnValue;
     }
-
+    
     /* instruction 44: CSRRC */
-    compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("CSRRC_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 44);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,44);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32);
-            auto xrs1 = tu.assignment(tu.load(rs1 + traits::X0, 0), 32);
-            if(rs1 != 0) {
-                tu.write_mem(traits::CSR, csr, tu.bitwise_and(xrd, tu.logical_neg(xrs1)));
-            }
-            if(rd != 0) {
-                tu.store(rd + traits::X0, xrd);
-            }
+        }
+        else{
+        	auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
+        	auto xrs1 = tu.assignment(tu.load(rs1+ traits::X0, 0),32);
+        	if(rs1!=0) {
+        	    tu.write_mem(traits::CSR, csr, tu.bitwise_and(
+        	       xrd,
+        	       tu.logical_neg(xrs1)));
+        	}
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          xrd);
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 44);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,44);
         return returnValue;
     }
-
+    
     /* instruction 45: CSRRWI */
-    compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("CSRRWI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 45);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,45);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t zimm = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t zimm = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32);
-            tu.write_mem(traits::CSR, csr, tu.constant((uint32_t)zimm, 32));
-            if(rd != 0) {
-                tu.store(rd + traits::X0, xrd);
-            }
+        }
+        else{
+        	auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
+        	tu.write_mem(traits::CSR, csr, tu.constant((uint32_t)zimm,32));
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          xrd);
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 45);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,45);
         return returnValue;
     }
-
+    
     /* instruction 46: CSRRSI */
-    compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("CSRRSI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 46);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,46);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t zimm = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t zimm = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32);
-            if(zimm != 0) {
-                tu.write_mem(traits::CSR, csr, tu.bitwise_or(xrd, tu.constant((uint32_t)zimm, 32)));
-            }
-            if(rd != 0) {
-                tu.store(rd + traits::X0, xrd);
-            }
+        }
+        else{
+        	auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
+        	if(zimm!=0) {
+        	    tu.write_mem(traits::CSR, csr, tu.bitwise_or(
+        	       xrd,
+        	       tu.constant((uint32_t)zimm,32)));
+        	}
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          xrd);
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 46);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,46);
         return returnValue;
     }
-
+    
     /* instruction 47: CSRRCI */
-    compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("CSRRCI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 47);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,47);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t zimm = ((bit_sub<15, 5>(instr)));
-        uint16_t csr = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t zimm = ((bit_sub<15,5>(instr)));
+        uint16_t csr = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"),
+                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32), 32);
-            if(zimm != 0) {
-                tu.write_mem(traits::CSR, csr, tu.bitwise_and(xrd, tu.constant(~((uint32_t)zimm), 32)));
-            }
-            if(rd != 0) {
-                tu.store(rd + traits::X0, xrd);
-            }
+        }
+        else{
+        	auto xrd = tu.assignment(tu.read_mem(traits::CSR, csr, 32),32);
+        	if(zimm!=0) {
+        	    tu.write_mem(traits::CSR, csr, tu.bitwise_and(
+        	       xrd,
+        	       tu.constant(~ ((uint32_t)zimm),32)));
+        	}
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          xrd);
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 47);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,47);
         return returnValue;
     }
-
+    
     /* instruction 48: FENCE_I */
-    compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("FENCE_I_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 48);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,48);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint16_t imm = ((bit_sub<20, 12>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint16_t imm = ((bit_sub<20,12>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        tu.write_mem(traits::FENCE, static_cast<uint32_t>(traits::fencei), tu.constant(imm, 16));
-        auto returnValue = std::make_tuple(CONT);
-
+        tu.write_mem(traits::FENCE, static_cast<uint32_t>(traits:: fencei), tu.constant(imm,16));
+        auto returnValue = std::make_tuple(FLUSH);
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 48);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,48);
         return returnValue;
     }
-
+    
     /* instruction 49: MUL */
-    compile_ret_t __mul(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __mul(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("MUL_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 49);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,49);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 64, true),
-                                                    tu.ext(tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), 64, true))),
-                                            64, true),
-                                     64);
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext(res, 32, false));
-            }
+        }
+        else{
+        	auto res = tu.assignment(tu.ext((tu.mul(
+        	   tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,true),
+        	   tu.ext(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),64,true))),64,true),64);
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext(res,32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 49);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,49);
         return returnValue;
     }
-
+    
     /* instruction 50: MULH */
-    compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("MULH_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 50);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,50);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 64, true),
-                                                    tu.ext(tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), 64, true))),
-                                            64, true),
-                                     64);
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext((tu.ashr(res, tu.constant(static_cast<uint32_t>(traits::XLEN), 32))), 32, false));
-            }
+        }
+        else{
+        	auto res = tu.assignment(tu.ext((tu.mul(
+        	   tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,true),
+        	   tu.ext(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),64,true))),64,true),64);
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext((tu.ashr(
+        	             res,
+        	             tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 50);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,50);
         return returnValue;
     }
-
+    
     /* instruction 51: MULHSU */
-    compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("MULHSU_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 51);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,51);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto res = tu.assignment(tu.ext((tu.mul(tu.ext(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 64, true),
-                                                    tu.ext(tu.load(rs2 + traits::X0, 0), 64, false))),
-                                            64, true),
-                                     64);
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext((tu.ashr(res, tu.constant(static_cast<uint32_t>(traits::XLEN), 32))), 32, false));
-            }
+        }
+        else{
+        	auto res = tu.assignment(tu.ext((tu.mul(
+        	   tu.ext(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),64,true),
+        	   tu.ext(tu.load(rs2+ traits::X0, 0),64,false))),64,true),64);
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext((tu.ashr(
+        	             res,
+        	             tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 51);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,51);
         return returnValue;
     }
-
+    
     /* instruction 52: MULHU */
-    compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("MULHU_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 52);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,52);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto res = tu.assignment(
-                tu.ext((tu.mul(tu.ext(tu.load(rs1 + traits::X0, 0), 64, false), tu.ext(tu.load(rs2 + traits::X0, 0), 64, false))), 64,
-                       false),
-                64);
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext((tu.lshr(res, tu.constant(static_cast<uint32_t>(traits::XLEN), 32))), 32, false));
-            }
+        }
+        else{
+        	auto res = tu.assignment(tu.ext((tu.mul(
+        	   tu.ext(tu.load(rs1+ traits::X0, 0),64,false),
+        	   tu.ext(tu.load(rs2+ traits::X0, 0),64,false))),64,false),64);
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext((tu.lshr(
+        	             res,
+        	             tu.constant(static_cast<uint32_t>(traits:: XLEN),32))),32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 52);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,52);
         return returnValue;
     }
-
+    
     /* instruction 53: DIV */
-    compile_ret_t __div(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __div(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("DIV_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 53);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,53);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto dividend = tu.assignment(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), 32);
-            auto divisor = tu.assignment(tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), 32);
-            if(rd != 0) {
-                tu.open_if(tu.icmp(ICmpInst::ICMP_NE, divisor, tu.constant(0, 8)));
-                auto MMIN = tu.assignment(tu.constant(((uint32_t)1) << (static_cast<uint32_t>(traits::XLEN) - 1), 32), 32);
-                tu.open_if(tu.logical_and(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + traits::X0, 0), MMIN),
-                                          tu.icmp(ICmpInst::ICMP_EQ, divisor, tu.constant(-1, 8))));
-                tu.store(rd + traits::X0, MMIN);
-                tu.open_else();
-                tu.store(rd + traits::X0, tu.ext((tu.sdiv(dividend, divisor)), 32, false));
-                tu.close_scope();
-                tu.open_else();
-                tu.store(rd + traits::X0, tu.constant((uint32_t)-1, 32));
-                tu.close_scope();
-            }
+        }
+        else{
+        	auto dividend = tu.assignment(tu.ext(tu.load(rs1+ traits::X0, 0),32,true),32);
+        	auto divisor = tu.assignment(tu.ext(tu.load(rs2+ traits::X0, 0),32,true),32);
+        	if(rd!=0){ tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
+        	   divisor,
+        	   tu.constant(0,8)));
+        	auto MMIN = tu.assignment(tu.constant(((uint32_t)1)<<(static_cast<uint32_t>(traits:: XLEN)-1),32),32);
+        	tu.open_if(tu.logical_and(
+        	   tu.icmp(ICmpInst::ICMP_EQ,
+        	      tu.load(rs1+ traits::X0, 0),
+        	      MMIN),
+        	   tu.icmp(ICmpInst::ICMP_EQ,
+        	      divisor,
+        	      tu.constant(- 1,8))));
+        	tu.store(rd + traits::X0,
+        	      MMIN);
+        	tu.open_else();
+        	tu.store(rd + traits::X0,
+        	      tu.ext((tu.sdiv(
+        	         dividend,
+        	         divisor)),32,false));
+        	tu.close_scope();
+        	tu.open_else();
+        	tu.store(rd + traits::X0,
+        	      tu.constant((uint32_t)- 1,32));
+        	tu.close_scope();
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 53);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,53);
         return returnValue;
     }
-
+    
     /* instruction 54: DIVU */
-    compile_ret_t __divu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __divu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("DIVU_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 54);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,54);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2 + traits::X0, 0), tu.constant(0, 8)));
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext((tu.udiv(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false));
-            }
-            tu.open_else();
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.constant((uint32_t)-1, 32));
-            }
-            tu.close_scope();
+        }
+        else{
+        	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
+        	   tu.load(rs2+ traits::X0, 0),
+        	   tu.constant(0,8)));
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext((tu.udiv(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.load(rs2+ traits::X0, 0))),32,false));
+        	}
+        	tu.open_else();
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.constant((uint32_t)- 1,32));
+        	}
+        	tu.close_scope();
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 54);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,54);
         return returnValue;
     }
-
+    
     /* instruction 55: REM */
-    compile_ret_t __rem(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __rem(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("REM_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 55);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,55);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2 + traits::X0, 0), tu.constant(0, 8)));
-            auto MMIN = tu.assignment(tu.constant((uint32_t)1 << (static_cast<uint32_t>(traits::XLEN) - 1), 32), 32);
-            tu.open_if(tu.logical_and(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + traits::X0, 0), MMIN),
-                                      tu.icmp(ICmpInst::ICMP_EQ, tu.ext(tu.load(rs2 + traits::X0, 0), 32, true), tu.constant(-1, 8))));
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.constant(0, 8));
-            }
-            tu.open_else();
-            if(rd != 0) {
-                tu.store(rd + traits::X0,
-                         tu.ext((tu.srem(tu.ext(tu.load(rs1 + traits::X0, 0), 32, true), tu.ext(tu.load(rs2 + traits::X0, 0), 32, true))),
-                                32, false));
-            }
-            tu.close_scope();
-            tu.open_else();
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0));
-            }
-            tu.close_scope();
+        }
+        else{
+        	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
+        	   tu.load(rs2+ traits::X0, 0),
+        	   tu.constant(0,8)));
+        	auto MMIN = tu.assignment(tu.constant((uint32_t)1<<(static_cast<uint32_t>(traits:: XLEN)-1),32),32);
+        	tu.open_if(tu.logical_and(
+        	   tu.icmp(ICmpInst::ICMP_EQ,
+        	      tu.load(rs1+ traits::X0, 0),
+        	      MMIN),
+        	   tu.icmp(ICmpInst::ICMP_EQ,
+        	      tu.ext(tu.load(rs2+ traits::X0, 0),32,true),
+        	      tu.constant(- 1,8))));
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.constant(0,8));
+        	}
+        	tu.open_else();
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext((tu.srem(
+        	             tu.ext(tu.load(rs1+ traits::X0, 0),32,true),
+        	             tu.ext(tu.load(rs2+ traits::X0, 0),32,true))),32,false));
+        	}
+        	tu.close_scope();
+        	tu.open_else();
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.load(rs1+ traits::X0, 0));
+        	}
+        	tu.close_scope();
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 55);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,55);
         return returnValue;
     }
-
+    
     /* instruction 56: REMU */
-    compile_ret_t __remu(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __remu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("REMU_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 56);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,56);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<15, 5>(instr)));
-        uint8_t rs2 = ((bit_sub<20, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 4;
+        pc=pc+ 4;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rs1 >= static_cast<uint32_t>(traits::RFS) ||
-           rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rs1>=static_cast<uint32_t>(traits:: RFS)||rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs2 + traits::X0, 0), tu.constant(0, 8)));
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.urem(tu.load(rs1 + traits::X0, 0), tu.load(rs2 + traits::X0, 0)));
-            }
-            tu.open_else();
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.load(rs1 + traits::X0, 0));
-            }
-            tu.close_scope();
+        }
+        else{
+        	tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
+        	   tu.load(rs2+ traits::X0, 0),
+        	   tu.constant(0,8)));
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.urem(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.load(rs2+ traits::X0, 0)));
+        	}
+        	tu.open_else();
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.load(rs1+ traits::X0, 0));
+        	}
+        	tu.close_scope();
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 56);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,56);
         return returnValue;
     }
-
+    
     /* instruction 57: C__ADDI4SPN */
-    compile_ret_t __c__addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__ADDI4SPN_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 57);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,57);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<2, 3>(instr)));
-        uint16_t imm =
-            ((bit_sub<5, 1>(instr) << 3) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<7, 4>(instr) << 6) | (bit_sub<11, 2>(instr) << 4));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<2,3>(instr)));
+        uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"), fmt::arg("rd", name(8 + rd)),
-                                        fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__addi4spn"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         if(imm) {
-            tu.store(rd + 8 + traits::X0, tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant(imm, 16))), 32, false));
-        } else {
-            this->gen_raise_trap(tu, 0, 2);
+            tu.store(rd+8 + traits::X0,
+                  tu.ext((tu.add(
+                     tu.load(2+ traits::X0, 0),
+                     tu.constant(imm,16))),32,false));
+        }
+        else{
+        	this->gen_raise_trap(tu, 0, 2);
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 57);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,57);
         return returnValue;
     }
-
+    
     /* instruction 58: C__LW */
-    compile_ret_t __c__lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__LW_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 58);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,58);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<2, 3>(instr)));
-        uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<2,3>(instr)));
+        uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"),
-                                        fmt::arg("rd", name(8 + rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__lw"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        auto offs = tu.assignment(tu.ext((tu.add(tu.load(rs1 + 8 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32);
-        tu.store(rd + 8 + traits::X0, tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32), 32, true), 32, false));
+        auto offs = tu.assignment(tu.ext((tu.add(
+           tu.load(rs1+8+ traits::X0, 0),
+           tu.constant(uimm,8))),32,false),32);
+        tu.store(rd+8 + traits::X0,
+              tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false));
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 58);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,58);
         return returnValue;
     }
-
+    
     /* instruction 59: C__SW */
-    compile_ret_t __c__sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__SW_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 59);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,59);
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 3>(instr)));
-        uint8_t uimm = ((bit_sub<5, 1>(instr) << 6) | (bit_sub<6, 1>(instr) << 2) | (bit_sub<10, 3>(instr) << 3));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+        uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"),
-                                        fmt::arg("rs2", name(8 + rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8 + rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "c__sw"),
+                fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        auto offs = tu.assignment(tu.ext((tu.add(tu.load(rs1 + 8 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32);
-        tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2 + 8 + traits::X0, 0), 32, false));
+        auto offs = tu.assignment(tu.ext((tu.add(
+           tu.load(rs1+8+ traits::X0, 0),
+           tu.constant(uimm,8))),32,false),32);
+        tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2+8+ traits::X0, 0),32,false));
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 59);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,59);
         return returnValue;
     }
-
+    
     /* instruction 60: C__ADDI */
-    compile_ret_t __c__addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__ADDI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 60);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,60);
         uint64_t PC = pc.val;
-        uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__addi"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rs1 != 0) {
-                tu.store(rs1 + traits::X0, tu.ext((tu.add(tu.load(rs1 + traits::X0, 0), tu.constant((int8_t)sext<6>(imm), 8))), 32, false));
-            }
+        }
+        else{
+        	if(rs1!=0) {
+        	    tu.store(rs1 + traits::X0,
+        	          tu.ext((tu.add(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.constant((int8_t)sext<6>(imm),8))),32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 60);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,60);
         return returnValue;
     }
-
+    
     /* instruction 61: C__NOP */
-    compile_ret_t __c__nop(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__nop(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__NOP_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 61);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,61);
         uint64_t PC = pc.val;
-        uint8_t nzimm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
-        if(this->disass_enabled) {
+        uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c__nop");
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 61);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,61);
         return returnValue;
     }
-
+    
     /* instruction 62: C__JAL */
-    compile_ret_t __c__jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__JAL_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 62);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,62);
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) |
-             (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__jal"),
+                fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        tu.store(1 + traits::X0, tu.constant((uint32_t)(PC + 2), 32));
-        auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<12>(imm)), 32);
+        tu.store(1 + traits::X0,
+              tu.constant((uint32_t)(PC+2),32));
+        auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<12>(imm)),32);
         tu.store(traits::NEXT_PC, PC_val_v);
         tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 62);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,62);
         return returnValue;
     }
-
+    
     /* instruction 63: C__LI */
-    compile_ret_t __c__li(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__li(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__LI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 63);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,63);
         uint64_t PC = pc.val;
-        uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__li"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.constant((uint32_t)((int8_t)sext<6>(imm)), 32));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.constant((uint32_t)((int8_t)sext<6>(imm)),32));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 63);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,63);
         return returnValue;
     }
-
+    
     /* instruction 64: C__LUI */
-    compile_ret_t __c__lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__LUI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 64);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,64);
         uint64_t PC = pc.val;
-        uint32_t imm = ((bit_sub<2, 5>(instr) << 12) | (bit_sub<12, 1>(instr) << 17));
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "c__lui"),
+                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(imm == 0 || rd >= static_cast<uint32_t>(traits::RFS)) {
+        if(imm==0||rd>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
         }
-        if(rd != 0) {
-            tu.store(rd + traits::X0, tu.constant((uint32_t)((int32_t)sext<18>(imm)), 32));
+        if(rd!=0) {
+            tu.store(rd + traits::X0,
+                  tu.constant((uint32_t)((int32_t)sext<18>(imm)),32));
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 64);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,64);
         return returnValue;
     }
-
+    
     /* instruction 65: C__ADDI16SP */
-    compile_ret_t __c__addi16sp(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__addi16sp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__ADDI16SP_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 65);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,65);
         uint64_t PC = pc.val;
-        uint16_t nzimm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 7) | (bit_sub<5, 1>(instr) << 6) |
-                          (bit_sub<6, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 9));
-        if(this->disass_enabled) {
+        uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"), fmt::arg("nzimm", nzimm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "c__addi16sp"),
+                fmt::arg("nzimm", nzimm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         if(nzimm) {
-            tu.store(2 + traits::X0, tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant((int16_t)sext<10>(nzimm), 16))), 32, false));
-        } else {
-            this->gen_raise_trap(tu, 0, 2);
+            tu.store(2 + traits::X0,
+                  tu.ext((tu.add(
+                     tu.load(2+ traits::X0, 0),
+                     tu.constant((int16_t)sext<10>(nzimm),16))),32,false));
+        }
+        else{
+        	this->gen_raise_trap(tu, 0, 2);
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 65);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,65);
         return returnValue;
     }
-
+    
     /* instruction 66: __reserved_clui */
-    compile_ret_t ____reserved_clui(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t ____reserved_clui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("__reserved_clui_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 66);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,66);
         uint64_t PC = pc.val;
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "__reserved_clui");
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         this->gen_raise_trap(tu, 0, 2);
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 66);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,66);
         return returnValue;
     }
-
+    
     /* instruction 67: C__SRLI */
-    compile_ret_t __c__srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__SRLI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 67);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,67);
         uint64_t PC = pc.val;
-        uint8_t shamt = ((bit_sub<2, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t shamt = ((bit_sub<2,5>(instr)));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"), fmt::arg("rs1", name(8 + rs1)),
-                                        fmt::arg("shamt", shamt));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srli"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        tu.store(rs1 + 8 + traits::X0, tu.lshr(tu.load(rs1 + 8 + traits::X0, 0), tu.constant(shamt, 8)));
+        tu.store(rs1+8 + traits::X0,
+              tu.lshr(
+                 tu.load(rs1+8+ traits::X0, 0),
+                 tu.constant(shamt,8)));
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 67);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,67);
         return returnValue;
     }
-
+    
     /* instruction 68: C__SRAI */
-    compile_ret_t __c__srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__SRAI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 68);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,68);
         uint64_t PC = pc.val;
-        uint8_t shamt = ((bit_sub<2, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t shamt = ((bit_sub<2,5>(instr)));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"), fmt::arg("rs1", name(8 + rs1)),
-                                        fmt::arg("shamt", shamt));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c__srai"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(shamt) {
-            tu.store(rs1 + 8 + traits::X0,
-                     tu.ext((tu.ashr((tu.ext(tu.load(rs1 + 8 + traits::X0, 0), 32, true)), tu.constant(shamt, 8))), 32, false));
-        } else {
-            if(static_cast<uint32_t>(traits::XLEN) == 128) {
-                tu.store(rs1 + 8 + traits::X0,
-                         tu.ext((tu.ashr((tu.ext(tu.load(rs1 + 8 + traits::X0, 0), 32, true)), tu.constant(64, 8))), 32, false));
-            }
+        if(shamt){ tu.store(rs1+8 + traits::X0,
+              tu.ext((tu.ashr(
+                 (tu.ext(tu.load(rs1+8+ traits::X0, 0),32,true)),
+                 tu.constant(shamt,8))),32,false));
+        }
+        else{
+        	if(static_cast<uint32_t>(traits:: XLEN)==128){ tu.store(rs1+8 + traits::X0,
+        	      tu.ext((tu.ashr(
+        	         (tu.ext(tu.load(rs1+8+ traits::X0, 0),32,true)),
+        	         tu.constant(64,8))),32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 68);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,68);
         return returnValue;
     }
-
+    
     /* instruction 69: C__ANDI */
-    compile_ret_t __c__andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__ANDI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 69);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,69);
         uint64_t PC = pc.val;
-        uint8_t imm = ((bit_sub<2, 5>(instr)) | (bit_sub<12, 1>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"), fmt::arg("rs1", name(8 + rs1)),
-                                        fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__andi"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        tu.store(rs1 + 8 + traits::X0,
-                 tu.ext((tu.bitwise_and(tu.load(rs1 + 8 + traits::X0, 0), tu.constant((int8_t)sext<6>(imm), 8))), 32, false));
+        tu.store(rs1+8 + traits::X0,
+              tu.ext((tu.bitwise_and(
+                 tu.load(rs1+8+ traits::X0, 0),
+                 tu.constant((int8_t)sext<6>(imm),8))),32,false));
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 69);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,69);
         return returnValue;
     }
-
+    
     /* instruction 70: C__SUB */
-    compile_ret_t __c__sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__SUB_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 70);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,70);
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 3>(instr)));
-        uint8_t rd = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+        uint8_t rd = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"), fmt::arg("rd", name(8 + rd)),
-                                        fmt::arg("rs2", name(8 + rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__sub"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        tu.store(rd + 8 + traits::X0, tu.ext((tu.sub(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0))), 32, false));
+        tu.store(rd+8 + traits::X0,
+              tu.ext((tu.sub(
+                 tu.load(rd+8+ traits::X0, 0),
+                 tu.load(rs2+8+ traits::X0, 0))),32,false));
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 70);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,70);
         return returnValue;
     }
-
+    
     /* instruction 71: C__XOR */
-    compile_ret_t __c__xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__XOR_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 71);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,71);
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 3>(instr)));
-        uint8_t rd = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+        uint8_t rd = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"), fmt::arg("rd", name(8 + rd)),
-                                        fmt::arg("rs2", name(8 + rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__xor"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        tu.store(rd + 8 + traits::X0, tu.bitwise_xor(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0)));
+        tu.store(rd+8 + traits::X0,
+              tu.bitwise_xor(
+                 tu.load(rd+8+ traits::X0, 0),
+                 tu.load(rs2+8+ traits::X0, 0)));
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 71);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,71);
         return returnValue;
     }
-
+    
     /* instruction 72: C__OR */
-    compile_ret_t __c__or(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__OR_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 72);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,72);
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 3>(instr)));
-        uint8_t rd = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+        uint8_t rd = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"), fmt::arg("rd", name(8 + rd)),
-                                        fmt::arg("rs2", name(8 + rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__or"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        tu.store(rd + 8 + traits::X0, tu.bitwise_or(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0)));
+        tu.store(rd+8 + traits::X0,
+              tu.bitwise_or(
+                 tu.load(rd+8+ traits::X0, 0),
+                 tu.load(rs2+8+ traits::X0, 0)));
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 72);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,72);
         return returnValue;
     }
-
+    
     /* instruction 73: C__AND */
-    compile_ret_t __c__and(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__AND_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 73);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,73);
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 3>(instr)));
-        uint8_t rd = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+        uint8_t rd = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"), fmt::arg("rd", name(8 + rd)),
-                                        fmt::arg("rs2", name(8 + rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__and"),
+                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        tu.store(rd + 8 + traits::X0, tu.bitwise_and(tu.load(rd + 8 + traits::X0, 0), tu.load(rs2 + 8 + traits::X0, 0)));
+        tu.store(rd+8 + traits::X0,
+              tu.bitwise_and(
+                 tu.load(rd+8+ traits::X0, 0),
+                 tu.load(rs2+8+ traits::X0, 0)));
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 73);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,73);
         return returnValue;
     }
-
+    
     /* instruction 74: C__J */
-    compile_ret_t __c__j(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__j(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__J_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 74);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,74);
         uint64_t PC = pc.val;
-        uint16_t imm =
-            ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 3>(instr) << 1) | (bit_sub<6, 1>(instr) << 7) | (bit_sub<7, 1>(instr) << 6) |
-             (bit_sub<8, 1>(instr) << 10) | (bit_sub<9, 2>(instr) << 8) | (bit_sub<11, 1>(instr) << 4) | (bit_sub<12, 1>(instr) << 11));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"), fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c__j"),
+                fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<12>(imm)), 32);
+        auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<12>(imm)),32);
         tu.store(traits::NEXT_PC, PC_val_v);
         tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 74);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,74);
         return returnValue;
     }
-
+    
     /* instruction 75: C__BEQZ */
-    compile_ret_t __c__beqz(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__beqz(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__BEQZ_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 75);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,75);
         uint64_t PC = pc.val;
-        uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) |
-                        (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"), fmt::arg("rs1", name(8 + rs1)),
-                                        fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__beqz"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        tu.open_if(tu.icmp(ICmpInst::ICMP_EQ, tu.load(rs1 + 8 + traits::X0, 0), tu.constant(0, 8)));
-        auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<9>(imm)), 32);
+        tu.open_if(tu.icmp(ICmpInst::ICMP_EQ,
+           tu.load(rs1+8+ traits::X0, 0),
+           tu.constant(0,8)));
+        auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32);
         tu.store(traits::NEXT_PC, PC_val_v);
         tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
         tu.close_scope();
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 75);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,75);
         return returnValue;
     }
-
+    
     /* instruction 76: C__BNEZ */
-    compile_ret_t __c__bnez(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__bnez(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__BNEZ_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 76);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,76);
         uint64_t PC = pc.val;
-        uint16_t imm = ((bit_sub<2, 1>(instr) << 5) | (bit_sub<3, 2>(instr) << 1) | (bit_sub<5, 2>(instr) << 6) |
-                        (bit_sub<10, 2>(instr) << 3) | (bit_sub<12, 1>(instr) << 8));
-        uint8_t rs1 = ((bit_sub<7, 3>(instr)));
-        if(this->disass_enabled) {
+        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
+        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"), fmt::arg("rs1", name(8 + rs1)),
-                                        fmt::arg("imm", imm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c__bnez"),
+                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        tu.open_if(tu.icmp(ICmpInst::ICMP_NE, tu.load(rs1 + 8 + traits::X0, 0), tu.constant(0, 8)));
-        auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC + (int16_t)sext<9>(imm)), 32);
+        tu.open_if(tu.icmp(ICmpInst::ICMP_NE,
+           tu.load(rs1+8+ traits::X0, 0),
+           tu.constant(0,8)));
+        auto PC_val_v = tu.assignment("PC_val", (uint32_t)(PC+(int16_t)sext<9>(imm)),32);
         tu.store(traits::NEXT_PC, PC_val_v);
         tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
         tu.close_scope();
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 76);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,76);
         return returnValue;
     }
-
+    
     /* instruction 77: C__SLLI */
-    compile_ret_t __c__slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__SLLI_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 77);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,77);
         uint64_t PC = pc.val;
-        uint8_t nzuimm = ((bit_sub<2, 5>(instr)));
-        uint8_t rs1 = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t nzuimm = ((bit_sub<2,5>(instr)));
+        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"), fmt::arg("rs1", name(rs1)),
-                                        fmt::arg("nzuimm", nzuimm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "c__slli"),
+                fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rs1 != 0) {
-                tu.store(rs1 + traits::X0, tu.shl(tu.load(rs1 + traits::X0, 0), tu.constant(nzuimm, 8)));
-            }
+        }
+        else{
+        	if(rs1!=0) {
+        	    tu.store(rs1 + traits::X0,
+        	          tu.shl(
+        	             tu.load(rs1+ traits::X0, 0),
+        	             tu.constant(nzuimm,8)));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 77);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,77);
         return returnValue;
     }
-
+    
     /* instruction 78: C__LWSP */
-    compile_ret_t __c__lwsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__lwsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__LWSP_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 78);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,78);
         uint64_t PC = pc.val;
-        uint8_t uimm = ((bit_sub<2, 2>(instr) << 6) | (bit_sub<4, 3>(instr) << 2) | (bit_sub<12, 1>(instr) << 5));
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("uimm", uimm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "c__lwsp"),
+                fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS) || rd == 0) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)||rd==0) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto offs = tu.assignment(tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32);
-            tu.store(rd + traits::X0, tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32), 32, true), 32, false));
+        }
+        else{
+        	auto offs = tu.assignment(tu.ext((tu.add(
+        	   tu.load(2+ traits::X0, 0),
+        	   tu.constant(uimm,8))),32,false),32);
+        	tu.store(rd + traits::X0,
+        	      tu.ext(tu.ext(tu.read_mem(traits::MEM, offs, 32),32,true),32,false));
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 78);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,78);
         return returnValue;
     }
-
+    
     /* instruction 79: C__MV */
-    compile_ret_t __c__mv(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__mv(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__MV_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 79);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,79);
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 5>(instr)));
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,5>(instr)));
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__mv"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.load(rs2 + traits::X0, 0));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.load(rs2+ traits::X0, 0));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 79);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,79);
         return returnValue;
     }
-
+    
     /* instruction 80: C__JR */
-    compile_ret_t __c__jr(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__jr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__JR_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 80);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,80);
         uint64_t PC = pc.val;
-        uint8_t rs1 = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jr"),
+                fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs1 && rs1 < static_cast<uint32_t>(traits::RFS)) {
-            auto PC_val_v = tu.assignment(
-                "PC_val", tu.bitwise_and(tu.load(rs1 % static_cast<uint32_t>(traits::RFS) + traits::X0, 0), tu.constant(~0x1, 8)), 32);
-            tu.store(traits::NEXT_PC, PC_val_v);
-            tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
-        } else {
-            this->gen_raise_trap(tu, 0, 2);
+        if(rs1&&rs1<static_cast<uint32_t>(traits:: RFS)){ auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
+           tu.load(rs1%static_cast<uint32_t>(traits:: RFS)+ traits::X0, 0),
+           tu.constant(~ 1,32)),32);
+        tu.store(traits::NEXT_PC, PC_val_v);
+        tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
+        }
+        else{
+        	this->gen_raise_trap(tu, 0, 2);
         }
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 80);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,80);
         return returnValue;
     }
-
+    
     /* instruction 81: __reserved_cmv */
-    compile_ret_t ____reserved_cmv(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t ____reserved_cmv(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("__reserved_cmv_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 81);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,81);
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "__reserved_cmv");
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         this->gen_raise_trap(tu, 0, 2);
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 81);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,81);
         return returnValue;
     }
-
+    
     /* instruction 82: C__ADD */
-    compile_ret_t __c__add(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__ADD_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 82);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,82);
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 5>(instr)));
-        uint8_t rd = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,5>(instr)));
+        uint8_t rd = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"), fmt::arg("rd", name(rd)),
-                                        fmt::arg("rs2", name(rs2)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "c__add"),
+                fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rd >= static_cast<uint32_t>(traits::RFS)) {
+        if(rd>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            if(rd != 0) {
-                tu.store(rd + traits::X0, tu.ext((tu.add(tu.load(rd + traits::X0, 0), tu.load(rs2 + traits::X0, 0))), 32, false));
-            }
+        }
+        else{
+        	if(rd!=0) {
+        	    tu.store(rd + traits::X0,
+        	          tu.ext((tu.add(
+        	             tu.load(rd+ traits::X0, 0),
+        	             tu.load(rs2+ traits::X0, 0))),32,false));
+        	}
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 82);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,82);
         return returnValue;
     }
-
+    
     /* instruction 83: C__JALR */
-    compile_ret_t __c__jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__JALR_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 83);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,83);
         uint64_t PC = pc.val;
-        uint8_t rs1 = ((bit_sub<7, 5>(instr)));
-        if(this->disass_enabled) {
+        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"), fmt::arg("rs1", name(rs1)));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "c__jalr"),
+                fmt::arg("rs1", name(rs1)));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs1 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs1>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto new_pc = tu.assignment(tu.load(rs1 + traits::X0, 0), 32);
-            tu.store(1 + traits::X0, tu.constant((uint32_t)(PC + 2), 32));
-            auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(new_pc, tu.constant(~0x1, 8)), 32);
-            tu.store(traits::NEXT_PC, PC_val_v);
-            tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
+        }
+        else{
+        	auto new_pc = tu.assignment(tu.load(rs1+ traits::X0, 0),32);
+        	tu.store(1 + traits::X0,
+        	      tu.constant((uint32_t)(PC+2),32));
+        	auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
+        	   new_pc,
+        	   tu.constant(~ 1,32)),32);
+        	tu.store(traits::NEXT_PC, PC_val_v);
+        	tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
         }
         auto returnValue = std::make_tuple(BRANCH);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 83);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,83);
         return returnValue;
     }
-
+    
     /* instruction 84: C__EBREAK */
-    compile_ret_t __c__ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__EBREAK_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 84);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,84);
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c__ebreak");
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         this->gen_raise_trap(tu, 0, 3);
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 84);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,84);
         return returnValue;
     }
-
+    
     /* instruction 85: C__SWSP */
-    compile_ret_t __c__swsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __c__swsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("C__SWSP_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 85);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,85);
         uint64_t PC = pc.val;
-        uint8_t rs2 = ((bit_sub<2, 5>(instr)));
-        uint8_t uimm = ((bit_sub<7, 2>(instr) << 6) | (bit_sub<9, 4>(instr) << 2));
-        if(this->disass_enabled) {
+        uint8_t rs2 = ((bit_sub<2,5>(instr)));
+        uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
+        if(this->disass_enabled){
             /* generate console output when executing the command */
-            auto mnemonic = fmt::format("{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"), fmt::arg("rs2", name(rs2)),
-                                        fmt::arg("uimm", uimm));
+            auto mnemonic = fmt::format(
+                "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "c__swsp"),
+                fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic);
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
-        if(rs2 >= static_cast<uint32_t>(traits::RFS)) {
+        if(rs2>=static_cast<uint32_t>(traits:: RFS)) {
             this->gen_raise_trap(tu, 0, 2);
-        } else {
-            auto offs = tu.assignment(tu.ext((tu.add(tu.load(2 + traits::X0, 0), tu.constant(uimm, 8))), 32, false), 32);
-            tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2 + traits::X0, 0), 32, false));
+        }
+        else{
+        	auto offs = tu.assignment(tu.ext((tu.add(
+        	   tu.load(2+ traits::X0, 0),
+        	   tu.constant(uimm,8))),32,false),32);
+        	tu.write_mem(traits::MEM, offs, tu.ext(tu.load(rs2+ traits::X0, 0),32,false));
         }
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 85);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,85);
         return returnValue;
     }
-
+    
     /* instruction 86: DII */
-    compile_ret_t __dii(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t __dii(virt_addr_t& pc, code_word_t instr, tu_builder& tu){
         tu("DII_{:#010x}:", pc.val);
-        vm_base<ARCH>::gen_sync(tu, PRE_SYNC, 86);
+        vm_base<ARCH>::gen_sync(tu, PRE_SYNC,86);
         uint64_t PC = pc.val;
-        if(this->disass_enabled) {
+        if(this->disass_enabled){
             /* generate console output when executing the command */
             tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "dii");
         }
         auto cur_pc_val = tu.constant(pc.val, traits::reg_bit_widths[traits::PC]);
-        pc = pc + 2;
+        pc=pc+ 2;
         gen_set_pc(tu, pc, traits::NEXT_PC);
         tu.open_scope();
         this->gen_raise_trap(tu, 0, 2);
         auto returnValue = std::make_tuple(CONT);
-
+        
         tu.close_scope();
-        gen_trap_check(tu);
-        vm_base<ARCH>::gen_sync(tu, POST_SYNC, 86);
+        gen_trap_check(tu);        
+        vm_base<ARCH>::gen_sync(tu, POST_SYNC,86);
         return returnValue;
     }
-
+    
     /****************************************************************************
      * end opcode definitions
      ****************************************************************************/
-    compile_ret_t illegal_intruction(virt_addr_t& pc, code_word_t instr, tu_builder& tu) {
+    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr, tu_builder& tu) {
         vm_impl::gen_sync(tu, iss::PRE_SYNC, instr_descr.size());
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
-        gen_raise_trap(tu, 0, 2); // illegal instruction trap
+        gen_raise_trap(tu, 0, 2);     // illegal instruction trap
         vm_impl::gen_sync(tu, iss::POST_SYNC, instr_descr.size());
         vm_impl::gen_trap_check(tu);
         return BRANCH;
     }
+    
+    //decoding functionality
 
-    // decoding functionality
-
-    void populate_decoding_tree(decoding_tree_node* root) {
-        // create submask
-        for(auto instr : root->instrs) {
+    void populate_decoding_tree(decoding_tree_node* root){
+        //create submask
+        for(auto instr: root->instrs){
             root->submask &= instr.mask;
         }
-        // put each instr according to submask&encoding into children
-        for(auto instr : root->instrs) {
+        //put each instr according to submask&encoding into children
+        for(auto instr: root->instrs){
             bool foundMatch = false;
-            for(auto child : root->children) {
-                // use value as identifying trait
-                if(child->value == (instr.value & root->submask)) {
+            for(auto child: root->children){
+                //use value as identifying trait
+                if(child->value == (instr.value&root->submask)){
                     child->instrs.push_back(instr);
                     foundMatch = true;
                 }
             }
-            if(!foundMatch) {
-                decoding_tree_node* child = new decoding_tree_node(instr.value & root->submask);
+            if(!foundMatch){
+                decoding_tree_node* child = new decoding_tree_node(instr.value&root->submask);
                 child->instrs.push_back(instr);
                 root->children.push_back(child);
             }
         }
         root->instrs.clear();
-        // call populate_decoding_tree for all children
-        if(root->children.size() > 1)
-            for(auto child : root->children) {
-                populate_decoding_tree(child);
+        //call populate_decoding_tree for all children
+        if(root->children.size() >1)
+            for(auto child: root->children){
+                populate_decoding_tree(child);      
             }
-        else {
-            // sort instrs by value of the mask, this works bc we want to have the least restrictive one last
-            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(),
-                      [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) { return instr1.mask > instr2.mask; });
+        else{
+            //sort instrs by value of the mask, this works bc we want to have the least restrictive one last
+            std::sort(root->children[0]->instrs.begin(), root->children[0]->instrs.end(), [](const instruction_descriptor& instr1, const instruction_descriptor& instr2) {
+            return instr1.mask > instr2.mask;
+            }); 
         }
     }
-    compile_func decode_instr(decoding_tree_node* node, code_word_t word) {
-        if(!node->children.size()) {
-            if(node->instrs.size() == 1)
-                return node->instrs[0].op;
-            for(auto instr : node->instrs) {
-                if((instr.mask & word) == instr.value)
-                    return instr.op;
+    compile_func decode_instr(decoding_tree_node* node, code_word_t word){
+        if(!node->children.size()){
+            if(node->instrs.size() == 1) return node->instrs[0].op;
+            for(auto instr : node->instrs){
+                if((instr.mask&word) == instr.value) return instr.op;
             }
-        } else {
-            for(auto child : node->children) {
-                if(child->value == (node->submask & word)) {
+        }
+        else{
+            for(auto child : node->children){
+                if (child->value == (node->submask&word)){
                     return decode_instr(child, word);
-                }
-            }
+                }  
+            }  
         }
         return nullptr;
     }
@@ -3273,41 +3570,40 @@ template <typename CODE_WORD> void debug_fn(CODE_WORD instr) {
 template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
 
 template <typename ARCH>
-vm_impl<ARCH>::vm_impl(ARCH& core, unsigned core_id, unsigned cluster_id)
+vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
     root = new decoding_tree_node(std::numeric_limits<uint32_t>::max());
-    for(auto instr : instr_descr) {
+    for(auto instr:instr_descr){
         root->instrs.push_back(instr);
     }
     populate_decoding_tree(root);
 }
 
 template <typename ARCH>
-std::tuple<continuation_e> vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, tu_builder& tu) {
+std::tuple<continuation_e>
+vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, tu_builder& tu) {
     // we fetch at max 4 byte, alignment is 2
-    enum { TRAP_ID = 1 << 16 };
+    enum {TRAP_ID=1<<16};
     code_word_t instr = 0;
     phys_addr_t paddr(pc);
     if(this->core.has_mmu())
         paddr = this->core.virt2phys(pc);
-    // TODO: re-add page handling
-    //    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
-    //        auto res = this->core.read(paddr, 2, data);
-    //        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
-    //        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
-    //            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
-    //        }
-    //    } else {
-    auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
-    if(res != iss::Ok)
-        throw trap_access(TRAP_ID, pc.val);
-    //    }
-    if(instr == 0x0000006f || (instr & 0xffff) == 0xa001)
-        throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+    //TODO: re-add page handling
+//    if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
+//        auto res = this->core.read(paddr, 2, data);
+//        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//        if ((insn & 0x3) == 0x3) { // this is a 32bit instruction
+//            res = this->core.read(this->core.v2p(pc + 2), 2, data + 2);
+//        }
+//    } else {
+        auto res = this->core.read(paddr, 4, reinterpret_cast<uint8_t*>(&instr));
+        if (res != iss::Ok) throw trap_access(TRAP_ID, pc.val);
+//    }
+    if (instr == 0x0000006f || (instr&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
     // curr pc on stack
     ++inst_cnt;
     auto f = decode_instr(root, instr);
-    if(f == nullptr) {
+    if (f == nullptr) {
         f = &this_class::illegal_intruction;
     }
     return (this->*f)(pc, instr, tu);
@@ -3315,7 +3611,7 @@ std::tuple<continuation_e> vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t&
 
 template <typename ARCH> void vm_impl<ARCH>::gen_raise_trap(tu_builder& tu, uint16_t trap_id, uint16_t cause) {
     tu("  *trap_state = {:#x};", 0x80 << 24 | (cause << 16) | trap_id);
-    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
+    tu.store(traits::NEXT_PC, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
 }
 
 template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsigned lvl) {
@@ -3324,25 +3620,26 @@ template <typename ARCH> void vm_impl<ARCH>::gen_leave_trap(tu_builder& tu, unsi
     tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
 }
 
-template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {}
+template <typename ARCH> void vm_impl<ARCH>::gen_wait(tu_builder& tu, unsigned type) {
+}
 
 template <typename ARCH> void vm_impl<ARCH>::gen_trap_behavior(tu_builder& tu) {
     tu("trap_entry:");
-    this->gen_sync(tu, POST_SYNC, -1);
+    this->gen_sync(tu, POST_SYNC, -1);    
     tu("enter_trap(core_ptr, *trap_state, *pc, 0);");
-    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(), 32));
+    tu.store(traits::LAST_BRANCH, tu.constant(std::numeric_limits<uint32_t>::max(),32));
     tu("return *next_pc;");
 }
 
 } // namespace tgc5c
 
-template <> std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c* core, unsigned short port, bool dump) {
+template <>
+std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short port, bool dump) {
     auto ret = new tgc5c::vm_impl<arch::tgc5c>(*core, dump);
-    if(port != 0)
-        debugger::server<debugger::gdb_session>::run_server(ret, port);
+    if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
     return std::unique_ptr<vm_if>(ret);
 }
-} // namespace tcc
+} // namesapce tcc
 } // namespace iss
 
 #include <iss/arch/riscv_hart_m_p.h>
@@ -3351,20 +3648,27 @@ template <> std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c* core, unsign
 namespace iss {
 namespace {
 volatile std::array<bool, 2> dummy = {
-    core_factory::instance().register_creator("tgc5c|m_p|tcc",
-                                              [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr> {
-                                                  auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
-                                                  auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
-                                                  if(port != 0)
-                                                      debugger::server<debugger::gdb_session>::run_server(vm, port);
-                                                  return {cpu_ptr{cpu}, vm_ptr{vm}};
-                                              }),
-    core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned port, void*) -> std::tuple<cpu_ptr, vm_ptr> {
-        auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
-        auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
-        if(port != 0)
-            debugger::server<debugger::gdb_session>::run_server(vm, port);
-        return {cpu_ptr{cpu}, vm_ptr{vm}};
-    })};
+        core_factory::instance().register_creator("tgc5c|m_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
+		    auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        }),
+        core_factory::instance().register_creator("tgc5c|mu_p|tcc", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
+            auto* cpu = new iss::arch::riscv_hart_mu_p<iss::arch::tgc5c>();
+		    auto vm = new tcc::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
+		    if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
+            if(init_data){
+                auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
+                cpu->set_semihosting_callback(*cb);
+            }
+            return {cpu_ptr{cpu}, vm_ptr{vm}};
+        })
+};
 }
-} // namespace iss
+}
+// clang-format on
\ No newline at end of file