From eb8365f4c3684aa9aae321a2f1f3fbb47c0a33db Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Thu, 11 Apr 2019 05:40:02 +0000 Subject: [PATCH 1/6] Updated SC-Components --- README.md | 7 ------- platform/src/sysc/plic.cpp | 2 +- platform/src/sysc/pwm.cpp | 12 ++++++------ platform/src/sysc/spi.cpp | 6 +++--- riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl | 1 + riscv/incl/iss/arch/riscv_hart_msu_vp.h | 1 + riscv/incl/iss/debugger/riscv_target_adapter.h | 1 + riscv/src/internal/vm_rv32gc.cpp | 1 + riscv/src/internal/vm_rv32imac.cpp | 1 + riscv/src/internal/vm_rv64gc.cpp | 1 + riscv/src/internal/vm_rv64i.cpp | 1 + sc-components | 2 +- 12 files changed, 18 insertions(+), 18 deletions(-) diff --git a/README.md b/README.md index 49d29e1..d65cd25 100644 --- a/README.md +++ b/README.md @@ -10,16 +10,9 @@ The implementation is based on LLVM 4.0. Eclipse CDT 4.7 (Oxygen) is recommended DBT-RISE-RISCV uses libGIS (https://github.com/vsergeev/libGIS) as well as ELFIO (http://elfio.sourceforge.net/), both under MIT license -**What's missing** - -* F & D standard extensions for 32bit to be implemented -* MACF &D standard extensions for 64bit to be implemented and verified - **Planned features** * add platform peripherals beyond programmers view to resemble E300 platform - * QSPI - * PWM * ... * and more diff --git a/platform/src/sysc/plic.cpp b/platform/src/sysc/plic.cpp index e0b1b64..589b2b3 100644 --- a/platform/src/sysc/plic.cpp +++ b/platform/src/sysc/plic.cpp @@ -50,7 +50,7 @@ plic::plic(sc_core::sc_module_name nm) { regs->registerResources(*this); // register callbacks - regs->claim_complete.set_write_cb([this](scc::sc_register reg, uint32_t v, sc_core::sc_time d) -> bool { + regs->claim_complete.set_write_cb([this](scc::sc_register& reg, const uint32_t& v, sc_core::sc_time d) -> bool { reg.put(v); reset_pending_int(v); // std::cout << "Value of register: 0x" << std::hex << reg << std::endl; diff --git a/platform/src/sysc/pwm.cpp b/platform/src/sysc/pwm.cpp index 2a7ff54..fc741f4 100644 --- a/platform/src/sysc/pwm.cpp +++ b/platform/src/sysc/pwm.cpp @@ -51,14 +51,14 @@ pwm::pwm(sc_core::sc_module_name nm) regs->registerResources(*this); regs->pwmcfg.set_write_cb( - [this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { + [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { if (d.value()) wait(d); reg.put(data); update_counter(); return true; }); regs->pwmcount.set_write_cb( - [this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { + [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { if (d.value()) wait(d); reg.put(data); update_counter(); @@ -83,25 +83,25 @@ pwm::pwm(sc_core::sc_module_name nm) return true; }); regs->pwmcmp0.set_write_cb( - [this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { + [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { reg.put(data); update_counter(); return true; }); regs->pwmcmp1.set_write_cb( - [this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { + [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { reg.put(data); update_counter(); return true; }); regs->pwmcmp2.set_write_cb( - [this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { + [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { reg.put(data); update_counter(); return true; }); regs->pwmcmp3.set_write_cb( - [this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { + [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { reg.put(data); update_counter(); return true; diff --git a/platform/src/sysc/spi.cpp b/platform/src/sysc/spi.cpp index 1129fad..8c579c0 100644 --- a/platform/src/sysc/spi.cpp +++ b/platform/src/sysc/spi.cpp @@ -124,7 +124,7 @@ beh::beh(sc_core::sc_module_name nm) return true; }); regs->csmode.set_write_cb( - [this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { + [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { if (regs->r_csmode.mode == 2 && regs->r_csmode.mode != bit_sub<0, 2>(data) && regs->r_csid < 4) { tlm::tlm_phase phase(tlm::BEGIN_REQ); sc_core::sc_time delay(SC_ZERO_TIME); @@ -136,7 +136,7 @@ beh::beh(sc_core::sc_module_name nm) reg.put(data); return true; }); - regs->csid.set_write_cb([this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { + regs->csid.set_write_cb([this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { if (regs->r_csmode.mode == 2 && regs->csid != data && regs->r_csid < 4) { tlm::tlm_phase phase(tlm::BEGIN_REQ); sc_core::sc_time delay(SC_ZERO_TIME); @@ -148,7 +148,7 @@ beh::beh(sc_core::sc_module_name nm) reg.put(data); return true; }); - regs->csdef.set_write_cb([this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { + regs->csdef.set_write_cb([this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { auto diff = regs->csdef ^ data; if (regs->r_csmode.mode == 2 && diff != 0 && (regs->r_csid < 4) && (diff & (1 << regs->r_csid)) != 0) { tlm::tlm_phase phase(tlm::BEGIN_REQ); diff --git a/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl b/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl index 709da48..4002097 100644 --- a/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl +++ b/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl @@ -38,6 +38,7 @@ #include #include +#define FMT_HEADER_ONLY #include #include diff --git a/riscv/incl/iss/arch/riscv_hart_msu_vp.h b/riscv/incl/iss/arch/riscv_hart_msu_vp.h index d6fbc76..04d421f 100644 --- a/riscv/incl/iss/arch/riscv_hart_msu_vp.h +++ b/riscv/incl/iss/arch/riscv_hart_msu_vp.h @@ -40,6 +40,7 @@ #include "iss/instrumentation_if.h" #include "iss/log_categories.h" #include "iss/vm_if.h" +#define FMT_HEADER_ONLY #include #include #include diff --git a/riscv/incl/iss/debugger/riscv_target_adapter.h b/riscv/incl/iss/debugger/riscv_target_adapter.h index e6ec40e..97e4afe 100644 --- a/riscv/incl/iss/debugger/riscv_target_adapter.h +++ b/riscv/incl/iss/debugger/riscv_target_adapter.h @@ -40,6 +40,7 @@ #include #include +#define FMT_HEADER_ONLY #include #include diff --git a/riscv/src/internal/vm_rv32gc.cpp b/riscv/src/internal/vm_rv32gc.cpp index 4cb95a4..8d58336 100644 --- a/riscv/src/internal/vm_rv32gc.cpp +++ b/riscv/src/internal/vm_rv32gc.cpp @@ -38,6 +38,7 @@ #include #include +#define FMT_HEADER_ONLY #include #include diff --git a/riscv/src/internal/vm_rv32imac.cpp b/riscv/src/internal/vm_rv32imac.cpp index b153309..e7f57af 100644 --- a/riscv/src/internal/vm_rv32imac.cpp +++ b/riscv/src/internal/vm_rv32imac.cpp @@ -38,6 +38,7 @@ #include #include +#define FMT_HEADER_ONLY #include #include diff --git a/riscv/src/internal/vm_rv64gc.cpp b/riscv/src/internal/vm_rv64gc.cpp index 451efa7..6261ca7 100644 --- a/riscv/src/internal/vm_rv64gc.cpp +++ b/riscv/src/internal/vm_rv64gc.cpp @@ -38,6 +38,7 @@ #include #include +#define FMT_HEADER_ONLY #include #include diff --git a/riscv/src/internal/vm_rv64i.cpp b/riscv/src/internal/vm_rv64i.cpp index e9a1be3..37ea5e8 100644 --- a/riscv/src/internal/vm_rv64i.cpp +++ b/riscv/src/internal/vm_rv64i.cpp @@ -38,6 +38,7 @@ #include #include +#define FMT_HEADER_ONLY #include #include diff --git a/sc-components b/sc-components index 05ba880..7c989da 160000 --- a/sc-components +++ b/sc-components @@ -1 +1 @@ -Subproject commit 05ba88052cf922b1e93550342d8e297338619b5d +Subproject commit 7c989da05673bb40e1358561d51b86e71c1ac68c From 67d9beb7bd4aed56ffa16b387c53e17c5135d797 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 11 Jun 2019 16:49:37 +0000 Subject: [PATCH 2/6] reorganized layout to only contain risc-v stuff --- .cproject | 6 +- .gitignore | 1 + .gitmodules | 12 - CMakeLists.txt | 173 +- CMakeLists.txt.orig | 119 ++ build.sh | 6 - cmake/Common.cmake | 20 - cmake/Conan.cmake | 46 - cmake/DoxygenTarget.cmake | 24 - cmake/FindTcmalloc.cmake | 38 - cmake/GetGitRevisionDescription.cmake | 130 -- cmake/GetGitRevisionDescription.cmake.in | 41 - cmake/GitFunctions.cmake | 22 - cmake/PackageConfigurator.cmake | 44 - cmake/Submodules.cmake | 57 - conanfile.txt | 19 - cycles.txt | 1728 ----------------- dbt-core | 1 - etc/CoreDSL generator.launch | 8 - etc/cmake DBT-RISE-RISCV Debug.launch | 15 - etc/cmake DBT-RISE-RISCV Release.launch | 7 - etc/cmake.sh | 47 - etc/dbt-riscv Debug hello gdb.launch | 42 - etc/dbt-riscv Debug hello w plugin.launch | 42 - etc/hello Debug.launch | 47 - external/CMakeLists.txt | 28 - external/elfio | 1 - external/libGIS | 1 - {riscv => gen_input}/.gitignore | 0 .../RISCVBase.core_desc | 0 .../gen_input => gen_input}/RV32I.core_desc | 0 .../gen_input => gen_input}/RV64I.core_desc | 0 {riscv/gen_input => gen_input}/RVA.core_desc | 0 {riscv/gen_input => gen_input}/RVC.core_desc | 0 {riscv/gen_input => gen_input}/RVD.core_desc | 0 {riscv/gen_input => gen_input}/RVF.core_desc | 0 {riscv/gen_input => gen_input}/RVM.core_desc | 0 .../minres_rv.core_desc | 0 .../templates/CORENAME_cyles.txt.gtl | 0 .../templates/incl-CORENAME.h.gtl | 0 .../templates/src-CORENAME.cpp.gtl | 0 .../templates/vm-vm_CORENAME.cpp.gtl | 0 html/app.js | 64 - html/index.html | 14 - html/lib/jquery.min.js | 16 - html/ws.html | 105 - .../iss/arch/riscv_hart_msu_vp.h | 0 {riscv/incl => incl}/iss/arch/rv32gc.h | 0 {riscv/incl => incl}/iss/arch/rv32imac.h | 0 {riscv/incl => incl}/iss/arch/rv64gc.h | 0 {riscv/incl => incl}/iss/arch/rv64i.h | 0 .../iss/debugger/riscv_target_adapter.h | 0 .../incl => incl}/iss/plugin/cycle_estimate.h | 0 .../iss/plugin/instruction_count.h | 0 {riscv/incl => incl}/sysc/core_complex.h | 0 platform/CMakeLists.txt | 57 - platform/gen_input/aon.rdl | 158 -- platform/gen_input/clint.rdl | 27 - platform/gen_input/fe310.rdl | 25 - platform/gen_input/gpio.rdl | 121 -- platform/gen_input/plic.rdl | 27 - platform/gen_input/prci.rdl | 41 - platform/gen_input/pwm.rdl | 96 - platform/gen_input/spi.rdl | 173 -- platform/gen_input/uart.rdl | 46 - platform/incl/sysc/SiFive/aon.h | 63 - platform/incl/sysc/SiFive/clint.h | 74 - platform/incl/sysc/SiFive/fe310.h | 106 - platform/incl/sysc/SiFive/gen/aon_regs.h | 170 -- platform/incl/sysc/SiFive/gen/clint_regs.h | 80 - platform/incl/sysc/SiFive/gen/e300_plat_t.h | 21 - platform/incl/sysc/SiFive/gen/gpio_regs.h | 169 -- platform/incl/sysc/SiFive/gen/plic_regs.h | 93 - platform/incl/sysc/SiFive/gen/prci_regs.h | 104 - platform/incl/sysc/SiFive/gen/pwm_regs.h | 129 -- platform/incl/sysc/SiFive/gen/spi_regs.h | 188 -- platform/incl/sysc/SiFive/gen/uart_regs.h | 119 -- platform/incl/sysc/SiFive/gpio.h | 87 - platform/incl/sysc/SiFive/plic.h | 72 - platform/incl/sysc/SiFive/prci.h | 64 - platform/incl/sysc/SiFive/pwm.h | 79 - platform/incl/sysc/SiFive/spi.h | 88 - platform/incl/sysc/SiFive/uart.h | 75 - platform/incl/sysc/sc_comm_singleton.h | 114 -- platform/incl/sysc/tlm_extensions.h | 70 - platform/incl/sysc/top/BLDC.h | 131 -- platform/incl/sysc/top/dcmotor.h | 68 - platform/incl/sysc/top/h_bridge.h | 66 - platform/incl/sysc/top/hifive1.h | 68 - platform/incl/sysc/top/mcp_adc.h | 120 -- platform/incl/sysc/top/system.h | 62 - platform/incl/sysc/top/terminal.h | 69 - platform/src/CLIParser.cpp | 112 -- platform/src/CLIParser.h | 60 - platform/src/CMakeLists.txt | 106 - platform/src/sc_main.cpp | 142 -- platform/src/sysc/BLDC.cpp | 188 -- platform/src/sysc/aon.cpp | 78 - platform/src/sysc/clint.cpp | 124 -- platform/src/sysc/dcmotor.cpp | 114 -- platform/src/sysc/fe310.cpp | 194 -- platform/src/sysc/gpio.cpp | 224 --- platform/src/sysc/h_bridge.cpp | 103 - platform/src/sysc/hifive1.cpp | 111 -- platform/src/sysc/mcp_adc.cpp | 202 -- platform/src/sysc/plic.cpp | 170 -- platform/src/sysc/prci.cpp | 143 -- platform/src/sysc/pwm.cpp | 231 --- platform/src/sysc/sc_comm_singleton.cpp | 169 -- platform/src/sysc/spi.cpp | 271 --- platform/src/sysc/system.cpp | 115 -- platform/src/sysc/terminal.cpp | 87 - platform/src/sysc/uart.cpp | 180 -- riscv/CMakeLists.txt | 52 - riscv/gen_input/.gitignore | 1 - sc-components | 1 - {riscv/src => src}/CMakeLists.txt | 0 {riscv/src => src}/internal/fp_functions.cpp | 0 {riscv/src => src}/internal/vm_rv32gc.cpp | 0 {riscv/src => src}/internal/vm_rv32imac.cpp | 0 {riscv/src => src}/internal/vm_rv64gc.cpp | 0 {riscv/src => src}/internal/vm_rv64i.cpp | 0 {riscv/src => src}/iss/rv32gc.cpp | 0 {riscv/src => src}/iss/rv32imac.cpp | 0 {riscv/src => src}/iss/rv64gc.cpp | 0 {riscv/src => src}/iss/rv64i.cpp | 0 {riscv/src => src}/main.cpp | 0 src/plugin/GCOV.cpp | 821 ++++++++ src/plugin/GCOV.h | 460 +++++ {riscv/src => src}/plugin/cycle_estimate.cpp | 0 .../src => src}/plugin/instruction_count.cpp | 0 {riscv/src => src}/sysc/core_complex.cpp | 0 system.json | 34 - 133 files changed, 1460 insertions(+), 9277 deletions(-) delete mode 100644 .gitmodules create mode 100644 CMakeLists.txt.orig delete mode 100644 build.sh delete mode 100644 cmake/Common.cmake delete mode 100644 cmake/Conan.cmake delete mode 100644 cmake/DoxygenTarget.cmake delete mode 100644 cmake/FindTcmalloc.cmake delete mode 100644 cmake/GetGitRevisionDescription.cmake delete mode 100644 cmake/GetGitRevisionDescription.cmake.in delete mode 100644 cmake/GitFunctions.cmake delete mode 100644 cmake/PackageConfigurator.cmake delete mode 100644 cmake/Submodules.cmake delete mode 100644 conanfile.txt delete mode 100644 cycles.txt delete mode 160000 dbt-core delete mode 100644 etc/CoreDSL generator.launch delete mode 100644 etc/cmake DBT-RISE-RISCV Debug.launch delete mode 100644 etc/cmake DBT-RISE-RISCV Release.launch delete mode 100755 etc/cmake.sh delete mode 100644 etc/dbt-riscv Debug hello gdb.launch delete mode 100644 etc/dbt-riscv Debug hello w plugin.launch delete mode 100644 etc/hello Debug.launch delete mode 100644 external/CMakeLists.txt delete mode 160000 external/elfio delete mode 160000 external/libGIS rename {riscv => gen_input}/.gitignore (100%) rename {riscv/gen_input => gen_input}/RISCVBase.core_desc (100%) rename {riscv/gen_input => gen_input}/RV32I.core_desc (100%) rename {riscv/gen_input => gen_input}/RV64I.core_desc (100%) rename {riscv/gen_input => gen_input}/RVA.core_desc (100%) rename {riscv/gen_input => gen_input}/RVC.core_desc (100%) rename {riscv/gen_input => gen_input}/RVD.core_desc (100%) rename {riscv/gen_input => gen_input}/RVF.core_desc (100%) rename {riscv/gen_input => gen_input}/RVM.core_desc (100%) rename {riscv/gen_input => gen_input}/minres_rv.core_desc (100%) rename {riscv/gen_input => gen_input}/templates/CORENAME_cyles.txt.gtl (100%) rename {riscv/gen_input => gen_input}/templates/incl-CORENAME.h.gtl (100%) rename {riscv/gen_input => gen_input}/templates/src-CORENAME.cpp.gtl (100%) rename {riscv/gen_input => gen_input}/templates/vm-vm_CORENAME.cpp.gtl (100%) delete mode 100644 html/app.js delete mode 100644 html/index.html delete mode 100644 html/lib/jquery.min.js delete mode 100644 html/ws.html rename {riscv/incl => incl}/iss/arch/riscv_hart_msu_vp.h (100%) rename {riscv/incl => incl}/iss/arch/rv32gc.h (100%) rename {riscv/incl => incl}/iss/arch/rv32imac.h (100%) rename {riscv/incl => incl}/iss/arch/rv64gc.h (100%) rename {riscv/incl => incl}/iss/arch/rv64i.h (100%) rename {riscv/incl => incl}/iss/debugger/riscv_target_adapter.h (100%) rename {riscv/incl => incl}/iss/plugin/cycle_estimate.h (100%) rename {riscv/incl => incl}/iss/plugin/instruction_count.h (100%) rename {riscv/incl => incl}/sysc/core_complex.h (100%) delete mode 100644 platform/CMakeLists.txt delete mode 100644 platform/gen_input/aon.rdl delete mode 100644 platform/gen_input/clint.rdl delete mode 100644 platform/gen_input/fe310.rdl delete mode 100644 platform/gen_input/gpio.rdl delete mode 100644 platform/gen_input/plic.rdl delete mode 100644 platform/gen_input/prci.rdl delete mode 100644 platform/gen_input/pwm.rdl delete mode 100644 platform/gen_input/spi.rdl delete mode 100644 platform/gen_input/uart.rdl delete mode 100644 platform/incl/sysc/SiFive/aon.h delete mode 100644 platform/incl/sysc/SiFive/clint.h delete mode 100644 platform/incl/sysc/SiFive/fe310.h delete mode 100644 platform/incl/sysc/SiFive/gen/aon_regs.h delete mode 100644 platform/incl/sysc/SiFive/gen/clint_regs.h delete mode 100644 platform/incl/sysc/SiFive/gen/e300_plat_t.h delete mode 100644 platform/incl/sysc/SiFive/gen/gpio_regs.h delete mode 100644 platform/incl/sysc/SiFive/gen/plic_regs.h delete mode 100644 platform/incl/sysc/SiFive/gen/prci_regs.h delete mode 100644 platform/incl/sysc/SiFive/gen/pwm_regs.h delete mode 100644 platform/incl/sysc/SiFive/gen/spi_regs.h delete mode 100644 platform/incl/sysc/SiFive/gen/uart_regs.h delete mode 100644 platform/incl/sysc/SiFive/gpio.h delete mode 100644 platform/incl/sysc/SiFive/plic.h delete mode 100644 platform/incl/sysc/SiFive/prci.h delete mode 100644 platform/incl/sysc/SiFive/pwm.h delete mode 100644 platform/incl/sysc/SiFive/spi.h delete mode 100644 platform/incl/sysc/SiFive/uart.h delete mode 100644 platform/incl/sysc/sc_comm_singleton.h delete mode 100644 platform/incl/sysc/tlm_extensions.h delete mode 100644 platform/incl/sysc/top/BLDC.h delete mode 100644 platform/incl/sysc/top/dcmotor.h delete mode 100644 platform/incl/sysc/top/h_bridge.h delete mode 100644 platform/incl/sysc/top/hifive1.h delete mode 100644 platform/incl/sysc/top/mcp_adc.h delete mode 100644 platform/incl/sysc/top/system.h delete mode 100644 platform/incl/sysc/top/terminal.h delete mode 100644 platform/src/CLIParser.cpp delete mode 100644 platform/src/CLIParser.h delete mode 100644 platform/src/CMakeLists.txt delete mode 100644 platform/src/sc_main.cpp delete mode 100644 platform/src/sysc/BLDC.cpp delete mode 100644 platform/src/sysc/aon.cpp delete mode 100644 platform/src/sysc/clint.cpp delete mode 100644 platform/src/sysc/dcmotor.cpp delete mode 100644 platform/src/sysc/fe310.cpp delete mode 100644 platform/src/sysc/gpio.cpp delete mode 100644 platform/src/sysc/h_bridge.cpp delete mode 100644 platform/src/sysc/hifive1.cpp delete mode 100644 platform/src/sysc/mcp_adc.cpp delete mode 100644 platform/src/sysc/plic.cpp delete mode 100644 platform/src/sysc/prci.cpp delete mode 100644 platform/src/sysc/pwm.cpp delete mode 100644 platform/src/sysc/sc_comm_singleton.cpp delete mode 100644 platform/src/sysc/spi.cpp delete mode 100644 platform/src/sysc/system.cpp delete mode 100644 platform/src/sysc/terminal.cpp delete mode 100644 platform/src/sysc/uart.cpp delete mode 100644 riscv/CMakeLists.txt delete mode 100644 riscv/gen_input/.gitignore delete mode 160000 sc-components rename {riscv/src => src}/CMakeLists.txt (100%) rename {riscv/src => src}/internal/fp_functions.cpp (100%) rename {riscv/src => src}/internal/vm_rv32gc.cpp (100%) rename {riscv/src => src}/internal/vm_rv32imac.cpp (100%) rename {riscv/src => src}/internal/vm_rv64gc.cpp (100%) rename {riscv/src => src}/internal/vm_rv64i.cpp (100%) rename {riscv/src => src}/iss/rv32gc.cpp (100%) rename {riscv/src => src}/iss/rv32imac.cpp (100%) rename {riscv/src => src}/iss/rv64gc.cpp (100%) rename {riscv/src => src}/iss/rv64i.cpp (100%) rename {riscv/src => src}/main.cpp (100%) create mode 100644 src/plugin/GCOV.cpp create mode 100644 src/plugin/GCOV.h rename {riscv/src => src}/plugin/cycle_estimate.cpp (100%) rename {riscv/src => src}/plugin/instruction_count.cpp (100%) rename {riscv/src => src}/sysc/core_complex.cpp (100%) delete mode 100644 system.json diff --git a/.cproject b/.cproject index 66a4d92..b924aa3 100644 --- a/.cproject +++ b/.cproject @@ -187,7 +187,11 @@ - + + + + + diff --git a/.gitignore b/.gitignore index 2865d22..37563ca 100644 --- a/.gitignore +++ b/.gitignore @@ -30,3 +30,4 @@ language.settings.xml /.gdbinit /*.out /dump.json +/src-gen/ diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index 7ae8575..0000000 --- a/.gitmodules +++ /dev/null @@ -1,12 +0,0 @@ -[submodule "dbt-core"] - path = dbt-core - url = https://git.minres.com/DBT-RISE/DBT-RISE-Core.git -[submodule "sc-components"] - path = sc-components - url = https://git.minres.com/SystemC/SystemC-Components.git -[submodule "external/elfio"] - path = external/elfio - url = http://git.code.sf.net/p/elfio/code -[submodule "external/libGIS"] - path = external/libGIS - url = https://github.com/vsergeev/libGIS.git diff --git a/CMakeLists.txt b/CMakeLists.txt index 8b70e49..162b857 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,119 +1,54 @@ -cmake_minimum_required(VERSION 3.3) -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake ${CMAKE_CURRENT_SOURCE_DIR}/sc-components/cmake) - -set(ENABLE_SCV TRUE CACHE BOOL "Enable use of SCV") -set(ENABLE_SHARED TRUE CACHE BOOL "Build shared libraries") - -include(GitFunctions) -get_branch_from_git() -# if we are not on master or develop set the submodules to develop -IF(NOT ${GIT_BRANCH} MATCHES "master") - IF(NOT ${GIT_BRANCH} MATCHES "develop") - message(STATUS "main branch is '${GIT_BRANCH}', setting submodules to 'develop'") - set(GIT_BRANCH develop) - endif() -endif() - -### set the directory names of the submodules -set(GIT_SUBMODULES elfio libGIS sc-components dbt-core) -set(GIT_SUBMODULE_DIR_sc-components .) -set(GIT_SUBMODULE_DIR_dbt-core .) -### set each submodules's commit or tag that is to be checked out -### (leave empty if you want master) -#set(GIT_SUBMODULE_VERSION_sc-comp 3af6b9836589b082c19d9131c5d0b7afa8ddd7cd) -set(GIT_SUBMODULE_BRANCH_sc-components ${GIT_BRANCH}) -set(GIT_SUBMODULE_BRANCH_dbt-core ${GIT_BRANCH}) - -include(GNUInstallDirs) -include(Submodules) -include(Conan) - -#enable_testing() - -set(CMAKE_CXX_STANDARD 14) -set(CMAKE_CXX_STANDARD_REQUIRED ON) -set(CMAKE_CXX_EXTENSIONS OFF) -set(CMAKE_POSITION_INDEPENDENT_CODE ON) - -include(CheckCXXCompilerFlag) -CHECK_CXX_COMPILER_FLAG("-march=native" COMPILER_SUPPORTS_MARCH_NATIVE) -if(COMPILER_SUPPORTS_MARCH_NATIVE) -if("${CMAKE_BUILD_TYPE}" STREQUAL "") - set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=native") -elseif(NOT(${CMAKE_BUILD_TYPE} STREQUAL "RelWithDebInfo")) - set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=native") -endif() -endif() - -if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" OR "${CMAKE_CXX_COMPILER_ID}" STREQUAL "Clang") - set(warnings "-Wall -Wextra -Werror") - #set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D_GLIBCXX_USE_CXX11_ABI=0") - set(CMAKE_CXX_FLAGS_RELEASE "-O3 -DNDEBUG") - set(CMAKE_C_FLAGS_RELEASE "-O3 -DNDEBUG") -elseif ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC") - set(warnings "/W4 /WX /EHsc") -endif() - -setup_conan() - -# This line finds the boost lib and headers. -set(Boost_NO_BOOST_CMAKE ON) # Don't do a find_package in config mode before searching for a regular boost install. -find_package(Boost COMPONENTS program_options system thread filesystem REQUIRED) - -if(DEFINED ENV{LLVM_HOME}) - find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm) -endif(DEFINED ENV{LLVM_HOME}) -find_package(LLVM REQUIRED CONFIG) -message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}") -message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}") -llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser) - -find_package(Threads) -find_package(Tcmalloc) -find_package(ZLIB) -find_package(SystemC) -if(SystemC_FOUND) - message(STATUS "SystemC headers at ${SystemC_INCLUDE_DIRS}") - message(STATUS "SystemC library at ${SystemC_LIBRARY_DIRS}") - if(SCV_FOUND) - message(STATUS "SCV headers at ${SCV_INCLUDE_DIRS}") - message(STATUS "SCV library at ${SCV_LIBRARY_DIRS}") - endif(SCV_FOUND) - if(CCI_FOUND) - message(STATUS "CCI headers at ${CCI_INCLUDE_DIRS}") - message(STATUS "CCI library at ${CCI_LIBRARY_DIRS}") - endif() -endif(SystemC_FOUND) - -set(PROJECT_3PARTY_DIRS external) -include(clang-format) - -set(ENABLE_CLANG_TIDY OFF CACHE BOOL "Add clang-tidy automatically to builds") -if (ENABLE_CLANG_TIDY) - find_program (CLANG_TIDY_EXE NAMES "clang-tidy" PATHS /usr/local/opt/llvm/bin ) - if (CLANG_TIDY_EXE) - message(STATUS "clang-tidy found: ${CLANG_TIDY_EXE}") - set(CLANG_TIDY_CHECKS "-*,modernize-*") - set(CMAKE_CXX_CLANG_TIDY "${CLANG_TIDY_EXE};-checks=${CLANG_TIDY_CHECKS};-header-filter='${CMAKE_SOURCE_DIR}/*';-fix" - CACHE STRING "" FORCE) - else() - message(AUTHOR_WARNING "clang-tidy not found!") - set(CMAKE_CXX_CLANG_TIDY "" CACHE STRING "" FORCE) # delete it - endif() -endif() - -# Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0) -set(VERSION_MAJOR "1") -set(VERSION_MINOR "0") -set(VERSION_PATCH "0") -set(VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}) - -add_subdirectory(external) -add_subdirectory(dbt-core) -add_subdirectory(sc-components) -add_subdirectory(softfloat) -GET_DIRECTORY_PROPERTY(SOFTFLOAT_INCLUDE_DIRS DIRECTORY softfloat DEFINITION SOFTFLOAT_INCLUDE_DIRS) -add_subdirectory(riscv) -add_subdirectory(platform) - -message(STATUS "Build Type: ${CMAKE_BUILD_TYPE}") +cmake_minimum_required(VERSION 3.3) +set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../cmake) # main (top) cmake dir +set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake) # project specific cmake dir + +# CMake useful variables +set(CMAKE_RUNTIME_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/bin") +set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib") +set(CMAKE_LIBRARY_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib") + +add_subdirectory(softfloat) + +# Set the name of your project here +project("riscv") + +include(Common) + +conan_basic_setup() + +# This sets the include directory for the reference project. This is the -I flag in gcc. +include_directories( + ${PROJECT_SOURCE_DIR}/incl + ${SOFTFLOAT_INCLUDE_DIRS} + ${LLVM_INCLUDE_DIRS} +) +add_dependent_subproject(dbt-core) +add_dependent_subproject(sc-components) +include_directories( + ${PROJECT_SOURCE_DIR}/incl + ${PROJECT_SOURCE_DIR}/../external/elfio + ${PROJECT_SOURCE_DIR}/../external/libGIS + ${Boost_INCLUDE_DIRS} +) + + +# Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH) +set(CMAKE_MACOSX_RPATH ON) +set(CMAKE_SKIP_BUILD_RPATH FALSE) +set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE) +set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib") +set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE) + +add_subdirectory(src) + +# +# SYSTEM PACKAGING (RPM, TGZ, ...) +# _____________________________________________________________________________ + +#include(CPackConfig) + +# +# CMAKE PACKAGING (for other CMake projects to use this one easily) +# _____________________________________________________________________________ + +#include(PackageConfigurator) \ No newline at end of file diff --git a/CMakeLists.txt.orig b/CMakeLists.txt.orig new file mode 100644 index 0000000..8b70e49 --- /dev/null +++ b/CMakeLists.txt.orig @@ -0,0 +1,119 @@ +cmake_minimum_required(VERSION 3.3) +set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake ${CMAKE_CURRENT_SOURCE_DIR}/sc-components/cmake) + +set(ENABLE_SCV TRUE CACHE BOOL "Enable use of SCV") +set(ENABLE_SHARED TRUE CACHE BOOL "Build shared libraries") + +include(GitFunctions) +get_branch_from_git() +# if we are not on master or develop set the submodules to develop +IF(NOT ${GIT_BRANCH} MATCHES "master") + IF(NOT ${GIT_BRANCH} MATCHES "develop") + message(STATUS "main branch is '${GIT_BRANCH}', setting submodules to 'develop'") + set(GIT_BRANCH develop) + endif() +endif() + +### set the directory names of the submodules +set(GIT_SUBMODULES elfio libGIS sc-components dbt-core) +set(GIT_SUBMODULE_DIR_sc-components .) +set(GIT_SUBMODULE_DIR_dbt-core .) +### set each submodules's commit or tag that is to be checked out +### (leave empty if you want master) +#set(GIT_SUBMODULE_VERSION_sc-comp 3af6b9836589b082c19d9131c5d0b7afa8ddd7cd) +set(GIT_SUBMODULE_BRANCH_sc-components ${GIT_BRANCH}) +set(GIT_SUBMODULE_BRANCH_dbt-core ${GIT_BRANCH}) + +include(GNUInstallDirs) +include(Submodules) +include(Conan) + +#enable_testing() + +set(CMAKE_CXX_STANDARD 14) +set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_CXX_EXTENSIONS OFF) +set(CMAKE_POSITION_INDEPENDENT_CODE ON) + +include(CheckCXXCompilerFlag) +CHECK_CXX_COMPILER_FLAG("-march=native" COMPILER_SUPPORTS_MARCH_NATIVE) +if(COMPILER_SUPPORTS_MARCH_NATIVE) +if("${CMAKE_BUILD_TYPE}" STREQUAL "") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=native") +elseif(NOT(${CMAKE_BUILD_TYPE} STREQUAL "RelWithDebInfo")) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -march=native") +endif() +endif() + +if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "GNU" OR "${CMAKE_CXX_COMPILER_ID}" STREQUAL "Clang") + set(warnings "-Wall -Wextra -Werror") + #set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D_GLIBCXX_USE_CXX11_ABI=0") + set(CMAKE_CXX_FLAGS_RELEASE "-O3 -DNDEBUG") + set(CMAKE_C_FLAGS_RELEASE "-O3 -DNDEBUG") +elseif ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "MSVC") + set(warnings "/W4 /WX /EHsc") +endif() + +setup_conan() + +# This line finds the boost lib and headers. +set(Boost_NO_BOOST_CMAKE ON) # Don't do a find_package in config mode before searching for a regular boost install. +find_package(Boost COMPONENTS program_options system thread filesystem REQUIRED) + +if(DEFINED ENV{LLVM_HOME}) + find_path (LLVM_DIR LLVM-Config.cmake $ENV{LLVM_HOME}/lib/cmake/llvm) +endif(DEFINED ENV{LLVM_HOME}) +find_package(LLVM REQUIRED CONFIG) +message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}") +message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}") +llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser) + +find_package(Threads) +find_package(Tcmalloc) +find_package(ZLIB) +find_package(SystemC) +if(SystemC_FOUND) + message(STATUS "SystemC headers at ${SystemC_INCLUDE_DIRS}") + message(STATUS "SystemC library at ${SystemC_LIBRARY_DIRS}") + if(SCV_FOUND) + message(STATUS "SCV headers at ${SCV_INCLUDE_DIRS}") + message(STATUS "SCV library at ${SCV_LIBRARY_DIRS}") + endif(SCV_FOUND) + if(CCI_FOUND) + message(STATUS "CCI headers at ${CCI_INCLUDE_DIRS}") + message(STATUS "CCI library at ${CCI_LIBRARY_DIRS}") + endif() +endif(SystemC_FOUND) + +set(PROJECT_3PARTY_DIRS external) +include(clang-format) + +set(ENABLE_CLANG_TIDY OFF CACHE BOOL "Add clang-tidy automatically to builds") +if (ENABLE_CLANG_TIDY) + find_program (CLANG_TIDY_EXE NAMES "clang-tidy" PATHS /usr/local/opt/llvm/bin ) + if (CLANG_TIDY_EXE) + message(STATUS "clang-tidy found: ${CLANG_TIDY_EXE}") + set(CLANG_TIDY_CHECKS "-*,modernize-*") + set(CMAKE_CXX_CLANG_TIDY "${CLANG_TIDY_EXE};-checks=${CLANG_TIDY_CHECKS};-header-filter='${CMAKE_SOURCE_DIR}/*';-fix" + CACHE STRING "" FORCE) + else() + message(AUTHOR_WARNING "clang-tidy not found!") + set(CMAKE_CXX_CLANG_TIDY "" CACHE STRING "" FORCE) # delete it + endif() +endif() + +# Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0) +set(VERSION_MAJOR "1") +set(VERSION_MINOR "0") +set(VERSION_PATCH "0") +set(VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}) + +add_subdirectory(external) +add_subdirectory(dbt-core) +add_subdirectory(sc-components) +add_subdirectory(softfloat) +GET_DIRECTORY_PROPERTY(SOFTFLOAT_INCLUDE_DIRS DIRECTORY softfloat DEFINITION SOFTFLOAT_INCLUDE_DIRS) +add_subdirectory(riscv) +add_subdirectory(platform) + +message(STATUS "Build Type: ${CMAKE_BUILD_TYPE}") diff --git a/build.sh b/build.sh deleted file mode 100644 index e84cd2f..0000000 --- a/build.sh +++ /dev/null @@ -1,6 +0,0 @@ -mkdir -f build/Release -cd build/Release -cmake ../.. -DCMAKE_BUILD_TYPE=RelWithDebInfo && \ - cmake --build . && \ - bin/riscv --reset=0x20400000 --verbose=4 $HOME/eclipse-workspace/RiscV-dhrystone/dhrystone - diff --git a/cmake/Common.cmake b/cmake/Common.cmake deleted file mode 100644 index 673ec59..0000000 --- a/cmake/Common.cmake +++ /dev/null @@ -1,20 +0,0 @@ -# Function to link between sub-projects -function(add_dependent_subproject subproject_name) - #if (NOT TARGET ${subproject_name}) # target unknown - if(NOT PROJECT_${subproject_name}) # var unknown because we build only this subproject - find_package(${subproject_name} CONFIG REQUIRED) - else () # we know the target thus we are doing a build from the top directory - include_directories(../${subproject_name}/incl) - endif () -endfunction(add_dependent_subproject) - -# Make sure we tell the topdir CMakeLists that we exist (if build from topdir) -get_directory_property(hasParent PARENT_DIRECTORY) -if(hasParent) - set(PROJECT_${PROJECT_NAME} true PARENT_SCOPE) -endif() - -# Function to link between sub-projects -function(add_dependent_header subproject_name) - include_directories(../${subproject_name}/incl) -endfunction(add_dependent_header) diff --git a/cmake/Conan.cmake b/cmake/Conan.cmake deleted file mode 100644 index 7fd859f..0000000 --- a/cmake/Conan.cmake +++ /dev/null @@ -1,46 +0,0 @@ -macro(setup_conan) - find_program(conan conan) - if(NOT EXISTS ${conan}) - message(FATAL_ERROR "Conan is required. Please see README.md") - return() - endif() - - if(${CMAKE_HOST_SYSTEM_NAME} STREQUAL Darwin) - set(os Macos) - else() - set(os ${CMAKE_HOST_SYSTEM_NAME}) - endif() - - if(${CMAKE_CXX_COMPILER_ID} STREQUAL GNU) - set(compiler gcc) - elseif(${CMAKE_CXX_COMPILER_ID} STREQUAL AppleClang) - set(compiler apple-clang) - else() - message(FATAL_ERROR "Unknown compiler: ${CMAKE_CXX_COMPILER_ID}") - endif() - - string(SUBSTRING ${CMAKE_CXX_COMPILER_VERSION} 0 3 compiler_version) - - set(conanfile ${CMAKE_SOURCE_DIR}/conanfile.txt) - set(conanfile_cmake ${CMAKE_BINARY_DIR}/conanbuildinfo.cmake) - set(compiler_libcxx libstdc++11) - - if("${CMAKE_BUILD_TYPE}" STREQUAL "") - set(CONAN_BUILD_TYPE Debug) - elseif("${CMAKE_BUILD_TYPE}" STREQUAL "RelWithDebInfo") - set(CONAN_BUILD_TYPE Release) - else() - set(CONAN_BUILD_TYPE ${CMAKE_BUILD_TYPE}) - endif() - - execute_process(COMMAND ${conan} install --build=missing - -s build_type=${CONAN_BUILD_TYPE} -s compiler.libcxx=${compiler_libcxx} - ${CMAKE_SOURCE_DIR} RESULT_VARIABLE return_code) - if(NOT ${return_code} EQUAL 0) - message(FATAL_ERROR "conan install command failed.") - endif() - - include(${conanfile_cmake}) - #conan_basic_setup(TARGETS) - conan_basic_setup() -endmacro() diff --git a/cmake/DoxygenTarget.cmake b/cmake/DoxygenTarget.cmake deleted file mode 100644 index 49d5dd4..0000000 --- a/cmake/DoxygenTarget.cmake +++ /dev/null @@ -1,24 +0,0 @@ -function(PrepareDocTarget) - - # Configure the doxygen config file with current settings: - configure_file(documentation-config.doxygen.in ${CMAKE_CURRENT_BINARY_DIR}/documentation-config.doxygen @ONLY) - - # Set the name of the target : "doc" if it doesn't already exist and "doc" if it does. - # This way we make sure to have a single "doc" target. Either it is the one of the top directory or - # it is the one of the subproject that we are compiling alone. - set(DOC_TARGET_NAME "doc") - if(TARGET doc) - set(DOC_TARGET_NAME "doc${PROJECT_NAME}") - endif() - - add_custom_target(${DOC_TARGET_NAME} ${TARGET_ALL} - ${DOXYGEN_EXECUTABLE} ${CMAKE_CURRENT_BINARY_DIR}/documentation-config.doxygen - WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - COMMENT "Generating API documentation using doxygen for ${PROJECT_NAME}" VERBATIM) - - set(INSTALL_DOC_DIR ${CMAKE_BINARY_DIR}/doc/${PROJECT_NAME}/html) - file(MAKE_DIRECTORY ${INSTALL_DOC_DIR}) # needed for install - - install(DIRECTORY ${INSTALL_DOC_DIR} DESTINATION share/${PROJECT_NAME}-${VERSION_MAJOR} COMPONENT doc) - -endfunction() \ No newline at end of file diff --git a/cmake/FindTcmalloc.cmake b/cmake/FindTcmalloc.cmake deleted file mode 100644 index 825ee8d..0000000 --- a/cmake/FindTcmalloc.cmake +++ /dev/null @@ -1,38 +0,0 @@ -# - Find Tcmalloc -# Find the native Tcmalloc library -# -# Tcmalloc_LIBRARIES - List of libraries when using Tcmalloc. -# Tcmalloc_FOUND - True if Tcmalloc found. - -if (USE_TCMALLOC) - set(Tcmalloc_NAMES tcmalloc) -else () - set(Tcmalloc_NAMES tcmalloc_minimal tcmalloc tcmalloc_minimal4 libtcmalloc_minimal.so.4) -endif () - -find_library(Tcmalloc_LIBRARY NO_DEFAULT_PATH - NAMES ${Tcmalloc_NAMES} - PATHS ${HT_DEPENDENCY_LIB_DIR} /lib /usr/lib /usr/lib/x86_64-linux-gnu /usr/local/lib /opt/local/lib -) - -if (Tcmalloc_LIBRARY) - set(Tcmalloc_FOUND TRUE) - set( Tcmalloc_LIBRARIES ${Tcmalloc_LIBRARY} ) -else () - set(Tcmalloc_FOUND FALSE) - set( Tcmalloc_LIBRARIES ) -endif () - -if (Tcmalloc_FOUND) - message(STATUS "Found Tcmalloc: ${Tcmalloc_LIBRARY}") -else () - message(STATUS "Not Found Tcmalloc: ${Tcmalloc_LIBRARY}") - if (Tcmalloc_FIND_REQUIRED) - message(STATUS "Looked for Tcmalloc libraries named ${Tcmalloc_NAMES}.") - message(FATAL_ERROR "Could NOT find Tcmalloc library") - endif () -endif () - -mark_as_advanced( - Tcmalloc_LIBRARY -) \ No newline at end of file diff --git a/cmake/GetGitRevisionDescription.cmake b/cmake/GetGitRevisionDescription.cmake deleted file mode 100644 index bcd1d72..0000000 --- a/cmake/GetGitRevisionDescription.cmake +++ /dev/null @@ -1,130 +0,0 @@ -# - Returns a version string from Git -# -# These functions force a re-configure on each git commit so that you can -# trust the values of the variables in your build system. -# -# get_git_head_revision( [ ...]) -# -# Returns the refspec and sha hash of the current head revision -# -# git_describe( [ ...]) -# -# Returns the results of git describe on the source tree, and adjusting -# the output so that it tests false if an error occurs. -# -# git_get_exact_tag( [ ...]) -# -# Returns the results of git describe --exact-match on the source tree, -# and adjusting the output so that it tests false if there was no exact -# matching tag. -# -# Requires CMake 2.6 or newer (uses the 'function' command) -# -# Original Author: -# 2009-2010 Ryan Pavlik -# http://academic.cleardefinition.com -# Iowa State University HCI Graduate Program/VRAC -# -# Copyright Iowa State University 2009-2010. -# Distributed under the Boost Software License, Version 1.0. -# (See accompanying file LICENSE_1_0.txt or copy at -# http://www.boost.org/LICENSE_1_0.txt) - -if(__get_git_revision_description) - return() -endif() -set(__get_git_revision_description YES) - -# We must run the following at "include" time, not at function call time, -# to find the path to this module rather than the path to a calling list file -get_filename_component(_gitdescmoddir ${CMAKE_CURRENT_LIST_FILE} PATH) - -function(get_git_head_revision _refspecvar _hashvar) - set(GIT_PARENT_DIR "${CMAKE_CURRENT_LIST_DIR}") - set(GIT_DIR "${GIT_PARENT_DIR}/.git") - while(NOT EXISTS "${GIT_DIR}") # .git dir not found, search parent directories - set(GIT_PREVIOUS_PARENT "${GIT_PARENT_DIR}") - get_filename_component(GIT_PARENT_DIR ${GIT_PARENT_DIR} PATH) - if(GIT_PARENT_DIR STREQUAL GIT_PREVIOUS_PARENT) - # We have reached the root directory, we are not in git - set(${_refspecvar} "GITDIR-NOTFOUND" PARENT_SCOPE) - set(${_hashvar} "GITDIR-NOTFOUND" PARENT_SCOPE) - return() - endif() - set(GIT_DIR "${GIT_PARENT_DIR}/.git") - endwhile() - # check if this is a submodule - if(NOT IS_DIRECTORY ${GIT_DIR}) - file(READ ${GIT_DIR} submodule) - string(REGEX REPLACE "gitdir: (.*)\n$" "\\1" GIT_DIR_RELATIVE ${submodule}) - get_filename_component(SUBMODULE_DIR ${GIT_DIR} PATH) - get_filename_component(GIT_DIR ${SUBMODULE_DIR}/${GIT_DIR_RELATIVE} ABSOLUTE) - endif() - set(GIT_DATA "${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/git-data") - if(NOT EXISTS "${GIT_DATA}") - file(MAKE_DIRECTORY "${GIT_DATA}") - endif() - - if(NOT EXISTS "${GIT_DIR}/HEAD") - return() - endif() - set(HEAD_FILE "${GIT_DATA}/HEAD") - configure_file("${GIT_DIR}/HEAD" "${HEAD_FILE}" COPYONLY) - - configure_file("${_gitdescmoddir}/GetGitRevisionDescription.cmake.in" - "${GIT_DATA}/grabRef.cmake" - @ONLY) - include("${GIT_DATA}/grabRef.cmake") - - set(${_refspecvar} "${HEAD_REF}" PARENT_SCOPE) - set(${_hashvar} "${HEAD_HASH}" PARENT_SCOPE) -endfunction() - -function(git_describe _var) - if(NOT GIT_FOUND) - find_package(Git QUIET) - endif() - get_git_head_revision(refspec hash) - if(NOT GIT_FOUND) - set(${_var} "GIT-NOTFOUND" PARENT_SCOPE) - return() - endif() - if(NOT hash) - set(${_var} "HEAD-HASH-NOTFOUND" PARENT_SCOPE) - return() - endif() - - # TODO sanitize - #if((${ARGN}" MATCHES "&&") OR - # (ARGN MATCHES "||") OR - # (ARGN MATCHES "\\;")) - # message("Please report the following error to the project!") - # message(FATAL_ERROR "Looks like someone's doing something nefarious with git_describe! Passed arguments ${ARGN}") - #endif() - - #message(STATUS "Arguments to execute_process: ${ARGN}") - - execute_process(COMMAND - "${GIT_EXECUTABLE}" - describe - ${hash} - ${ARGN} - WORKING_DIRECTORY - "${CMAKE_SOURCE_DIR}" - RESULT_VARIABLE - res - OUTPUT_VARIABLE - out - ERROR_QUIET - OUTPUT_STRIP_TRAILING_WHITESPACE) - if(NOT res EQUAL 0) - set(out "${out}-${res}-NOTFOUND") - endif() - - set(${_var} "${out}" PARENT_SCOPE) -endfunction() - -function(git_get_exact_tag _var) - git_describe(out --exact-match ${ARGN}) - set(${_var} "${out}" PARENT_SCOPE) -endfunction() diff --git a/cmake/GetGitRevisionDescription.cmake.in b/cmake/GetGitRevisionDescription.cmake.in deleted file mode 100644 index 6d8b708..0000000 --- a/cmake/GetGitRevisionDescription.cmake.in +++ /dev/null @@ -1,41 +0,0 @@ -# -# Internal file for GetGitRevisionDescription.cmake -# -# Requires CMake 2.6 or newer (uses the 'function' command) -# -# Original Author: -# 2009-2010 Ryan Pavlik -# http://academic.cleardefinition.com -# Iowa State University HCI Graduate Program/VRAC -# -# Copyright Iowa State University 2009-2010. -# Distributed under the Boost Software License, Version 1.0. -# (See accompanying file LICENSE_1_0.txt or copy at -# http://www.boost.org/LICENSE_1_0.txt) - -set(HEAD_HASH) - -file(READ "@HEAD_FILE@" HEAD_CONTENTS LIMIT 1024) - -string(STRIP "${HEAD_CONTENTS}" HEAD_CONTENTS) -if(HEAD_CONTENTS MATCHES "ref") - # named branch - string(REPLACE "ref: " "" HEAD_REF "${HEAD_CONTENTS}") - if(EXISTS "@GIT_DIR@/${HEAD_REF}") - configure_file("@GIT_DIR@/${HEAD_REF}" "@GIT_DATA@/head-ref" COPYONLY) - else() - configure_file("@GIT_DIR@/packed-refs" "@GIT_DATA@/packed-refs" COPYONLY) - file(READ "@GIT_DATA@/packed-refs" PACKED_REFS) - if(${PACKED_REFS} MATCHES "([0-9a-z]*) ${HEAD_REF}") - set(HEAD_HASH "${CMAKE_MATCH_1}") - endif() - endif() -else() - # detached HEAD - configure_file("@GIT_DIR@/HEAD" "@GIT_DATA@/head-ref" COPYONLY) -endif() - -if(NOT HEAD_HASH) - file(READ "@GIT_DATA@/head-ref" HEAD_HASH LIMIT 1024) - string(STRIP "${HEAD_HASH}" HEAD_HASH) -endif() diff --git a/cmake/GitFunctions.cmake b/cmake/GitFunctions.cmake deleted file mode 100644 index bbb4903..0000000 --- a/cmake/GitFunctions.cmake +++ /dev/null @@ -1,22 +0,0 @@ -if(__git_functions) - return() -endif() -set(__git_functions YES) - -function( get_branch_from_git ) - execute_process( - COMMAND git rev-parse --abbrev-ref HEAD - WORKING_DIRECTORY ${PROJECT_SOURCE_DIR} - RESULT_VARIABLE git_result - OUTPUT_VARIABLE git_branch - ERROR_VARIABLE git_error - OUTPUT_STRIP_TRAILING_WHITESPACE - ERROR_STRIP_TRAILING_WHITESPACE - ) - if( NOT git_result EQUAL 0 ) - message( FATAL_ERROR "Failed to execute Git: ${git_error}" ) - endif() - - set( GIT_BRANCH ${git_branch} PARENT_SCOPE ) -endfunction( get_branch_from_git ) - diff --git a/cmake/PackageConfigurator.cmake b/cmake/PackageConfigurator.cmake deleted file mode 100644 index b67615d..0000000 --- a/cmake/PackageConfigurator.cmake +++ /dev/null @@ -1,44 +0,0 @@ -# Create package-config files : -# - ConfigVersion.cmake -# - Config.cmake -# They are installed in lib/cmake/. -# -# Required variables : -# - VERSION -# - PROJECT_NAME -# - -# Include needed for 'write_basic_package_version_file' -include(CMakePackageConfigHelpers) - -write_basic_package_version_file( - "${CMAKE_CURRENT_BINARY_DIR}/cmake/${PROJECT_NAME}ConfigVersion.cmake" - VERSION ${VERSION} - COMPATIBILITY AnyNewerVersion -) - -configure_file(cmake/${PROJECT_NAME}Config.cmake - "${CMAKE_CURRENT_BINARY_DIR}/cmake/${PROJECT_NAME}Config.cmake" - COPYONLY -) - -# Destination -set(config_install_dir lib/cmake/${PROJECT_NAME}) - -# Config installation -# * /lib/cmake//Targets.cmake -install( - EXPORT ${PROJECT_NAME}Targets - DESTINATION ${config_install_dir} -) - -# Config installation -# * /lib/cmake//Config.cmake -# * /lib/cmake//ConfigVersion.cmake -install( - FILES - cmake/${PROJECT_NAME}Config.cmake - "${CMAKE_CURRENT_BINARY_DIR}/cmake/${PROJECT_NAME}ConfigVersion.cmake" - DESTINATION ${config_install_dir} - COMPONENT devel -) \ No newline at end of file diff --git a/cmake/Submodules.cmake b/cmake/Submodules.cmake deleted file mode 100644 index 0d1b89d..0000000 --- a/cmake/Submodules.cmake +++ /dev/null @@ -1,57 +0,0 @@ -if(EXISTS "${PROJECT_SOURCE_DIR}/.gitmodules") -message(STATUS "Updating submodules to their latest/fixed versions") -message(STATUS "(this can take a while, please be patient)") - -### First, get all submodules in -if(${GIT_SUBMODULES_CHECKOUT_QUIET}) - execute_process( - COMMAND git submodule update --init --recursive - WORKING_DIRECTORY ${PROJECT_SOURCE_DIR} - OUTPUT_QUIET - ERROR_QUIET - ) -else() - execute_process( - COMMAND git submodule update --init --recursive - WORKING_DIRECTORY ${PROJECT_SOURCE_DIR} - ) -endif() - -### Then, checkout each submodule to the specified commit -# Note: Execute separate processes here, to make sure each one is run, -# should one crash (because of branch not existing, this, that ... whatever) -foreach(GIT_SUBMODULE ${GIT_SUBMODULES}) - - if( "${GIT_SUBMODULE_VERSION_${GIT_SUBMODULE}}" STREQUAL "" ) - message(STATUS "no specific version given for submodule ${GIT_SUBMODULE}, checking out master") - if( "${GIT_SUBMODULE_BRANCH_${GIT_SUBMODULE}}" STREQUAL "" ) - set(GIT_SUBMODULE_VERSION_${GIT_SUBMODULE} "master") - else() - set(GIT_SUBMODULE_VERSION_${GIT_SUBMODULE} ${GIT_SUBMODULE_BRANCH_${GIT_SUBMODULE}}) - endif() - endif() - - if( "${GIT_SUBMODULE_DIR_${GIT_SUBMODULE}}" STREQUAL "" ) - set(GIT_SUBMODULES_DIRECTORY external) - else() - set(GIT_SUBMODULES_DIRECTORY ${GIT_SUBMODULE_DIR_${GIT_SUBMODULE}}) - endif() - - if(${GIT_SUBMODULES_CHECKOUT_QUIET}) - execute_process( - COMMAND git checkout ${GIT_SUBMODULE_VERSION_${GIT_SUBMODULE}} - WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}/${GIT_SUBMODULES_DIRECTORY}/${GIT_SUBMODULE} - OUTPUT_QUIET - ERROR_QUIET - ) - else() - message(STATUS "checking out ${GIT_SUBMODULE}'s commit/tag ${GIT_SUBMODULE_VERSION_${GIT_SUBMODULE}}") - execute_process( - COMMAND git checkout ${GIT_SUBMODULE_VERSION_${GIT_SUBMODULE}} - WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}/${GIT_SUBMODULES_DIRECTORY}/${GIT_SUBMODULE} - ) - endif() - -endforeach(${GIT_SUBMODULE}) - -endif() diff --git a/conanfile.txt b/conanfile.txt deleted file mode 100644 index 3d6f0e2..0000000 --- a/conanfile.txt +++ /dev/null @@ -1,19 +0,0 @@ -[requires] - gsl_microsoft/20180102@bincrafters/stable - spdlog/0.16.3@bincrafters/stable - fmt/5.2.1@bincrafters/stable - Seasocks/1.3.2@minres/stable - SystemC/2.3.2@minres/stable - SystemCVerification/2.0.1@minres/stable - SystemC-CCI/1.0.0@minres/stable - -[generators] - cmake - -[options] - Seasocks:shared=True - fmt:header_only=True - SystemC:stdcxx=14 - SystemC:shared=True - SystemCVerification:stdcxx=14 - SystemC-CCI:stdcxx=14 diff --git a/cycles.txt b/cycles.txt deleted file mode 100644 index 2f86175..0000000 --- a/cycles.txt +++ /dev/null @@ -1,1728 +0,0 @@ -{ - "RV32GC" : [ - { - "name" : "LUI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AUIPC", - "size" : 32, - "delay" : 1 - }, - { - "name" : "JAL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "JALR", - "size" : 32, - "delay" : 1 - }, - { - "name" : "BEQ", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BNE", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BLT", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BGE", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BLTU", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BGEU", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "LB", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LH", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LBU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LHU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SB", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SH", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ADDI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLTI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLTIU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "XORI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ORI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ANDI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLLI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRLI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRAI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ADD", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SUB", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLT", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLTU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "XOR", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRA", - "size" : 32, - "delay" : 1 - }, - { - "name" : "OR", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AND", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FENCE", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FENCE_I", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ECALL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "EBREAK", - "size" : 32, - "delay" : 1 - }, - { - "name" : "URET", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRET", - "size" : 32, - "delay" : 1 - }, - { - "name" : "MRET", - "size" : 32, - "delay" : 1 - }, - { - "name" : "WFI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SFENCE.VMA", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRS", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRC", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRWI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRSI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRCI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "MUL", - "size" : 32, - "delay" : 5 - }, - { - "name" : "MULH", - "size" : 32, - "delay" : 5 - }, - { - "name" : "MULHSU", - "size" : 320, - "delay" : 5 - }, - { - "name" : "MULHU", - "size" : 32, - "delay" : 5 - }, - { - "name" : "DIV", - "size" : 32, - "delay" : 10 - }, - { - "name" : "DIVU", - "size" : 32, - "delay" : 10 - }, - { - "name" : "REM", - "size" : 32, - "delay" : 10 - }, - { - "name" : "REMU", - "size" : 32, - "delay" : 10 - }, - { - "name" : "LR.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SC.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOSWAP.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOADD.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOXOR.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOAND.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOOR.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMIN.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMAX.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMINU.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMAXU.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "C.ADDI4SPN", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.LW", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.SW", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.ADDI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.NOP", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.JAL", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.LI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.LUI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.ADDI16SP", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.SRLI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.SRAI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.ANDI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.SUB", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.XOR", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.OR", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.AND", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.J", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.BEQZ", - "size" : 16, - "delay" : [1, 3] - }, - { - "name" : "C.BNEZ", - "size" : 16, - "delay" : [1, 3] - }, - { - "name" : "C.SLLI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.LWSP", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.MV", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.JR", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.ADD", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.JALR", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.EBREAK", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.SWSP", - "size" : 16, - "delay" : 1 - }, - { - "name" : "DII", - "size" : 16, - "delay" : 1 - }, - { - "name" : "FLW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMADD.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMSUB.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FNMADD.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FNMSUB.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FADD.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSUB.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMUL.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FDIV.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSQRT.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSGNJ.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSGNJN.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSGNJX.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMIN.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMAX.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCVT.W.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCVT.WU.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FEQ.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FLT.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FLE.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCLASS.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCVT.S.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCVT.S.WU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMV.X.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMV.W.X", - "size" : 32, - "delay" : 1 - }, - { - "name" : "C.FLW", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.FSW", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.FLWSP", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.FSWSP", - "size" : 16, - "delay" : 1 - }, - { - "name" : "FLD", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSD", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMADD.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMSUB.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FNMADD.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FNMSUB.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FADD.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSUB.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMUL.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FDIV.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSQRT.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSGNJ.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSGNJN.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FSGNJX.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMIN.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FMAX.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCVT.S.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCVT.D.S", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FEQ.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FLT.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FLE.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCLASS.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCVT.W.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCVT.WU.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCVT.D.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FCVT.D.WU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "C.FLD", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.FSD", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.FLDSP", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.FSDSP", - "size" : 16, - "delay" : 1 - } - ], - "RV32IMAC" : [ - { - "name" : "LUI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AUIPC", - "size" : 32, - "delay" : 1 - }, - { - "name" : "JAL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "JALR", - "size" : 32, - "delay" : 1 - }, - { - "name" : "BEQ", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BNE", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BLT", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BGE", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BLTU", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BGEU", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "LB", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LH", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LBU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LHU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SB", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SH", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ADDI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLTI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLTIU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "XORI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ORI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ANDI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLLI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRLI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRAI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ADD", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SUB", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLT", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLTU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "XOR", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRA", - "size" : 32, - "delay" : 1 - }, - { - "name" : "OR", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AND", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FENCE", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FENCE_I", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ECALL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "EBREAK", - "size" : 32, - "delay" : 1 - }, - { - "name" : "URET", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRET", - "size" : 32, - "delay" : 1 - }, - { - "name" : "MRET", - "size" : 32, - "delay" : 1 - }, - { - "name" : "WFI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SFENCE.VMA", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRS", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRC", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRWI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRSI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRCI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "MUL", - "size" : 32, - "delay" : 5 - }, - { - "name" : "MULH", - "size" : 32, - "delay" : 5 - }, - { - "name" : "MULHSU", - "size" : 32, - "delay" : 5 - }, - { - "name" : "MULHU", - "size" : 32, - "delay" : 5 - }, - { - "name" : "DIV", - "size" : 32, - "delay" : 10 - }, - { - "name" : "DIVU", - "size" : 32, - "delay" : 10 - }, - { - "name" : "REM", - "size" : 32, - "delay" : 10 - }, - { - "name" : "REMU", - "size" : 32, - "delay" : 10 - }, - { - "name" : "LR.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SC.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOSWAP.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOADD.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOXOR.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOAND.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOOR.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMIN.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMAX.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMINU.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMAXU.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "C.ADDI4SPN", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.LW", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.SW", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.ADDI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.NOP", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.JAL", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.LI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.LUI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.ADDI16SP", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.SRLI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.SRAI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.ANDI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.SUB", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.XOR", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.OR", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.AND", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.J", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.BEQZ", - "size" : 16, - "delay" : [1, 3] - }, - { - "name" : "C.BNEZ", - "size" : 16, - "delay" : [1, 3] - }, - { - "name" : "C.SLLI", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.LWSP", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.MV", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.JR", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.ADD", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.JALR", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.EBREAK", - "size" : 16, - "delay" : 1 - }, - { - "name" : "C.SWSP", - "size" : 16, - "delay" : 1 - }, - { - "name" : "DII", - "size" : 16, - "delay" : 1 - } - ], - "RV64IA" : [ - { - "name" : "LWU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LD", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SD", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLLI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRLI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRAI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ADDIW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLLIW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRLIW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRAIW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ADDW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SUBW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLLW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRLW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRAW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LUI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AUIPC", - "size" : 32, - "delay" : 1 - }, - { - "name" : "JAL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "JALR", - "size" : 32, - "delay" : 1 - }, - { - "name" : "BEQ", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BNE", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BLT", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BGE", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BLTU", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "BGEU", - "size" : 32, - "delay" : [1, 3] - }, - { - "name" : "LB", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LH", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LBU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LHU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SB", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SH", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ADDI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLTI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLTIU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "XORI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ORI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ANDI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ADD", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SUB", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLT", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SLTU", - "size" : 32, - "delay" : 1 - }, - { - "name" : "XOR", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRA", - "size" : 32, - "delay" : 1 - }, - { - "name" : "OR", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AND", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FENCE", - "size" : 32, - "delay" : 1 - }, - { - "name" : "FENCE_I", - "size" : 32, - "delay" : 1 - }, - { - "name" : "ECALL", - "size" : 32, - "delay" : 1 - }, - { - "name" : "EBREAK", - "size" : 32, - "delay" : 1 - }, - { - "name" : "URET", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SRET", - "size" : 32, - "delay" : 1 - }, - { - "name" : "MRET", - "size" : 32, - "delay" : 1 - }, - { - "name" : "WFI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SFENCE.VMA", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRW", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRS", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRC", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRWI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRSI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "CSRRCI", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LR.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SC.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOSWAP.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOADD.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOXOR.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOAND.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOOR.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMIN.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMAX.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMINU.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMAXU.D", - "size" : 32, - "delay" : 1 - }, - { - "name" : "LR.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "SC.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOSWAP.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOADD.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOXOR.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOAND.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOOR.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMIN.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMAX.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMINU.W", - "size" : 32, - "delay" : 1 - }, - { - "name" : "AMOMAXU.W", - "size" : 32, - "delay" : 1 - } - ] -} \ No newline at end of file diff --git a/dbt-core b/dbt-core deleted file mode 160000 index 2f4aab8..0000000 --- a/dbt-core +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 2f4aab87b0f86504a26cd8a6e781fc43bfd6e00f diff --git a/etc/CoreDSL generator.launch b/etc/CoreDSL generator.launch deleted file mode 100644 index e6e6eda..0000000 --- a/etc/CoreDSL generator.launch +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/etc/cmake DBT-RISE-RISCV Debug.launch b/etc/cmake DBT-RISE-RISCV Debug.launch deleted file mode 100644 index 30e3133..0000000 --- a/etc/cmake DBT-RISE-RISCV Debug.launch +++ /dev/null @@ -1,15 +0,0 @@ - - - - - - - - - - - - - - - diff --git a/etc/cmake DBT-RISE-RISCV Release.launch b/etc/cmake DBT-RISE-RISCV Release.launch deleted file mode 100644 index c9c08c8..0000000 --- a/etc/cmake DBT-RISE-RISCV Release.launch +++ /dev/null @@ -1,7 +0,0 @@ - - - - - - - diff --git a/etc/cmake.sh b/etc/cmake.sh deleted file mode 100755 index 2ffcd32..0000000 --- a/etc/cmake.sh +++ /dev/null @@ -1,47 +0,0 @@ -#!/bin/sh -#****************************************************************************** -# Copyright (C) 2018 MINRES Technologies GmbH -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its contributors -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -#******************************************************************************/ -## - -if [ -n "$1" ]; then - suffix=$1 -else - suffix=Debug -fi -cwd=`pwd` -for i in $*; do - if echo "$i" | grep 'CMAKE_BUILD_TYPE='; then - suffix=`echo $i | sed 's/-DCMAKE_BUILD_TYPE=//'` - fi -done -mkdir -p build/$suffix && cd build/$suffix -cmake $* $cwd diff --git a/etc/dbt-riscv Debug hello gdb.launch b/etc/dbt-riscv Debug hello gdb.launch deleted file mode 100644 index 07be1e0..0000000 --- a/etc/dbt-riscv Debug hello gdb.launch +++ /dev/null @@ -1,42 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/etc/dbt-riscv Debug hello w plugin.launch b/etc/dbt-riscv Debug hello w plugin.launch deleted file mode 100644 index 5701194..0000000 --- a/etc/dbt-riscv Debug hello w plugin.launch +++ /dev/null @@ -1,42 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/etc/hello Debug.launch b/etc/hello Debug.launch deleted file mode 100644 index 100dbaa..0000000 --- a/etc/hello Debug.launch +++ /dev/null @@ -1,47 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/external/CMakeLists.txt b/external/CMakeLists.txt deleted file mode 100644 index 34c7ad1..0000000 --- a/external/CMakeLists.txt +++ /dev/null @@ -1,28 +0,0 @@ -cmake_minimum_required(VERSION 3.3) -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../cmake) - -# Set the name of your project here -project("external") - -include(Common) - - -include_directories( ${PROJECT_SOURCE_DIR}/libGIS ) - -FILE(GLOB ElfioHeaders elfio *.hpp) -FILE(GLOB GISHeaders libGis *.h) - -set(LIB_HEADERS ${ElfioHeaders} ${GISHeaders}) -set(LIB_SOURCES - libGIS/atmel_generic.c - libGIS/ihex.c - libGIS/srecord.c -) - -# Define two variables in order not to repeat ourselves. -set(LIBRARY_NAME external) - -# Define the library -add_library(${LIBRARY_NAME} ${LIB_SOURCES}) - - diff --git a/external/elfio b/external/elfio deleted file mode 160000 index 1fdbb64..0000000 --- a/external/elfio +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 1fdbb6423528684e7b5d6dd9095b64f5617b1434 diff --git a/external/libGIS b/external/libGIS deleted file mode 160000 index f82b9dd..0000000 --- a/external/libGIS +++ /dev/null @@ -1 +0,0 @@ -Subproject commit f82b9dd3018d479230ad68a02da41fa95cad9123 diff --git a/riscv/.gitignore b/gen_input/.gitignore similarity index 100% rename from riscv/.gitignore rename to gen_input/.gitignore diff --git a/riscv/gen_input/RISCVBase.core_desc b/gen_input/RISCVBase.core_desc similarity index 100% rename from riscv/gen_input/RISCVBase.core_desc rename to gen_input/RISCVBase.core_desc diff --git a/riscv/gen_input/RV32I.core_desc b/gen_input/RV32I.core_desc similarity index 100% rename from riscv/gen_input/RV32I.core_desc rename to gen_input/RV32I.core_desc diff --git a/riscv/gen_input/RV64I.core_desc b/gen_input/RV64I.core_desc similarity index 100% rename from riscv/gen_input/RV64I.core_desc rename to gen_input/RV64I.core_desc diff --git a/riscv/gen_input/RVA.core_desc b/gen_input/RVA.core_desc similarity index 100% rename from riscv/gen_input/RVA.core_desc rename to gen_input/RVA.core_desc diff --git a/riscv/gen_input/RVC.core_desc b/gen_input/RVC.core_desc similarity index 100% rename from riscv/gen_input/RVC.core_desc rename to gen_input/RVC.core_desc diff --git a/riscv/gen_input/RVD.core_desc b/gen_input/RVD.core_desc similarity index 100% rename from riscv/gen_input/RVD.core_desc rename to gen_input/RVD.core_desc diff --git a/riscv/gen_input/RVF.core_desc b/gen_input/RVF.core_desc similarity index 100% rename from riscv/gen_input/RVF.core_desc rename to gen_input/RVF.core_desc diff --git a/riscv/gen_input/RVM.core_desc b/gen_input/RVM.core_desc similarity index 100% rename from riscv/gen_input/RVM.core_desc rename to gen_input/RVM.core_desc diff --git a/riscv/gen_input/minres_rv.core_desc b/gen_input/minres_rv.core_desc similarity index 100% rename from riscv/gen_input/minres_rv.core_desc rename to gen_input/minres_rv.core_desc diff --git a/riscv/gen_input/templates/CORENAME_cyles.txt.gtl b/gen_input/templates/CORENAME_cyles.txt.gtl similarity index 100% rename from riscv/gen_input/templates/CORENAME_cyles.txt.gtl rename to gen_input/templates/CORENAME_cyles.txt.gtl diff --git a/riscv/gen_input/templates/incl-CORENAME.h.gtl b/gen_input/templates/incl-CORENAME.h.gtl similarity index 100% rename from riscv/gen_input/templates/incl-CORENAME.h.gtl rename to gen_input/templates/incl-CORENAME.h.gtl diff --git a/riscv/gen_input/templates/src-CORENAME.cpp.gtl b/gen_input/templates/src-CORENAME.cpp.gtl similarity index 100% rename from riscv/gen_input/templates/src-CORENAME.cpp.gtl rename to gen_input/templates/src-CORENAME.cpp.gtl diff --git a/riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl b/gen_input/templates/vm-vm_CORENAME.cpp.gtl similarity index 100% rename from riscv/gen_input/templates/vm-vm_CORENAME.cpp.gtl rename to gen_input/templates/vm-vm_CORENAME.cpp.gtl diff --git a/html/app.js b/html/app.js deleted file mode 100644 index 2e384f1..0000000 --- a/html/app.js +++ /dev/null @@ -1,64 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. 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- - - diff --git a/riscv/incl/iss/arch/riscv_hart_msu_vp.h b/incl/iss/arch/riscv_hart_msu_vp.h similarity index 100% rename from riscv/incl/iss/arch/riscv_hart_msu_vp.h rename to incl/iss/arch/riscv_hart_msu_vp.h diff --git a/riscv/incl/iss/arch/rv32gc.h b/incl/iss/arch/rv32gc.h similarity index 100% rename from riscv/incl/iss/arch/rv32gc.h rename to incl/iss/arch/rv32gc.h diff --git a/riscv/incl/iss/arch/rv32imac.h b/incl/iss/arch/rv32imac.h similarity index 100% rename from riscv/incl/iss/arch/rv32imac.h rename to incl/iss/arch/rv32imac.h diff --git a/riscv/incl/iss/arch/rv64gc.h b/incl/iss/arch/rv64gc.h similarity index 100% rename from riscv/incl/iss/arch/rv64gc.h rename to incl/iss/arch/rv64gc.h diff --git a/riscv/incl/iss/arch/rv64i.h b/incl/iss/arch/rv64i.h similarity index 100% rename from riscv/incl/iss/arch/rv64i.h rename to incl/iss/arch/rv64i.h diff --git a/riscv/incl/iss/debugger/riscv_target_adapter.h b/incl/iss/debugger/riscv_target_adapter.h similarity index 100% rename from riscv/incl/iss/debugger/riscv_target_adapter.h rename to incl/iss/debugger/riscv_target_adapter.h diff --git a/riscv/incl/iss/plugin/cycle_estimate.h b/incl/iss/plugin/cycle_estimate.h similarity index 100% rename from riscv/incl/iss/plugin/cycle_estimate.h rename to incl/iss/plugin/cycle_estimate.h diff --git a/riscv/incl/iss/plugin/instruction_count.h b/incl/iss/plugin/instruction_count.h similarity index 100% rename from riscv/incl/iss/plugin/instruction_count.h rename to incl/iss/plugin/instruction_count.h diff --git a/riscv/incl/sysc/core_complex.h b/incl/sysc/core_complex.h similarity index 100% rename from riscv/incl/sysc/core_complex.h rename to incl/sysc/core_complex.h diff --git a/platform/CMakeLists.txt b/platform/CMakeLists.txt deleted file mode 100644 index a96449f..0000000 --- a/platform/CMakeLists.txt +++ /dev/null @@ -1,57 +0,0 @@ -cmake_minimum_required(VERSION 3.3) -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../cmake) # main (top) cmake dir -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake) # project specific cmake dir - -# CMake useful variables -set(CMAKE_RUNTIME_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/bin") -set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib") -set(CMAKE_LIBRARY_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib") - -# Set the name of your project here -project("platform") - -include(Common) -# check that we have averything we need -if(!SystemC_FOUND) - message( FATAL_ERROR "SystemC library not found." ) -endif() - -if(!CCI_FOUND) - message( FATAL_ERROR "SystemC CCI library not found." ) -endif() - -# This sets the include directory for the reference project. This is the -I flag in gcc. - -add_dependent_subproject(dbt-core) -add_dependent_subproject(sc-components) -add_dependent_subproject(riscv) - -include_directories( - ${PROJECT_SOURCE_DIR}/../external/elfio - ${PROJECT_SOURCE_DIR}/../external/libGIS - ${Boost_INCLUDE_DIRS} -) - -# Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH) -set(CMAKE_MACOSX_RPATH ON) -set(CMAKE_SKIP_BUILD_RPATH FALSE) -set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE) -set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib") -set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE) - -## the following setting needs to be consistent with the library -#add_definitions(-DSC_DEFAULT_WRITER_POLICY=SC_MANY_WRITERS) - -add_subdirectory(src) - -# -# SYSTEM PACKAGING (RPM, TGZ, ...) -# _____________________________________________________________________________ - -#include(CPackConfig) - -# -# CMAKE PACKAGING (for other CMake projects to use this one easily) -# _____________________________________________________________________________ - -#include(PackageConfigurator) \ No newline at end of file diff --git a/platform/gen_input/aon.rdl b/platform/gen_input/aon.rdl deleted file mode 100644 index 234d313..0000000 --- a/platform/gen_input/aon.rdl +++ /dev/null @@ -1,158 +0,0 @@ -regfile aon_regs { - // Watchdog Timer Registers - reg { - name = "wdogcfg"; - desc = "Watchdog Timer Config Register"; - field { - name="data"; - } data[31:0]; - } wdogcfg @0x00; - reg { - name ="wdogcount"; - desc = "Watchdog Timer Count Registers"; - field { - name="data"; - } data[31:0]; - } wdogcount @0x08; - reg { - name ="wdogs"; - desc = ""; - field { - name="data"; - } data[31:0]; - } wdogs @0x10; - reg { - name ="wdogfeed"; - desc = ""; - field { - name="data"; - } data[31:0]; - } wdogfeed @0x18; - reg { - name ="wdogkey"; - desc = ""; - field { - name="data"; - } data[31:0]; - } wdogkey @0x1C; - reg { - name ="wdogcmp"; - desc = ""; - field { - name="data"; - } data[31:0]; - } wdogcmp @0x20; - // Real-Time Clock Registers - reg { - name ="rtccfg"; - desc = ""; - field { - name="data"; - } data[31:0]; - } rtccfg @0x40; - reg { - name ="rtclo"; - desc = ""; - field { - name="data"; - } data[31:0]; - } rtclo @0x48; - reg { - name ="rtchi"; - desc = ""; - field { - name="data"; - } data[31:0]; - } rtchi @0x4C; - reg { - name ="rtcs"; - desc = ""; - field { - name="data"; - } data[31:0]; - } rtcs @0x50; - reg { - name ="rtccmp"; - desc = ""; - field { - name="data"; - } data[31:0]; - } rtccmp @0x60; - // AON Clock Configuration Registers - reg { - name ="lfrosccfg"; - desc = ""; - field { - name="data"; - } data[31:0]; - } lfrosccfg @0x70; - // Backup Registers - reg { - name ="lfrosccfg"; - desc = ""; - field { - name="data"; - } data[31:0]; - } backup[32] @0x80; - // Power Management Unit - reg { - name ="pmuwakeupi"; - desc = ""; - field { - name="delay"; - } delay[3:0]; - field { - name="vddpaden"; - } vddpaden[5:5]; - field { - name="corerst"; - } corerst[7:7]; - field { - name="hfclkrst"; - } hfclkrst[8:8]; - } pmuwakeupi[8] @0x0100; - reg { - name ="pmusleepi"; - desc = ""; - field { - name="delay"; - } delay[3:0]; - field { - name="vddpaden"; - } vddpaden[5:5]; - field { - name="corerst"; - } corerst[7:7]; - field { - name="hfclkrst"; - } hfclkrst[8:8]; - } pmusleepi[8] @0x0120; - reg { - name ="pmuie"; - desc = ""; - field { - name="data"; - } data[31:0]; - } pmuie @0x0140; - reg { - name ="pmucause"; - desc = ""; - field { - name="data"; - } data[31:0]; - } pmucause @0x0144; - reg { - name ="pmusleep"; - desc = ""; - field { - name="data"; - } data[31:0]; - } pmusleep @0x0148; - reg { - name ="pmukey"; - desc = ""; - field { - name="data"; - } data[31:0]; - } pmukey @0x014C; -}; \ No newline at end of file diff --git a/platform/gen_input/clint.rdl b/platform/gen_input/clint.rdl deleted file mode 100644 index 4d61ba6..0000000 --- a/platform/gen_input/clint.rdl +++ /dev/null @@ -1,27 +0,0 @@ -regfile clint_regs { - reg { - name = "msip"; - desc = "Hart 0 software interrupt register"; - field { - name="msip"; - } msip[0:0]; - } msip @0; - reg { - name = "mtimecmp"; - desc = "Hart 0 time comparator register"; - regwidth=64; - field { - name="data"; - fieldwidth=64; - } data = 64'h7FFFFFFFFFFFFFFF; - } mtimecmp @0x4000; - reg { - name = "mtime"; - desc = "Timer register"; - regwidth=64; - field { - fieldwidth=64; - name="data"; - } data[63:0]; - } mtime @0xBFF8; -}; \ No newline at end of file diff --git a/platform/gen_input/fe310.rdl b/platform/gen_input/fe310.rdl deleted file mode 100644 index aedabcb..0000000 --- a/platform/gen_input/fe310.rdl +++ /dev/null @@ -1,25 +0,0 @@ -`include "gpio.rdl" -`include "uart.rdl" -`include "spi.rdl" -`include "pwm.rdl" -`include "plic.rdl" -`include "aon.rdl" -`include "prci.rdl" -`include "clint.rdl" - -addrmap e300_plat_t { - lsb0; - clint_regs clint @0x02000000; - plic_regs plic @0x0C000000; - aon_regs aon @0x10000000; - prci_regs prci @0x10008000; - gpio_regs gpio0 @0x10012000; - uart_regs uart0 @0x10013000; - spi_regs qspi0 @0x10014000; - pwm_regs pwm0 @0x10015000; - uart_regs uart1 @0x10023000; - spi_regs qspi1 @0x10024000; - pwm_regs pwm1 @0x10025000; - spi_regs qspi2 @0x10034000; - pwm_regs pwm2 @0x10035000; -} e300_plat; diff --git a/platform/gen_input/gpio.rdl b/platform/gen_input/gpio.rdl deleted file mode 100644 index 483f4b6..0000000 --- a/platform/gen_input/gpio.rdl +++ /dev/null @@ -1,121 +0,0 @@ -regfile gpio_regs { - reg { - name="value"; - desc="pin value"; - field { - name = "data"; - } data[31:0]; - } value @0x000; - reg { - name="input_en"; - desc="* pin input enable"; - field { - name = "data"; - } data[31:0]; - } input_en @0x004; - reg { - name="output_en"; - desc="pin output enable"; - field { - name = "data"; - } data[31:0]; - } output_en @0x008; - reg { - name="port"; - desc="output port value"; - field { - name = "data"; - } data[31:0]; - } port @0x00C; - reg { - name="pue"; - desc="internal pull-up enable"; - field { - name = "data"; - } data[31:0]; - } pue @0x010; - reg { - name="ds"; - desc="Pin Drive Strength"; - field { - name = "data"; - } data[31:0]; - } ds @0x014; - reg { - name="rise_ie"; - desc="rise interrupt enable"; - field { - name = "data"; - } data[31:0]; - } rise_ie @0x018; - reg { - name="rise_ip"; - desc="rise interrupt pending"; - field { - name = "data"; - } data[31:0]; - } rise_ip @0x01C; - reg { - name="fall_ie"; - desc="fall interrupt enable"; - field { - name = "data"; - } data[31:0]; - } fall_ie @0x020; - reg { - name="fall_ip"; - desc="fall interrupt pending"; - field { - name = "data"; - } data[31:0]; - } fall_ip @0x024; - reg { - name="high_ie"; - desc="high interrupt enable"; - field { - name = "data"; - } data[31:0]; - } high_ie @0x028; - reg { - name="high_ip"; - desc="high interrupt pending"; - field { - name = "data"; - } data[31:0]; - } high_ip @0x02C; - reg { - name="low_ie"; - desc="low interrupt enable"; - field { - name = "data"; - } data[31:0]; - } low_ie @0x030; - reg { - name="low_ip"; - desc="low interrupt pending"; - field { - name = "data"; - } data[31:0]; - } low_ip @0x034; - reg { - name="iof_en"; - desc="HW I/O Function enable"; - field { - name = "data"; - } data[31:0]; - } iof_en @0x038; - reg { - name="iof_sel"; - desc="HW I/O Function select"; - field { - name = "data"; - } data[31:0]; - } iof_sel @0x03C; - reg { - name="out_xor"; - desc="Output XOR (invert)"; - field { - name = "data"; - } data[31:0]; - } out_xor @0x040; -}; \ No newline at end of file diff --git a/platform/gen_input/plic.rdl b/platform/gen_input/plic.rdl deleted file mode 100644 index 68591aa..0000000 --- a/platform/gen_input/plic.rdl +++ /dev/null @@ -1,27 +0,0 @@ -regfile plic_regs { - reg { - name="priority"; - desc="interrupt source priority"; - field {} priority[2:0]; - } priority[256] @0x000; - reg { - name="pending"; - desc="pending irq"; - field {} pending[31:0]; - } pending[8] @0x1000; - reg { - name="enabled"; - desc="enabled interrupts"; - field {} enabled[31:0]; - } enabled[8] @0x2000; - reg { - name="threshold"; - desc="interrupt priority threshold"; - field {} \threshold[2:0]; - } \threshold @0x200000; - reg { - name="claim/complete"; - desc="interrupt handling completed"; - field {} interrupt_claimed[31:0]; - } claim_complete @0x200004; -}; \ No newline at end of file diff --git a/platform/gen_input/prci.rdl b/platform/gen_input/prci.rdl deleted file mode 100644 index ee00de8..0000000 --- a/platform/gen_input/prci.rdl +++ /dev/null @@ -1,41 +0,0 @@ -regfile prci_regs { - reg { - name ="hfrosccfg"; - desc = ""; - field {} hfroscdiv[5:0]; - field {} hfrosctrim[20:16]; - field {} hfroscen[30:30]; - field {} hfroscrdy[31:31]; - } hfrosccfg @0x00; - reg { - name ="hfxosccfg"; - desc = ""; - field {} hfxoscrdy[31:31]; - field {} hfxoscen[30:30]; - } hfxosccfg @0x04; - reg { - name ="pllcfg"; - desc = ""; - field {} pllr[2:0]; - field {} pllf[9:4]; - field {} pllq[11:10]; - field {} pllsel[16:16]; - field {} pllrefsel[17:17]; - field {} pllbypass[18:18]; - field {} plllock[31:31]; - } pllcfg @0x08; - reg { - name ="plloutdiv"; - desc = ""; - field { - name="data"; - } data[31:0]; - } plloutdiv @0x0c; - reg { - name ="coreclkcfg"; - desc = ""; - field { - name="data"; - } data[31:0]; - } coreclkcfg @0x10; -}; \ No newline at end of file diff --git a/platform/gen_input/pwm.rdl b/platform/gen_input/pwm.rdl deleted file mode 100644 index c51be51..0000000 --- a/platform/gen_input/pwm.rdl +++ /dev/null @@ -1,96 +0,0 @@ -regfile pwm_regs { - reg { - name="pwmcfg"; - desc="pin value"; - field { - name = "pwmscale"; - } pwmscale[3:0]; - field { - name = "pwmsticky"; - } pwmsticky[8:8]; - field { - name = "pwmzerocmp"; - } pwmsticky[9:9]; - field { - name = "pwmdeglitch"; - } pwmsticky[10:10]; - field { - name = "pwmenalways"; - } pwmenalways[12:12]; - field { - name = "pwmenoneshot"; - } pwmenalways[13:13]; - field { - name = "pwmcmp0center"; - } pwmcmp0center[16:16]; - field { - name = "pwmcmp1center"; - } pwmcmp1center[17:17]; - field { - name = "pwmcmp2center"; - } pwmcmp2center[18:18]; - field { - name = "pwmcmp3center"; - } pwmcmp3center[19:19]; - field { - name = "pwmcmp0gang"; - } pwmcmp0gang[24:24]; - field { - name = "pwmcmp1gang"; - } pwmcmp1gang[25:25]; - field { - name = "pwmcmp2gang"; - } pwmcmp2gang[26:26]; - field { - name = "pwmcmp3gang"; - } pwmcmp3gang[27:27]; - field { - name = "pwmcmp0ip"; - } pwmcmp0ip[28:28]; - field { - name = "pwmcmp1ip"; - } pwmcmp1ip[29:29]; - field { - name = "pwmcmp2ip"; - } pwmcmp2ip[30:30]; - field { - name = "pwmcmp3ip"; - } pwmcmp3ip[31:31]; - } pwmcfg @0x000; - reg { - name="pwmcount"; - field { - name = "pwmcount"; - } pwmcount[31:0]; - } pwmcount @0x008; - reg { - name="pwms"; - field { - name = "pwms"; - }pwms[15:0]; - } pwms @0x010; - reg { - name="pwmcmp0"; - field { - name = "pwmcmp0"; - } pwmcmp0[15:0]; - } pwmcmp0 @0x020; - reg { - name="pwmcmp1"; - field { - name = "pwmcmp0"; - } pwmcmp0[15:0]; - } pwmcmp1 @0x024; - reg { - name="pwmcmp2"; - field { - name = "pwmcmp0"; - } pwmcmp0[15:0]; - } pwmcmp2 @0x028; - reg { - name="pwmcmp3"; - field { - name = "pwmcmp0"; - } pwmcmp0[15:0]; - } pwmcmp3 @0x02C; -}; diff --git a/platform/gen_input/spi.rdl b/platform/gen_input/spi.rdl deleted file mode 100644 index 44c8222..0000000 --- a/platform/gen_input/spi.rdl +++ /dev/null @@ -1,173 +0,0 @@ -regfile spi_regs { - reg { - name="sckdiv"; - desc="Serial clock divisor"; - field { - name ="div"; - } div[12]; - } sckdiv @0x000; - reg { - name="sckmode"; - desc="Serial clock mode"; - field { - name="pha"; - } pha[1]; - field { - name="pol"; - } pol[1]; - } sckmode @0x004; - reg { - name="csid"; - desc="Chip select ID"; - field { - name="csid"; - } csid[32]; - } csid @0x010; - reg { - name="csdef"; - desc="Chip select default"; - field { - name="csdef"; - } csdef[32]; - } csdef @0x014; - reg { - name="csmode"; - desc="Chip select mode"; - field { - name="mode"; - } mode[2]; - } csmode @0x018; - reg { - name="delay0"; - desc="Delay control 0"; - field { - name="cssck"; - } cssck[7:0]; - field { - name ="sckcs"; - } sckcs[23:16]; - } delay0 @0x028; - reg { - name="delay1"; - desc="Delay control 1"; - field { - name="intercs"; - }intercs[15:0]; - field { - name="interxfr"; - } interxfr[23:16]; - } delay1 @0x02C; - reg { - name="fmt"; - desc="Frame format"; - field{ - name ="proto"; - }proto[2]; - field { - name="endian"; - } endian[1]; - field { - name="dir"; - } dir[1]; - field { - name="len"; - } len[19:16]; - } fmt @0x040; - reg { - name="txdata"; - desc="Tx FIFO data"; - field { - name="data"; - } data[8]; - field { - name="full"; - } full[31:31]; - } txdata @0x048; - reg { - name="rxdata"; - desc="Rx FIFO data"; - field{ - name="data"; - } data[8]; - field{ - name="empty"; - } empty[31:31]; - } rxdata @0x04C; - reg { - name="txmark"; - desc="Tx FIFO watermark"; - field { - name="txmark"; - } txmark[3]; - } txmark @0x050; - reg { - name="rxmark"; - desc="Rx FIFO watermark"; - field { - name="rxmark"; - } rxmark[3]; - } rxmark @0x054; - reg { - name="fctrl"; - desc="SPI flash interface control"; - field { - name="en"; - } en[1]; - } fctrl @0x060; - reg { - name="ffmt"; - desc="SPI flash instruction format"; - field { - name="cmd_en"; - reset=0x1; - } cmd_en[1]; - field { - name="addr_len"; - reset=0x3; - } addr_len[2]; - field { - name="pad_cnt"; - reset=0x0; - } pad_cnt[4]; - field { - name="cmd_proto"; - reset=0x0; - } cmd_proto[2]; - field { - name="addr_proto"; - reset=0x0; - } addr_proto[2]; - field { - name="data_proto"; - reset=0x0; - } data_proto[2]; - field { - name="cmd_code"; - reset=0x3; - } cmd_code[23:16]; - field { - name="pad_code"; - reset=0x0; - } pad_code[8]; - } ffmt @0x064; - reg { - name="ie"; - desc="SPI interrupt enable"; - field{ - name="txwm"; - } txwm[1]; - field{ - name="rxwm"; - } rxwm[1]; - } ie @0x070; - reg { - name="ip"; - desc="SPI interrupt pending"; - field{ - name="txwm"; - } txwm[1]; - field{ - name="rxwm"; - } rxwm[1]; - } ip @0x074; -}; diff --git a/platform/gen_input/uart.rdl b/platform/gen_input/uart.rdl deleted file mode 100644 index d095437..0000000 --- a/platform/gen_input/uart.rdl +++ /dev/null @@ -1,46 +0,0 @@ -regfile uart_regs { - reg { - name="txdata"; - desc="Transmit data register"; - field {} data[7:0]; - field {} full[31:31]; - } txdata @0x00; - reg { - name="rxdata"; - desc="Receive data register"; - field {} data[7:0]; - field {} empty[31:31]; - }rxdata @0x04; - reg { - name="txctrl"; - desc="Transmit control register"; - field {} txen[1]; - field {} nstop[1]; - field {} txcnt[18:16]; - }txctrl @0x08; - reg { - name="rxctrl"; - desc="Receive control register"; - field {} rxen[1]; - field {} rxcnt[18:16]; - }rxctrl @0x0C; - reg { - name="ie"; - desc="UART interrupt enable"; - field{} txwm[1]; - field{} rxwm[1]; - }ie @0x10; - reg { - name="ip"; - desc="UART Interrupt pending"; - field{} txwm[1]; - field{} rxwm[1]; - } ip @0x14; - reg { - name="div"; - desc="Baud rate divisor"; - field{} div[16]; - } div @0x18; -}; - - \ No newline at end of file diff --git a/platform/incl/sysc/SiFive/aon.h b/platform/incl/sysc/SiFive/aon.h deleted file mode 100644 index 1cf097f..0000000 --- a/platform/incl/sysc/SiFive/aon.h +++ /dev/null @@ -1,63 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _AON_H_ -#define _AON_H_ - -#include "scc/tlm_target.h" - -namespace sysc { - -class aon_regs; - -class aon : public sc_core::sc_module, public scc::tlm_target<> { -public: - SC_HAS_PROCESS(aon);// NOLINT - sc_core::sc_in clk_i; - sc_core::sc_in erst_n_i; - sc_core::sc_out lfclkc_o; - sc_core::sc_out rst_o; - aon(sc_core::sc_module_name nm); - virtual ~aon() override; // need to keep it in source file because of fwd declaration of aon_regs - -protected: - void start_of_simulation() override; - void clock_cb(); - void reset_cb(); - void reset_internal_cb(); - sc_core::sc_time clk; - std::unique_ptr regs; -}; - -} /* namespace sysc */ - -#endif /* _GPIO_H_ */ diff --git a/platform/incl/sysc/SiFive/clint.h b/platform/incl/sysc/SiFive/clint.h deleted file mode 100644 index 5d2f12f..0000000 --- a/platform/incl/sysc/SiFive/clint.h +++ /dev/null @@ -1,74 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _CLINT_H_ -#define _CLINT_H_ - -#include "scc/tlm_target.h" - -namespace iss { -namespace arch { -template class riscv_hart_msu_vp; -} -} - -namespace sysc { - -class clint_regs; -namespace SiFive { -class core_complex; -} - -class clint : public sc_core::sc_module, public scc::tlm_target<> { -public: - SC_HAS_PROCESS(clint);// NOLINT - sc_core::sc_in tlclk_i; - sc_core::sc_in lfclk_i; - sc_core::sc_in rst_i; - sc_core::sc_out mtime_int_o; - sc_core::sc_out msip_int_o; - clint(sc_core::sc_module_name nm); - virtual ~clint() override; // NOLINT // need to keep it in source file because of fwd declaration of clint_regs - -protected: - void clock_cb(); - void reset_cb(); - void update_mtime(); - sc_core::sc_time clk, last_updt; - unsigned cnt_fraction; - std::unique_ptr regs; - sc_core::sc_event mtime_evt; -}; - -} /* namespace sysc */ - -#endif /* _CLINT_H_ */ diff --git a/platform/incl/sysc/SiFive/fe310.h b/platform/incl/sysc/SiFive/fe310.h deleted file mode 100644 index 3898e5e..0000000 --- a/platform/incl/sysc/SiFive/fe310.h +++ /dev/null @@ -1,106 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _PLATFORM_H_ -#define _PLATFORM_H_ - -#include "aon.h" -#include "clint.h" -#include "gpio.h" -#include "plic.h" -#include "prci.h" -#include "pwm.h" -#include "spi.h" -#include "sysc/core_complex.h" -#include "uart.h" - -#include "cci_configuration" -#include "scc/memory.h" -#include "scc/router.h" -#include "scc/utilities.h" -#include "tlm/tlm_signal_sockets.h" -#include -#include -#include - -namespace sysc { - -class fe310 : public sc_core::sc_module { -public: - SC_HAS_PROCESS(fe310);// NOLINT - - sc_core::sc_vector> pins_o; - sc_core::sc_vector> pins_i; - - sc_core::sc_in erst_n; - - fe310(sc_core::sc_module_name nm); - - cci::cci_param use_rtl; - -private: - std::unique_ptr i_core_complex; - std::unique_ptr> i_router; - std::unique_ptr i_uart0, i_uart1; - std::unique_ptr i_qspi0, i_qspi1, i_qspi2; - std::unique_ptr i_pwm0, i_pwm1, i_pwm2; - std::unique_ptr i_gpio0; - std::unique_ptr i_plic; - std::unique_ptr i_aon; - std::unique_ptr i_prci; - std::unique_ptr i_clint; - - using mem_qspi_t = scc::memory<512_MB, 32>; - std::unique_ptr i_mem_qspi; - using mem_ram_t = scc::memory<128_kB, 32>; - std::unique_ptr i_mem_ram; - - sc_core::sc_signal s_tlclk; - sc_core::sc_signal s_lfclk; - - sc_core::sc_signal s_rst, s_mtime_int, s_msie_int; - - sc_core::sc_vector> s_global_int, s_local_int; - sc_core::sc_signal s_core_int; - - sc_core::sc_vector s_dummy_sck_i; - sc_core::sc_vector s_dummy_sck_o; - -protected: - void gen_reset(); - -#include "gen/e300_plat_t.h" -}; - -} /* namespace sysc */ - -#endif /* _PLATFORM_H_ */ diff --git a/platform/incl/sysc/SiFive/gen/aon_regs.h b/platform/incl/sysc/SiFive/gen/aon_regs.h deleted file mode 100644 index c4f203d..0000000 --- a/platform/incl/sysc/SiFive/gen/aon_regs.h +++ /dev/null @@ -1,170 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _AON_REGS_H_ -#define _AON_REGS_H_ - -#include -#include -#include -#include - -namespace sysc { - -class aon_regs : public sc_core::sc_module, public scc::resetable { -public: - // storage declarations - uint32_t r_wdogcfg; - - uint32_t r_wdogcount; - - uint32_t r_wdogs; - - uint32_t r_wdogfeed; - - uint32_t r_wdogkey; - - uint32_t r_wdogcmp; - - uint32_t r_rtccfg; - - uint32_t r_rtclo; - - uint32_t r_rtchi; - - uint32_t r_rtcs; - - uint32_t r_rtccmp; - - uint32_t r_lfrosccfg; - - std::array r_backup; - - BEGIN_BF_DECL(pmuwakeupi_t, uint32_t); - BF_FIELD(delay, 0, 4); - BF_FIELD(vddpaden, 5, 1); - BF_FIELD(corerst, 7, 1); - BF_FIELD(hfclkrst, 8, 1); - END_BF_DECL(); - std::array r_pmuwakeupi; - - BEGIN_BF_DECL(pmusleepi_t, uint32_t); - BF_FIELD(delay, 0, 4); - BF_FIELD(vddpaden, 5, 1); - BF_FIELD(corerst, 7, 1); - BF_FIELD(hfclkrst, 8, 1); - END_BF_DECL(); - std::array r_pmusleepi; - - uint32_t r_pmuie; - - uint32_t r_pmucause; - - uint32_t r_pmusleep; - - uint32_t r_pmukey; - - // register declarations - scc::sc_register wdogcfg; - scc::sc_register wdogcount; - scc::sc_register wdogs; - scc::sc_register wdogfeed; - scc::sc_register wdogkey; - scc::sc_register wdogcmp; - scc::sc_register rtccfg; - scc::sc_register rtclo; - scc::sc_register rtchi; - scc::sc_register rtcs; - scc::sc_register rtccmp; - scc::sc_register lfrosccfg; - scc::sc_register_indexed backup; - scc::sc_register_indexed pmuwakeupi; - scc::sc_register_indexed pmusleepi; - scc::sc_register pmuie; - scc::sc_register pmucause; - scc::sc_register pmusleep; - scc::sc_register pmukey; - - aon_regs(sc_core::sc_module_name nm); - - template void registerResources(scc::tlm_target &target); -}; -} -////////////////////////////////////////////////////////////////////////////// -// member functions -////////////////////////////////////////////////////////////////////////////// - -inline sysc::aon_regs::aon_regs(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, NAMED(wdogcfg, r_wdogcfg, 0, *this) -, NAMED(wdogcount, r_wdogcount, 0, *this) -, NAMED(wdogs, r_wdogs, 0, *this) -, NAMED(wdogfeed, r_wdogfeed, 0, *this) -, NAMED(wdogkey, r_wdogkey, 0, *this) -, NAMED(wdogcmp, r_wdogcmp, 0, *this) -, NAMED(rtccfg, r_rtccfg, 0, *this) -, NAMED(rtclo, r_rtclo, 0, *this) -, NAMED(rtchi, r_rtchi, 0, *this) -, NAMED(rtcs, r_rtcs, 0, *this) -, NAMED(rtccmp, r_rtccmp, 0, *this) -, NAMED(lfrosccfg, r_lfrosccfg, 0, *this) -, NAMED(backup, r_backup, 0, *this) -, NAMED(pmuwakeupi, r_pmuwakeupi, 0, *this) -, NAMED(pmusleepi, r_pmusleepi, 0, *this) -, NAMED(pmuie, r_pmuie, 0, *this) -, NAMED(pmucause, r_pmucause, 0, *this) -, NAMED(pmusleep, r_pmusleep, 0, *this) -, NAMED(pmukey, r_pmukey, 0, *this) {} - -template inline void sysc::aon_regs::registerResources(scc::tlm_target &target) { - target.addResource(wdogcfg, 0x0UL); - target.addResource(wdogcount, 0x8UL); - target.addResource(wdogs, 0x10UL); - target.addResource(wdogfeed, 0x18UL); - target.addResource(wdogkey, 0x1cUL); - target.addResource(wdogcmp, 0x20UL); - target.addResource(rtccfg, 0x40UL); - target.addResource(rtclo, 0x48UL); - target.addResource(rtchi, 0x4cUL); - target.addResource(rtcs, 0x50UL); - target.addResource(rtccmp, 0x60UL); - target.addResource(lfrosccfg, 0x70UL); - target.addResource(backup, 0x80UL); - target.addResource(pmuwakeupi, 0x100UL); - target.addResource(pmusleepi, 0x120UL); - target.addResource(pmuie, 0x140UL); - target.addResource(pmucause, 0x144UL); - target.addResource(pmusleep, 0x148UL); - target.addResource(pmukey, 0x14cUL); -} - -#endif // _AON_REGS_H_ diff --git a/platform/incl/sysc/SiFive/gen/clint_regs.h b/platform/incl/sysc/SiFive/gen/clint_regs.h deleted file mode 100644 index b8bedb0..0000000 --- a/platform/incl/sysc/SiFive/gen/clint_regs.h +++ /dev/null @@ -1,80 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _CLINT_REGS_H_ -#define _CLINT_REGS_H_ - -#include -#include -#include -#include - -namespace sysc { - -class clint_regs : public sc_core::sc_module, public scc::resetable { -public: - // storage declarations - BEGIN_BF_DECL(msip_t, uint32_t); - BF_FIELD(msip, 0, 1); - END_BF_DECL() r_msip; - - uint64_t r_mtimecmp; - - uint64_t r_mtime; - - // register declarations - scc::sc_register msip; - scc::sc_register mtimecmp; - scc::sc_register mtime; - - clint_regs(sc_core::sc_module_name nm); - - template void registerResources(scc::tlm_target &target); -}; -} -////////////////////////////////////////////////////////////////////////////// -// member functions -////////////////////////////////////////////////////////////////////////////// - -inline sysc::clint_regs::clint_regs(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, NAMED(msip, r_msip, 0, *this) -, NAMED(mtimecmp, r_mtimecmp, 0, *this) -, NAMED(mtime, r_mtime, 0, *this) {} - -template inline void sysc::clint_regs::registerResources(scc::tlm_target &target) { - target.addResource(msip, 0x0UL); - target.addResource(mtimecmp, 0x4000UL); - target.addResource(mtime, 0xbff8UL); -} - -#endif // _CLINT_REGS_H_ diff --git a/platform/incl/sysc/SiFive/gen/e300_plat_t.h b/platform/incl/sysc/SiFive/gen/e300_plat_t.h deleted file mode 100644 index f58e93e..0000000 --- a/platform/incl/sysc/SiFive/gen/e300_plat_t.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef _E300_PLAT_T_MAP_H_ -#define _E300_PLAT_T_MAP_H_ -// need double braces, see -// https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191 -const std::array, 13> e300_plat_t_map = {{ - {i_clint->socket, 0x2000000, 0xc000}, - {i_plic->socket, 0xc000000, 0x200008}, - {i_aon->socket, 0x10000000, 0x150}, - {i_prci->socket, 0x10008000, 0x14}, - {i_gpio0->socket, 0x10012000, 0x44}, - {i_uart0->socket, 0x10013000, 0x1c}, - {i_qspi0->socket, 0x10014000, 0x78}, - {i_pwm0->socket, 0x10015000, 0x30}, - {i_uart1->socket, 0x10023000, 0x1c}, - {i_qspi1->socket, 0x10024000, 0x78}, - {i_pwm1->socket, 0x10025000, 0x30}, - {i_qspi2->socket, 0x10034000, 0x78}, - {i_pwm2->socket, 0x10035000, 0x30}, -}}; - -#endif /* _E300_PLAT_T_MAP_H_ */ diff --git a/platform/incl/sysc/SiFive/gen/gpio_regs.h b/platform/incl/sysc/SiFive/gen/gpio_regs.h deleted file mode 100644 index ebf488d..0000000 --- a/platform/incl/sysc/SiFive/gen/gpio_regs.h +++ /dev/null @@ -1,169 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _GPIO_REGS_H_ -#define _GPIO_REGS_H_ - -#include -#include -#include -#include - -namespace sysc { - -class gpio_regs : public sc_core::sc_module, public scc::resetable { -public: - // storage declarations - uint32_t r_value; - - uint32_t r_input_en; - - uint32_t r_output_en; - - uint32_t r_port; - - uint32_t r_pue; - - uint32_t r_ds; - - uint32_t r_rise_ie; - - uint32_t r_rise_ip; - - uint32_t r_fall_ie; - - uint32_t r_fall_ip; - - uint32_t r_high_ie; - - uint32_t r_high_ip; - - uint32_t r_low_ie; - - uint32_t r_low_ip; - - uint32_t r_iof_en; - - uint32_t r_iof_sel; - - uint32_t r_out_xor; - - // register declarations - scc::sc_register value; - scc::sc_register input_en; - scc::sc_register output_en; - scc::sc_register port; - scc::sc_register pue; - scc::sc_register ds; - scc::sc_register rise_ie; - scc::sc_register rise_ip; - scc::sc_register fall_ie; - scc::sc_register fall_ip; - scc::sc_register high_ie; - scc::sc_register high_ip; - scc::sc_register low_ie; - scc::sc_register low_ip; - scc::sc_register iof_en; - scc::sc_register iof_sel; - scc::sc_register out_xor; - - gpio_regs(sc_core::sc_module_name nm); - - template void registerResources(scc::tlm_target &target); - void trace(sc_core::sc_trace_file *tf) const override; -}; -} -////////////////////////////////////////////////////////////////////////////// -// member functions -////////////////////////////////////////////////////////////////////////////// - -inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, NAMED(value, r_value, 0, *this) -, NAMED(input_en, r_input_en, 0, *this) -, NAMED(output_en, r_output_en, 0, *this) -, NAMED(port, r_port, 0, *this) -, NAMED(pue, r_pue, 0, *this) -, NAMED(ds, r_ds, 0, *this) -, NAMED(rise_ie, r_rise_ie, 0, *this) -, NAMED(rise_ip, r_rise_ip, 0, *this) -, NAMED(fall_ie, r_fall_ie, 0, *this) -, NAMED(fall_ip, r_fall_ip, 0, *this) -, NAMED(high_ie, r_high_ie, 0, *this) -, NAMED(high_ip, r_high_ip, 0, *this) -, NAMED(low_ie, r_low_ie, 0, *this) -, NAMED(low_ip, r_low_ip, 0, *this) -, NAMED(iof_en, r_iof_en, 0, *this) -, NAMED(iof_sel, r_iof_sel, 0, *this) -, NAMED(out_xor, r_out_xor, 0, *this) {} - -template inline void sysc::gpio_regs::registerResources(scc::tlm_target &target) { - target.addResource(value, 0x0UL); - target.addResource(input_en, 0x4UL); - target.addResource(output_en, 0x8UL); - target.addResource(port, 0xcUL); - target.addResource(pue, 0x10UL); - target.addResource(ds, 0x14UL); - target.addResource(rise_ie, 0x18UL); - target.addResource(rise_ip, 0x1cUL); - target.addResource(fall_ie, 0x20UL); - target.addResource(fall_ip, 0x24UL); - target.addResource(high_ie, 0x28UL); - target.addResource(high_ip, 0x2cUL); - target.addResource(low_ie, 0x30UL); - target.addResource(low_ip, 0x34UL); - target.addResource(iof_en, 0x38UL); - target.addResource(iof_sel, 0x3cUL); - target.addResource(out_xor, 0x40UL); -} - -inline void sysc::gpio_regs::trace(sc_core::sc_trace_file *tf) const { - value.trace(tf); - input_en.trace(tf); - output_en.trace(tf); - port.trace(tf); - pue.trace(tf); - ds.trace(tf); - rise_ie.trace(tf); - rise_ip.trace(tf); - fall_ie.trace(tf); - fall_ip.trace(tf); - high_ie.trace(tf); - high_ip.trace(tf); - low_ie.trace(tf); - low_ip.trace(tf); - iof_en.trace(tf); - iof_sel.trace(tf); - out_xor.trace(tf); -} - -#endif // _GPIO_REGS_H_ diff --git a/platform/incl/sysc/SiFive/gen/plic_regs.h b/platform/incl/sysc/SiFive/gen/plic_regs.h deleted file mode 100644 index 80c0646..0000000 --- a/platform/incl/sysc/SiFive/gen/plic_regs.h +++ /dev/null @@ -1,93 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _PLIC_REGS_H_ -#define _PLIC_REGS_H_ - -#include -#include -#include -#include - -namespace sysc { - -class plic_regs : public sc_core::sc_module, public scc::resetable { -public: - // storage declarations - BEGIN_BF_DECL(priority_t, uint32_t); - BF_FIELD(priority, 0, 3); - END_BF_DECL(); - std::array r_priority; - - std::array r_pending; - - std::array r_enabled; - - BEGIN_BF_DECL(threshold_t, uint32_t); - BF_FIELD(threshold, 0, 3); - END_BF_DECL() r_threshold; - - uint32_t r_claim_complete; - - // register declarations - scc::sc_register_indexed priority; - scc::sc_register_indexed pending; - scc::sc_register_indexed enabled; - scc::sc_register threshold; - scc::sc_register claim_complete; - - plic_regs(sc_core::sc_module_name nm); - - template void registerResources(scc::tlm_target &target); -}; -} -////////////////////////////////////////////////////////////////////////////// -// member functions -////////////////////////////////////////////////////////////////////////////// - -inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, NAMED(priority, r_priority, 0, *this) -, NAMED(pending, r_pending, 0, *this) -, NAMED(enabled, r_enabled, 0, *this) -, NAMED(threshold, r_threshold, 0, *this) -, NAMED(claim_complete, r_claim_complete, 0, *this) {} - -template inline void sysc::plic_regs::registerResources(scc::tlm_target &target) { - target.addResource(priority, 0x0UL); - target.addResource(pending, 0x1000UL); - target.addResource(enabled, 0x2000UL); - target.addResource(threshold, 0x200000UL); - target.addResource(claim_complete, 0x200004UL); -} - -#endif // _PLIC_REGS_H_ diff --git a/platform/incl/sysc/SiFive/gen/prci_regs.h b/platform/incl/sysc/SiFive/gen/prci_regs.h deleted file mode 100644 index 59043fc..0000000 --- a/platform/incl/sysc/SiFive/gen/prci_regs.h +++ /dev/null @@ -1,104 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _PRCI_REGS_H_ -#define _PRCI_REGS_H_ - -#include -#include -#include -#include - -namespace sysc { - -class prci_regs : public sc_core::sc_module, public scc::resetable { -public: - // storage declarations - BEGIN_BF_DECL(hfrosccfg_t, uint32_t); - BF_FIELD(hfroscdiv, 0, 6); - BF_FIELD(hfrosctrim, 16, 5); - BF_FIELD(hfroscen, 30, 1); - BF_FIELD(hfroscrdy, 31, 1); - END_BF_DECL() r_hfrosccfg; - - BEGIN_BF_DECL(hfxosccfg_t, uint32_t); - BF_FIELD(hfxoscrdy, 31, 1); - BF_FIELD(hfxoscen, 30, 1); - END_BF_DECL() r_hfxosccfg; - - BEGIN_BF_DECL(pllcfg_t, uint32_t); - BF_FIELD(pllr, 0, 3); - BF_FIELD(pllf, 4, 6); - BF_FIELD(pllq, 10, 2); - BF_FIELD(pllsel, 16, 1); - BF_FIELD(pllrefsel, 17, 1); - BF_FIELD(pllbypass, 18, 1); - BF_FIELD(plllock, 31, 1); - END_BF_DECL() r_pllcfg; - - uint32_t r_plloutdiv; - - uint32_t r_coreclkcfg; - - // register declarations - scc::sc_register hfrosccfg; - scc::sc_register hfxosccfg; - scc::sc_register pllcfg; - scc::sc_register plloutdiv; - scc::sc_register coreclkcfg; - - prci_regs(sc_core::sc_module_name nm); - - template void registerResources(scc::tlm_target &target); -}; -} -////////////////////////////////////////////////////////////////////////////// -// member functions -////////////////////////////////////////////////////////////////////////////// - -inline sysc::prci_regs::prci_regs(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, NAMED(hfrosccfg, r_hfrosccfg, 0, *this) -, NAMED(hfxosccfg, r_hfxosccfg, 0x40000000, *this) -, NAMED(pllcfg, r_pllcfg, 0, *this) -, NAMED(plloutdiv, r_plloutdiv, 0, *this) -, NAMED(coreclkcfg, r_coreclkcfg, 0, *this) {} - -template inline void sysc::prci_regs::registerResources(scc::tlm_target &target) { - target.addResource(hfrosccfg, 0x0UL); - target.addResource(hfxosccfg, 0x4UL); - target.addResource(pllcfg, 0x8UL); - target.addResource(plloutdiv, 0xcUL); - target.addResource(coreclkcfg, 0x10UL); -} - -#endif // _PRCI_REGS_H_ diff --git a/platform/incl/sysc/SiFive/gen/pwm_regs.h b/platform/incl/sysc/SiFive/gen/pwm_regs.h deleted file mode 100644 index 1b7423f..0000000 --- a/platform/incl/sysc/SiFive/gen/pwm_regs.h +++ /dev/null @@ -1,129 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _PWM_REGS_H_ -#define _PWM_REGS_H_ - -#include -#include -#include -#include - -namespace sysc { - -class pwm_regs : public sc_core::sc_module, public scc::resetable { -public: - // storage declarations - BEGIN_BF_DECL(pwmcfg_t, uint32_t); - BF_FIELD(pwmscale, 0, 4); - BF_FIELD(pwmsticky, 8, 1); - BF_FIELD(pwmzerocmp, 9, 1); - BF_FIELD(pwmdeglitch, 10, 1); - BF_FIELD(pwmenalways, 12, 1); - BF_FIELD(pwmenoneshot, 13, 1); - BF_FIELD(pwmcmp0center, 16, 1); - BF_FIELD(pwmcmp1center, 17, 1); - BF_FIELD(pwmcmp2center, 18, 1); - BF_FIELD(pwmcmp3center, 19, 1); - BF_FIELD(pwmcmp0gang, 24, 1); - BF_FIELD(pwmcmp1gang, 25, 1); - BF_FIELD(pwmcmp2gang, 26, 1); - BF_FIELD(pwmcmp3gang, 27, 1); - BF_FIELD(pwmcmp0ip, 28, 1); - BF_FIELD(pwmcmp1ip, 29, 1); - BF_FIELD(pwmcmp2ip, 30, 1); - BF_FIELD(pwmcmp3ip, 31, 1); - END_BF_DECL() r_pwmcfg; - - BEGIN_BF_DECL(pwmcount_t, uint32_t); - BF_FIELD(pwmcount, 0, 31); - END_BF_DECL() r_pwmcount; - - BEGIN_BF_DECL(pwms_t, uint32_t); - BF_FIELD(pwms, 0, 16); - END_BF_DECL() r_pwms; - - BEGIN_BF_DECL(pwmcmp0_t, uint32_t); - BF_FIELD(pwmcmp0, 0, 16); - END_BF_DECL() r_pwmcmp0; - - BEGIN_BF_DECL(pwmcmp1_t, uint32_t); - BF_FIELD(pwmcmp0, 0, 16); - END_BF_DECL() r_pwmcmp1; - - BEGIN_BF_DECL(pwmcmp2_t, uint32_t); - BF_FIELD(pwmcmp0, 0, 16); - END_BF_DECL() r_pwmcmp2; - - BEGIN_BF_DECL(pwmcmp3_t, uint32_t); - BF_FIELD(pwmcmp0, 0, 16); - END_BF_DECL() r_pwmcmp3; - - // register declarations - scc::sc_register pwmcfg; - scc::sc_register pwmcount; - scc::sc_register pwms; - scc::sc_register pwmcmp0; - scc::sc_register pwmcmp1; - scc::sc_register pwmcmp2; - scc::sc_register pwmcmp3; - - pwm_regs(sc_core::sc_module_name nm); - - template void registerResources(scc::tlm_target &target); -}; -} -////////////////////////////////////////////////////////////////////////////// -// member functions -////////////////////////////////////////////////////////////////////////////// - -inline sysc::pwm_regs::pwm_regs(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, NAMED(pwmcfg, r_pwmcfg, 0, *this) -, NAMED(pwmcount, r_pwmcount, 0, *this) -, NAMED(pwms, r_pwms, 0, *this) -, NAMED(pwmcmp0, r_pwmcmp0, 0, *this) -, NAMED(pwmcmp1, r_pwmcmp1, 0, *this) -, NAMED(pwmcmp2, r_pwmcmp2, 0, *this) -, NAMED(pwmcmp3, r_pwmcmp3, 0, *this) {} - -template inline void sysc::pwm_regs::registerResources(scc::tlm_target &target) { - target.addResource(pwmcfg, 0x0UL); - target.addResource(pwmcount, 0x8UL); - target.addResource(pwms, 0x10UL); - target.addResource(pwmcmp0, 0x20UL); - target.addResource(pwmcmp1, 0x24UL); - target.addResource(pwmcmp2, 0x28UL); - target.addResource(pwmcmp3, 0x2cUL); -} - -#endif // _PWM_REGS_H_ diff --git a/platform/incl/sysc/SiFive/gen/spi_regs.h b/platform/incl/sysc/SiFive/gen/spi_regs.h deleted file mode 100644 index eda9b27..0000000 --- a/platform/incl/sysc/SiFive/gen/spi_regs.h +++ /dev/null @@ -1,188 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _SPI_REGS_H_ -#define _SPI_REGS_H_ - -#include -#include -#include -#include - -namespace sysc { - -class spi_regs : public sc_core::sc_module, public scc::resetable { -public: - // storage declarations - BEGIN_BF_DECL(sckdiv_t, uint32_t); - BF_FIELD(div, 0, 12); - END_BF_DECL() r_sckdiv; - - BEGIN_BF_DECL(sckmode_t, uint32_t); - BF_FIELD(pha, 0, 1); - BF_FIELD(pol, 1, 1); - END_BF_DECL() r_sckmode; - - uint32_t r_csid; - - uint32_t r_csdef; - - BEGIN_BF_DECL(csmode_t, uint32_t); - BF_FIELD(mode, 0, 2); - END_BF_DECL() r_csmode; - - BEGIN_BF_DECL(delay0_t, uint32_t); - BF_FIELD(cssck, 0, 8); - BF_FIELD(sckcs, 16, 8); - END_BF_DECL() r_delay0; - - BEGIN_BF_DECL(delay1_t, uint32_t); - BF_FIELD(intercs, 0, 16); - BF_FIELD(interxfr, 16, 8); - END_BF_DECL() r_delay1; - - BEGIN_BF_DECL(fmt_t, uint32_t); - BF_FIELD(proto, 0, 2); - BF_FIELD(endian, 2, 1); - BF_FIELD(dir, 3, 1); - BF_FIELD(len, 16, 4); - END_BF_DECL() r_fmt; - - BEGIN_BF_DECL(txdata_t, uint32_t); - BF_FIELD(data, 0, 8); - BF_FIELD(full, 31, 1); - END_BF_DECL() r_txdata; - - BEGIN_BF_DECL(rxdata_t, uint32_t); - BF_FIELD(data, 0, 8); - BF_FIELD(empty, 31, 1); - END_BF_DECL() r_rxdata; - - BEGIN_BF_DECL(txmark_t, uint32_t); - BF_FIELD(txmark, 0, 3); - END_BF_DECL() r_txmark; - - BEGIN_BF_DECL(rxmark_t, uint32_t); - BF_FIELD(rxmark, 0, 3); - END_BF_DECL() r_rxmark; - - BEGIN_BF_DECL(fctrl_t, uint32_t); - BF_FIELD(en, 0, 1); - END_BF_DECL() r_fctrl; - - BEGIN_BF_DECL(ffmt_t, uint32_t); - BF_FIELD(cmd_en, 0, 1); - BF_FIELD(addr_len, 1, 2); - BF_FIELD(pad_cnt, 3, 4); - BF_FIELD(cmd_proto, 7, 2); - BF_FIELD(addr_proto, 9, 2); - BF_FIELD(data_proto, 11, 2); - BF_FIELD(cmd_code, 16, 8); - BF_FIELD(pad_code, 24, 8); - END_BF_DECL() r_ffmt; - - BEGIN_BF_DECL(ie_t, uint32_t); - BF_FIELD(txwm, 0, 1); - BF_FIELD(rxwm, 1, 1); - END_BF_DECL() r_ie; - - BEGIN_BF_DECL(ip_t, uint32_t); - BF_FIELD(txwm, 0, 1); - BF_FIELD(rxwm, 1, 1); - END_BF_DECL() r_ip; - - // register declarations - scc::sc_register sckdiv; - scc::sc_register sckmode; - scc::sc_register csid; - scc::sc_register csdef; - scc::sc_register csmode; - scc::sc_register delay0; - scc::sc_register delay1; - scc::sc_register fmt; - scc::sc_register txdata; - scc::sc_register rxdata; - scc::sc_register txmark; - scc::sc_register rxmark; - scc::sc_register fctrl; - scc::sc_register ffmt; - scc::sc_register ie; - scc::sc_register ip; - - spi_regs(sc_core::sc_module_name nm); - - template void registerResources(scc::tlm_target &target); -}; -} -////////////////////////////////////////////////////////////////////////////// -// member functions -////////////////////////////////////////////////////////////////////////////// - -inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, NAMED(sckdiv, r_sckdiv, 0, *this) -, NAMED(sckmode, r_sckmode, 0, *this) -, NAMED(csid, r_csid, 0, *this) -, NAMED(csdef, r_csdef, 0, *this) -, NAMED(csmode, r_csmode, 0, *this) -, NAMED(delay0, r_delay0, 0, *this) -, NAMED(delay1, r_delay1, 0, *this) -, NAMED(fmt, r_fmt, 0, *this) -, NAMED(txdata, r_txdata, 0, *this) -, NAMED(rxdata, r_rxdata, 0, *this) -, NAMED(txmark, r_txmark, 0, *this) -, NAMED(rxmark, r_rxmark, 0, *this) -, NAMED(fctrl, r_fctrl, 0, *this) -, NAMED(ffmt, r_ffmt, 0, *this) -, NAMED(ie, r_ie, 0, *this) -, NAMED(ip, r_ip, 0, *this) {} - -template inline void sysc::spi_regs::registerResources(scc::tlm_target &target) { - target.addResource(sckdiv, 0x0UL); - target.addResource(sckmode, 0x4UL); - target.addResource(csid, 0x10UL); - target.addResource(csdef, 0x14UL); - target.addResource(csmode, 0x18UL); - target.addResource(delay0, 0x28UL); - target.addResource(delay1, 0x2cUL); - target.addResource(fmt, 0x40UL); - target.addResource(txdata, 0x48UL); - target.addResource(rxdata, 0x4cUL); - target.addResource(txmark, 0x50UL); - target.addResource(rxmark, 0x54UL); - target.addResource(fctrl, 0x60UL); - target.addResource(ffmt, 0x64UL); - target.addResource(ie, 0x70UL); - target.addResource(ip, 0x74UL); -} - -#endif // _SPI_REGS_H_ diff --git a/platform/incl/sysc/SiFive/gen/uart_regs.h b/platform/incl/sysc/SiFive/gen/uart_regs.h deleted file mode 100644 index d86bd71..0000000 --- a/platform/incl/sysc/SiFive/gen/uart_regs.h +++ /dev/null @@ -1,119 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _UART_REGS_H_ -#define _UART_REGS_H_ - -#include -#include -#include -#include - -namespace sysc { - -class uart_regs : public sc_core::sc_module, public scc::resetable { -public: - // storage declarations - BEGIN_BF_DECL(txdata_t, uint32_t); - BF_FIELD(data, 0, 8); - BF_FIELD(full, 31, 1); - END_BF_DECL() r_txdata; - - BEGIN_BF_DECL(rxdata_t, uint32_t); - BF_FIELD(data, 0, 8); - BF_FIELD(empty, 31, 1); - END_BF_DECL() r_rxdata; - - BEGIN_BF_DECL(txctrl_t, uint32_t); - BF_FIELD(txen, 0, 1); - BF_FIELD(nstop, 1, 1); - BF_FIELD(txcnt, 16, 3); - END_BF_DECL() r_txctrl; - - BEGIN_BF_DECL(rxctrl_t, uint32_t); - BF_FIELD(rxen, 0, 1); - BF_FIELD(rxcnt, 16, 3); - END_BF_DECL() r_rxctrl; - - BEGIN_BF_DECL(ie_t, uint32_t); - BF_FIELD(txwm, 0, 1); - BF_FIELD(rxwm, 1, 1); - END_BF_DECL() r_ie; - - BEGIN_BF_DECL(ip_t, uint32_t); - BF_FIELD(txwm, 0, 1); - BF_FIELD(rxwm, 1, 1); - END_BF_DECL() r_ip; - - BEGIN_BF_DECL(div_t, uint32_t); - BF_FIELD(div, 0, 16); - END_BF_DECL() r_div; - - // register declarations - scc::sc_register txdata; - scc::sc_register rxdata; - scc::sc_register txctrl; - scc::sc_register rxctrl; - scc::sc_register ie; - scc::sc_register ip; - scc::sc_register div; - - uart_regs(sc_core::sc_module_name nm); - - template void registerResources(scc::tlm_target &target); -}; -} -////////////////////////////////////////////////////////////////////////////// -// member functions -////////////////////////////////////////////////////////////////////////////// - -inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, NAMED(txdata, r_txdata, 0, *this) -, NAMED(rxdata, r_rxdata, 0, *this) -, NAMED(txctrl, r_txctrl, 0, *this) -, NAMED(rxctrl, r_rxctrl, 0, *this) -, NAMED(ie, r_ie, 0, *this) -, NAMED(ip, r_ip, 0, *this) -, NAMED(div, r_div, 0, *this) {} - -template inline void sysc::uart_regs::registerResources(scc::tlm_target &target) { - target.addResource(txdata, 0x0UL); - target.addResource(rxdata, 0x4UL); - target.addResource(txctrl, 0x8UL); - target.addResource(rxctrl, 0xcUL); - target.addResource(ie, 0x10UL); - target.addResource(ip, 0x14UL); - target.addResource(div, 0x18UL); -} - -#endif // _UART_REGS_H_ diff --git a/platform/incl/sysc/SiFive/gpio.h b/platform/incl/sysc/SiFive/gpio.h deleted file mode 100644 index ccac42f..0000000 --- a/platform/incl/sysc/SiFive/gpio.h +++ /dev/null @@ -1,87 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _GPIO_H_ -#define _GPIO_H_ - -#include "cci_configuration" -#include "scc/signal_initiator_mixin.h" -#include "scc/signal_target_mixin.h" -#include "scc/tlm_target.h" -#include -#include - -namespace sysc { - -class gpio_regs; -class WsHandler; - -class gpio : public sc_core::sc_module, public scc::tlm_target<> { -public: - SC_HAS_PROCESS(gpio);// NOLINT - sc_core::sc_in clk_i; - sc_core::sc_in rst_i; - // sc_core::sc_inout_rv<32> pins_io; - - sc_core::sc_vector pins_o; - sc_core::sc_vector pins_i; - - sc_core::sc_vector iof0_o; - sc_core::sc_vector iof1_o; - sc_core::sc_vector iof0_i; - sc_core::sc_vector iof1_i; - - gpio(sc_core::sc_module_name nm); - virtual ~gpio() override; // need to keep it in source file because of fwd declaration of gpio_regs - - cci::cci_param write_to_ws; - -protected: - void clock_cb(); - void reset_cb(); - void update_pins(uint32_t changed_bits); - void before_end_of_elaboration(); - void pin_input(unsigned int tag, tlm::tlm_signal_gp &gp, sc_core::sc_time &delay); - void forward_pin_input(unsigned int tag, tlm::tlm_signal_gp &gp); - void iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay); - sc_core::sc_time clk; - std::array last_iof0, last_iof1; - std::unique_ptr regs; - std::shared_ptr handler; - -private: - tlm::tlm_phase write_output(tlm::tlm_signal_gp &gp, size_t i, sc_dt::sc_logic val); -}; - -} /* namespace sysc */ - -#endif /* _GPIO_H_ */ diff --git a/platform/incl/sysc/SiFive/plic.h b/platform/incl/sysc/SiFive/plic.h deleted file mode 100644 index 8315711..0000000 --- a/platform/incl/sysc/SiFive/plic.h +++ /dev/null @@ -1,72 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _PLIC_H_ -#define _PLIC_H_ - -#include -#include - -namespace sysc { - -class plic_regs; - -class plic : public sc_core::sc_module, public scc::tlm_target<> { -public: - SC_HAS_PROCESS(plic);// NOLINT - sc_core::sc_in clk_i; - sc_core::sc_in rst_i; - sc_core::sc_vector> global_interrupts_i; - sc_core::sc_out core_interrupt_o; - sc_core::sc_event raise_int_ev; - sc_core::sc_event clear_int_ev; - plic(sc_core::sc_module_name nm); - ~plic() override; - -protected: - void clock_cb(); - void reset_cb(); - - void global_int_port_cb(); - void handle_pending_int(); - void reset_pending_int(uint32_t irq); - - void raise_core_interrupt(); - void clear_core_interrupt(); - sc_core::sc_time clk; - std::unique_ptr regs; - std::function, uint32_t)> m_claim_complete_write_cb; -}; - -} /* namespace sysc */ - -#endif /* _PLIC_H_ */ diff --git a/platform/incl/sysc/SiFive/prci.h b/platform/incl/sysc/SiFive/prci.h deleted file mode 100644 index 5bdf110..0000000 --- a/platform/incl/sysc/SiFive/prci.h +++ /dev/null @@ -1,64 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _PRCI_H_ -#define _PRCI_H_ - -#include "scc/tlm_target.h" - -namespace sysc { - -class prci_regs; - -class prci : public sc_core::sc_module, public scc::tlm_target<> { -public: - SC_HAS_PROCESS(prci);// NOLINT - sc_core::sc_port, 1, sc_core::SC_ZERO_OR_MORE_BOUND> hfxosc_i; - sc_core::sc_in rst_i; - sc_core::sc_out hfclk_o; - prci(sc_core::sc_module_name nm); - virtual ~prci() override; // need to keep it in source file because of fwd declaration of prci_regs - -protected: - void hfxosc_cb(); - void reset_cb(); - void hfrosc_en_cb(); - void hfxosc_en_cb(); - void update_hfclk(); - sc_core::sc_time hfxosc_clk, hfrosc_clk, pll_clk, hfclk; - std::unique_ptr regs; - sc_core::sc_event hfrosc_en_evt, hfxosc_en_evt; -}; - -} /* namespace sysc */ - -#endif /* _GPIO_H_ */ diff --git a/platform/incl/sysc/SiFive/pwm.h b/platform/incl/sysc/SiFive/pwm.h deleted file mode 100644 index 34572d7..0000000 --- a/platform/incl/sysc/SiFive/pwm.h +++ /dev/null @@ -1,79 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017,2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _PWM_H_ -#define _PWM_H_ - -#include "cci_configuration" -#include "scc/signal_initiator_mixin.h" -#include "scc/signal_target_mixin.h" -#include "scc/tlm_target.h" -#include - -namespace sysc { - -class pwm_regs; - -class pwm : public sc_core::sc_module, public scc::tlm_target<> { -public: - SC_HAS_PROCESS(pwm);// NOLINT - sc_core::sc_in clk_i; - sc_core::sc_in rst_i; - - sc_core::sc_vector cmpgpio_o; - sc_core::sc_vector> cmpip_o; - - pwm(sc_core::sc_module_name nm); - virtual ~pwm() override; // need to keep it in source file because of fwd declaration of gpio_regs - -protected: - sc_core::sc_time clk, last_clk; - void clock_cb(); - void reset_cb(); - inline double get_pulses(sc_core::sc_time d) { - auto t = sc_core::sc_time_stamp() + d; - return last_clk > sc_core::SC_ZERO_TIME ? (t - last_cnt_update) / last_clk : 0.; - } - void update_counter(); - void write_cmpgpio(size_t, bool); - std::unique_ptr regs; - uint64_t current_cnt; - sc_core::sc_time last_cnt_update; - double clk_remainder = 0.0; - bool last_enable = false, reset_cnt = false; - sc_core::sc_event update_counter_evt; - std::array pwmcmp_ip; -}; - -} /* namespace sysc */ - -#endif /* _GPIO_H_ */ diff --git a/platform/incl/sysc/SiFive/spi.h b/platform/incl/sysc/SiFive/spi.h deleted file mode 100644 index 165f1df..0000000 --- a/platform/incl/sysc/SiFive/spi.h +++ /dev/null @@ -1,88 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _SPI_H_ -#define _SPI_H_ - -#include -#include - -namespace sysc { - -namespace spi_impl { -class beh; -class rtl; -} - -class spi : public sc_core::sc_module { -public: - template - static std::unique_ptr create(sc_core::sc_module_name nm); - - template using tlm_in = tlm::tlm_signal_opt_target_socket; - template using tlm_out = tlm::tlm_signal_opt_initiator_socket; - - tlm::tlm_target_socket<> socket; - sc_core::sc_in clk_i; - sc_core::sc_in rst_i; - tlm_out sck_o; - tlm_out mosi_o; - tlm_in miso_i; - sc_core::sc_vector> scs_o; - - sc_core::sc_out irq_o; - - spi(spi &other) = delete; - - spi(spi &&other) = delete; - - spi &operator=(spi &other) = delete; - - spi &operator=(spi &&other) = delete; - - ~spi() override = default; - -protected: - spi(sc_core::sc_module_name nm) - : sc_core::sc_module(nm) - , NAMED(clk_i) - , NAMED(rst_i) - , NAMED(sck_o) - , NAMED(mosi_o) - , NAMED(miso_i) - , NAMED(scs_o, 4) - , NAMED(irq_o){}; -}; - -} /* namespace sysc */ - -#endif /* _SPI_H_ */ diff --git a/platform/incl/sysc/SiFive/uart.h b/platform/incl/sysc/SiFive/uart.h deleted file mode 100644 index 6d635d9..0000000 --- a/platform/incl/sysc/SiFive/uart.h +++ /dev/null @@ -1,75 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _UART_H_ -#define _UART_H_ - -#include "cci_configuration" -#include "scc/signal_initiator_mixin.h" -#include "scc/signal_target_mixin.h" -#include "scc/tlm_target.h" -#include - -namespace sysc { -class tlm_signal_uart_extension; -class uart_regs; -class WsHandler; - -class uart : public sc_core::sc_module, public scc::tlm_target<> { -public: - SC_HAS_PROCESS(uart);// NOLINT - sc_core::sc_in clk_i; - sc_core::sc_in rst_i; - scc::tlm_signal_bool_out tx_o; - scc::tlm_signal_bool_in rx_i; - - sc_core::sc_out irq_o; - - cci::cci_param bit_true_transfer; - - uart(sc_core::sc_module_name nm); - virtual ~uart() override; - -protected: - void clock_cb(); - void reset_cb(); - void transmit_data(); - void receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay); - void update_irq(); - sc_core::sc_time clk{sc_core::SC_ZERO_TIME}, rx_last_start{sc_core::SC_ZERO_TIME}; - std::unique_ptr regs; - sc_core::sc_fifo rx_fifo, tx_fifo; -}; - -} /* namespace sysc */ - -#endif /* _UART_H_ */ diff --git a/platform/incl/sysc/sc_comm_singleton.h b/platform/incl/sysc/sc_comm_singleton.h deleted file mode 100644 index 349193e..0000000 --- a/platform/incl/sysc/sc_comm_singleton.h +++ /dev/null @@ -1,114 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _SYSC_SC_COMM_SINGLETON_H_ -#define _SYSC_SC_COMM_SINGLETON_H_ - -#include "seasocks/WebSocket.h" -#include -#include - -#include -#include -#include -#include - -namespace sysc { - -class WsHandler : public seasocks::WebSocket::Handler { -public: - explicit WsHandler() {} - - void onConnect(seasocks::WebSocket *connection) override; - - void onData(seasocks::WebSocket *connection, const char *data) override; - - void onDisconnect(seasocks::WebSocket *connection) override; - - void send(std::string msg) { - for (auto *con : _connections) con->send(msg); - } - - void set_receive_callback(std::function cb) { callback = cb; } - -private: - std::set _connections; - std::function callback; -}; - -class sc_comm_singleton : public sc_core::sc_module { - struct DefaultPageHandler : public seasocks::PageHandler { - DefaultPageHandler(sc_comm_singleton &o) - : owner(o) {} - virtual std::shared_ptr handle(const seasocks::Request &request); - sc_comm_singleton &owner; - }; - -public: - sc_comm_singleton() = delete; - - sc_comm_singleton(const sc_comm_singleton &) = delete; - - sc_comm_singleton &operator=(sc_comm_singleton &o) = delete; - - virtual ~sc_comm_singleton(); - - static sc_comm_singleton &inst() { - static sc_comm_singleton i("__sc_singleton"); - return i; - } - - seasocks::Server &get_server(); - - void registerWebSocketHandler(const char *endpoint, std::shared_ptr handler, - bool allowCrossOriginRequests = false); - - void execute(std::function f); - - void start_client(); - -protected: - void start_of_simulation() override; - void end_of_simulation() override; - -private: - sc_comm_singleton(sc_core::sc_module_name nm); - std::unique_ptr m_serv; - std::thread t; - void thread_func(); - bool needs_client, client_started; - std::vector endpoints; -}; - -} /* namespace sysc */ - -#endif /* _SYSC_SC_COMM_SINGLETON_H_ */ diff --git a/platform/incl/sysc/tlm_extensions.h b/platform/incl/sysc/tlm_extensions.h deleted file mode 100644 index 6b25a4a..0000000 --- a/platform/incl/sysc/tlm_extensions.h +++ /dev/null @@ -1,70 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _SYSC_TLM_EXTENSIONS_H_ -#define _SYSC_TLM_EXTENSIONS_H_ - -#include "tlm/tlm_extensions.h" - -namespace sysc { -struct tlm_signal_uart_extension : public tlm::tlm_unmanaged_extension { - - struct uart_tx { - unsigned data_bits : 4; - unsigned stop_bits : 2; - bool parity : 1; - unsigned baud_rate : 24; - unsigned data; - } tx; - sc_core::sc_time start_time; -}; - -struct tlm_signal_spi_extension : public tlm::tlm_unmanaged_extension { - - struct spi_tx { - unsigned data_bits : 5; - bool msb_first : 1; - bool m2s_data_valid : 1; - bool s2m_data_valid : 1; - unsigned m2s_data, s2m_data; - } tx; - sc_core::sc_time start_time; - - void copy_from(tlm_extension_base const &other) override { - auto &o = static_cast(other); - this->tx = o.tx; - this->start_time = o.start_time; - } -}; -} - -#endif /* _SYSC_TLM_EXTENSIONS_H_ */ diff --git a/platform/incl/sysc/top/BLDC.h b/platform/incl/sysc/top/BLDC.h deleted file mode 100644 index 84b98a9..0000000 --- a/platform/incl/sysc/top/BLDC.h +++ /dev/null @@ -1,131 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef BLDC_H_ -#define BLDC_H_ - -#include -namespace odeint = boost::numeric::odeint; - -inline double norm_angle(double alpha) { - double alpha_n = fmod(alpha, M_PI * 2); - while (alpha_n < 0.) alpha_n += (M_PI * 2); - return alpha_n; -} - -class BLDC { -public: - struct Config { - double inertia = 0.0005; /* aka 'J' in kg/(m^2) */ - double damping = 0.000089; /* aka 'B' in Nm/(rad/s) */ - double static_friction = 0.0; /* in Nm */ - // double Kv = 0.0042; /* motor constant in RPM/V */ - double Ke = 0.0042; /* back emf constant in V/rad/s*/ - double L = 0.0027; /* Coil inductance in H */ - double M = -0.000069; /* Mutual coil inductance in H */ - double R = 2.875; /* Coil resistence in Ohm */ - int NbPoles = - 2; /* NbPoles / 2 = Number of pole pairs (you count the permanent magnets on the rotor to get NbPoles) */ - }; - - using StateVector = std::array; - - struct State { - double θ /* angle of the rotor */ - double ω /* angular speed of the rotor */ - double &ia; /* phase a current */ - double &ib; /* phase b current */ - double ⁣ /* phase c current */ - explicit State(StateVector &v) - : theta(v[0]) - , omega(v[1]) - , ia(v[2]) - , ib(v[3]) - , ic(v[4]) {} - State(State &&) = delete; - State(const State &) = delete; - State &operator=(const State &) = delete; // Copy assignment operator - State &operator=(const State &&) = delete; // Move assignment operator - ~State() {} - void init() { - theta = ia = ib = ic = 0; - omega = 0.; - } - }; - - explicit BLDC(const Config config); - - virtual ~BLDC(); - - void set_input(std::array vin) { this->vin = vin; } - - void run(double dt); - - void printToStream(std::ostream &) const; - - double get_current_time() { return current_time; } - - std::array get_voltages() { - return std::array{voltages[VA], voltages[VB], voltages[VC], voltages[VCENTER], - voltages[EA], voltages[EB], voltages[EC]}; - } - const State &getState() { return state; } - - void setLoad(double torque) { torque_load = torque; } - - const double dt = 0.00000001; - -protected: - Config config; - StateVector stateVector; - State state; - std::array vin; - double current_time = 0.0; - double torque_load = 0.0001; - double etorque = 0.0, mtorque = 0.0; - std::array voltages; - enum VoltageNames { EA = 0, EB = 1, EC = 2, VA = 3, VB = 4, VC = 5, VCENTER = 6 }; - double calc_bemf_factor(const State &state, double theta); - void calc_back_emf(const State &state, double theta_e); - void calc_voltages(); - // ODE part - // boost::numeric::odeint::runge_kutta4< StateVector > stepper; - // boost::numeric::odeint::runge_kutta_cash_karp54 stepper; - // using stepper_type = odeint::runge_kutta_dopri5; - // using stepper_type = odeint::runge_kutta_cash_karp54< StateVector>; - using stepper_type = odeint::runge_kutta_fehlberg78; - void rotor_dyn(const StateVector &x, StateVector &dxdt, const double t); -}; - -std::ostream &operator<<(std::ostream &os, const BLDC &bldc); - -#endif /* BLDC_H_ */ diff --git a/platform/incl/sysc/top/dcmotor.h b/platform/incl/sysc/top/dcmotor.h deleted file mode 100644 index d6d59e8..0000000 --- a/platform/incl/sysc/top/dcmotor.h +++ /dev/null @@ -1,68 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _SYSC_TOP_DCMOTOR_H_ -#define _SYSC_TOP_DCMOTOR_H_ - -#include "BLDC.h" -#include "cci_configuration" -#include "scc/traceable.h" -#include - -namespace sysc { - -class dc_motor : public sc_core::sc_module, public scc::traceable { -public: - SC_HAS_PROCESS(dc_motor);// NOLINT - - sc_core::sc_in va_i, vb_i, vc_i; - sc_core::sc_out va_o, vb_o, vc_o, vcenter_o; - - dc_motor(const sc_core::sc_module_name &nm); - - virtual ~dc_motor(); - - void trace(sc_core::sc_trace_file *trf) const override; - - cci::cci_param max_integ_step; - cci::cci_param load; - -private: - void thread(void); - BLDC bldc_model; - const BLDC::State &bldc_state; - std::array vout; -}; - -} /* namespace sysc */ - -#endif /* RISCV_SC_INCL_SYSC_TOP_DCMOTOR_H_ */ diff --git a/platform/incl/sysc/top/h_bridge.h b/platform/incl/sysc/top/h_bridge.h deleted file mode 100644 index 6606038..0000000 --- a/platform/incl/sysc/top/h_bridge.h +++ /dev/null @@ -1,66 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef RISCV_SC_INCL_SYSC_TOP_H_BRIDGE_H_ -#define RISCV_SC_INCL_SYSC_TOP_H_BRIDGE_H_ - -#include "cci_configuration" -#include - -namespace sysc { - -class h_bridge : public sc_core::sc_module { -public: - SC_HAS_PROCESS(h_bridge);// NOLINT - - sc_core::sc_in ha_i, la_i; - sc_core::sc_in hb_i, lb_i; - sc_core::sc_in hc_i, lc_i; - - sc_core::sc_out va_o, vb_o, vc_o; - - cci::cci_param vcc; - - h_bridge(const sc_core::sc_module_name &nm); - - virtual ~h_bridge(); - -private: - void ain_cb(); - void bin_cb(); - void cin_cb(); - void write_output(sc_dt::sc_logic h_i, sc_dt::sc_logic l_i, sc_core::sc_out &v_o); -}; - -} /* namespace sysc */ - -#endif /* RISCV_SC_INCL_SYSC_TOP_H_BRIDGE_H_ */ diff --git a/platform/incl/sysc/top/hifive1.h b/platform/incl/sysc/top/hifive1.h deleted file mode 100644 index 030bb95..0000000 --- a/platform/incl/sysc/top/hifive1.h +++ /dev/null @@ -1,68 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _SIFIVE_HIFIVE1_H_ -#define _SIFIVE_HIFIVE1_H_ - -#include -#include -#include "tlm/tlm_signal_sockets.h" -#include -#include -#include - -namespace sysc { - -struct hifive1 : public sc_core::sc_module { - - SC_HAS_PROCESS(hifive1); - - sc_core::sc_in erst_n; - sc_core::sc_in vref_i; -#define PORT_DECL(z, n, _) sc_core::sc_in adc_ch##n##_i; - BOOST_PP_REPEAT(8, PORT_DECL, _); -#undef PORT_DECL - sc_core::sc_out ha_o, la_o, hb_o, lb_o,hc_o, lc_o; - - hifive1(sc_core::sc_module_name nm); - -protected: - sc_core::sc_vector> s_gpio; - sc_core::sc_vector h_bridge; - fe310 i_fe310; - terminal i_terminal; - mcp_3208 i_adc; -}; - -} - -#endif /* _SYSC_SIFIVE_HIFIVE1_H_ */ diff --git a/platform/incl/sysc/top/mcp_adc.h b/platform/incl/sysc/top/mcp_adc.h deleted file mode 100644 index 7c09396..0000000 --- a/platform/incl/sysc/top/mcp_adc.h +++ /dev/null @@ -1,120 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _SYSC_TOP_MCP3008_H_ -#define _SYSC_TOP_MCP3008_H_ - -#include "cci_configuration" -#include "scc/signal_initiator_mixin.h" -#include "scc/signal_target_mixin.h" -#include "sysc/tlm_extensions.h" -#include -#include -#include - -namespace sysc { - -class mcp_adc : public sc_core::sc_module { -public: - - template - static std::unique_ptr create(sc_core::sc_module_name nm); - - scc::tlm_signal_logic_in sck_i; - scc::tlm_signal_logic_out miso_o; - scc::tlm_signal_logic_in mosi_i; - scc::tlm_signal_logic_in cs_i; - - sc_core::sc_in vref_i; - sc_core::sc_vector> ch_i; - - mcp_adc(mcp_adc &other) = delete; - - mcp_adc(mcp_adc &&other) = delete; - - mcp_adc &operator=(mcp_adc &other) = delete; - - mcp_adc &operator=(mcp_adc &&other) = delete; - - ~mcp_adc() override = default; - -protected: - mcp_adc(sc_core::sc_module_name nm, size_t channel_no) - : sc_core::sc_module(nm) - , NAMED(sck_i) - , NAMED(miso_o) - , NAMED(mosi_i) - , NAMED(cs_i) - , NAMED(vref_i) - , NAMED(ch_i, channel_no) {} -}; - -class mcp_3008 : public mcp_adc { -public: - SC_HAS_PROCESS(mcp_3008);// NOLINT - - mcp_3008(sc_core::sc_module_name nm); - ~mcp_3008() override = default; - -private: - tlm::tlm_sync_enum receive(tlm::tlm_signal_gp &, tlm::tlm_phase &, sc_core::sc_time &); - void do_conversion(); - unsigned idx, rx_bits; - std::array rx_bytes, tx_bytes; - sc_dt::sc_logic mosi_v, miso_v, cs_v; - sysc::tlm_signal_spi_extension *ext, tx_ext; - sc_core::sc_time last_tx_start; -}; - -class mcp_3208 : public mcp_adc { -public: - SC_HAS_PROCESS(mcp_3208);// NOLINT - - mcp_3208(sc_core::sc_module_name nm); - ~mcp_3208() override = default; - -private: - tlm::tlm_sync_enum receive(tlm::tlm_signal_gp &, tlm::tlm_phase &, sc_core::sc_time &); - void sample_inputs(); - void do_conversion(); - unsigned idx, rx_bits, byte_offs, bit_offs; - std::array rx_bytes, tx_bytes; - sc_dt::sc_logic mosi_v, sck_v, cs_v; - sysc::tlm_signal_spi_extension *ext, tx_ext; - sc_core::sc_time last_tx_start; - sc_core::sc_event clk_sample_evt; -}; - - -} /* namespace sysc */ - -#endif /* _SYSC_TOP_MCP3008_H_ */ diff --git a/platform/incl/sysc/top/system.h b/platform/incl/sysc/top/system.h deleted file mode 100644 index 3d60001..0000000 --- a/platform/incl/sysc/top/system.h +++ /dev/null @@ -1,62 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef __SYSC_GENERAL_SYSTEM_H_ -#define __SYSC_GENERAL_SYSTEM_H_ - -#include "dcmotor.h" -#include "h_bridge.h" -#include -#include -#include "hifive1.h" - -namespace sysc { - -class system : sc_core::sc_module { -public: - SC_HAS_PROCESS(system);// NOLINT - - system(sc_core::sc_module_name nm); - virtual ~system(); - -private: - sc_core::sc_signal s_ha, s_la, s_hb, s_lb, s_hc, s_lc; - sc_core::sc_signal s_rst_n; - sc_core::sc_signal s_vref, s_va, s_vb, s_vc, s_vasens, s_vbsens, s_vcsens, s_vcentersens; - sc_core::sc_vector> s_ana; - sysc::hifive1 i_hifive1; - sysc::h_bridge i_h_bridge; - sysc::dc_motor i_motor; - void gen_por(); -}; -} -#endif /* __SYSC_GENERAL_SYSTEM_H_ */ diff --git a/platform/incl/sysc/top/terminal.h b/platform/incl/sysc/top/terminal.h deleted file mode 100644 index 50a494b..0000000 --- a/platform/incl/sysc/top/terminal.h +++ /dev/null @@ -1,69 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef _SYSC_TOP_TERMINAL_H_ -#define _SYSC_TOP_TERMINAL_H_ - -#include "cci_configuration" -#include "scc/signal_initiator_mixin.h" -#include "scc/signal_target_mixin.h" -#include "tlm/tlm_signal.h" -#include -#include - -namespace sysc { -class WsHandler; - -class terminal : public sc_core::sc_module { -public: - scc::tlm_signal_logic_out tx_o; - scc::tlm_signal_logic_in rx_i; - - terminal(); - - terminal(const sc_core::sc_module_name &nm); - - virtual ~terminal(); - - cci::cci_param write_to_ws; - -protected: - void before_end_of_elaboration(); - void receive(tlm::tlm_signal_gp &gp, sc_core::sc_time &delay); - - std::vector queue; - std::shared_ptr handler; - sc_core::sc_time last_tx_start = sc_core::SC_ZERO_TIME; -}; -} - -#endif /* _SYSC_TOP_TERMINAL_H_ */ diff --git a/platform/src/CLIParser.cpp b/platform/src/CLIParser.cpp deleted file mode 100644 index e4d74f7..0000000 --- a/platform/src/CLIParser.cpp +++ /dev/null @@ -1,112 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "CLIParser.h" -#include -#include -#include -#include - -namespace po = boost::program_options; -using namespace sc_core; - -CLIParser::CLIParser(int argc, char *argv[]) -: desc("Options") -, valid(false) { - scc::init_logging(); - LOGGER(DEFAULT)::reporting_level() = logging::WARNING; - LOGGER(connection)::reporting_level() = logging::WARNING; - LOGGER(SystemC)::reporting_level() = logging::WARNING; - - build(); - try { - po::store(po::parse_command_line(argc, argv, desc), vm_); // can throw - // --help option - if (vm_.count("help")) { - std::cout << "DBT-RISE-RiscV simulator for RISC-V" << std::endl << desc << std::endl; - } - po::notify(vm_); // throws on error, so do after help in case there are any problems - valid = true; - } catch (po::error &e) { - std::cerr << "ERROR: " << e.what() << std::endl << std::endl; - std::cerr << desc << std::endl; - } - if (vm_.count("verbose")) { // NONE, FATAL, ERROR, WARNING, INFO, DEBUG, TRACE - const std::array verbosity = {SC_NONE, // Logging::NONE - SC_LOW, // Logging::FATAL - SC_LOW, // Logging::ERROR - SC_LOW, // Logging::WARNING - SC_MEDIUM, // Logging::INFO - SC_HIGH, // logging::DEBUG - SC_FULL, // logging::TRACE - SC_DEBUG}; // logging::TRACE+1 - auto log_level = vm_["verbose"].as(); - auto l = logging::as_log_level(log_level > 6 ? 6 : log_level); - LOGGER(DEFAULT)::reporting_level() = l; - LOGGER(DEFAULT)::print_time() = false; - LOGGER(connection)::reporting_level() = l; - LOGGER(connection)::print_time() = false; - LOGGER(SystemC)::reporting_level() = l; - LOGGER(SystemC)::print_time() = false; - sc_report_handler::set_verbosity_level(verbosity[log_level]); - } - if (vm_.count("log-file")) { - // configure the connection logger - auto f = fopen(vm_["log-file"].as().c_str(), "w"); - LOG_OUTPUT(DEFAULT)::stream() = f; - LOG_OUTPUT(connection)::stream() = f; - LOG_OUTPUT(SystemC)::stream() = f; - } -} - -void CLIParser::build() { - // clang-format off - desc.add_options() - ("help,h", "Print help message") - ("verbose,v", po::value()->implicit_value(3), "Sets logging verbosity") - ("log-file", po::value(), "Sets default log file.") - ("disass,d", po::value()->implicit_value(""), "Enables disassembly") - ("elf,l", po::value(), "ELF file to load") - ("gdb-port,g", po::value()->default_value(0), "enable gdb server and specify port to use") - ("dump-ir", "dump the intermediate representation") - ("quantum", po::value(), "SystemC quantum time in ns") - ("reset,r", po::value(), "reset address") - ("trace-level,t", po::value()->default_value(0), "enable tracing, or combination of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite") - ("trace-default-on", "enables tracing for all unspecified modules") - ("trace-file", po::value()->default_value("system"), "set th ename of the trace file") - ("max_time,m", po::value(), "maximum time to run") - ("config-file,c", po::value()->default_value(""), "read configuration from file") - ("dump-config,dc", po::value()->default_value(""), "dump configuration to file file"); - // clang-format on -} - -CLIParser::~CLIParser() = default; diff --git a/platform/src/CLIParser.h b/platform/src/CLIParser.h deleted file mode 100644 index f6faa0c..0000000 --- a/platform/src/CLIParser.h +++ /dev/null @@ -1,60 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#ifndef PLATFORM_SRC_CLIPARSER_H_ -#define PLATFORM_SRC_CLIPARSER_H_ - -#include -#include - -class CLIParser { -public: - CLIParser(int argc, char *argv[]); - - virtual ~CLIParser(); - - bool is_valid() { return valid; } - - const boost::program_options::variables_map &vm() { return vm_; } - - bool is_set(const char *option) { return vm_.count(option) != 0; } - - template const T &get(const char *option) { return vm_[option].as(); } - -private: - void build(); - bool valid; - boost::program_options::variables_map vm_; - boost::program_options::options_description desc; -}; - -#endif /* PLATFORM_SRC_CLIPARSER_H_ */ diff --git a/platform/src/CMakeLists.txt b/platform/src/CMakeLists.txt deleted file mode 100644 index fd1f117..0000000 --- a/platform/src/CMakeLists.txt +++ /dev/null @@ -1,106 +0,0 @@ -# library files -FILE(GLOB RiscVSCHeaders ${PROJECT_SOURCE_DIR}/incl/sysc/*.h ${PROJECT_SOURCE_DIR}/incl/sysc/*/*.h) -set(LIB_HEADERS ${RiscVSCHeaders} ) -set(LIB_SOURCES - sysc/aon.cpp - sysc/BLDC.cpp - sysc/clint.cpp - sysc/dcmotor.cpp - sysc/gpio.cpp - sysc/h_bridge.cpp - sysc/hifive1.cpp - sysc/fe310.cpp - sysc/mcp_adc.cpp - sysc/plic.cpp - sysc/prci.cpp - sysc/pwm.cpp - sysc/sc_comm_singleton.cpp - sysc/spi.cpp - sysc/system.cpp - sysc/terminal.cpp - sysc/uart.cpp - CLIParser.cpp ) - -set(APP_SOURCES sc_main.cpp) - -# Define two variables in order not to repeat ourselves. -set(LIBRARY_NAME platform) - -## the following setting needs to be consistent with the library -#add_definitions(-DSC_DEFAULT_WRITER_POLICY=SC_MANY_WRITERS) - -# Define the library -add_library(${LIBRARY_NAME} SHARED ${LIB_SOURCES}) - -# Links the target exe against the libraries -target_link_libraries(${LIBRARY_NAME} riscv_sc) -target_link_libraries(${LIBRARY_NAME} dbt-core) -target_link_libraries(${LIBRARY_NAME} softfloat) -target_link_libraries(${LIBRARY_NAME} sc-components) -target_link_libraries(${LIBRARY_NAME} ${CONAN_LIBS_SEASOCKS}) -target_link_libraries(${LIBRARY_NAME} external) -target_link_libraries(${LIBRARY_NAME} ${llvm_libs}) -target_link_libraries(${LIBRARY_NAME} ${Boost_LIBRARIES} ) - -set_target_properties(${LIBRARY_NAME} PROPERTIES - VERSION ${VERSION} # ${VERSION} was defined in the main CMakeLists. - FRAMEWORK FALSE - PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers -) - -# This is a make target, so you can do a "make riscv-sc" -set(APPLICATION_NAME riscv.vp) - -include_directories(${PROJECT_SOURCE_DIR}/incl) -include_directories(${CONAN_INCLUDE_DIRS_SEASOCKS}) -add_definitions(-DWITH_SYSTEMC) # or -DSC_NO_WRITE_CHECK -include_directories(${SystemC_INCLUDE_DIRS}) -include_directories(${CCI_INCLUDE_DIRS}) -if(SCV_FOUND) - add_definitions(-DWITH_SCV) - include_directories(${SCV_INCLUDE_DIRS}) -endif() - - -link_directories(${SystemC_LIBRARY_DIRS}) -link_directories(${CCI_LIBRARY_DIRS}) -link_directories(${CONAN_LIB_DIRS_SEASOCKS}) - -add_executable(${APPLICATION_NAME} ${APP_SOURCES}) -# include files for this application -target_include_directories(${APPLICATION_NAME} SYSTEM PRIVATE ${LLVM_INCLUDE_DIRS}) -# Links the target exe against the libraries -target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME}) -target_link_libraries(${APPLICATION_NAME} riscv_sc) -target_link_libraries(${APPLICATION_NAME} dbt-core) -target_link_libraries(${APPLICATION_NAME} softfloat) -target_link_libraries(${APPLICATION_NAME} sc-components) -target_link_libraries(${APPLICATION_NAME} ${CONAN_LIBS_SEASOCKS}) -target_link_libraries(${APPLICATION_NAME} external) -target_link_libraries(${APPLICATION_NAME} ${llvm_libs}) -target_link_libraries(${APPLICATION_NAME} ${CCI_LIBRARIES} ) -target_link_libraries(${APPLICATION_NAME} ${SystemC_LIBRARIES} ) -if(SCV_FOUND) - link_directories(${SCV_LIBRARY_DIRS}) - target_link_libraries (${APPLICATION_NAME} ${SCV_LIBRARIES}) -endif() -target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} ) -if (Tcmalloc_FOUND) - target_link_libraries(${APPLICATION_NAME} ${Tcmalloc_LIBRARIES}) -endif(Tcmalloc_FOUND) - -# Says how and where to install software -# Targets: -# * /lib/ -# * header location after install: /include//*.h -# * headers can be included by C++ code `#/Bar.hpp>` -install(TARGETS ${LIBRARY_NAME} ${APPLICATION_NAME} - EXPORT ${PROJECT_NAME}Targets # for downstream dependencies - ARCHIVE DESTINATION lib COMPONENT libs # static lib - RUNTIME DESTINATION bin COMPONENT libs # binaries - LIBRARY DESTINATION lib COMPONENT libs # shared lib - FRAMEWORK DESTINATION bin COMPONENT libs # for mac - PUBLIC_HEADER DESTINATION incl/${PROJECT_NAME} COMPONENT devel # headers for mac (note the different component -> different package) - INCLUDES DESTINATION incl # headers -) - diff --git a/platform/src/sc_main.cpp b/platform/src/sc_main.cpp deleted file mode 100644 index 27c058a..0000000 --- a/platform/src/sc_main.cpp +++ /dev/null @@ -1,142 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "CLIParser.h" -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -using namespace sysc; -namespace po = boost::program_options; - -namespace { -const size_t ERROR_IN_COMMAND_LINE = 1; -const size_t SUCCESS = 0; -const size_t ERROR_UNHANDLED_EXCEPTION = 2; -} // namespace - -int sc_main(int argc, char *argv[]) { - /////////////////////////////////////////////////////////////////////////// - // SystemC >=2.2 got picky about multiple drivers so disable check - /////////////////////////////////////////////////////////////////////////// - sc_report_handler::set_actions(SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, SC_DO_NOTHING); - /////////////////////////////////////////////////////////////////////////// - // create global CCI broker - /////////////////////////////////////////////////////////////////////////// - cci::cci_register_broker(new cci_utils::broker("Global Broker")); - /////////////////////////////////////////////////////////////////////////// - // CLI argument parsing & logging setup - /////////////////////////////////////////////////////////////////////////// - CLIParser parser(argc, argv); - if (!parser.is_valid()) return ERROR_IN_COMMAND_LINE; - /////////////////////////////////////////////////////////////////////////// - // set up infrastructure - /////////////////////////////////////////////////////////////////////////// - iss::init_jit(argc, argv); - /////////////////////////////////////////////////////////////////////////// - // set up configuration - /////////////////////////////////////////////////////////////////////////// - scc::configurer cfg(parser.get("config-file")); - /////////////////////////////////////////////////////////////////////////// - // set up tracing & transaction recording - /////////////////////////////////////////////////////////////////////////// - auto trace_level = parser.get("trace-level"); - scc::configurable_tracer trace(parser.get("trace-file"), - static_cast(trace_level >> 1), // bit3-bit1 define the kind of transaction trace - (trace_level&0x1) != 0, // bit0 enables vcd - parser.is_set("trace-default-on")); - /////////////////////////////////////////////////////////////////////////// - // instantiate top level - /////////////////////////////////////////////////////////////////////////// - auto i_system = std::make_unique("i_system"); - /////////////////////////////////////////////////////////////////////////// - // add non-implemented 'enableTracing' properties - /////////////////////////////////////////////////////////////////////////// - trace.add_control(); - /////////////////////////////////////////////////////////////////////////// - // dump configuration if requested - /////////////////////////////////////////////////////////////////////////// - if (parser.get("dump-config").size() > 0) { - std::ofstream of{parser.get("dump-config")}; - if (of.is_open()) cfg.dump_configuration(of); - } - cfg.configure(); - /////////////////////////////////////////////////////////////////////////// - // overwrite config with command line settings - /////////////////////////////////////////////////////////////////////////// - cfg.set_value("i_system.i_hifive1.i_fe310.i_core_complex.gdb_server_port", parser.get("gdb-port")); - cfg.set_value("i_system.i_hifive1.i_fe310.i_core_complex.dump_ir", parser.is_set("dump-ir")); - if (parser.is_set("elf")) cfg.set_value("i_system.i_hifive1.i_fe310.i_core_complex.elf_file", parser.get("elf")); - if (parser.is_set("quantum")) - tlm::tlm_global_quantum::instance().set(sc_core::sc_time(parser.get("quantum"), sc_core::SC_NS)); - if (parser.is_set("reset")) { - auto str = parser.get("reset"); - uint64_t start_address = str.find("0x") == 0 ? std::stoull(str.substr(2), nullptr, 16) : std::stoull(str, nullptr, 10); - cfg.set_value("i_system.i_hifive1.i_fe310.i_core_complex.reset_address", start_address); - } - if (parser.is_set("disass")) { - cfg.set_value("i_system.i_hifive1.i_fe310.i_core_complex.enable_disass", true); - LOGGER(disass)::reporting_level() = logging::INFO; - auto file_name = parser.get("disass"); - if (file_name.length() > 0) { - LOG_OUTPUT(disass)::stream() = fopen(file_name.c_str(), "w"); - LOGGER(disass)::print_time() = false; - LOGGER(disass)::print_severity() = false; - } - } - /////////////////////////////////////////////////////////////////////////// - // run simulation - /////////////////////////////////////////////////////////////////////////// - try { - if (parser.is_set("max_time")) { - sc_core::sc_start(scc::parse_from_string(parser.get("max_time"))); - } else - sc_core::sc_start(); - if (!sc_core::sc_end_of_simulation_invoked()) sc_core::sc_stop(); - } catch (sc_core::sc_report &rep) { - sc_core::sc_report_handler::get_handler()(rep, sc_core::SC_DISPLAY | sc_core::SC_STOP); - } - return 0; -} diff --git a/platform/src/sysc/BLDC.cpp b/platform/src/sysc/BLDC.cpp deleted file mode 100644 index e7f2a1b..0000000 --- a/platform/src/sysc/BLDC.cpp +++ /dev/null @@ -1,188 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/top/BLDC.h" - -// implementation according to Modeling of BLDC Motor with Ideal Back-EMF for Automotive Applications -// Proceedings of the World Congress on Engineering 2011 Vol II WCE 2011, July 6 - 8, 2011, London, U.K. -BLDC::BLDC(const Config config) -: config(config) -, stateVector({{0.0, 0.0, 0.0, 0.0, 0.0}}) -, state(stateVector) -, vin({{0.0, 0.0, 0.0}}) -, voltages({{0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0}}) { - state.init(); -} - -BLDC::~BLDC() = default; - -double BLDC::calc_bemf_factor(const State &x, double theta) { - if (theta >= 0 && theta < 2. / 3. * M_PI) { - return 1; - } else if (theta >= 2. / 3. * M_PI && theta < M_PI) { - return 1 - 6 / M_PI * (theta - 2. / 3. * M_PI); - } else if (theta >= M_PI && theta < 5. / 3. * M_PI) { - return -1; - } else if (theta >= 5. / 3. * M_PI && theta <= 2. * M_PI) { - return -1 + 6 / M_PI * (theta - 5. / 3. * M_PI); - } else { - fprintf(stderr, "ERROR: angle out of bounds can not calculate bemf %f\n", theta); - throw std::runtime_error("angle out of bounds can not calculate bemf"); - } -} - -void BLDC::calc_back_emf(const State &state, double theta_e) { - double max_bemf = config.Ke * state.omega; - theta_e-=M_PI * (1. / 3.); - voltages[EA] = max_bemf * calc_bemf_factor(state, norm_angle(theta_e)); - voltages[EB] = max_bemf * calc_bemf_factor(state, norm_angle(theta_e + M_PI * (2. / 3.))); - voltages[EC] = max_bemf * calc_bemf_factor(state, norm_angle(theta_e + M_PI * (4. / 3.))); -} - -void BLDC::calc_voltages() { - const double NaN = nan(""); - /* Check which phases are excited. */ - bool pa = isnan(vin[0]) ? false : true; - bool pb = isnan(vin[1]) ? false : true; - bool pc = isnan(vin[2]) ? false : true; - - if (pa && pb && pc) { - voltages[VA] = vin[0]; - voltages[VB] = vin[1]; - voltages[VC] = vin[2]; - voltages[VCENTER] = - (voltages[VA] + voltages[VB] + voltages[VC] - voltages[EA] - voltages[EB] - voltages[EC]) / 3.; - } else if (pa && pb) { - voltages[VA] = vin[0]; - voltages[VB] = vin[1]; - voltages[VCENTER] = (voltages[VA] + voltages[VB] - voltages[EA] - voltages[EB]) / 2.; - voltages[VC] = voltages[EC] + voltages[VCENTER]; - } else if (pa && pc) { - voltages[VA] = vin[0]; - voltages[VC] = vin[2]; - voltages[VCENTER] = (voltages[VA] + voltages[VC] - voltages[EA] - voltages[EC]) / 2.; - voltages[VB] = voltages[EB] + voltages[VCENTER]; - } else if (pb && pc) { - voltages[VB] = vin[1]; - voltages[VC] = vin[2]; - voltages[VCENTER] = (voltages[VB] + voltages[VC] - voltages[EB] - voltages[EC]) / 2.; - voltages[VA] = voltages[EA] + voltages[VCENTER]; - } else if (pa) { - voltages[VA] = vin[0]; - voltages[VCENTER] = (voltages[VA] - voltages[EA]); - voltages[VB] = voltages[EB] + voltages[VCENTER]; - voltages[VC] = voltages[EC] + voltages[VCENTER]; - } else if (pb) { - voltages[VB] = vin[1]; - voltages[VCENTER] = (voltages[VB] - voltages[EB]); - voltages[VA] = voltages[EA] + voltages[VCENTER]; - voltages[VC] = voltages[EC] + voltages[VCENTER]; - } else if (pc) { - voltages[VC] = vin[0]; - voltages[VCENTER] = (voltages[VC] - voltages[EC]); - voltages[VA] = voltages[EA] + voltages[VCENTER]; - voltages[VB] = voltages[EB] + voltages[VCENTER]; - } else { - voltages[VA] = voltages[EA]; - voltages[VB] = voltages[EB]; - voltages[VC] = voltages[EC]; - voltages[VCENTER] = 0; - // return; - } - auto vmax = std::max({pa ? vin[0] : 0, pb ? vin[1] : 0, pc ? vin[2] : 0}); - voltages[VCENTER] = vmax / 2; -} - -void BLDC::printToStream(std::ostream &os) const { - os << state.omega << ";" << state.theta << ";" << state.ia << ";" << state.ib << ";" << state.ic << ";" - << voltages[VA] << ";" << voltages[VB] << ";" << voltages[VC] << ";" << voltages[EA] << ";" << voltages[EB] - << ";" << voltages[EC] << ";" << voltages[VCENTER] << ";" << vin[0] << ";" << vin[1] << ";" << vin[2] << ";" - << etorque; -} - -void BLDC::rotor_dyn(const StateVector &x_, StateVector &dxdt_, const double t) { - const State x(const_cast(x_)); - State dxdt(dxdt_); - double theta_e = state.theta * (config.NbPoles / 2.); - /* Calculate backemf voltages. */ - calc_back_emf(x, theta_e); - /* Calculate voltages. */ - calc_voltages(); - /* Electromagnetic torque. */ - // if (x.omega == 0) { - // printf("ERROR: input state vector omega equals 0!!!\n"); - // throw std::runtime_error("input state vector omega equals 0"); - // } - /* electrical torque */ - // etorque = ((voltages[EA] * x.ia) + (voltages[EB] * x.ib) + (voltages[EC] * x.ic)) / x.omega; - // which is equivalent to: - etorque = config.Ke * (x.ia * (calc_bemf_factor(state, norm_angle(theta_e))) + - x.ib * (calc_bemf_factor(state, norm_angle(theta_e + M_PI * (2. / 3.)))) + - x.ic * (calc_bemf_factor(state, norm_angle(theta_e + M_PI * (4. / 3.))))); - /* Mechanical torque. */ - mtorque = ((etorque * (config.NbPoles / 2)) - (config.damping * x.omega) - torque_load); - - if ((mtorque > 0) && (mtorque <= config.static_friction)) { - mtorque = 0; - } else if (mtorque > config.static_friction) { - mtorque -= config.static_friction; - } else if ((mtorque < 0) && (mtorque >= -(config.static_friction))) { - mtorque = 0; - } else if (mtorque < -(config.static_friction)) { - mtorque += config.static_friction; - } - /* Position of the rotor */ - dxdt.theta = x.omega; - /* Acceleration of the rotor. (omega_dot) */ - // a=M/J with M->torque, J->Inertia, a->angular acceleration - dxdt.omega = mtorque / config.inertia; - /* Calculate dot currents. */ - dxdt.ia = (voltages[VA] - (config.R * x.ia) - voltages[EA] - voltages[VCENTER]) / (config.L - config.M); - dxdt.ib = (voltages[VB] - (config.R * x.ib) - voltages[EB] - voltages[VCENTER]) / (config.L - config.M); - dxdt.ic = (voltages[VC] - (config.R * x.ic) - voltages[EC] - voltages[VCENTER]) / (config.L - config.M); -} - -void BLDC::run(double incr) { - if (dt > incr) throw std::runtime_error("incr needs to be larger than dt"); - double next_time = current_time + incr; - odeint::integrate_adaptive( - make_controlled(1.0e-10, 1.0e-6, stepper_type()), - [this](const StateVector &x, StateVector &dxdt, double t) { this->rotor_dyn(x, dxdt, t); }, stateVector, - current_time, next_time, dt); - current_time = next_time; - state.theta = norm_angle(state.theta); -} - -std::ostream &operator<<(std::ostream &os, const BLDC &bldc) { - bldc.printToStream(os); - return os; -} diff --git a/platform/src/sysc/aon.cpp b/platform/src/sysc/aon.cpp deleted file mode 100644 index dd18fb2..0000000 --- a/platform/src/sysc/aon.cpp +++ /dev/null @@ -1,78 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * Contributors: - * eyck@minres.com - initial implementation - * - * - *******************************************************************************/ - -#include "sysc/SiFive/aon.h" - -#include "scc/utilities.h" -#include "sysc/SiFive/gen/aon_regs.h" - -namespace sysc { - -aon::aon(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, tlm_target<>(clk) -, NAMED(clk_i) -, NAMED(erst_n_i) -, NAMED(lfclkc_o) -, NAMED(rst_o) -, NAMEDD(regs, aon_regs) { - regs->registerResources(*this); - SC_METHOD(clock_cb); - sensitive << clk_i; - SC_METHOD(reset_cb); - sensitive << erst_n_i; -} - -void aon::start_of_simulation() { rst_o = true; } - -void aon::clock_cb() { this->clk = clk_i.read(); } - -aon::~aon() {} // NOLINT - -void aon::reset_cb() { - if (!erst_n_i.read()) { - regs->reset_start(); - rst_o = true; - } else { - regs->reset_stop(); - rst_o = false; - } - lfclkc_o.write(sc_core::sc_time(1 / 32768., sc_core::SC_SEC)); -} - -void aon::reset_internal_cb() {} - -} /* namespace sysc */ diff --git a/platform/src/sysc/clint.cpp b/platform/src/sysc/clint.cpp deleted file mode 100644 index c0753aa..0000000 --- a/platform/src/sysc/clint.cpp +++ /dev/null @@ -1,124 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/SiFive/clint.h" - -#include "scc/report.h" -#include "scc/utilities.h" -#include "sysc/SiFive/gen/clint_regs.h" - -namespace sysc { -using namespace sc_core; - -const int lfclk_mutiplier = 1 << 12; - -clint::clint(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, tlm_target<>(clk) -, NAMED(tlclk_i) -, NAMED(lfclk_i) -, NAMED(rst_i) -, NAMED(mtime_int_o) -, NAMED(msip_int_o) -, NAMEDD(regs, clint_regs) -, cnt_fraction(0) { - regs->registerResources(*this); - SC_METHOD(clock_cb); - sensitive << tlclk_i << lfclk_i; - SC_METHOD(reset_cb); - sensitive << rst_i; - dont_initialize(); - regs->mtimecmp.set_write_cb([this](scc::sc_register ®, uint64_t data, sc_core::sc_time d) -> bool { - if (!regs->in_reset()) { - reg.put(data); - this->update_mtime(); - } - return true; - }); - regs->mtime.set_read_cb([this](const scc::sc_register ®, uint64_t &data, sc_core::sc_time d) -> bool { - this->update_mtime(); - data = reg.get(); - return true; - }); - regs->mtime.set_write_cb( - [this](scc::sc_register ®, uint64_t data, sc_core::sc_time d) -> bool { return false; }); - regs->msip.set_write_cb([this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - reg.put(data); - msip_int_o.write(regs->r_msip.msip); - return true; - }); - SC_METHOD(update_mtime); - sensitive << mtime_evt; - dont_initialize(); -} - -void clint::clock_cb() { - update_mtime(); - clk = lfclk_i.read(); - update_mtime(); -} - -clint::~clint() = default; - -void clint::reset_cb() { - if (rst_i.read()) { - regs->reset_start(); - msip_int_o.write(false); - mtime_int_o.write(false); - cnt_fraction = 0; - } else - regs->reset_stop(); -} - -void clint::update_mtime() { - if (clk > SC_ZERO_TIME) { - uint64_t elapsed_clks = - (sc_time_stamp() - last_updt) / clk; // get the number of clock periods since last invocation - last_updt += elapsed_clks * clk; // increment the last_updt timestamp by the number of clocks - if (elapsed_clks) { // update mtime reg if we have more than 0 elapsed clk periods - regs->r_mtime += elapsed_clks; - mtime_evt.cancel(); - if (regs->r_mtimecmp > 0) - if (regs->r_mtimecmp > regs->r_mtime && clk > sc_core::SC_ZERO_TIME) { - sc_core::sc_time next_trigger = - (clk * lfclk_mutiplier) * (regs->r_mtimecmp - regs->mtime) - cnt_fraction * clk; - SCTRACE() << "Timer fires at " << sc_time_stamp() + next_trigger; - mtime_evt.notify(next_trigger); - mtime_int_o.write(false); - } else - mtime_int_o.write(true); - } - } else - last_updt = sc_time_stamp(); -} - -} /* namespace sysc */ diff --git a/platform/src/sysc/dcmotor.cpp b/platform/src/sysc/dcmotor.cpp deleted file mode 100644 index 1ecc199..0000000 --- a/platform/src/sysc/dcmotor.cpp +++ /dev/null @@ -1,114 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/top/dcmotor.h" -#include "scc/utilities.h" -#include - -namespace sysc { - -using namespace sc_core; - -auto get_config = []() -> BLDC::Config { - BLDC::Config config{}; - config.Ke = 1. / 4000., // 0.01; // V/rad/s, = 1/Kv - config.R = 0.5; // Ohm - config.Ke = 0.01; - config.inertia = 0.0005; - config.NbPoles = 2; - config.damping = 0.00001; - return config; -}; - -dc_motor::dc_motor(const sc_module_name &nm) -: sc_module(nm) -, NAMED(va_i) -, NAMED(vb_i) -, NAMED(vc_i) -, NAMED(va_o) -, NAMED(vb_o) -, NAMED(vc_o) -, NAMED(vcenter_o) -, NAMED(max_integ_step, sc_time(10, SC_US)) -, NAMED(load, 0.1) -, bldc_model(get_config()) -, bldc_state(bldc_model.getState()) { - bldc_model.setLoad(0.0001); - SC_THREAD(thread); -} - -dc_motor::~dc_motor() = default; - -void dc_motor::trace(sc_trace_file *trf) const { - auto &ia = bldc_state.ia; - sc_core::sc_trace(trf, bldc_state.ia, std::string(this->name()) +"." "ia"); - sc_core::sc_trace(trf, bldc_state.ib, std::string(this->name()) +"." "ib"); - sc_core::sc_trace(trf, bldc_state.ic, std::string(this->name()) +"." "ic"); - sc_core::sc_trace(trf, bldc_state.theta, std::string(this->name()) +"." "theta"); - sc_core::sc_trace(trf, bldc_state.omega, std::string(this->name()) +"." "omega"); - sc_core::sc_trace(trf, vout[0], std::string(this->name()) + "." "va"); - sc_core::sc_trace(trf, vout[1], std::string(this->name()) + "." "vb"); - sc_core::sc_trace(trf, vout[2], std::string(this->name()) + "." "vc"); - sc_core::sc_trace(trf, vout[3], std::string(this->name()) + "." "vcenter"); - sc_core::sc_trace(trf, vout[4], std::string(this->name()) + "." "ea"); - sc_core::sc_trace(trf, vout[5], std::string(this->name()) + "." "eb"); - sc_core::sc_trace(trf, vout[6], std::string(this->name()) + "." "ec"); -} - -void dc_motor::thread() { - const auto divider = 10.0; - wait(SC_ZERO_TIME); - std::array vin{0., 0., 0.}; - auto eval_model = [this](std::array vin, const sc_time step) -> std::array { - bldc_model.set_input(vin); - bldc_model.run(step.to_seconds()); - return bldc_model.get_voltages(); - }; - while (true) { - vin[0] = va_i.read(); - vin[1] = vb_i.read(); - vin[2] = vc_i.read(); - // auto sim_res=std::async(std::launch::async, eval_model, vin, step); - auto start = sc_time_stamp(); - wait(max_integ_step, va_i.value_changed_event() | vb_i.value_changed_event() | vc_i.value_changed_event()); - auto diff = sc_time_stamp() - start; - if (diff.to_seconds() >= bldc_model.dt) { - vout = eval_model(vin, diff); // sim_res.get(); - va_o = vout[0] / divider; - vb_o = vout[1] / divider; - vc_o = vout[2] / divider; - vcenter_o = vout[3] / divider; - } - } -} - -} /* namespace sysc */ diff --git a/platform/src/sysc/fe310.cpp b/platform/src/sysc/fe310.cpp deleted file mode 100644 index 1cab7e2..0000000 --- a/platform/src/sysc/fe310.cpp +++ /dev/null @@ -1,194 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/SiFive/fe310.h" - -namespace sysc { -using namespace sc_core; -using namespace SiFive; - -#ifdef HAS_VERILATOR -inline std::unique_ptr create_spi(sc_module_name nm, bool use_rtl) { - return use_rtl ? spi::create("i_qspi1") : spi::create("i_qspi1"); -} -#else -inline std::unique_ptr create_spi(sc_module_name nm, bool use_rtl) { - return spi::create("i_qspi1"); -} -#endif - -fe310::fe310(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, NAMED(pins_o, 32) -, NAMED(pins_i, 32) -, NAMED(erst_n) -, NAMED(use_rtl, false) -, NAMEDD(i_core_complex, core_complex) -, NAMEDD(i_router, scc::router<>, e300_plat_t_map.size() + 2, 1) -, NAMEDD(i_uart0, uart) -, NAMEDD(i_uart1, uart) -, NAMEDC(i_qspi0, spi, spi_impl::beh) -, i_qspi1(create_spi("i_qspi1", use_rtl)) -, NAMEDC(i_qspi2, spi, spi_impl::beh) -, NAMEDD(i_pwm0, pwm) -, NAMEDD(i_pwm1, pwm) -, NAMEDD(i_pwm2, pwm) -, NAMEDD(i_gpio0, gpio) -, NAMEDD(i_plic, plic) -, NAMEDD(i_aon, aon) -, NAMEDD(i_prci, prci) -, NAMEDD(i_clint, clint) -, NAMEDD(i_mem_qspi, mem_qspi_t) -, NAMEDD(i_mem_ram, mem_ram_t) -, NAMED(s_tlclk) -, NAMED(s_lfclk) -, NAMED(s_rst) -, NAMED(s_mtime_int) -, NAMED(s_msie_int) -, NAMED(s_global_int, 256) -, NAMED(s_local_int, 16) -, NAMED(s_core_int) -, NAMED(s_dummy_sck_i, 16) -, NAMED(s_dummy_sck_o, 16) { - i_core_complex->initiator(i_router->target[0]); - size_t i = 0; - for (const auto &e : e300_plat_t_map) { - i_router->initiator.at(i)(e.target); - i_router->set_target_range(i, e.start, e.size); - i++; - } - i_router->initiator.at(i)(i_mem_qspi->target); - i_router->set_target_range(i, 0x20000000, 512_MB); - i_router->initiator.at(++i)(i_mem_ram->target); - i_router->set_target_range(i, 0x80000000, 128_kB); - - i_uart0->clk_i(s_tlclk); - i_uart1->clk_i(s_tlclk); - i_qspi0->clk_i(s_tlclk); - i_qspi1->clk_i(s_tlclk); - i_qspi2->clk_i(s_tlclk); - i_pwm0->clk_i(s_tlclk); - i_pwm1->clk_i(s_tlclk); - i_pwm2->clk_i(s_tlclk); - i_gpio0->clk_i(s_tlclk); - i_plic->clk_i(s_tlclk); - i_aon->clk_i(s_tlclk); - i_aon->lfclkc_o(s_lfclk); - i_prci->hfclk_o(s_tlclk); // clock driver - i_clint->tlclk_i(s_tlclk); - i_clint->lfclk_i(s_lfclk); - i_core_complex->clk_i(s_tlclk); - - i_uart0->rst_i(s_rst); - i_uart1->rst_i(s_rst); - i_qspi0->rst_i(s_rst); - i_qspi1->rst_i(s_rst); - i_qspi2->rst_i(s_rst); - i_pwm0->rst_i(s_rst); - i_pwm1->rst_i(s_rst); - i_pwm2->rst_i(s_rst); - i_gpio0->rst_i(s_rst); - i_plic->rst_i(s_rst); - i_aon->rst_o(s_rst); - i_prci->rst_i(s_rst); - i_clint->rst_i(s_rst); - i_core_complex->rst_i(s_rst); - - i_aon->erst_n_i(erst_n); - - i_clint->mtime_int_o(s_mtime_int); - i_clint->msip_int_o(s_msie_int); - - i_plic->global_interrupts_i(s_global_int); - i_plic->core_interrupt_o(s_core_int); - - i_core_complex->sw_irq_i(s_msie_int); - i_core_complex->timer_irq_i(s_mtime_int); - i_core_complex->global_irq_i(s_core_int); - i_core_complex->local_irq_i(s_local_int); - - pins_i(i_gpio0->pins_i); - i_gpio0->pins_o(pins_o); - - i_gpio0->iof0_i[17](i_uart0->tx_o); - i_uart0->rx_i(i_gpio0->iof0_o[16]); - i_uart0->irq_o(s_global_int[3]); - - i_gpio0->iof0_i[5](i_qspi1->sck_o); - i_gpio0->iof0_i[3](i_qspi1->mosi_o); - i_qspi1->miso_i(i_gpio0->iof0_o[4]); - i_gpio0->iof0_i[2](i_qspi1->scs_o[0]); - i_gpio0->iof0_i[9](i_qspi1->scs_o[2]); - i_gpio0->iof0_i[10](i_qspi1->scs_o[3]); - - i_qspi0->irq_o(s_global_int[5]); - i_qspi1->irq_o(s_global_int[6]); - i_qspi2->irq_o(s_global_int[7]); - - s_dummy_sck_i[0](i_uart1->tx_o); - i_uart1->rx_i(s_dummy_sck_o[0]); - i_uart1->irq_o(s_global_int[4]); - - i_gpio0->iof1_i[0](i_pwm0->cmpgpio_o[0]); - i_gpio0->iof1_i[1](i_pwm0->cmpgpio_o[1]); - i_gpio0->iof1_i[2](i_pwm0->cmpgpio_o[2]); - i_gpio0->iof1_i[3](i_pwm0->cmpgpio_o[3]); - - i_gpio0->iof1_i[10](i_pwm2->cmpgpio_o[0]); - i_gpio0->iof1_i[11](i_pwm2->cmpgpio_o[1]); - i_gpio0->iof1_i[12](i_pwm2->cmpgpio_o[2]); - i_gpio0->iof1_i[13](i_pwm2->cmpgpio_o[3]); - - i_gpio0->iof1_i[19](i_pwm1->cmpgpio_o[0]); - i_gpio0->iof1_i[20](i_pwm1->cmpgpio_o[1]); - i_gpio0->iof1_i[21](i_pwm1->cmpgpio_o[2]); - i_gpio0->iof1_i[22](i_pwm1->cmpgpio_o[3]); - - i_pwm0->cmpip_o[0](s_global_int[40]); - i_pwm0->cmpip_o[1](s_global_int[41]); - i_pwm0->cmpip_o[2](s_global_int[42]); - i_pwm0->cmpip_o[3](s_global_int[43]); - - i_pwm1->cmpip_o[0](s_global_int[44]); - i_pwm1->cmpip_o[1](s_global_int[45]); - i_pwm1->cmpip_o[2](s_global_int[46]); - i_pwm1->cmpip_o[3](s_global_int[47]); - - i_pwm2->cmpip_o[0](s_global_int[48]); - i_pwm2->cmpip_o[1](s_global_int[49]); - i_pwm2->cmpip_o[2](s_global_int[50]); - i_pwm2->cmpip_o[3](s_global_int[51]); - - for (auto &sock : s_dummy_sck_i) sock.error_if_no_callback = false; -} - -} /* namespace sysc */ diff --git a/platform/src/sysc/gpio.cpp b/platform/src/sysc/gpio.cpp deleted file mode 100644 index 8c4f315..0000000 --- a/platform/src/sysc/gpio.cpp +++ /dev/null @@ -1,224 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/SiFive/gpio.h" -#include "scc/report.h" -#include "scc/utilities.h" -#include "sysc/SiFive/gen/gpio_regs.h" -#include "sysc/sc_comm_singleton.h" -#include - -namespace sysc { -using namespace sc_core; -using namespace sc_dt; - -gpio::gpio(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, tlm_target<>(clk) -, NAMED(clk_i) -, NAMED(rst_i) -, NAMED(pins_o, 32) -, NAMED(pins_i, 32) -, NAMED(iof0_o, 32) -, NAMED(iof1_o, 32) -, NAMED(iof0_i, 32) -, NAMED(iof1_i, 32) -, NAMEDD(regs, gpio_regs) -, NAMED(write_to_ws, false) { - regs->registerResources(*this); - SC_METHOD(clock_cb); - sensitive << clk_i; - SC_METHOD(reset_cb); - sensitive << rst_i; - dont_initialize(); - auto pins_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) -> tlm::tlm_sync_enum { - this->pin_input(tag, gp, delay); - return tlm::TLM_COMPLETED; - }; - auto i = 0U; - for (auto &s : pins_i) { - s.register_nb_transport(pins_i_cb, i); - ++i; - } - auto iof0_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) -> tlm::tlm_sync_enum { - last_iof0[tag] = gp.get_value(); - this->iof_input(tag, 0, gp, delay); - return tlm::TLM_COMPLETED; - }; - i = 0; - for (auto &s : iof0_i) { - s.register_nb_transport(iof0_i_cb, i); - ++i; - } - auto iof1_i_cb = [this](unsigned int tag, tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) -> tlm::tlm_sync_enum { - last_iof1[tag] = gp.get_value(); - this->iof_input(tag, 1, gp, delay); - return tlm::TLM_COMPLETED; - }; - i = 0; - for (auto &s : iof1_i) { - s.register_nb_transport(iof1_i_cb, i); - ++i; - } - auto update_pins_cb = [this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - if (!this->regs->in_reset()) { - auto changed_bits = (reg.get() ^ data); - reg.put(data); - update_pins(changed_bits); - } - return true; - }; - regs->port.set_write_cb(update_pins_cb); - regs->output_en.set_write_cb(update_pins_cb); - regs->out_xor.set_write_cb(update_pins_cb); - regs->iof_en.set_write_cb(update_pins_cb); - regs->iof_sel.set_write_cb(update_pins_cb); -} - -gpio::~gpio() = default; - -void gpio::before_end_of_elaboration() { - if (write_to_ws.get_value()) { - SCTRACE() << "Adding WS handler for " << (std::string{"/ws/"} + name()); - handler = std::make_shared(); - sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"} + name()).c_str(), handler); - } -} - -void gpio::reset_cb() { - if (rst_i.read()) { - regs->reset_start(); - } else { - regs->reset_stop(); - } - update_pins(std::numeric_limits::max()); -} - -void gpio::clock_cb() { this->clk = clk_i.read(); } - -tlm::tlm_phase gpio::write_output(tlm::tlm_signal_gp &gp, size_t i, sc_dt::sc_logic val) { - sc_core::sc_time delay{SC_ZERO_TIME}; - tlm::tlm_phase phase{tlm::BEGIN_REQ}; - gp.set_command(tlm::TLM_WRITE_COMMAND); - gp.set_response_status(tlm::TLM_OK_RESPONSE); - gp.set_value(val); - pins_o.at(i)->nb_transport_fw(gp, phase, delay); - return phase; -} - -void gpio::update_pins(uint32_t changed_bits) { - sc_core::sc_inout_rv<32>::data_type out_val; - tlm::tlm_signal_gp gp; - sc_logic val; - for (size_t i = 0, mask = 1; i < 32; ++i, mask <<= 1) { - if (changed_bits & mask) { - if ((regs->r_iof_en & mask != 0) && (iof0_i[i].size() == 0 || iof1_i[i].size() == 0)) { - if ((regs->r_iof_sel & mask) == 0 && iof0_i[i].size() > 0) { - val = last_iof0[i] ? sc_dt::Log_1 : sc_dt::Log_0; - } else if ((regs->r_iof_sel & mask) == 1 && iof1_i[i].size() > 0) - val = last_iof1[i] ? sc_dt::Log_1 : sc_dt::Log_0; - } else { - if (regs->r_output_en & mask) - val = regs->r_port & mask ? sc_dt::Log_1 : sc_dt::Log_0; - else - val = sc_dt::Log_Z; - if (regs->r_out_xor & mask) val = ~val; - } - tlm::tlm_phase phase = write_output(gp, i, val); - } - } -} - -void gpio::pin_input(unsigned int tag, tlm::tlm_signal_gp &gp, sc_core::sc_time &delay) { - if (delay > SC_ZERO_TIME) { - wait(delay); - delay = SC_ZERO_TIME; - } - auto mask = 1u << tag; - switch (gp.get_value().value()) { - case sc_dt::Log_1: - if (regs->r_output_en & mask == 0) regs->r_value |= mask; - forward_pin_input(tag, gp); - break; - case sc_dt::Log_0: - if (regs->r_output_en & mask == 0) regs->r_value &= ~mask; - forward_pin_input(tag, gp); - break; - } -} - -void gpio::forward_pin_input(unsigned int tag, tlm::tlm_signal_gp &gp) { - const auto mask = 1U << tag; - if (regs->iof_en & mask) { - auto &socket = regs->iof_sel & mask ? iof1_o[tag] : iof0_o[tag]; - tlm::tlm_signal_gp<> new_gp; - for (size_t i = 0; i < socket.size(); ++i) { - sc_core::sc_time delay{SC_ZERO_TIME}; - tlm::tlm_phase phase{tlm::BEGIN_REQ}; - new_gp.set_command(tlm::TLM_WRITE_COMMAND); - new_gp.set_response_status(tlm::TLM_OK_RESPONSE); - new_gp.set_value(gp.get_value().value() == sc_dt::Log_1); - new_gp.update_extensions_from(gp); - socket->nb_transport_fw(new_gp, phase, delay); // we don't care about phase and sync enum - } - } -} - -void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) { - if (delay > SC_ZERO_TIME) { - wait(delay); - delay = SC_ZERO_TIME; - } - const auto mask = 1U << tag; - if (regs->r_iof_en & mask) { - const auto idx = regs->r_iof_sel & mask ? 1 : 0; - if (iof_idx == idx) { - auto &socket = pins_o[tag]; - for (size_t i = 0; i < socket.size(); ++i) { - sc_core::sc_time delay{SC_ZERO_TIME}; - tlm::tlm_phase phase{tlm::BEGIN_REQ}; - tlm::tlm_signal_gp new_gp; - new_gp.set_command(tlm::TLM_WRITE_COMMAND); - auto val = gp.get_value(); - new_gp.set_value(val ? sc_dt::Log_1 : sc_dt::Log_0); - new_gp.copy_extensions_from(gp); - socket->nb_transport_fw(new_gp, phase, delay); // we don't care about phase and sync enum - gp.update_extensions_from(new_gp); - } - } - } -} - -} /* namespace sysc */ diff --git a/platform/src/sysc/h_bridge.cpp b/platform/src/sysc/h_bridge.cpp deleted file mode 100644 index 2007529..0000000 --- a/platform/src/sysc/h_bridge.cpp +++ /dev/null @@ -1,103 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/top/h_bridge.h" -#include "scc/utilities.h" -#include - -namespace sysc { -using namespace sc_core; -using namespace sc_dt; - -h_bridge::h_bridge(const sc_module_name &nm) -: sc_module(nm) -, NAMED(ha_i) -, NAMED(la_i) -, NAMED(hb_i) -, NAMED(lb_i) -, NAMED(hc_i) -, NAMED(lc_i) -, NAMED(va_o) -, NAMED(vb_o) -, NAMED(vc_o) -, NAMED(vcc, 48.0) { - SC_METHOD(ain_cb); - sensitive << ha_i << la_i; - SC_METHOD(bin_cb); - sensitive << hb_i << lb_i; - SC_METHOD(cin_cb); - sensitive << hc_i << lc_i; -} - -h_bridge::~h_bridge() = default; - -void h_bridge::ain_cb() { write_output(ha_i.read(), la_i.read(), va_o); } - -void h_bridge::bin_cb() { write_output(hb_i.read(), lb_i.read(), vb_o); } - -void h_bridge::cin_cb() { write_output(hc_i.read(), lc_i.read(), vc_o); } - -void h_bridge::write_output(sc_logic h_i, sc_logic l_i, sc_out &v_o) { - if (h_i == sc_dt::Log_1 && l_i == sc_dt::Log_0) - v_o.write(vcc); - else if (h_i == sc_dt::Log_0 && l_i == sc_dt::Log_1) - v_o.write(0.0); - else - v_o.write(nan("")); - /* - auto v = v_o.read(); - if(h_i==Log_1 && l_i==Log_0){ - if(isnan(v)){ - v_o.write(0.75*vcc); - next_trigger(2, SC_US); - } else - v_o.write(vcc); - } else if(h_i==Log_0 && l_i==Log_1){ - if(isnan(v)){ - v_o.write(0.25*vcc); - next_trigger(2, SC_US); - } else - v_o.write(0.0); - } else { - if(v_o.read()>0.8*vcc) { - v_o.write(0.75*vcc); - next_trigger(2, SC_US); - } else if(v_o.read()>0.8*vcc) { - v_o.write(0.25*vcc); - next_trigger(2, SC_US); - } else - v_o.write(nan("")); - } - */ -} - -} /* namespace sysc */ diff --git a/platform/src/sysc/hifive1.cpp b/platform/src/sysc/hifive1.cpp deleted file mode 100644 index 280f61e..0000000 --- a/platform/src/sysc/hifive1.cpp +++ /dev/null @@ -1,111 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include - -using namespace sc_core; -using namespace sc_dt; -using namespace sysc; - -hifive1::hifive1(sc_module_name nm) -: sc_module(nm) -, NAMED(erst_n) -, NAMED(vref_i) -#define PORT_NAMING(z, n, _) , NAMED(adc_ch##n##_i) -BOOST_PP_REPEAT(8, PORT_NAMING, _) -#undef PORT_NAMING -, NAMED(ha_o) -, NAMED(la_o) -, NAMED(hb_o) -, NAMED(lb_o) -, NAMED(hc_o) -, NAMED(lc_o) -, NAMED(s_gpio, 32) -, NAMED(h_bridge, 6) -, NAMED(i_fe310) -, NAMED(i_terminal) -, NAMED(i_adc) -{ - i_fe310.erst_n(erst_n); - for (auto i = 0U; i < s_gpio.size(); ++i) { - s_gpio[i].in(i_fe310.pins_o[i]); - i_fe310.pins_i[i](s_gpio[i].out); - } - // connect other units - // terminal - i_terminal.tx_o(s_gpio[16].in); - s_gpio[17].out(i_terminal.rx_i); - // adc digital io - s_gpio[2].out(i_adc.cs_i); - s_gpio[3].out(i_adc.mosi_i); - i_adc.miso_o(s_gpio[4].in); - s_gpio[5].out(i_adc.sck_i); - // adc analog inputs - i_adc.vref_i(vref_i); - i_adc.ch_i[0](adc_ch0_i); - i_adc.ch_i[1](adc_ch1_i); - i_adc.ch_i[2](adc_ch2_i); - i_adc.ch_i[3](adc_ch3_i); - i_adc.ch_i[4](adc_ch4_i); - i_adc.ch_i[5](adc_ch5_i); - i_adc.ch_i[6](adc_ch6_i); - i_adc.ch_i[7](adc_ch7_i); - // H-Bridge signal proxies - s_gpio[0].out(h_bridge[0]); - s_gpio[1].out(h_bridge[1]); - s_gpio[10].out(h_bridge[2]); - s_gpio[11].out(h_bridge[3]); - s_gpio[20].out(h_bridge[4]); - s_gpio[19].out(h_bridge[5]); - // proxy callbacks - h_bridge[0].register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum { - ha_o.write(gp.get_value()); - }); - h_bridge[1].register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum { - la_o.write(gp.get_value()); - }); - h_bridge[2].register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum { - hb_o.write(gp.get_value()); - }); - h_bridge[3].register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum { - lb_o.write(gp.get_value()); - }); - h_bridge[4].register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum { - hc_o.write(gp.get_value()); - }); - h_bridge[5].register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, sc_time &delay) -> tlm::tlm_sync_enum { - lc_o.write(gp.get_value()); - }); - - -} - diff --git a/platform/src/sysc/mcp_adc.cpp b/platform/src/sysc/mcp_adc.cpp deleted file mode 100644 index f21dad2..0000000 --- a/platform/src/sysc/mcp_adc.cpp +++ /dev/null @@ -1,202 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include -#include -#include - -namespace sysc { - - -mcp_3008::mcp_3008(sc_core::sc_module_name nm) -: sysc::mcp_adc(nm, 8) -, last_tx_start(sc_core::SC_ZERO_TIME) { - sck_i.register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) -> tlm::tlm_sync_enum { return tlm::TLM_COMPLETED; }); - - mosi_i.register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) -> tlm::tlm_sync_enum { - if (cs_v == sc_dt::Log_0) return receive(gp, phase, delay); - return tlm::TLM_COMPLETED; - }); - - cs_i.register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) -> tlm::tlm_sync_enum { - if (cs_v != sc_dt::Log_0 && gp.get_value() == sc_dt::Log_0) { - idx = 0; // falling edge - rx_bits = 0; - } - cs_v = gp.get_value(); - return tlm::TLM_COMPLETED; - }); -} - -tlm::tlm_sync_enum mcp_3008::receive(tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) { - gp.get_extension(ext); - if (ext) { - if (ext->start_time != last_tx_start) { - assert(ext->tx.data_bits == 8); - rx_bytes[idx] = bit_sub<0, 8>(ext->tx.m2s_data); - if (idx == 1) do_conversion(); - ext->tx.s2m_data = tx_bytes[idx]; - ext->tx.s2m_data_valid = true; - idx++; - last_tx_start = ext->start_time; - } - } - return tlm::TLM_COMPLETED; -} - -void mcp_3008::do_conversion() { - if (rx_bytes[0] == 0x1) { - auto mode = bit_sub<7, 1>(rx_bytes[1]); - auto channel = bit_sub<4, 3>(rx_bytes[1]); - auto vref = vref_i.read(); - if (mode) { // single ended - auto inp = ch_i[channel].read(); - auto norm = 1024.0 * inp / vref; - auto res = static_cast(norm); - SCDEBUG(this->name()) << "Converting " << inp << " to " << norm << " as int " << res; - tx_bytes[1] = bit_sub<8, 2>(res); - tx_bytes[2] = bit_sub<0, 8>(res); - } else { - tx_bytes[1] = 0; - tx_bytes[2] = 0; - } - } -} - -mcp_3208::mcp_3208(sc_core::sc_module_name nm) -: sysc::mcp_adc(nm, 8) -, ext(nullptr) -, last_tx_start(sc_core::SC_ZERO_TIME) { - sck_i.register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) -> tlm::tlm_sync_enum { - auto ret = tlm::TLM_COMPLETED; - if (cs_v == sc_dt::Log_0) ret = receive(gp, phase, delay); - sck_v = gp.get_value(); - return ret; - }); - - mosi_i.register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) -> tlm::tlm_sync_enum { - mosi_v = gp.get_value(); - return tlm::TLM_COMPLETED; - }); - - cs_i.register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) -> tlm::tlm_sync_enum { - if (cs_v != sc_dt::Log_0 && gp.get_value() == sc_dt::Log_0) { // falling edge of CS - idx = 0; - rx_bits = byte_offs = 0; - bit_offs = 7; - } - cs_v = gp.get_value(); - return tlm::TLM_COMPLETED; - }); - SC_METHOD(sample_inputs); - sensitive << clk_sample_evt; -} - -tlm::tlm_sync_enum mcp_3208::receive(tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) { - gp.get_extension(ext); - if (ext) { - if (ext->start_time != last_tx_start) { - assert(ext->tx.data_bits == 8); - if (ext->tx.m2s_data_valid) { - rx_bytes[idx] = bit_sub<0, 8>(ext->tx.m2s_data); - if (idx == 1) do_conversion(); - ext->tx.s2m_data = tx_bytes[idx]; - ext->tx.s2m_data_valid = true; - last_tx_start = ext->start_time; - idx++; - } - } - } else if (gp.get_value() == sc_dt::SC_LOGIC_1 && sck_v == sc_dt::SC_LOGIC_0) // sample an rising edge - clk_sample_evt.notify(sc_core::SC_ZERO_TIME); - return tlm::TLM_COMPLETED; -} - -void mcp_3208::sample_inputs() { - if (byte_offs >= 3) return; - if (bit_offs == 7) { - rx_bytes[byte_offs] = 0; - if (byte_offs == 0) tx_bytes[0] = tx_bytes[1] = tx_bytes[2] = 0; - } - auto mask = 1 << bit_offs; - if (mosi_v == sc_dt::SC_LOGIC_1) rx_bytes[byte_offs] |= mask; - miso_o.write_now(tx_bytes[byte_offs] & mask ? sc_dt::SC_LOGIC_1 : sc_dt::SC_LOGIC_0); - // increment counters - if (bit_offs == 0) { - bit_offs = 7; - byte_offs++; - } else - bit_offs--; - // sample if in the middle of second byte - if (byte_offs == 1 && bit_offs == 4) do_conversion(); -} - -void mcp_3208::do_conversion() { - if (rx_bytes[0] & 0x4) { - auto mode = bit_sub<1, 1>(rx_bytes[0]); - auto channel = bit_sub<0, 1>(rx_bytes[0]) * 4 + bit_sub<6, 2>(rx_bytes[1]); - auto vref = vref_i.read(); - if (mode) { // single ended - auto inp = ch_i[channel].read(); - auto norm = 4096.0 * inp / vref; - auto res = static_cast(norm); - SCDEBUG(this->name()) << "Converting channel " << channel << " " << inp << "V to " << norm << " as int " - << res; - tx_bytes[1] = bit_sub<8, 4>(res); - tx_bytes[2] = bit_sub<0, 8>(res); - } else { - tx_bytes[1] = 0; - tx_bytes[2] = 0; - } - } -} - -template <> -std::unique_ptr mcp_adc::create(sc_core::sc_module_name nm) { - auto *res = new mcp_3008(nm); - return std::unique_ptr(res); -} - -template <> -std::unique_ptr mcp_adc::create(sc_core::sc_module_name nm) { - auto *res = new mcp_3208(nm); - return std::unique_ptr(res); -} - -} /* namespace sysc */ diff --git a/platform/src/sysc/plic.cpp b/platform/src/sysc/plic.cpp deleted file mode 100644 index 589b2b3..0000000 --- a/platform/src/sysc/plic.cpp +++ /dev/null @@ -1,170 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include - -#include -#include -#include - -namespace sysc { - -plic::plic(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, tlm_target<>(clk) -, NAMED(clk_i) -, NAMED(rst_i) -, NAMED(global_interrupts_i, 256) -, NAMED(core_interrupt_o) -, NAMEDD(regs, plic_regs) - -{ - regs->registerResources(*this); - // register callbacks - regs->claim_complete.set_write_cb([this](scc::sc_register& reg, const uint32_t& v, sc_core::sc_time d) -> bool { - reg.put(v); - reset_pending_int(v); - // std::cout << "Value of register: 0x" << std::hex << reg << std::endl; - // todo: reset related interrupt and find next high-prio interrupt - return true; - }); - - // port callbacks - SC_METHOD(global_int_port_cb); - for (uint8_t i = 0; i < 255; i++) { - sensitive << global_interrupts_i[i].pos(); - } - dont_initialize(); - - // register event callbacks - SC_METHOD(clock_cb); - sensitive << clk_i; - SC_METHOD(reset_cb); - sensitive << rst_i; - dont_initialize(); -} - -plic::~plic() {}// NOLINT - -void plic::clock_cb() { this->clk = clk_i.read(); } - -void plic::reset_cb() { - if (rst_i.read()) - regs->reset_start(); - else - regs->reset_stop(); -} - -// Functional handling of interrupts: -// - global_int_port_cb() -// - set pending register bits -// - called by: incoming global_int -// - handle_pending_int() -// - update claim register content -// - generate core-interrupt pulse -// - called by: -// - incoming global_int -// - complete-register write access -// - reset_pending_int(int-id) -// - reset pending bit -// - call next handle_pending_int() -// - called by: -// - complete-reg write register content - -void plic::global_int_port_cb() { - auto handle_pending = false; - // set related pending bit if enable is set for incoming global_interrupt - for (uint32_t i = 1; i < 256; i++) { - auto reg_idx = i >> 5; - auto bit_ofs = i & 0x1F; - bool enable = regs->r_enabled[reg_idx] & (0x1 << bit_ofs); // read enable bit - - if (enable && global_interrupts_i[i].read() == 1) { - regs->r_pending[reg_idx] = regs->r_pending[reg_idx] | (0x1 << bit_ofs); - handle_pending = true; - SCDEBUG(this->name()) << "pending interrupt identified: " << i; - } - } - - if (handle_pending) handle_pending_int(); -} - -void plic::handle_pending_int() { - // identify high-prio pending interrupt and raise a core-interrupt - auto claim_int = 0U; // claim interrupt - auto claim_prio = 0U; // related priority (highest prio interrupt wins the race) - auto raise_int = false; - auto thold = regs->r_threshold.threshold; // threshold value - - for (size_t i = 1; i < 255; i++) { - auto reg_idx = i >> 5; - auto bit_ofs = i & 0x1F; - bool pending = (regs->r_pending[reg_idx] & (0x1 << bit_ofs)) ? true : false; - auto prio = regs->r_priority[i].priority; // read priority value - - if (pending && thold < prio) { - // below condition ensures implicitly that lowest id is selected in case of multiple identical - // priority-interrupts - if (prio > claim_prio) { - claim_prio = prio; - claim_int = i; - raise_int = true; - SCDEBUG(this->name()) << "pending interrupt activated: " << i; - } - } - } - - if (raise_int) { - regs->r_claim_complete = claim_int; - core_interrupt_o.write(true); - // todo: evluate clock period - } else { - regs->r_claim_complete = 0; - SCDEBUG(this->name()) << "no further pending interrupt."; - } -} - -void plic::reset_pending_int(uint32_t irq) { - // todo: evaluate enable register (see spec) - // todo: make sure that pending is set, otherwise don't reset irq ... read spec. - SCTRACE(this->name()) << "reset pending interrupt: " << irq; - // reset related pending bit - auto reg_idx = irq >> 5; - auto bit_ofs = irq & 0x1F; - regs->r_pending[reg_idx] &= ~(0x1 << bit_ofs); - core_interrupt_o.write(false); - - // evaluate next pending interrupt - handle_pending_int(); -} - -} /* namespace sysc */ diff --git a/platform/src/sysc/prci.cpp b/platform/src/sysc/prci.cpp deleted file mode 100644 index 71a24a3..0000000 --- a/platform/src/sysc/prci.cpp +++ /dev/null @@ -1,143 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/SiFive/prci.h" - -#include "scc/utilities.h" -#include "sysc/SiFive/gen/prci_regs.h" - -namespace sysc { -using namespace sc_core; - -prci::prci(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, tlm_target<>(hfclk) -, NAMED(rst_i) -, NAMED(hfclk_o) -, NAMEDD(regs, prci_regs) { - regs->registerResources(*this); - SC_METHOD(reset_cb); - sensitive << rst_i; - dont_initialize(); - SC_METHOD(hfxosc_cb); - sensitive << hfxosc_i; - SC_METHOD(hfrosc_en_cb); - sensitive << hfrosc_en_evt; - dont_initialize(); - - regs->hfxosccfg.set_write_cb([this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - reg.put(data); - if (this->regs->r_hfxosccfg.hfxoscen == 1) { // check rosc_en - this->hfxosc_en_evt.notify(1, sc_core::SC_US); - } else { - this->hfxosc_en_evt.notify(SC_ZERO_TIME); - } - return true; - }); - regs->hfrosccfg.set_write_cb([this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - reg.put(data); - if (this->regs->r_hfrosccfg.hfroscen == 1) { // check rosc_en - this->hfrosc_en_evt.notify(1, sc_core::SC_US); - } else { - this->hfrosc_en_evt.notify(SC_ZERO_TIME); - } - return true; - }); - regs->pllcfg.set_write_cb([this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - reg.put(data); - auto &pllcfg = this->regs->r_pllcfg; - if (pllcfg.pllbypass == 0 && pllcfg.pllq != 0) { // set pll_lock if pll is selected - pllcfg.plllock = 1; - } - update_hfclk(); - return true; - }); - regs->plloutdiv.set_write_cb([this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - reg.put(data); - update_hfclk(); - return true; - }); - hfxosc_clk = 62.5_ns; -} - -prci::~prci() = default; - -void prci::reset_cb() { - if (rst_i.read()) - regs->reset_start(); - else { - regs->reset_stop(); - this->hfxosc_en_evt.notify(1, sc_core::SC_US); - } -} - -void prci::hfxosc_cb() { - this->regs->r_hfxosccfg.hfxoscrdy = 0; - this->hfxosc_en_evt.notify(1, sc_core::SC_US); -} - -void prci::hfxosc_en_cb() { - update_hfclk(); - if (regs->r_hfxosccfg.hfxoscen == 1) // set rosc_rdy - regs->r_hfxosccfg.hfxoscrdy = 1; - else - regs->r_hfxosccfg.hfxoscrdy = 0; -} - -void prci::hfrosc_en_cb() { - update_hfclk(); - auto &hfrosccfg = regs->r_hfrosccfg; - if (regs->r_hfrosccfg.hfroscen == 1) { // set rosc_rdy - regs->r_hfrosccfg.hfroscrdy = 1; - } else { - regs->r_hfrosccfg.hfroscrdy = 0; - } -} - -void prci::update_hfclk() { - auto &hfrosccfg = regs->r_hfrosccfg; - auto &pllcfg = regs->r_pllcfg; - auto &plldiv = regs->r_plloutdiv; - uint32_t trim = hfrosccfg.hfrosctrim; - uint32_t div = hfrosccfg.hfroscdiv; - hfrosc_clk = sc_core::sc_time(((div + 1) * 1.0) / (70000000 + 12000.0 * trim), sc_core::SC_SEC); - auto pll_ref = pllcfg.pllrefsel == 1 ? hfxosc_clk : hfrosc_clk; - auto r = pllcfg.pllr + 1; - auto f = 2 * (pllcfg.pllf + 1); - auto q = 1 << pllcfg.pllq; - auto pll_out = pllcfg.pllbypass == 1 || pllcfg.plllock == 0 ? pll_ref : ((pll_ref * r) / f) * q; - auto pll_res = plldiv & 0x100 ? pll_out : 2 * pll_out * ((plldiv & 0x3f) + 1); - hfclk = pllcfg.pllsel ? pll_res : hfrosc_clk; - hfclk_o.write(hfclk); -} - -} /* namespace sysc */ diff --git a/platform/src/sysc/pwm.cpp b/platform/src/sysc/pwm.cpp deleted file mode 100644 index fc741f4..0000000 --- a/platform/src/sysc/pwm.cpp +++ /dev/null @@ -1,231 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/SiFive/pwm.h" - -#include "scc/utilities.h" -#include "sysc/SiFive/gen/pwm_regs.h" - -using namespace sysc; -using namespace sc_core; - -pwm::pwm(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, tlm_target<>(clk) -, NAMED(clk_i) -, NAMED(rst_i) -, NAMED(cmpgpio_o, 4) -, NAMED(cmpip_o, 4) -, NAMEDD(regs, pwm_regs) -, current_cnt(0) -, last_cnt_update() { - regs->registerResources(*this); - - regs->pwmcfg.set_write_cb( - [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { - if (d.value()) wait(d); - reg.put(data); - update_counter(); - return true; - }); - regs->pwmcount.set_write_cb( - [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { - if (d.value()) wait(d); - reg.put(data); - update_counter(); - current_cnt = data; - clk_remainder = 0.; - return true; - }); - regs->pwmcount.set_read_cb([this](const scc::sc_register ®, uint32_t &data, - sc_core::sc_time d) -> bool { - auto offset = regs->r_pwmcfg.pwmenalways || regs->r_pwmcfg.pwmenoneshot ? static_cast(get_pulses(d)) : 0; - data = current_cnt + offset; - regs->r_pwmcount.pwmcount = data; - return true; - }); - regs->pwms.set_write_cb( - [this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { return false; }); - regs->pwms.set_read_cb([this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { - auto offset = regs->r_pwmcfg.pwmenalways || regs->r_pwmcfg.pwmenoneshot ? static_cast(get_pulses(d)) : 0; - auto cnt = current_cnt + offset; - data = (cnt >> regs->r_pwmcfg.pwmscale) & 0xffff; - regs->r_pwms.pwms = static_cast(data); - return true; - }); - regs->pwmcmp0.set_write_cb( - [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { - reg.put(data); - update_counter(); - return true; - }); - regs->pwmcmp1.set_write_cb( - [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { - reg.put(data); - update_counter(); - return true; - }); - regs->pwmcmp2.set_write_cb( - [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { - reg.put(data); - update_counter(); - return true; - }); - regs->pwmcmp3.set_write_cb( - [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { - reg.put(data); - update_counter(); - return true; - }); - - SC_METHOD(clock_cb); - sensitive << clk_i; - SC_METHOD(reset_cb); - sensitive << rst_i; - SC_METHOD(update_counter); - sensitive << update_counter_evt; - dont_initialize(); -} - -void pwm::clock_cb() { - update_counter(); - clk = clk_i.read(); -} - -pwm::~pwm() = default; - -void pwm::reset_cb() { - if (rst_i.read()) { - regs->reset_start(); - } else { - regs->reset_stop(); - } -} - -void pwm::update_counter() { - auto now = sc_time_stamp(); - if (now == SC_ZERO_TIME) return; - update_counter_evt.cancel(); - if (regs->r_pwmcfg.pwmenalways || regs->r_pwmcfg.pwmenoneshot) { - std::array pwmcmp_new_ip{false, false, false, false}; - auto dpulses = get_pulses(SC_ZERO_TIME); - auto pulses = static_cast(dpulses); - clk_remainder += dpulses - pulses; - if (clk_remainder > 1) { - pulses++; - clk_remainder -= 1.0; - } - if (reset_cnt) { - current_cnt = 0; - reset_cnt = false; - } else if (last_enable) - current_cnt += pulses; - auto pwms = (current_cnt >> regs->r_pwmcfg.pwmscale) & 0xffff; - auto next_trigger_time = - (0xffff - pwms) * (1 << regs->r_pwmcfg.pwmscale) * clk; // next trigger based on wrap around - if (pwms == 0xffff) { // wrap around calculation - reset_cnt = true; - next_trigger_time = clk; - regs->r_pwmcfg.pwmenoneshot = 0; - } - auto pwms0 = (regs->r_pwmcfg.pwmcmp0center && (pwms & 0x8000) == 1) ? pwms ^ 0xffff : pwms; - if (pwms0 >= regs->r_pwmcmp0.pwmcmp0) { - pwmcmp_new_ip[0] = true; - regs->r_pwmcfg.pwmenoneshot = 0; - if (regs->r_pwmcfg.pwmzerocmp) { - reset_cnt = true; - next_trigger_time = clk; - } - } else { - pwmcmp_new_ip[0] = false; - // TODO: add correct calculation for regs->r_pwmcfg.pwmcmpXcenter==1 - auto nt = (regs->r_pwmcmp0.pwmcmp0 - pwms0) * (1 << regs->r_pwmcfg.pwmscale) * clk; - next_trigger_time = nt < next_trigger_time ? nt : next_trigger_time; - } - auto pwms1 = (regs->r_pwmcfg.pwmcmp0center && (pwms & 0x8000) == 1) ? pwms ^ 0xffff : pwms; - if (pwms1 >= regs->r_pwmcmp1.pwmcmp0) { - pwmcmp_new_ip[1] = true; - } else { - pwmcmp_new_ip[1] = false; - // TODO: add correct calculation for regs->r_pwmcfg.pwmcmpXcenter==1 - auto nt = (regs->r_pwmcmp0.pwmcmp0 - pwms0) * (1 << regs->r_pwmcfg.pwmscale) * clk; - next_trigger_time = nt < next_trigger_time ? nt : next_trigger_time; - } - auto pwms2 = (regs->r_pwmcfg.pwmcmp0center && (pwms & 0x8000) == 1) ? pwms ^ 0xffff : pwms; - if (pwms2 >= regs->r_pwmcmp2.pwmcmp0) { - pwmcmp_new_ip[2] = true; - } else { - pwmcmp_new_ip[2] = false; - // TODO: add correct calculation for regs->r_pwmcfg.pwmcmpXcenter==1 - auto nt = (regs->r_pwmcmp0.pwmcmp0 - pwms0) * regs->r_pwmcfg.pwmscale * clk; - next_trigger_time = nt < next_trigger_time ? nt : next_trigger_time; - } - auto pwms3 = (regs->r_pwmcfg.pwmcmp0center && (pwms & 0x8000) == 1) ? pwms ^ 0xffff : pwms; - if (pwms3 >= regs->r_pwmcmp3.pwmcmp0) { - pwmcmp_new_ip[3] = true; - } else { - pwmcmp_new_ip[3] = false; - // TODO: add correct calculation for regs->r_pwmcfg.pwmcmpXcenter==1 - auto nt = (regs->r_pwmcmp0.pwmcmp0 - pwms0) * (1 << regs->r_pwmcfg.pwmscale) * clk; - next_trigger_time = nt < next_trigger_time ? nt : next_trigger_time; - } - for (size_t i = 0; i < 4; ++i) { - // write gpio bits depending of gang bit - if (regs->r_pwmcfg & (1 < (24 + i))) - write_cmpgpio(i, pwmcmp_new_ip[i] && !pwmcmp_new_ip[(i + 1) % 4]); - else - write_cmpgpio(i, pwmcmp_new_ip[i]); - // detect rising edge and set ip bit if found - if (!pwmcmp_ip[i] && pwmcmp_new_ip[i]) regs->r_pwmcfg |= 1 << (28 + i); - pwmcmp_ip[i] = pwmcmp_new_ip[i]; - } - last_enable = true; - update_counter_evt.notify(next_trigger_time); - } else - last_enable = false; - cmpip_o[0].write(regs->r_pwmcfg.pwmcmp0ip != 0); - cmpip_o[1].write(regs->r_pwmcfg.pwmcmp1ip != 0); - cmpip_o[2].write(regs->r_pwmcfg.pwmcmp2ip != 0); - cmpip_o[3].write(regs->r_pwmcfg.pwmcmp3ip != 0); - last_cnt_update = now; - last_clk = clk; -} - -void pwm::write_cmpgpio(size_t index, bool val) { - if (cmpgpio_o[index].get_interface()) { - tlm::tlm_phase phase(tlm::BEGIN_REQ); - tlm::tlm_signal_gp<> gp; - sc_core::sc_time delay(SC_ZERO_TIME); - gp.set_value(val); - cmpgpio_o[index]->nb_transport_fw(gp, phase, delay); - } -} diff --git a/platform/src/sysc/sc_comm_singleton.cpp b/platform/src/sysc/sc_comm_singleton.cpp deleted file mode 100644 index 1832126..0000000 --- a/platform/src/sysc/sc_comm_singleton.cpp +++ /dev/null @@ -1,169 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/sc_comm_singleton.h" - -#include "seasocks/PrintfLogger.h" -#include "seasocks/ResponseWriter.h" -#include "seasocks/Server.h" -#include "seasocks/StringUtil.h" -#include "seasocks/util/CrackedUriPageHandler.h" -#include "seasocks/util/Json.h" -#include "seasocks/util/RootPageHandler.h" -#include "seasocks/util/StaticResponseHandler.h" - -#include -#include -#include -#include -#include -#include - -namespace sysc { - -using namespace seasocks; -using namespace std; - -namespace { -inline void die() { - perror(nullptr); - exit(errno); -} -} - -sc_comm_singleton::sc_comm_singleton(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, m_serv(new Server(std::make_shared(Logger::Level::WARNING))) -, needs_client(false) -, client_started(false) { - m_serv->addPageHandler(std::make_shared(*this)); -} - -sc_comm_singleton::~sc_comm_singleton() { - // Join the thread with the main thread - t.join(); -} - -void sc_comm_singleton::start_of_simulation() { - // Launch a thread - t = std::thread(&sc_comm_singleton::thread_func, this); - if (needs_client) start_client(); -} - -void sc_comm_singleton::end_of_simulation() { get_server().terminate(); } - -void sc_comm_singleton::start_client() { - if (client_started) return; - std::stringstream ss; -#ifndef WIN32 - if (fork() == 0) { - // daemonizing, see http://www.microhowto.info/howto/cause_a_process_to_become_a_daemon_in_c.html#id2407077 - // Fork, allowing the parent process to terminate. - pid_t pid = fork(); - if (pid == -1) { - die(); - } else if (pid != 0) { - _exit(0); - } - // Start a new session for the daemon. - if (setsid() == -1) die(); - // Fork again, allowing the parent process to terminate. - signal(SIGHUP, SIG_IGN); - pid = fork(); - if (pid == -1) { - die(); - } else if (pid != 0) { - _exit(0); - } - // Set the current working directory to the root directory. - if (chdir("/") == -1) die(); - // Set the user file creation mask to zero. - umask(0); - - // Close then reopen standard file descriptors. - close(STDIN_FILENO); - close(STDOUT_FILENO); - close(STDERR_FILENO); - if (open("/dev/null", O_RDONLY) == -1) die(); - if (open("/dev/null", O_WRONLY) == -1) die(); - if (open("/dev/null", O_RDWR) == -1) die(); - // now do what is needed - ss << "x-www-browser http://localhost:9090/ws.html"; // Linux - auto res = system(ss.str().c_str()); - if (res == 0) exit(0); - ss.str(""); - ss << "xdg-open http://localhost:9090/ws.html"; // Linux - res = system(ss.str().c_str()); - if (res == 0) exit(0); - ss.str(""); - ss << "open http://localhost:9090/ws.html"; // MacOS - res = system(ss.str().c_str()); - exit(0); - } -// #else -// on windows should be open, see https://www.experts-exchange.com/articles/1595/Execute-a-Program-with-C.html -#endif - client_started = true; -} - -void sc_comm_singleton::registerWebSocketHandler(const char *endpoint, std::shared_ptr handler, - bool allowCrossOriginRequests) { - get_server().addWebSocketHandler(endpoint, handler, allowCrossOriginRequests); - endpoints.emplace_back(endpoint); - needs_client = true; -} - -void sc_comm_singleton::execute(std::function f) { get_server().execute(f); } - -void sc_comm_singleton::thread_func() { get_server().serve("./html", 9090); } - -Server &sc_comm_singleton::get_server() { return *m_serv.get(); } - -std::shared_ptr sc_comm_singleton::DefaultPageHandler::handle(const Request &request) { - if (request.verb() == Request::Verb::Get && request.getRequestUri() == "conf.json") { - return Response::htmlResponse("{}"); - } - return Response::unhandled(); -} - -void WsHandler::onConnect(WebSocket *connection) { _connections.insert(connection); } - -void WsHandler::onData(WebSocket *connection, const char *data) { - if (0 == strcmp("close", data)) { - connection->close(); - } else if (callback) - callback(data); -} - -void WsHandler::onDisconnect(WebSocket *connection) { _connections.erase(connection); } - -} /* namespace sysc */ diff --git a/platform/src/sysc/spi.cpp b/platform/src/sysc/spi.cpp deleted file mode 100644 index 8c579c0..0000000 --- a/platform/src/sysc/spi.cpp +++ /dev/null @@ -1,271 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/SiFive/spi.h" -#include "cci_configuration" -#include "scc/signal_initiator_mixin.h" -#include "scc/signal_target_mixin.h" -#include "scc/tlm_target.h" - -#include "scc/utilities.h" -#include "sysc/SiFive/gen/spi_regs.h" -#include "sysc/tlm_extensions.h" -#include - -namespace sysc { -namespace spi_impl { -using namespace sc_core; - -class beh : public sysc::spi, public scc::tlm_target<> { -public: - SC_HAS_PROCESS(beh); // NOLINT - - cci::cci_param bit_true_transfer; - - beh(sc_core::sc_module_name nm); - ~beh() override; - -protected: - scc::tlm_signal_bool_opt_out _sck_o; - scc::tlm_signal_bool_opt_out _mosi_o; - scc::tlm_signal_bool_opt_in _miso_i; - sc_core::sc_vector _scs_o; - - void clock_cb(); - void reset_cb(); - void transmit_data(); - void receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay); - void update_irq(); - sc_core::sc_event update_irq_evt; - sc_core::sc_time clk; - std::unique_ptr regs; - sc_core::sc_fifo rx_fifo, tx_fifo; -}; - -beh::beh(sc_core::sc_module_name nm) -: sysc::spi(nm) -, tlm_target<>(clk) -, NAMED(_sck_o) -, NAMED(_mosi_o) -, NAMED(_miso_i) -, NAMED(_scs_o, 4) -, NAMED(bit_true_transfer, false) -, NAMEDD(regs, spi_regs) -, rx_fifo(8) -, tx_fifo(8) { - spi::socket(scc::tlm_target<>::socket); - _sck_o(sck_o); - _mosi_o(mosi_o); - miso_i(_miso_i); - _scs_o(scs_o); - - regs->registerResources(*this); - SC_METHOD(clock_cb); - sensitive << clk_i; - SC_METHOD(reset_cb); - sensitive << rst_i; - dont_initialize(); - SC_THREAD(transmit_data); - _miso_i.register_nb_transport( - [this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum { - this->receive_data(gp, delay); - return tlm::TLM_COMPLETED; - }); - regs->txdata.set_write_cb([this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - if (!this->regs->in_reset()) { - reg.put(data); - tx_fifo.nb_write(static_cast(regs->r_txdata.data)); - } - return true; - }); - regs->rxdata.set_read_cb([this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { - if (!this->regs->in_reset()) { - uint8_t val; - if (rx_fifo.nb_read(val)) { - regs->r_rxdata.empty = 0; - regs->r_rxdata.data = val; - if (regs->r_rxmark.rxmark <= rx_fifo.num_available()) { - regs->r_ip.rxwm = 1; - update_irq(); - } - } else - regs->r_rxdata.empty = 1; - data = reg.get() & reg.rdmask; - } - return true; - }); - regs->csmode.set_write_cb( - [this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { - if (regs->r_csmode.mode == 2 && regs->r_csmode.mode != bit_sub<0, 2>(data) && regs->r_csid < 4) { - tlm::tlm_phase phase(tlm::BEGIN_REQ); - sc_core::sc_time delay(SC_ZERO_TIME); - tlm::tlm_signal_gp<> gp; - gp.set_command(tlm::TLM_WRITE_COMMAND); - gp.set_value(true); - _scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay); - } - reg.put(data); - return true; - }); - regs->csid.set_write_cb([this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { - if (regs->r_csmode.mode == 2 && regs->csid != data && regs->r_csid < 4) { - tlm::tlm_phase phase(tlm::BEGIN_REQ); - sc_core::sc_time delay(SC_ZERO_TIME); - tlm::tlm_signal_gp<> gp; - gp.set_command(tlm::TLM_WRITE_COMMAND); - gp.set_value(true); - _scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay); - } - reg.put(data); - return true; - }); - regs->csdef.set_write_cb([this](const scc::sc_register ®, const uint32_t &data, sc_core::sc_time d) -> bool { - auto diff = regs->csdef ^ data; - if (regs->r_csmode.mode == 2 && diff != 0 && (regs->r_csid < 4) && (diff & (1 << regs->r_csid)) != 0) { - tlm::tlm_phase phase(tlm::BEGIN_REQ); - sc_core::sc_time delay(SC_ZERO_TIME); - tlm::tlm_signal_gp<> gp; - gp.set_command(tlm::TLM_WRITE_COMMAND); - gp.set_value(true); - _scs_o[regs->r_csid]->nb_transport_fw(gp, phase, delay); - } - reg.put(data); - return true; - }); - regs->ie.set_write_cb([this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - reg.put(data); - update_irq_evt.notify(); - return true; - }); - regs->ip.set_write_cb([this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - reg.put(data); - update_irq_evt.notify(); - return true; - }); - - SC_METHOD(update_irq); - sensitive << update_irq_evt << rx_fifo.data_written_event() << rx_fifo.data_read_event() - << tx_fifo.data_written_event() << tx_fifo.data_read_event(); -} - -beh::~beh() = default; - -void beh::clock_cb() { this->clk = clk_i.read(); } - -void beh::reset_cb() { - if (rst_i.read()) - regs->reset_start(); - else - regs->reset_stop(); -} - -void beh::transmit_data() { - uint8_t txdata; - tlm::tlm_phase phase(tlm::BEGIN_REQ); - sc_core::sc_time delay(SC_ZERO_TIME); - sc_core::sc_time bit_duration(SC_ZERO_TIME); - sc_core::sc_time start_time; - - auto set_bit = [&](bool val, scc::tlm_signal_bool_opt_out &socket, - bool data_valid = false) -> std::pair { - if (socket.get_interface() == nullptr) return std::pair{false, 0}; - auto *gp = tlm::tlm_signal_gp<>::create(); - auto *ext = new sysc::tlm_signal_spi_extension(); - ext->tx.data_bits = 8; - ext->start_time = start_time; - ext->tx.m2s_data = txdata; - ext->tx.m2s_data_valid = data_valid; - ext->tx.s2m_data_valid = false; - gp->set_extension(ext); - gp->set_command(tlm::TLM_WRITE_COMMAND); - gp->set_value(val); - tlm::tlm_phase phase(tlm::BEGIN_REQ); - gp->acquire(); - phase = tlm::BEGIN_REQ; - delay = SC_ZERO_TIME; - socket->nb_transport_fw(*gp, phase, delay); - std::pair ret{ext->tx.s2m_data_valid != 0, ext->tx.s2m_data}; - gp->release(); - return ret; - }; - - wait(delay); // intentionally 0ns; - while (true) { - wait(tx_fifo.data_written_event()); - if (regs->r_csmode.mode != 3 && regs->r_csid < 4) // not in OFF mode - set_bit(false, _scs_o[regs->r_csid]); - set_bit(regs->r_sckmode.pol, _sck_o); - while (tx_fifo.nb_read(txdata)) { - regs->r_txdata.full = tx_fifo.num_free() == 0; - regs->r_ip.txwm = regs->r_txmark.txmark <= (7 - tx_fifo.num_free()) ? 1 : 0; - update_irq_evt.notify(); - bit_duration = 2 * (regs->r_sckdiv.div + 1) * clk; - start_time = sc_core::sc_time_stamp(); - set_bit(txdata & 0x80, _mosi_o); // 8 data bits, MSB first - auto s2m = set_bit(1 - regs->r_sckmode.pol, _sck_o, true); - wait(bit_duration / 2); - set_bit(regs->r_sckmode.pol, _sck_o, true); - wait(bit_duration / 2); - if (bit_true_transfer.get_value()) { - for (size_t i = 0, mask = 0x40; i < 7; ++i, mask >= 1) { - set_bit(txdata & mask, _mosi_o); // 8 data bits, MSB first - set_bit(1 - regs->r_sckmode.pol, _sck_o); - wait(bit_duration / 2); - set_bit(regs->r_sckmode.pol, _sck_o); - wait(bit_duration / 2); - } - } else - wait(7 * bit_duration); - if (s2m.first) rx_fifo.nb_write(s2m.second & 0xff); - update_irq_evt.notify(); - } - if (regs->r_csmode.mode == 0 && regs->r_csid < 4) // in AUTO mode - set_bit(false, _scs_o[regs->r_csid]); - } -} - -void beh::receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) {} - -void beh::update_irq() { - regs->r_ip.rxwm = regs->r_rxmark.rxmark < rx_fifo.num_available(); - regs->r_ip.txwm = regs->r_txmark.txmark <= tx_fifo.num_available(); - regs->r_txdata.full = tx_fifo.num_free() == 0; - irq_o.write((regs->r_ie.rxwm > 0 && regs->r_ip.rxwm > 0) || (regs->r_ie.txwm > 0 && regs->r_ip.txwm > 0)); -} -} /* namespace spi:impl */ - -template <> std::unique_ptr spi::create(sc_core::sc_module_name nm) { - auto *res = new sysc::spi_impl::beh(nm); - return std::unique_ptr(res); -} - -} /* namespace sysc */ diff --git a/platform/src/sysc/system.cpp b/platform/src/sysc/system.cpp deleted file mode 100644 index 199e7b3..0000000 --- a/platform/src/sysc/system.cpp +++ /dev/null @@ -1,115 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/top/system.h" - -using namespace sysc; -using namespace sc_core; - -system::system(sc_module_name nm) -: sc_module(nm) -, NAMED(s_ha) -, NAMED(s_la) -, NAMED(s_hb) -, NAMED(s_lb) -, NAMED(s_hc) -, NAMED(s_lc) -, NAMED(s_rst_n) -, NAMED(s_vref) -, NAMED(s_va) -, NAMED(s_vb) -, NAMED(s_vc) -, NAMED(s_vasens) -, NAMED(s_vbsens) -, NAMED(s_vcsens) -, NAMED(s_vcentersens) -, NAMED(s_ana, 4) -, NAMED(i_hifive1) -, NAMED(i_h_bridge) -, NAMED(i_motor) { - // connect platform - i_hifive1.erst_n(s_rst_n); - // HiFive1 digital out - i_hifive1.ha_o(s_ha); - i_hifive1.la_o(s_la); - i_hifive1.hb_o(s_hb); - i_hifive1.lb_o(s_lb); - i_hifive1.hc_o(s_hc); - i_hifive1.lc_o(s_lc); - // HiFive1 analog in - i_hifive1.vref_i(s_vref); - i_hifive1.adc_ch0_i(s_vasens); - i_hifive1.adc_ch1_i(s_vbsens); - i_hifive1.adc_ch2_i(s_vcsens); - i_hifive1.adc_ch3_i(s_vcentersens); - i_hifive1.adc_ch4_i(s_ana[0]); - i_hifive1.adc_ch5_i(s_ana[1]); - i_hifive1.adc_ch6_i(s_ana[2]); - i_hifive1.adc_ch7_i(s_ana[3]); - // H-bridge digital in - i_h_bridge.ha_i(s_ha); - i_h_bridge.la_i(s_la); - i_h_bridge.hb_i(s_hb); - i_h_bridge.lb_i(s_lb); - i_h_bridge.hc_i(s_hc); - i_h_bridge.lc_i(s_lc); - // H-bridge analog out - i_h_bridge.va_o(s_va); - i_h_bridge.vb_o(s_vb); - i_h_bridge.vc_o(s_vc); - // motor analog in - i_motor.va_i(s_va); - i_motor.vb_i(s_vb); - i_motor.vc_i(s_vc); - // motor analog out - i_motor.va_o(s_vasens); - i_motor.vb_o(s_vbsens); - i_motor.vc_o(s_vcsens); - i_motor.vcenter_o(s_vcentersens); - - SC_THREAD(gen_por); -} - -system::~system() = default; - -void sysc::system::gen_por() { - // single shot - s_rst_n = false; - wait(1_us); - s_rst_n = true; - s_vref = 4.8; - double val = 0.1; - for (auto &sig : s_ana) { - sig = val; - val += 0.12; - } -} diff --git a/platform/src/sysc/terminal.cpp b/platform/src/sysc/terminal.cpp deleted file mode 100644 index 4003684..0000000 --- a/platform/src/sysc/terminal.cpp +++ /dev/null @@ -1,87 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/top/terminal.h" - -#include "scc/report.h" -#include "sysc/sc_comm_singleton.h" -#include "sysc/tlm_extensions.h" - -using namespace sysc; - -terminal::terminal() -: terminal(sc_core::sc_gen_unique_name("terminal")) {} - -terminal::terminal(const sc_core::sc_module_name &nm) -: sc_core::sc_module(nm) -, NAMED(tx_o) -, NAMED(rx_i) -, NAMED(write_to_ws, false) { - rx_i.register_nb_transport([this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, - sc_core::sc_time &delay) -> tlm::tlm_sync_enum { - this->receive(gp, delay); - return tlm::TLM_COMPLETED; - }); -} - -terminal::~terminal() = default; - -void terminal::before_end_of_elaboration() { - if (write_to_ws.get_value()) { - SCTRACE() << "Adding WS handler for " << (std::string{"/ws/"} + name()); - handler = std::make_shared(); - sc_comm_singleton::inst().registerWebSocketHandler((std::string{"/ws/"} + name()).c_str(), handler); - } -} - -void terminal::receive(tlm::tlm_signal_gp &gp, sc_core::sc_time &delay) { - sysc::tlm_signal_uart_extension *ext; - gp.get_extension(ext); - if (ext && ext->start_time != last_tx_start) { - auto txdata = static_cast(ext->tx.data); - last_tx_start = ext->start_time; - if (txdata != '\r') queue.push_back(txdata); - if (queue.size() >> 0 && (txdata == '\n' || txdata == 0)) { - std::string msg(queue.begin(), queue.end() - 1); - sc_core::sc_time now = sc_core::sc_time_stamp(); - if (handler) - sysc::sc_comm_singleton::inst().execute([this, msg, now]() { - std::stringstream os; - os << R"({"time":")" << now << R"(","message":")" << msg << R"("})"; - this->handler->send(os.str()); - }); - else - SCINFO(this->name()) << " receive: '" << msg << "'"; - queue.clear(); - } - } -} diff --git a/platform/src/sysc/uart.cpp b/platform/src/sysc/uart.cpp deleted file mode 100644 index 65ce1bd..0000000 --- a/platform/src/sysc/uart.cpp +++ /dev/null @@ -1,180 +0,0 @@ -/******************************************************************************* - * Copyright (C) 2017, 2018 MINRES Technologies GmbH - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *******************************************************************************/ - -#include "sysc/SiFive/uart.h" - -#include "scc/report.h" -#include "scc/utilities.h" -#include "sysc/SiFive/gen/uart_regs.h" -#include "sysc/tlm_extensions.h" - -using namespace std; - -namespace sysc { -using namespace sc_core; - -uart::uart(sc_core::sc_module_name nm) -: sc_core::sc_module(nm) -, tlm_target<>(clk) -, NAMED(clk_i) -, NAMED(rst_i) -, NAMED(tx_o) -, NAMED(rx_i) -, NAMED(irq_o) -, NAMED(bit_true_transfer, false) -, NAMEDD(regs, uart_regs) -, NAMED(rx_fifo, 8) -, NAMED(tx_fifo, 8) { - regs->registerResources(*this); - SC_METHOD(clock_cb); - sensitive << clk_i; - SC_METHOD(reset_cb); - sensitive << rst_i; - dont_initialize(); - SC_THREAD(transmit_data); - rx_i.register_nb_transport( - [this](tlm::tlm_signal_gp &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) -> tlm::tlm_sync_enum { - this->receive_data(gp, delay); - return tlm::TLM_COMPLETED; - }); - regs->txdata.set_write_cb([this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - if (!this->regs->in_reset()) { - reg.put(data); - tx_fifo.nb_write(static_cast(regs->r_txdata.data)); - regs->r_txdata.full = tx_fifo.num_free() == 0; - regs->r_ip.txwm = regs->r_txctrl.txcnt <= (7 - tx_fifo.num_free()) ? 1 : 0; - update_irq(); - } - return true; - }); - regs->rxdata.set_read_cb([this](const scc::sc_register ®, uint32_t &data, sc_core::sc_time d) -> bool { - if (!this->regs->in_reset()) { - uint8_t val; - if (rx_fifo.nb_read(val)) { - regs->r_rxdata.data = val; - if (regs->r_rxctrl.rxcnt <= rx_fifo.num_available()) { - regs->r_ip.rxwm = 1; - update_irq(); - } - } - data = reg.get() & reg.rdmask; - } - return true; - }); - regs->ie.set_write_cb([this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - update_irq(); - return true; - }); - regs->ip.set_write_cb([this](scc::sc_register ®, uint32_t data, sc_core::sc_time d) -> bool { - update_irq(); - return true; - }); -} - -uart::~uart() = default; - -void uart::update_irq() { - irq_o = (regs->r_ip.rxwm == 1 && regs->r_ie.rxwm == 1) || (regs->r_ip.txwm == 1 && regs->r_ie.txwm == 1); -} - -void uart::clock_cb() { this->clk = clk_i.read(); } - -void uart::reset_cb() { - if (rst_i.read()) - regs->reset_start(); - else - regs->reset_stop(); -} - -void uart::transmit_data() { - uint8_t txdata; - tlm::tlm_phase phase(tlm::BEGIN_REQ); - sc_core::sc_time delay(SC_ZERO_TIME); - sc_core::sc_time bit_duration(SC_ZERO_TIME); - sc_core::sc_time start_time; - - auto set_bit = [&](bool val) { - auto *gp = tlm::tlm_signal_gp<>::create(); - auto *ext = new sysc::tlm_signal_uart_extension(); - ext->tx.data_bits = 8; - ext->tx.parity = false; - ext->start_time = start_time; - ext->tx.baud_rate = static_cast(1 / bit_duration.to_seconds()); - ext->tx.stop_bits = 1 + regs->r_txctrl.nstop; - ext->tx.data = txdata; - gp->set_extension(ext); - gp->set_command(tlm::TLM_WRITE_COMMAND); - gp->set_value(val); - gp->acquire(); - phase = tlm::BEGIN_REQ; - delay = SC_ZERO_TIME; - tx_o->nb_transport_fw(*gp, phase, delay); - gp->release(); - if (delay < bit_duration) wait(bit_duration - delay); - }; - wait(delay); - while (true) { - set_bit(true); - wait(tx_fifo.data_written_event()); - while (tx_fifo.nb_read(txdata)) { - regs->r_txdata.full = tx_fifo.num_free() == 0; - regs->r_ip.txwm = regs->r_txctrl.txcnt <= (7 - tx_fifo.num_free()) ? 1 : 0; - bit_duration = (regs->r_div.div + 1) * clk; - start_time = sc_core::sc_time_stamp(); - set_bit(false); // start bit - if (bit_true_transfer.get_value()) { - for (int i = 8; i > 0; --i) set_bit(txdata & (1 << (i - 1))); // 8 data bits, MSB first - if (regs->r_txctrl.nstop) set_bit(true); // stop bit 1 - } else - wait(8 * bit_duration); - set_bit(true); // stop bit 1/2 - } - } -} - -void uart::receive_data(tlm::tlm_signal_gp<> &gp, sc_core::sc_time &delay) { - sysc::tlm_signal_uart_extension *ext{nullptr}; - gp.get_extension(ext); - if (ext && ext->start_time != rx_last_start) { - auto data = static_cast(ext->tx.data); - if (ext->tx.parity || ext->tx.data_bits != 8) data = rand(); // random value if wrong config - rx_fifo.write(data); - if (regs->r_rxctrl.rxcnt <= rx_fifo.num_available()) { - regs->r_ip.rxwm = 1; - update_irq(); - } - rx_last_start = ext->start_time; // omit repeated handling of signal changes - } - gp.set_response_status(tlm::TLM_OK_RESPONSE); -} - -} /* namespace sysc */ diff --git a/riscv/CMakeLists.txt b/riscv/CMakeLists.txt deleted file mode 100644 index 4a10465..0000000 --- a/riscv/CMakeLists.txt +++ /dev/null @@ -1,52 +0,0 @@ -cmake_minimum_required(VERSION 3.3) -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../cmake) # main (top) cmake dir -set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake) # project specific cmake dir - -# CMake useful variables -set(CMAKE_RUNTIME_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/bin") -set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib") -set(CMAKE_LIBRARY_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib") - -# Set the name of your project here -project("riscv") - -include(Common) - -conan_basic_setup() - -# This sets the include directory for the reference project. This is the -I flag in gcc. -include_directories( - ${PROJECT_SOURCE_DIR}/incl - ${SOFTFLOAT_INCLUDE_DIRS} - ${LLVM_INCLUDE_DIRS} -) -add_dependent_subproject(dbt-core) -add_dependent_subproject(sc-components) -include_directories( - ${PROJECT_SOURCE_DIR}/incl - ${PROJECT_SOURCE_DIR}/../external/elfio - ${PROJECT_SOURCE_DIR}/../external/libGIS - ${Boost_INCLUDE_DIRS} -) - - -# Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH) -set(CMAKE_MACOSX_RPATH ON) -set(CMAKE_SKIP_BUILD_RPATH FALSE) -set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE) -set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib") -set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE) - -add_subdirectory(src) - -# -# SYSTEM PACKAGING (RPM, TGZ, ...) -# _____________________________________________________________________________ - -#include(CPackConfig) - -# -# CMAKE PACKAGING (for other CMake projects to use this one easily) -# _____________________________________________________________________________ - -#include(PackageConfigurator) \ No newline at end of file diff --git a/riscv/gen_input/.gitignore b/riscv/gen_input/.gitignore deleted file mode 100644 index b34c537..0000000 --- a/riscv/gen_input/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/src-gen/ diff --git a/sc-components b/sc-components deleted file mode 160000 index 7c989da..0000000 --- a/sc-components +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 7c989da05673bb40e1358561d51b86e71c1ac68c diff --git a/riscv/src/CMakeLists.txt b/src/CMakeLists.txt similarity index 100% rename from riscv/src/CMakeLists.txt rename to src/CMakeLists.txt diff --git a/riscv/src/internal/fp_functions.cpp b/src/internal/fp_functions.cpp similarity index 100% rename from riscv/src/internal/fp_functions.cpp rename to src/internal/fp_functions.cpp diff --git a/riscv/src/internal/vm_rv32gc.cpp b/src/internal/vm_rv32gc.cpp similarity index 100% rename from riscv/src/internal/vm_rv32gc.cpp rename to src/internal/vm_rv32gc.cpp diff --git a/riscv/src/internal/vm_rv32imac.cpp b/src/internal/vm_rv32imac.cpp similarity index 100% rename from riscv/src/internal/vm_rv32imac.cpp rename to src/internal/vm_rv32imac.cpp diff --git a/riscv/src/internal/vm_rv64gc.cpp b/src/internal/vm_rv64gc.cpp similarity index 100% rename from riscv/src/internal/vm_rv64gc.cpp rename to src/internal/vm_rv64gc.cpp diff --git a/riscv/src/internal/vm_rv64i.cpp b/src/internal/vm_rv64i.cpp similarity index 100% rename from riscv/src/internal/vm_rv64i.cpp rename to src/internal/vm_rv64i.cpp diff --git a/riscv/src/iss/rv32gc.cpp b/src/iss/rv32gc.cpp similarity index 100% rename from riscv/src/iss/rv32gc.cpp rename to src/iss/rv32gc.cpp diff --git a/riscv/src/iss/rv32imac.cpp b/src/iss/rv32imac.cpp similarity index 100% rename from riscv/src/iss/rv32imac.cpp rename to src/iss/rv32imac.cpp diff --git a/riscv/src/iss/rv64gc.cpp b/src/iss/rv64gc.cpp similarity index 100% rename from riscv/src/iss/rv64gc.cpp rename to src/iss/rv64gc.cpp diff --git a/riscv/src/iss/rv64i.cpp b/src/iss/rv64i.cpp similarity index 100% rename from riscv/src/iss/rv64i.cpp rename to src/iss/rv64i.cpp diff --git a/riscv/src/main.cpp b/src/main.cpp similarity index 100% rename from riscv/src/main.cpp rename to src/main.cpp diff --git a/src/plugin/GCOV.cpp b/src/plugin/GCOV.cpp new file mode 100644 index 0000000..6ce6440 --- /dev/null +++ b/src/plugin/GCOV.cpp @@ -0,0 +1,821 @@ +//===- GCOV.cpp - LLVM coverage tool --------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// GCOV implements the interface to read and write coverage files that use +// 'gcov' format. +// +//===----------------------------------------------------------------------===// + +#include "GCOV.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/FileSystem.h" +#include "llvm/Support/Format.h" +#include "llvm/Support/Path.h" +#include "llvm/Support/raw_ostream.h" +#include +#include + +using namespace llvm; + +//===----------------------------------------------------------------------===// +// GCOVFile implementation. + +/// readGCNO - Read GCNO buffer. +bool GCOVFile::readGCNO(GCOVBuffer &Buffer) { + if (!Buffer.readGCNOFormat()) + return false; + if (!Buffer.readGCOVVersion(Version)) + return false; + + if (!Buffer.readInt(Checksum)) + return false; + while (true) { + if (!Buffer.readFunctionTag()) + break; + auto GFun = make_unique(*this); + if (!GFun->readGCNO(Buffer, Version)) + return false; + Functions.push_back(std::move(GFun)); + } + + GCNOInitialized = true; + return true; +} + +/// readGCDA - Read GCDA buffer. It is required that readGCDA() can only be +/// called after readGCNO(). +bool GCOVFile::readGCDA(GCOVBuffer &Buffer) { + assert(GCNOInitialized && "readGCDA() can only be called after readGCNO()"); + if (!Buffer.readGCDAFormat()) + return false; + GCOV::GCOVVersion GCDAVersion; + if (!Buffer.readGCOVVersion(GCDAVersion)) + return false; + if (Version != GCDAVersion) { + errs() << "GCOV versions do not match.\n"; + return false; + } + + uint32_t GCDAChecksum; + if (!Buffer.readInt(GCDAChecksum)) + return false; + if (Checksum != GCDAChecksum) { + errs() << "File checksums do not match: " << Checksum + << " != " << GCDAChecksum << ".\n"; + return false; + } + for (size_t i = 0, e = Functions.size(); i < e; ++i) { + if (!Buffer.readFunctionTag()) { + errs() << "Unexpected number of functions.\n"; + return false; + } + if (!Functions[i]->readGCDA(Buffer, Version)) + return false; + } + if (Buffer.readObjectTag()) { + uint32_t Length; + uint32_t Dummy; + if (!Buffer.readInt(Length)) + return false; + if (!Buffer.readInt(Dummy)) + return false; // checksum + if (!Buffer.readInt(Dummy)) + return false; // num + if (!Buffer.readInt(RunCount)) + return false; + Buffer.advanceCursor(Length - 3); + } + while (Buffer.readProgramTag()) { + uint32_t Length; + if (!Buffer.readInt(Length)) + return false; + Buffer.advanceCursor(Length); + ++ProgramCount; + } + + return true; +} + +void GCOVFile::print(raw_ostream &OS) const { + for (const auto &FPtr : Functions) + FPtr->print(OS); +} + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) +/// dump - Dump GCOVFile content to dbgs() for debugging purposes. +LLVM_DUMP_METHOD void GCOVFile::dump() const { + print(dbgs()); +} +#endif + +/// collectLineCounts - Collect line counts. This must be used after +/// reading .gcno and .gcda files. +void GCOVFile::collectLineCounts(FileInfo &FI) { + for (const auto &FPtr : Functions) + FPtr->collectLineCounts(FI); + FI.setRunCount(RunCount); + FI.setProgramCount(ProgramCount); +} + +//===----------------------------------------------------------------------===// +// GCOVFunction implementation. + +/// readGCNO - Read a function from the GCNO buffer. Return false if an error +/// occurs. +bool GCOVFunction::readGCNO(GCOVBuffer &Buff, GCOV::GCOVVersion Version) { + uint32_t Dummy; + if (!Buff.readInt(Dummy)) + return false; // Function header length + if (!Buff.readInt(Ident)) + return false; + if (!Buff.readInt(Checksum)) + return false; + if (Version != GCOV::V402) { + uint32_t CfgChecksum; + if (!Buff.readInt(CfgChecksum)) + return false; + if (Parent.getChecksum() != CfgChecksum) { + errs() << "File checksums do not match: " << Parent.getChecksum() + << " != " << CfgChecksum << " in (" << Name << ").\n"; + return false; + } + } + if (!Buff.readString(Name)) + return false; + if (!Buff.readString(Filename)) + return false; + if (!Buff.readInt(LineNumber)) + return false; + + // read blocks. + if (!Buff.readBlockTag()) { + errs() << "Block tag not found.\n"; + return false; + } + uint32_t BlockCount; + if (!Buff.readInt(BlockCount)) + return false; + for (uint32_t i = 0, e = BlockCount; i != e; ++i) { + if (!Buff.readInt(Dummy)) + return false; // Block flags; + Blocks.push_back(make_unique(*this, i)); + } + + // read edges. + while (Buff.readEdgeTag()) { + uint32_t EdgeCount; + if (!Buff.readInt(EdgeCount)) + return false; + EdgeCount = (EdgeCount - 1) / 2; + uint32_t BlockNo; + if (!Buff.readInt(BlockNo)) + return false; + if (BlockNo >= BlockCount) { + errs() << "Unexpected block number: " << BlockNo << " (in " << Name + << ").\n"; + return false; + } + for (uint32_t i = 0, e = EdgeCount; i != e; ++i) { + uint32_t Dst; + if (!Buff.readInt(Dst)) + return false; + Edges.push_back(make_unique(*Blocks[BlockNo], *Blocks[Dst])); + GCOVEdge *Edge = Edges.back().get(); + Blocks[BlockNo]->addDstEdge(Edge); + Blocks[Dst]->addSrcEdge(Edge); + if (!Buff.readInt(Dummy)) + return false; // Edge flag + } + } + + // read line table. + while (Buff.readLineTag()) { + uint32_t LineTableLength; + // Read the length of this line table. + if (!Buff.readInt(LineTableLength)) + return false; + uint32_t EndPos = Buff.getCursor() + LineTableLength * 4; + uint32_t BlockNo; + // Read the block number this table is associated with. + if (!Buff.readInt(BlockNo)) + return false; + if (BlockNo >= BlockCount) { + errs() << "Unexpected block number: " << BlockNo << " (in " << Name + << ").\n"; + return false; + } + GCOVBlock &Block = *Blocks[BlockNo]; + // Read the word that pads the beginning of the line table. This may be a + // flag of some sort, but seems to always be zero. + if (!Buff.readInt(Dummy)) + return false; + + // Line information starts here and continues up until the last word. + if (Buff.getCursor() != (EndPos - sizeof(uint32_t))) { + StringRef F; + // Read the source file name. + if (!Buff.readString(F)) + return false; + if (Filename != F) { + errs() << "Multiple sources for a single basic block: " << Filename + << " != " << F << " (in " << Name << ").\n"; + return false; + } + // Read lines up to, but not including, the null terminator. + while (Buff.getCursor() < (EndPos - 2 * sizeof(uint32_t))) { + uint32_t Line; + if (!Buff.readInt(Line)) + return false; + // Line 0 means this instruction was injected by the compiler. Skip it. + if (!Line) + continue; + Block.addLine(Line); + } + // Read the null terminator. + if (!Buff.readInt(Dummy)) + return false; + } + // The last word is either a flag or padding, it isn't clear which. Skip + // over it. + if (!Buff.readInt(Dummy)) + return false; + } + return true; +} + +/// readGCDA - Read a function from the GCDA buffer. Return false if an error +/// occurs. +bool GCOVFunction::readGCDA(GCOVBuffer &Buff, GCOV::GCOVVersion Version) { + uint32_t HeaderLength; + if (!Buff.readInt(HeaderLength)) + return false; // Function header length + + uint64_t EndPos = Buff.getCursor() + HeaderLength * sizeof(uint32_t); + + uint32_t GCDAIdent; + if (!Buff.readInt(GCDAIdent)) + return false; + if (Ident != GCDAIdent) { + errs() << "Function identifiers do not match: " << Ident + << " != " << GCDAIdent << " (in " << Name << ").\n"; + return false; + } + + uint32_t GCDAChecksum; + if (!Buff.readInt(GCDAChecksum)) + return false; + if (Checksum != GCDAChecksum) { + errs() << "Function checksums do not match: " << Checksum + << " != " << GCDAChecksum << " (in " << Name << ").\n"; + return false; + } + + uint32_t CfgChecksum; + if (Version != GCOV::V402) { + if (!Buff.readInt(CfgChecksum)) + return false; + if (Parent.getChecksum() != CfgChecksum) { + errs() << "File checksums do not match: " << Parent.getChecksum() + << " != " << CfgChecksum << " (in " << Name << ").\n"; + return false; + } + } + + if (Buff.getCursor() < EndPos) { + StringRef GCDAName; + if (!Buff.readString(GCDAName)) + return false; + if (Name != GCDAName) { + errs() << "Function names do not match: " << Name << " != " << GCDAName + << ".\n"; + return false; + } + } + + if (!Buff.readArcTag()) { + errs() << "Arc tag not found (in " << Name << ").\n"; + return false; + } + + uint32_t Count; + if (!Buff.readInt(Count)) + return false; + Count /= 2; + + // This for loop adds the counts for each block. A second nested loop is + // required to combine the edge counts that are contained in the GCDA file. + for (uint32_t BlockNo = 0; Count > 0; ++BlockNo) { + // The last block is always reserved for exit block + if (BlockNo >= Blocks.size()) { + errs() << "Unexpected number of edges (in " << Name << ").\n"; + return false; + } + if (BlockNo == Blocks.size() - 1) + errs() << "(" << Name << ") has arcs from exit block.\n"; + GCOVBlock &Block = *Blocks[BlockNo]; + for (size_t EdgeNo = 0, End = Block.getNumDstEdges(); EdgeNo < End; + ++EdgeNo) { + if (Count == 0) { + errs() << "Unexpected number of edges (in " << Name << ").\n"; + return false; + } + uint64_t ArcCount; + if (!Buff.readInt64(ArcCount)) + return false; + Block.addCount(EdgeNo, ArcCount); + --Count; + } + Block.sortDstEdges(); + } + return true; +} + +/// getEntryCount - Get the number of times the function was called by +/// retrieving the entry block's count. +uint64_t GCOVFunction::getEntryCount() const { + return Blocks.front()->getCount(); +} + +/// getExitCount - Get the number of times the function returned by retrieving +/// the exit block's count. +uint64_t GCOVFunction::getExitCount() const { + return Blocks.back()->getCount(); +} + +void GCOVFunction::print(raw_ostream &OS) const { + OS << "===== " << Name << " (" << Ident << ") @ " << Filename << ":" + << LineNumber << "\n"; + for (const auto &Block : Blocks) + Block->print(OS); +} + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) +/// dump - Dump GCOVFunction content to dbgs() for debugging purposes. +LLVM_DUMP_METHOD void GCOVFunction::dump() const { + print(dbgs()); +} +#endif + +/// collectLineCounts - Collect line counts. This must be used after +/// reading .gcno and .gcda files. +void GCOVFunction::collectLineCounts(FileInfo &FI) { + // If the line number is zero, this is a function that doesn't actually appear + // in the source file, so there isn't anything we can do with it. + if (LineNumber == 0) + return; + + for (const auto &Block : Blocks) + Block->collectLineCounts(FI); + FI.addFunctionLine(Filename, LineNumber, this); +} + +//===----------------------------------------------------------------------===// +// GCOVBlock implementation. + +/// ~GCOVBlock - Delete GCOVBlock and its content. +GCOVBlock::~GCOVBlock() { + SrcEdges.clear(); + DstEdges.clear(); + Lines.clear(); +} + +/// addCount - Add to block counter while storing the edge count. If the +/// destination has no outgoing edges, also update that block's count too. +void GCOVBlock::addCount(size_t DstEdgeNo, uint64_t N) { + assert(DstEdgeNo < DstEdges.size()); // up to caller to ensure EdgeNo is valid + DstEdges[DstEdgeNo]->Count = N; + Counter += N; + if (!DstEdges[DstEdgeNo]->Dst.getNumDstEdges()) + DstEdges[DstEdgeNo]->Dst.Counter += N; +} + +/// sortDstEdges - Sort destination edges by block number, nop if already +/// sorted. This is required for printing branch info in the correct order. +void GCOVBlock::sortDstEdges() { + if (!DstEdgesAreSorted) { + SortDstEdgesFunctor SortEdges; + std::stable_sort(DstEdges.begin(), DstEdges.end(), SortEdges); + } +} + +/// collectLineCounts - Collect line counts. This must be used after +/// reading .gcno and .gcda files. +void GCOVBlock::collectLineCounts(FileInfo &FI) { + for (uint32_t N : Lines) + FI.addBlockLine(Parent.getFilename(), N, this); +} + +void GCOVBlock::print(raw_ostream &OS) const { + OS << "Block : " << Number << " Counter : " << Counter << "\n"; + if (!SrcEdges.empty()) { + OS << "\tSource Edges : "; + for (const GCOVEdge *Edge : SrcEdges) + OS << Edge->Src.Number << " (" << Edge->Count << "), "; + OS << "\n"; + } + if (!DstEdges.empty()) { + OS << "\tDestination Edges : "; + for (const GCOVEdge *Edge : DstEdges) + OS << Edge->Dst.Number << " (" << Edge->Count << "), "; + OS << "\n"; + } + if (!Lines.empty()) { + OS << "\tLines : "; + for (uint32_t N : Lines) + OS << (N) << ","; + OS << "\n"; + } +} + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) +/// dump - Dump GCOVBlock content to dbgs() for debugging purposes. +LLVM_DUMP_METHOD void GCOVBlock::dump() const { + print(dbgs()); +} +#endif + +//===----------------------------------------------------------------------===// +// FileInfo implementation. + +// Safe integer division, returns 0 if numerator is 0. +static uint32_t safeDiv(uint64_t Numerator, uint64_t Divisor) { + if (!Numerator) + return 0; + return Numerator / Divisor; +} + +// This custom division function mimics gcov's branch ouputs: +// - Round to closest whole number +// - Only output 0% or 100% if it's exactly that value +static uint32_t branchDiv(uint64_t Numerator, uint64_t Divisor) { + if (!Numerator) + return 0; + if (Numerator == Divisor) + return 100; + + uint8_t Res = (Numerator * 100 + Divisor / 2) / Divisor; + if (Res == 0) + return 1; + if (Res == 100) + return 99; + return Res; +} + +namespace { +struct formatBranchInfo { + formatBranchInfo(const GCOV::Options &Options, uint64_t Count, uint64_t Total) + : Options(Options), Count(Count), Total(Total) {} + + void print(raw_ostream &OS) const { + if (!Total) + OS << "never executed"; + else if (Options.BranchCount) + OS << "taken " << Count; + else + OS << "taken " << branchDiv(Count, Total) << "%"; + } + + const GCOV::Options &Options; + uint64_t Count; + uint64_t Total; +}; + +static raw_ostream &operator<<(raw_ostream &OS, const formatBranchInfo &FBI) { + FBI.print(OS); + return OS; +} + +class LineConsumer { + std::unique_ptr Buffer; + StringRef Remaining; + +public: + LineConsumer(StringRef Filename) { + ErrorOr> BufferOrErr = + MemoryBuffer::getFileOrSTDIN(Filename); + if (std::error_code EC = BufferOrErr.getError()) { + errs() << Filename << ": " << EC.message() << "\n"; + Remaining = ""; + } else { + Buffer = std::move(BufferOrErr.get()); + Remaining = Buffer->getBuffer(); + } + } + bool empty() { return Remaining.empty(); } + void printNext(raw_ostream &OS, uint32_t LineNum) { + StringRef Line; + if (empty()) + Line = "/*EOF*/"; + else + std::tie(Line, Remaining) = Remaining.split("\n"); + OS << format("%5u:", LineNum) << Line << "\n"; + } +}; +} // end anonymous namespace + +/// Convert a path to a gcov filename. If PreservePaths is true, this +/// translates "/" to "#", ".." to "^", and drops ".", to match gcov. +static std::string mangleCoveragePath(StringRef Filename, bool PreservePaths) { + if (!PreservePaths) + return sys::path::filename(Filename).str(); + + // This behaviour is defined by gcov in terms of text replacements, so it's + // not likely to do anything useful on filesystems with different textual + // conventions. + llvm::SmallString<256> Result(""); + StringRef::iterator I, S, E; + for (I = S = Filename.begin(), E = Filename.end(); I != E; ++I) { + if (*I != '/') + continue; + + if (I - S == 1 && *S == '.') { + // ".", the current directory, is skipped. + } else if (I - S == 2 && *S == '.' && *(S + 1) == '.') { + // "..", the parent directory, is replaced with "^". + Result.append("^#"); + } else { + if (S < I) + // Leave other components intact, + Result.append(S, I); + // And separate with "#". + Result.push_back('#'); + } + S = I + 1; + } + + if (S < I) + Result.append(S, I); + return Result.str(); +} + +std::string FileInfo::getCoveragePath(StringRef Filename, + StringRef MainFilename) { + if (Options.NoOutput) + // This is probably a bug in gcov, but when -n is specified, paths aren't + // mangled at all, and the -l and -p options are ignored. Here, we do the + // same. + return Filename; + + std::string CoveragePath; + if (Options.LongFileNames && !Filename.equals(MainFilename)) + CoveragePath = + mangleCoveragePath(MainFilename, Options.PreservePaths) + "##"; + CoveragePath += mangleCoveragePath(Filename, Options.PreservePaths) + ".gcov"; + return CoveragePath; +} + +std::unique_ptr +FileInfo::openCoveragePath(StringRef CoveragePath) { + if (Options.NoOutput) + return llvm::make_unique(); + + std::error_code EC; + auto OS = llvm::make_unique(CoveragePath, EC, + sys::fs::F_Text); + if (EC) { + errs() << EC.message() << "\n"; + return llvm::make_unique(); + } + return std::move(OS); +} + +/// print - Print source files with collected line count information. +void FileInfo::print(raw_ostream &InfoOS, StringRef MainFilename, + StringRef GCNOFile, StringRef GCDAFile) { + SmallVector Filenames; + for (const auto &LI : LineInfo) + Filenames.push_back(LI.first()); + std::sort(Filenames.begin(), Filenames.end()); + + for (StringRef Filename : Filenames) { + auto AllLines = LineConsumer(Filename); + + std::string CoveragePath = getCoveragePath(Filename, MainFilename); + std::unique_ptr CovStream = openCoveragePath(CoveragePath); + raw_ostream &CovOS = *CovStream; + + CovOS << " -: 0:Source:" << Filename << "\n"; + CovOS << " -: 0:Graph:" << GCNOFile << "\n"; + CovOS << " -: 0:Data:" << GCDAFile << "\n"; + CovOS << " -: 0:Runs:" << RunCount << "\n"; + CovOS << " -: 0:Programs:" << ProgramCount << "\n"; + + const LineData &Line = LineInfo[Filename]; + GCOVCoverage FileCoverage(Filename); + for (uint32_t LineIndex = 0; LineIndex < Line.LastLine || !AllLines.empty(); + ++LineIndex) { + if (Options.BranchInfo) { + FunctionLines::const_iterator FuncsIt = Line.Functions.find(LineIndex); + if (FuncsIt != Line.Functions.end()) + printFunctionSummary(CovOS, FuncsIt->second); + } + + BlockLines::const_iterator BlocksIt = Line.Blocks.find(LineIndex); + if (BlocksIt == Line.Blocks.end()) { + // No basic blocks are on this line. Not an executable line of code. + CovOS << " -:"; + AllLines.printNext(CovOS, LineIndex + 1); + } else { + const BlockVector &Blocks = BlocksIt->second; + + // Add up the block counts to form line counts. + DenseMap LineExecs; + uint64_t LineCount = 0; + for (const GCOVBlock *Block : Blocks) { + if (Options.AllBlocks) { + // Only take the highest block count for that line. + uint64_t BlockCount = Block->getCount(); + LineCount = LineCount > BlockCount ? LineCount : BlockCount; + } else { + // Sum up all of the block counts. + LineCount += Block->getCount(); + } + + if (Options.FuncCoverage) { + // This is a slightly convoluted way to most accurately gather line + // statistics for functions. Basically what is happening is that we + // don't want to count a single line with multiple blocks more than + // once. However, we also don't simply want to give the total line + // count to every function that starts on the line. Thus, what is + // happening here are two things: + // 1) Ensure that the number of logical lines is only incremented + // once per function. + // 2) If there are multiple blocks on the same line, ensure that the + // number of lines executed is incremented as long as at least + // one of the blocks are executed. + const GCOVFunction *Function = &Block->getParent(); + if (FuncCoverages.find(Function) == FuncCoverages.end()) { + std::pair KeyValue( + Function, GCOVCoverage(Function->getName())); + FuncCoverages.insert(KeyValue); + } + GCOVCoverage &FuncCoverage = FuncCoverages.find(Function)->second; + + if (LineExecs.find(Function) == LineExecs.end()) { + if (Block->getCount()) { + ++FuncCoverage.LinesExec; + LineExecs[Function] = true; + } else { + LineExecs[Function] = false; + } + ++FuncCoverage.LogicalLines; + } else if (!LineExecs[Function] && Block->getCount()) { + ++FuncCoverage.LinesExec; + LineExecs[Function] = true; + } + } + } + + if (LineCount == 0) + CovOS << " #####:"; + else { + CovOS << format("%9" PRIu64 ":", LineCount); + ++FileCoverage.LinesExec; + } + ++FileCoverage.LogicalLines; + + AllLines.printNext(CovOS, LineIndex + 1); + + uint32_t BlockNo = 0; + uint32_t EdgeNo = 0; + for (const GCOVBlock *Block : Blocks) { + // Only print block and branch information at the end of the block. + if (Block->getLastLine() != LineIndex + 1) + continue; + if (Options.AllBlocks) + printBlockInfo(CovOS, *Block, LineIndex, BlockNo); + if (Options.BranchInfo) { + size_t NumEdges = Block->getNumDstEdges(); + if (NumEdges > 1) + printBranchInfo(CovOS, *Block, FileCoverage, EdgeNo); + else if (Options.UncondBranch && NumEdges == 1) + printUncondBranchInfo(CovOS, EdgeNo, + (*Block->dst_begin())->Count); + } + } + } + } + FileCoverages.push_back(std::make_pair(CoveragePath, FileCoverage)); + } + + // FIXME: There is no way to detect calls given current instrumentation. + if (Options.FuncCoverage) + printFuncCoverage(InfoOS); + printFileCoverage(InfoOS); +} + +/// printFunctionSummary - Print function and block summary. +void FileInfo::printFunctionSummary(raw_ostream &OS, + const FunctionVector &Funcs) const { + for (const GCOVFunction *Func : Funcs) { + uint64_t EntryCount = Func->getEntryCount(); + uint32_t BlocksExec = 0; + for (const GCOVBlock &Block : Func->blocks()) + if (Block.getNumDstEdges() && Block.getCount()) + ++BlocksExec; + + OS << "function " << Func->getName() << " called " << EntryCount + << " returned " << safeDiv(Func->getExitCount() * 100, EntryCount) + << "% blocks executed " + << safeDiv(BlocksExec * 100, Func->getNumBlocks() - 1) << "%\n"; + } +} + +/// printBlockInfo - Output counts for each block. +void FileInfo::printBlockInfo(raw_ostream &OS, const GCOVBlock &Block, + uint32_t LineIndex, uint32_t &BlockNo) const { + if (Block.getCount() == 0) + OS << " $$$$$:"; + else + OS << format("%9" PRIu64 ":", Block.getCount()); + OS << format("%5u-block %2u\n", LineIndex + 1, BlockNo++); +} + +/// printBranchInfo - Print conditional branch probabilities. +void FileInfo::printBranchInfo(raw_ostream &OS, const GCOVBlock &Block, + GCOVCoverage &Coverage, uint32_t &EdgeNo) { + SmallVector BranchCounts; + uint64_t TotalCounts = 0; + for (const GCOVEdge *Edge : Block.dsts()) { + BranchCounts.push_back(Edge->Count); + TotalCounts += Edge->Count; + if (Block.getCount()) + ++Coverage.BranchesExec; + if (Edge->Count) + ++Coverage.BranchesTaken; + ++Coverage.Branches; + + if (Options.FuncCoverage) { + const GCOVFunction *Function = &Block.getParent(); + GCOVCoverage &FuncCoverage = FuncCoverages.find(Function)->second; + if (Block.getCount()) + ++FuncCoverage.BranchesExec; + if (Edge->Count) + ++FuncCoverage.BranchesTaken; + ++FuncCoverage.Branches; + } + } + + for (uint64_t N : BranchCounts) + OS << format("branch %2u ", EdgeNo++) + << formatBranchInfo(Options, N, TotalCounts) << "\n"; +} + +/// printUncondBranchInfo - Print unconditional branch probabilities. +void FileInfo::printUncondBranchInfo(raw_ostream &OS, uint32_t &EdgeNo, + uint64_t Count) const { + OS << format("unconditional %2u ", EdgeNo++) + << formatBranchInfo(Options, Count, Count) << "\n"; +} + +// printCoverage - Print generic coverage info used by both printFuncCoverage +// and printFileCoverage. +void FileInfo::printCoverage(raw_ostream &OS, + const GCOVCoverage &Coverage) const { + OS << format("Lines executed:%.2f%% of %u\n", + double(Coverage.LinesExec) * 100 / Coverage.LogicalLines, + Coverage.LogicalLines); + if (Options.BranchInfo) { + if (Coverage.Branches) { + OS << format("Branches executed:%.2f%% of %u\n", + double(Coverage.BranchesExec) * 100 / Coverage.Branches, + Coverage.Branches); + OS << format("Taken at least once:%.2f%% of %u\n", + double(Coverage.BranchesTaken) * 100 / Coverage.Branches, + Coverage.Branches); + } else { + OS << "No branches\n"; + } + OS << "No calls\n"; // to be consistent with gcov + } +} + +// printFuncCoverage - Print per-function coverage info. +void FileInfo::printFuncCoverage(raw_ostream &OS) const { + for (const auto &FC : FuncCoverages) { + const GCOVCoverage &Coverage = FC.second; + OS << "Function '" << Coverage.Name << "'\n"; + printCoverage(OS, Coverage); + OS << "\n"; + } +} + +// printFileCoverage - Print per-file coverage info. +void FileInfo::printFileCoverage(raw_ostream &OS) const { + for (const auto &FC : FileCoverages) { + const std::string &Filename = FC.first; + const GCOVCoverage &Coverage = FC.second; + OS << "File '" << Coverage.Name << "'\n"; + printCoverage(OS, Coverage); + if (!Options.NoOutput) + OS << Coverage.Name << ":creating '" << Filename << "'\n"; + OS << "\n"; + } +} diff --git a/src/plugin/GCOV.h b/src/plugin/GCOV.h new file mode 100644 index 0000000..497f80b --- /dev/null +++ b/src/plugin/GCOV.h @@ -0,0 +1,460 @@ +//===- GCOV.h - LLVM coverage tool ------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This header provides the interface to read and write coverage files that +// use 'gcov' format. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_PROFILEDATA_GCOV_H +#define LLVM_PROFILEDATA_GCOV_H + +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/MapVector.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringMap.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/iterator.h" +#include "llvm/ADT/iterator_range.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/raw_ostream.h" +#include +#include +#include +#include +#include +#include + +namespace llvm { + +class GCOVFunction; +class GCOVBlock; +class FileInfo; + +namespace GCOV { + +enum GCOVVersion { V402, V404, V704 }; + +/// \brief A struct for passing gcov options between functions. +struct Options { + Options(bool A, bool B, bool C, bool F, bool P, bool U, bool L, bool N) + : AllBlocks(A), BranchInfo(B), BranchCount(C), FuncCoverage(F), + PreservePaths(P), UncondBranch(U), LongFileNames(L), NoOutput(N) {} + + bool AllBlocks; + bool BranchInfo; + bool BranchCount; + bool FuncCoverage; + bool PreservePaths; + bool UncondBranch; + bool LongFileNames; + bool NoOutput; +}; + +} // end namespace GCOV + +/// GCOVBuffer - A wrapper around MemoryBuffer to provide GCOV specific +/// read operations. +class GCOVBuffer { +public: + GCOVBuffer(MemoryBuffer *B) : Buffer(B) {} + + /// readGCNOFormat - Check GCNO signature is valid at the beginning of buffer. + bool readGCNOFormat() { + StringRef File = Buffer->getBuffer().slice(0, 4); + if (File != "oncg") { + errs() << "Unexpected file type: " << File << ".\n"; + return false; + } + Cursor = 4; + return true; + } + + /// readGCDAFormat - Check GCDA signature is valid at the beginning of buffer. + bool readGCDAFormat() { + StringRef File = Buffer->getBuffer().slice(0, 4); + if (File != "adcg") { + errs() << "Unexpected file type: " << File << ".\n"; + return false; + } + Cursor = 4; + return true; + } + + /// readGCOVVersion - Read GCOV version. + bool readGCOVVersion(GCOV::GCOVVersion &Version) { + StringRef VersionStr = Buffer->getBuffer().slice(Cursor, Cursor + 4); + if (VersionStr == "*204") { + Cursor += 4; + Version = GCOV::V402; + return true; + } + if (VersionStr == "*404") { + Cursor += 4; + Version = GCOV::V404; + return true; + } + if (VersionStr == "*704") { + Cursor += 4; + Version = GCOV::V704; + return true; + } + errs() << "Unexpected version: " << VersionStr << ".\n"; + return false; + } + + /// readFunctionTag - If cursor points to a function tag then increment the + /// cursor and return true otherwise return false. + bool readFunctionTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4); + if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' || + Tag[3] != '\1') { + return false; + } + Cursor += 4; + return true; + } + + /// readBlockTag - If cursor points to a block tag then increment the + /// cursor and return true otherwise return false. + bool readBlockTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4); + if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x41' || + Tag[3] != '\x01') { + return false; + } + Cursor += 4; + return true; + } + + /// readEdgeTag - If cursor points to an edge tag then increment the + /// cursor and return true otherwise return false. + bool readEdgeTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4); + if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x43' || + Tag[3] != '\x01') { + return false; + } + Cursor += 4; + return true; + } + + /// readLineTag - If cursor points to a line tag then increment the + /// cursor and return true otherwise return false. + bool readLineTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4); + if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\x45' || + Tag[3] != '\x01') { + return false; + } + Cursor += 4; + return true; + } + + /// readArcTag - If cursor points to an gcda arc tag then increment the + /// cursor and return true otherwise return false. + bool readArcTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4); + if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\xa1' || + Tag[3] != '\1') { + return false; + } + Cursor += 4; + return true; + } + + /// readObjectTag - If cursor points to an object summary tag then increment + /// the cursor and return true otherwise return false. + bool readObjectTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4); + if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' || + Tag[3] != '\xa1') { + return false; + } + Cursor += 4; + return true; + } + + /// readProgramTag - If cursor points to a program summary tag then increment + /// the cursor and return true otherwise return false. + bool readProgramTag() { + StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor + 4); + if (Tag.empty() || Tag[0] != '\0' || Tag[1] != '\0' || Tag[2] != '\0' || + Tag[3] != '\xa3') { + return false; + } + Cursor += 4; + return true; + } + + bool readInt(uint32_t &Val) { + if (Buffer->getBuffer().size() < Cursor + 4) { + errs() << "Unexpected end of memory buffer: " << Cursor + 4 << ".\n"; + return false; + } + StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor + 4); + Cursor += 4; + Val = *(const uint32_t *)(Str.data()); + return true; + } + + bool readInt64(uint64_t &Val) { + uint32_t Lo, Hi; + if (!readInt(Lo) || !readInt(Hi)) + return false; + Val = ((uint64_t)Hi << 32) | Lo; + return true; + } + + bool readString(StringRef &Str) { + uint32_t Len = 0; + // Keep reading until we find a non-zero length. This emulates gcov's + // behaviour, which appears to do the same. + while (Len == 0) + if (!readInt(Len)) + return false; + Len *= 4; + if (Buffer->getBuffer().size() < Cursor + Len) { + errs() << "Unexpected end of memory buffer: " << Cursor + Len << ".\n"; + return false; + } + Str = Buffer->getBuffer().slice(Cursor, Cursor + Len).split('\0').first; + Cursor += Len; + return true; + } + + uint64_t getCursor() const { return Cursor; } + void advanceCursor(uint32_t n) { Cursor += n * 4; } + +private: + MemoryBuffer *Buffer; + uint64_t Cursor = 0; +}; + +/// GCOVFile - Collects coverage information for one pair of coverage file +/// (.gcno and .gcda). +class GCOVFile { +public: + GCOVFile() = default; + + bool readGCNO(GCOVBuffer &Buffer); + bool readGCDA(GCOVBuffer &Buffer); + uint32_t getChecksum() const { return Checksum; } + void print(raw_ostream &OS) const; + void dump() const; + void collectLineCounts(FileInfo &FI); + +private: + bool GCNOInitialized = false; + GCOV::GCOVVersion Version; + uint32_t Checksum = 0; + SmallVector, 16> Functions; + uint32_t RunCount = 0; + uint32_t ProgramCount = 0; +}; + +/// GCOVEdge - Collects edge information. +struct GCOVEdge { + GCOVEdge(GCOVBlock &S, GCOVBlock &D) : Src(S), Dst(D) {} + + GCOVBlock &Src; + GCOVBlock &Dst; + uint64_t Count = 0; +}; + +/// GCOVFunction - Collects function information. +class GCOVFunction { +public: + using BlockIterator = pointee_iterator>::const_iterator>; + + GCOVFunction(GCOVFile &P) : Parent(P) {} + + bool readGCNO(GCOVBuffer &Buffer, GCOV::GCOVVersion Version); + bool readGCDA(GCOVBuffer &Buffer, GCOV::GCOVVersion Version); + StringRef getName() const { return Name; } + StringRef getFilename() const { return Filename; } + size_t getNumBlocks() const { return Blocks.size(); } + uint64_t getEntryCount() const; + uint64_t getExitCount() const; + + BlockIterator block_begin() const { return Blocks.begin(); } + BlockIterator block_end() const { return Blocks.end(); } + iterator_range blocks() const { + return make_range(block_begin(), block_end()); + } + + void print(raw_ostream &OS) const; + void dump() const; + void collectLineCounts(FileInfo &FI); + +private: + GCOVFile &Parent; + uint32_t Ident = 0; + uint32_t Checksum; + uint32_t LineNumber = 0; + StringRef Name; + StringRef Filename; + SmallVector, 16> Blocks; + SmallVector, 16> Edges; +}; + +/// GCOVBlock - Collects block information. +class GCOVBlock { + struct EdgeWeight { + EdgeWeight(GCOVBlock *D) : Dst(D) {} + + GCOVBlock *Dst; + uint64_t Count = 0; + }; + + struct SortDstEdgesFunctor { + bool operator()(const GCOVEdge *E1, const GCOVEdge *E2) { + return E1->Dst.Number < E2->Dst.Number; + } + }; + +public: + using EdgeIterator = SmallVectorImpl::const_iterator; + + GCOVBlock(GCOVFunction &P, uint32_t N) : Parent(P), Number(N) {} + ~GCOVBlock(); + + const GCOVFunction &getParent() const { return Parent; } + void addLine(uint32_t N) { Lines.push_back(N); } + uint32_t getLastLine() const { return Lines.back(); } + void addCount(size_t DstEdgeNo, uint64_t N); + uint64_t getCount() const { return Counter; } + + void addSrcEdge(GCOVEdge *Edge) { + assert(&Edge->Dst == this); // up to caller to ensure edge is valid + SrcEdges.push_back(Edge); + } + + void addDstEdge(GCOVEdge *Edge) { + assert(&Edge->Src == this); // up to caller to ensure edge is valid + // Check if adding this edge causes list to become unsorted. + if (DstEdges.size() && DstEdges.back()->Dst.Number > Edge->Dst.Number) + DstEdgesAreSorted = false; + DstEdges.push_back(Edge); + } + + size_t getNumSrcEdges() const { return SrcEdges.size(); } + size_t getNumDstEdges() const { return DstEdges.size(); } + void sortDstEdges(); + + EdgeIterator src_begin() const { return SrcEdges.begin(); } + EdgeIterator src_end() const { return SrcEdges.end(); } + iterator_range srcs() const { + return make_range(src_begin(), src_end()); + } + + EdgeIterator dst_begin() const { return DstEdges.begin(); } + EdgeIterator dst_end() const { return DstEdges.end(); } + iterator_range dsts() const { + return make_range(dst_begin(), dst_end()); + } + + void print(raw_ostream &OS) const; + void dump() const; + void collectLineCounts(FileInfo &FI); + +private: + GCOVFunction &Parent; + uint32_t Number; + uint64_t Counter = 0; + bool DstEdgesAreSorted = true; + SmallVector SrcEdges; + SmallVector DstEdges; + SmallVector Lines; +}; + +class FileInfo { + // It is unlikely--but possible--for multiple functions to be on the same + // line. + // Therefore this typedef allows LineData.Functions to store multiple + // functions + // per instance. This is rare, however, so optimize for the common case. + using FunctionVector = SmallVector; + using FunctionLines = DenseMap; + using BlockVector = SmallVector; + using BlockLines = DenseMap; + + struct LineData { + LineData() = default; + + BlockLines Blocks; + FunctionLines Functions; + uint32_t LastLine = 0; + }; + + struct GCOVCoverage { + GCOVCoverage(StringRef Name) : Name(Name) {} + + StringRef Name; + + uint32_t LogicalLines = 0; + uint32_t LinesExec = 0; + + uint32_t Branches = 0; + uint32_t BranchesExec = 0; + uint32_t BranchesTaken = 0; + }; + +public: + FileInfo(const GCOV::Options &Options) : Options(Options) {} + + void addBlockLine(StringRef Filename, uint32_t Line, const GCOVBlock *Block) { + if (Line > LineInfo[Filename].LastLine) + LineInfo[Filename].LastLine = Line; + LineInfo[Filename].Blocks[Line - 1].push_back(Block); + } + + void addFunctionLine(StringRef Filename, uint32_t Line, + const GCOVFunction *Function) { + if (Line > LineInfo[Filename].LastLine) + LineInfo[Filename].LastLine = Line; + LineInfo[Filename].Functions[Line - 1].push_back(Function); + } + + void setRunCount(uint32_t Runs) { RunCount = Runs; } + void setProgramCount(uint32_t Programs) { ProgramCount = Programs; } + void print(raw_ostream &OS, StringRef MainFilename, StringRef GCNOFile, + StringRef GCDAFile); + +private: + std::string getCoveragePath(StringRef Filename, StringRef MainFilename); + std::unique_ptr openCoveragePath(StringRef CoveragePath); + void printFunctionSummary(raw_ostream &OS, const FunctionVector &Funcs) const; + void printBlockInfo(raw_ostream &OS, const GCOVBlock &Block, + uint32_t LineIndex, uint32_t &BlockNo) const; + void printBranchInfo(raw_ostream &OS, const GCOVBlock &Block, + GCOVCoverage &Coverage, uint32_t &EdgeNo); + void printUncondBranchInfo(raw_ostream &OS, uint32_t &EdgeNo, + uint64_t Count) const; + + void printCoverage(raw_ostream &OS, const GCOVCoverage &Coverage) const; + void printFuncCoverage(raw_ostream &OS) const; + void printFileCoverage(raw_ostream &OS) const; + + const GCOV::Options &Options; + StringMap LineInfo; + uint32_t RunCount = 0; + uint32_t ProgramCount = 0; + + using FileCoverageList = SmallVector, 4>; + using FuncCoverageMap = MapVector; + + FileCoverageList FileCoverages; + FuncCoverageMap FuncCoverages; +}; + +} // end namespace llvm + +#endif // LLVM_SUPPORT_GCOV_H diff --git a/riscv/src/plugin/cycle_estimate.cpp b/src/plugin/cycle_estimate.cpp similarity index 100% rename from riscv/src/plugin/cycle_estimate.cpp rename to src/plugin/cycle_estimate.cpp diff --git a/riscv/src/plugin/instruction_count.cpp b/src/plugin/instruction_count.cpp similarity index 100% rename from riscv/src/plugin/instruction_count.cpp rename to src/plugin/instruction_count.cpp diff --git a/riscv/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp similarity index 100% rename from riscv/src/sysc/core_complex.cpp rename to src/sysc/core_complex.cpp diff --git a/system.json b/system.json deleted file mode 100644 index 33364c9..0000000 --- a/system.json +++ /dev/null @@ -1,34 +0,0 @@ -{ - "i_system":{ - "enableTracing" : true, - "i_motor.enableTracing" : true, - "i_h_bridge.enableTracing" : false, - "i_h_bridge.vcc" : 48.0, - "i_hifive1" : - { - "i_adc.enableTracing" : false, - "i_terminal.enableTracing" : true, - "i_terminal.write_to_ws" : false, - "i_fe310": { - "enableTracing" : false, - "i_gpio.write_to_ws": true, - "i_pwm0.enableTracing" : true, - "i_pwm0.regs.enableTracing" : true, - "i_uart0.bit_true_transfer": false, - "i_uart1":{ - "bit_true_transfer": false - }, - "i_qspi0":{ - "bit_true_transfer": false - }, - "i_qspi1":{ - "bit_true_transfer": false, - "enableTracing": true - }, - "i_qspi2":{ - "bit_true_transfer": false - } - } - } - } -} From 2758933c16a6a0d8b5ade685b0ceb44a329343be Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 11 Jun 2019 19:22:07 +0000 Subject: [PATCH 3/6] Modernized CMake --- CMakeLists.txt | 99 ++++++++++++++++++++++++++++++++++++++-- softfloat/CMakeLists.txt | 10 +--- src/CMakeLists.txt | 87 ----------------------------------- 3 files changed, 96 insertions(+), 100 deletions(-) delete mode 100644 src/CMakeLists.txt diff --git a/CMakeLists.txt b/CMakeLists.txt index 162b857..5a54eea 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -7,8 +7,6 @@ set(CMAKE_RUNTIME_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/bin") set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib") set(CMAKE_LIBRARY_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib") -add_subdirectory(softfloat) - # Set the name of your project here project("riscv") @@ -22,8 +20,7 @@ include_directories( ${SOFTFLOAT_INCLUDE_DIRS} ${LLVM_INCLUDE_DIRS} ) -add_dependent_subproject(dbt-core) -add_dependent_subproject(sc-components) + include_directories( ${PROJECT_SOURCE_DIR}/incl ${PROJECT_SOURCE_DIR}/../external/elfio @@ -39,7 +36,99 @@ set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE) set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib") set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE) -add_subdirectory(src) +add_subdirectory(softfloat) + +# library files +FILE(GLOB RiscVSCHeaders ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*.h ${CMAKE_CURRENT_SOURCE_DIR}/incl/sysc/*/*.h) +set(LIB_HEADERS ${RiscVSCHeaders} ) +set(LIB_SOURCES + src/iss/rv32gc.cpp + src/iss/rv32imac.cpp + src/iss/rv64i.cpp + src/iss/rv64gc.cpp + src/internal/fp_functions.cpp + src/internal/vm_rv32gc.cpp + src/internal/vm_rv32imac.cpp + src/internal/vm_rv64i.cpp + src/internal/vm_rv64gc.cpp + src/plugin/instruction_count.cpp + src/plugin/cycle_estimate.cpp) + +# Define two variables in order not to repeat ourselves. +set(LIBRARY_NAME riscv) + +# Define the library +add_library(${LIBRARY_NAME} ${LIB_SOURCES}) +SET(${LIBRARY_NAME} -Wl,-whole-archive -l${LIBRARY_NAME} -Wl,-no-whole-archive) +target_link_libraries(${LIBRARY_NAME} softfloat) +target_link_libraries(${LIBRARY_NAME} dbt-core) +target_link_libraries(${LIBRARY_NAME} scc) +set_target_properties(${LIBRARY_NAME} PROPERTIES + VERSION ${VERSION} # ${VERSION} was defined in the main CMakeLists. + FRAMEWORK FALSE + PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers +) +#set_property(TARGET ${LIBRARY_NAME} PROPERTY POSITION_INDEPENDENT_CODE ON) + +if(SystemC_FOUND) + set(SC_LIBRARY_NAME riscv_sc) + add_library(${SC_LIBRARY_NAME} SHARED src/sysc/core_complex.cpp) + add_definitions(-DWITH_SYSTEMC) + include_directories(${SystemC_INCLUDE_DIRS}) + + include_directories(${CCI_INCLUDE_DIRS}) + + if(SCV_FOUND) + add_definitions(-DWITH_SCV) + include_directories(${SCV_INCLUDE_DIRS}) + endif() + target_link_libraries(${SC_LIBRARY_NAME} ${LIBRARY_NAME}) + target_link_libraries(${SC_LIBRARY_NAME} dbt-core) + target_link_libraries(${SC_LIBRARY_NAME} softfloat) + target_link_libraries(${SC_LIBRARY_NAME} scc) + target_link_libraries(${SC_LIBRARY_NAME} external) + target_link_libraries(${SC_LIBRARY_NAME} ${llvm_libs}) + target_link_libraries(${SC_LIBRARY_NAME} ${Boost_LIBRARIES} ) + set_target_properties(${SC_LIBRARY_NAME} PROPERTIES + VERSION ${VERSION} # ${VERSION} was defined in the main CMakeLists. + FRAMEWORK FALSE + PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers + ) +endif() + +# This is a make target, so you can do a "make riscv-sc" +set(APPLICATION_NAME riscv-sim) + +add_executable(${APPLICATION_NAME} src/main.cpp) + +# Links the target exe against the libraries +target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME}) +target_link_libraries(${APPLICATION_NAME} jsoncpp) +target_link_libraries(${APPLICATION_NAME} dbt-core) +target_link_libraries(${APPLICATION_NAME} softfloat) +target_link_libraries(${APPLICATION_NAME} external) +target_link_libraries(${APPLICATION_NAME} ${llvm_libs}) +target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} ) +if (Tcmalloc_FOUND) + target_link_libraries(${APPLICATION_NAME} ${Tcmalloc_LIBRARIES}) +endif(Tcmalloc_FOUND) + +# Says how and where to install software +# Targets: +# * /lib/ +# * header location after install: /include//*.h +# * headers can be included by C++ code `#/Bar.hpp>` +install(TARGETS ${LIBRARY_NAME} ${APPLICATION_NAME} + EXPORT ${PROJECT_NAME}Targets # for downstream dependencies + ARCHIVE DESTINATION lib COMPONENT libs # static lib + RUNTIME DESTINATION bin COMPONENT libs # binaries + LIBRARY DESTINATION lib COMPONENT libs # shared lib + FRAMEWORK DESTINATION bin COMPONENT libs # for mac + PUBLIC_HEADER DESTINATION incl/${PROJECT_NAME} COMPONENT devel # headers for mac (note the different component -> different package) + INCLUDES DESTINATION incl # headers +) + + # # SYSTEM PACKAGING (RPM, TGZ, ...) diff --git a/softfloat/CMakeLists.txt b/softfloat/CMakeLists.txt index 90e31f8..8c13151 100644 --- a/softfloat/CMakeLists.txt +++ b/softfloat/CMakeLists.txt @@ -26,13 +26,6 @@ add_definitions( # -DTHREAD_LOCAL=__thread ) -set(SOFTFLOAT_INCLUDE_DIRS - ${PROJECT_SOURCE_DIR}/build/Linux-x86_64-GCC - ${PROJECT_SOURCE_DIR}/source/include - ${PROJECT_SOURCE_DIR}/source/${SPECIALIZATION} -) - -include_directories(${SOFTFLOAT_INCLUDE_DIRS}) set(LIB_HEADERS source/include/softfloat.h source/include/softfloat_types.h) set(PRIMITIVES @@ -354,6 +347,8 @@ set(LIBRARY_NAME softfloat) # Define the library add_library(${LIBRARY_NAME} ${LIB_SOURCES}) set_property(TARGET ${LIBRARY_NAME} PROPERTY C_STANDARD 99) +target_include_directories(${LIBRARY_NAME} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/build/Linux-x86_64-GCC) +target_include_directories(${LIBRARY_NAME} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/source/include ${CMAKE_CURRENT_SOURCE_DIR}/source/${SPECIALIZATION}) # Set the build version. It will be used in the name of the lib, with corresponding # symlinks created. SOVERSION could also be specified for api version. set_target_properties(${LIBRARY_NAME} PROPERTIES @@ -361,7 +356,6 @@ set_target_properties(${LIBRARY_NAME} PROPERTIES FRAMEWORK FALSE PUBLIC_HEADER "${LIB_HEADERS}" ) -target_include_directories (softfloat PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/source/include) # Says how and where to install software # Targets: diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt deleted file mode 100644 index 845d769..0000000 --- a/src/CMakeLists.txt +++ /dev/null @@ -1,87 +0,0 @@ -# library files -FILE(GLOB RiscVSCHeaders ${PROJECT_SOURCE_DIR}/incl/sysc/*.h ${PROJECT_SOURCE_DIR}/incl/sysc/*/*.h) -set(LIB_HEADERS ${RiscVSCHeaders} ) -set(LIB_SOURCES - iss/rv32gc.cpp - iss/rv32imac.cpp - iss/rv64i.cpp - iss/rv64gc.cpp - internal/fp_functions.cpp - internal/vm_rv32gc.cpp - internal/vm_rv32imac.cpp - internal/vm_rv64i.cpp - internal/vm_rv64gc.cpp - plugin/instruction_count.cpp - plugin/cycle_estimate.cpp) - -# Define two variables in order not to repeat ourselves. -set(LIBRARY_NAME riscv) - -# Define the library -add_library(${LIBRARY_NAME} ${LIB_SOURCES}) -SET(${LIBRARY_NAME} -Wl,-whole-archive -l${LIBRARY_NAME} -Wl,-no-whole-archive) -set_target_properties(${LIBRARY_NAME} PROPERTIES - VERSION ${VERSION} # ${VERSION} was defined in the main CMakeLists. - FRAMEWORK FALSE - PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers -) -#set_property(TARGET ${LIBRARY_NAME} PROPERTY POSITION_INDEPENDENT_CODE ON) - -if(SystemC_FOUND) - set(SC_LIBRARY_NAME riscv_sc) - add_library(${SC_LIBRARY_NAME} SHARED sysc/core_complex.cpp) - add_definitions(-DWITH_SYSTEMC) - include_directories(${SystemC_INCLUDE_DIRS}) - - include_directories(${CCI_INCLUDE_DIRS}) - - if(SCV_FOUND) - add_definitions(-DWITH_SCV) - include_directories(${SCV_INCLUDE_DIRS}) - endif() - set_target_properties(${SC_LIBRARY_NAME} PROPERTIES - VERSION ${VERSION} # ${VERSION} was defined in the main CMakeLists. - FRAMEWORK FALSE - PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers - ) - target_link_libraries(${SC_LIBRARY_NAME} ${LIBRARY_NAME}) - target_link_libraries(${SC_LIBRARY_NAME} dbt-core) - target_link_libraries(${SC_LIBRARY_NAME} softfloat) - target_link_libraries(${SC_LIBRARY_NAME} sc-components) - target_link_libraries(${SC_LIBRARY_NAME} external) - target_link_libraries(${SC_LIBRARY_NAME} ${llvm_libs}) - target_link_libraries(${SC_LIBRARY_NAME} ${Boost_LIBRARIES} ) -endif() - -# This is a make target, so you can do a "make riscv-sc" -set(APPLICATION_NAME riscv-sim) - -add_executable(${APPLICATION_NAME} main.cpp) - -# Links the target exe against the libraries -target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME}) -target_link_libraries(${APPLICATION_NAME} jsoncpp) -target_link_libraries(${APPLICATION_NAME} dbt-core) -target_link_libraries(${APPLICATION_NAME} softfloat) -target_link_libraries(${APPLICATION_NAME} external) -target_link_libraries(${APPLICATION_NAME} ${llvm_libs}) -target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} ) -if (Tcmalloc_FOUND) - target_link_libraries(${APPLICATION_NAME} ${Tcmalloc_LIBRARIES}) -endif(Tcmalloc_FOUND) - -# Says how and where to install software -# Targets: -# * /lib/ -# * header location after install: /include//*.h -# * headers can be included by C++ code `#/Bar.hpp>` -install(TARGETS ${LIBRARY_NAME} ${APPLICATION_NAME} - EXPORT ${PROJECT_NAME}Targets # for downstream dependencies - ARCHIVE DESTINATION lib COMPONENT libs # static lib - RUNTIME DESTINATION bin COMPONENT libs # binaries - LIBRARY DESTINATION lib COMPONENT libs # shared lib - FRAMEWORK DESTINATION bin COMPONENT libs # for mac - PUBLIC_HEADER DESTINATION incl/${PROJECT_NAME} COMPONENT devel # headers for mac (note the different component -> different package) - INCLUDES DESTINATION incl # headers -) - From d93c2feec4c80ece0773fb2366821d01e11db4b6 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 18 Jun 2019 19:20:43 +0000 Subject: [PATCH 4/6] Cleanup dependencies --- CMakeLists.txt | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 5a54eea..6e57ba3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -14,6 +14,8 @@ include(Common) conan_basic_setup() +find_package(Boost COMPONENTS program_options system thread filesystem REQUIRED) + # This sets the include directory for the reference project. This is the -I flag in gcc. include_directories( ${PROJECT_SOURCE_DIR}/incl @@ -62,7 +64,7 @@ add_library(${LIBRARY_NAME} ${LIB_SOURCES}) SET(${LIBRARY_NAME} -Wl,-whole-archive -l${LIBRARY_NAME} -Wl,-no-whole-archive) target_link_libraries(${LIBRARY_NAME} softfloat) target_link_libraries(${LIBRARY_NAME} dbt-core) -target_link_libraries(${LIBRARY_NAME} scc) +target_link_libraries(${LIBRARY_NAME} scc-util) set_target_properties(${LIBRARY_NAME} PROPERTIES VERSION ${VERSION} # ${VERSION} was defined in the main CMakeLists. FRAMEWORK FALSE @@ -72,7 +74,7 @@ set_target_properties(${LIBRARY_NAME} PROPERTIES if(SystemC_FOUND) set(SC_LIBRARY_NAME riscv_sc) - add_library(${SC_LIBRARY_NAME} SHARED src/sysc/core_complex.cpp) + add_library(${SC_LIBRARY_NAME} src/sysc/core_complex.cpp) add_definitions(-DWITH_SYSTEMC) include_directories(${SystemC_INCLUDE_DIRS}) @@ -96,6 +98,8 @@ if(SystemC_FOUND) ) endif() +project("riscv-sim") + # This is a make target, so you can do a "make riscv-sc" set(APPLICATION_NAME riscv-sim) @@ -105,7 +109,6 @@ add_executable(${APPLICATION_NAME} src/main.cpp) target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME}) target_link_libraries(${APPLICATION_NAME} jsoncpp) target_link_libraries(${APPLICATION_NAME} dbt-core) -target_link_libraries(${APPLICATION_NAME} softfloat) target_link_libraries(${APPLICATION_NAME} external) target_link_libraries(${APPLICATION_NAME} ${llvm_libs}) target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} ) From 7f06bba239c2f15a08c65f701e31d60d229a66cb Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Fri, 28 Jun 2019 20:58:02 +0200 Subject: [PATCH 5/6] Fixed time csr handling --- gen_input/templates/src-CORENAME.cpp.gtl | 2 +- incl/sysc/core_complex.h | 3 +++ src/iss/rv32gc.cpp | 2 +- src/iss/rv64gc.cpp | 2 +- src/iss/rv64i.cpp | 2 +- src/sysc/core_complex.cpp | 20 +++++++++++++++++++- 6 files changed, 26 insertions(+), 5 deletions(-) diff --git a/gen_input/templates/src-CORENAME.cpp.gtl b/gen_input/templates/src-CORENAME.cpp.gtl index ee9641b..6dee5fc 100644 --- a/gen_input/templates/src-CORENAME.cpp.gtl +++ b/gen_input/templates/src-CORENAME.cpp.gtl @@ -103,7 +103,7 @@ void ${coreDef.name.toLowerCase()}::reset(uint64_t address) { reg.PC=address; reg.NEXT_PC=reg.PC; reg.trap_state=0; - reg.machine_state=0x0; + reg.machine_state=0x3; reg.icount=0; } diff --git a/incl/sysc/core_complex.h b/incl/sysc/core_complex.h index 99e22f0..047f897 100644 --- a/incl/sysc/core_complex.h +++ b/incl/sysc/core_complex.h @@ -39,6 +39,7 @@ #include "scv4tlm/tlm_rec_initiator_socket.h" #include #include +#include #include #include @@ -90,6 +91,8 @@ public: sc_core::sc_vector> local_irq_i; + sc_core::sc_port, 1, sc_core::SC_ZERO_OR_MORE_BOUND> mtime_o; + cci::cci_param elf_file; cci::cci_param enable_disass; diff --git a/src/iss/rv32gc.cpp b/src/iss/rv32gc.cpp index a5f3ce7..4149503 100644 --- a/src/iss/rv32gc.cpp +++ b/src/iss/rv32gc.cpp @@ -66,7 +66,7 @@ void rv32gc::reset(uint64_t address) { reg.PC=address; reg.NEXT_PC=reg.PC; reg.trap_state=0; - reg.machine_state=0x0; + reg.machine_state=0x3; reg.icount=0; } diff --git a/src/iss/rv64gc.cpp b/src/iss/rv64gc.cpp index 8d27912..7353643 100644 --- a/src/iss/rv64gc.cpp +++ b/src/iss/rv64gc.cpp @@ -67,7 +67,7 @@ void rv64gc::reset(uint64_t address) { reg.PC=address; reg.NEXT_PC=reg.PC; reg.trap_state=0; - reg.machine_state=0x0; + reg.machine_state=0x3; reg.icount=0; } diff --git a/src/iss/rv64i.cpp b/src/iss/rv64i.cpp index 0d09f20..b3b875c 100644 --- a/src/iss/rv64i.cpp +++ b/src/iss/rv64i.cpp @@ -65,7 +65,7 @@ void rv64i::reset(uint64_t address) { reg.PC=address; reg.NEXT_PC=reg.PC; reg.trap_state=0; - reg.machine_state=0x0; + reg.machine_state=0x3; reg.icount=0; } diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp index 16166b3..ff53186 100644 --- a/src/sysc/core_complex.cpp +++ b/src/sysc/core_complex.cpp @@ -93,7 +93,9 @@ public: using base_type = arch::riscv_hart_msu_vp; using phys_addr_t = typename arch::traits::phys_addr_t; core_wrapper(core_complex *owner) - : owner(owner) {} + : owner(owner) + { + } uint32_t get_mode() { return this->reg.machine_state; } @@ -144,6 +146,22 @@ public: } } + status read_csr(unsigned addr, reg_t &val) override { + if((addr==arch::time || addr==arch::timeh) && owner->mtime_o.get_interface(0)){ + uint64_t time_val; + bool ret = owner->mtime_o->nb_peek(time_val); + if (addr == iss::arch::time) { + val = static_cast(time_val); + } else if (addr == iss::arch::timeh) { + if (sizeof(reg_t) != 4) return iss::Err; + val = static_cast(time_val >> 32); + } + return ret?Ok:Err; + } else { + return base_type::read_csr(addr, val); + } + } + void wait_until(uint64_t flags) override { SCDEBUG(owner->name()) << "Sleeping until interrupt"; do { From cc21afaaff520a5691f302986e948f98a58699ca Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Fri, 28 Jun 2019 21:24:01 +0200 Subject: [PATCH 6/6] Fixed CMakeLists.txt dependencies --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6e57ba3..9fb364a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -22,7 +22,7 @@ include_directories( ${SOFTFLOAT_INCLUDE_DIRS} ${LLVM_INCLUDE_DIRS} ) - +add_dependent_subproject(dbt-core) include_directories( ${PROJECT_SOURCE_DIR}/incl ${PROJECT_SOURCE_DIR}/../external/elfio