From e87b7d5fd00559b1023856bb8ca56edac8077c99 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Wed, 24 Jul 2024 14:48:50 +0200 Subject: [PATCH] applies clang-format --- src/iss/arch/riscv_hart_m_p.h | 109 ++++++++++++++++++++------------ src/iss/arch/riscv_hart_mu_p.h | 112 +++++++++++++++++++++------------ 2 files changed, 143 insertions(+), 78 deletions(-) diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index ea24bb4..30c15e4 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -61,7 +61,8 @@ namespace iss { namespace arch { -template class riscv_hart_m_p : public BASE, public riscv_hart_common { +template +class riscv_hart_m_p : public BASE, public riscv_hart_common { protected: const std::array lvl = {{'U', 'S', 'H', 'M'}}; const std::array trap_str = {{"" @@ -276,7 +277,7 @@ public: void disass_output(uint64_t pc, const std::string instr) override { NSCLOG(INFO, LOGCAT) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]", pc, instr, (reg_t)state.mstatus, - this->reg.icount + cycle_offset); + this->reg.icount + cycle_offset); }; iss::instrumentation_if* get_instrumentation_if() override { return &instr_if; } @@ -564,7 +565,8 @@ riscv_hart_m_p::riscv_hart_m_p(feature_config cfg) hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return this->write_mem(a, l, d); }; } -template std::pair riscv_hart_m_p::load_file(std::string name, int type) { +template +std::pair riscv_hart_m_p::load_file(std::string name, int type) { get_sym_table(name); try { tohost = symbol_table.at("tohost"); @@ -620,7 +622,7 @@ template std::pair inline void riscv_hart_m_p::insert_mem_range(uint64_t base, uint64_t size, std::function rd_f, - std::function wr_fn) { + std::function wr_fn) { std::tuple entry{base, size}; auto it = std::upper_bound( memfn_range.begin(), memfn_range.end(), entry, @@ -632,8 +634,8 @@ inline void riscv_hart_m_p::insert_mem_range(uint64_t base, } template -iss::status riscv_hart_m_p::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, - const unsigned length, uint8_t* const data) { +iss::status riscv_hart_m_p::read(const address_type type, const access_type access, const uint32_t space, + const uint64_t addr, const unsigned length, uint8_t* const data) { #ifndef NDEBUG if(access && iss::access_type::DEBUG) { CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; @@ -716,8 +718,8 @@ iss::status riscv_hart_m_p::read(const address_type type, co } template -iss::status riscv_hart_m_p::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, - const unsigned length, const uint8_t* const data) { +iss::status riscv_hart_m_p::write(const address_type type, const access_type access, const uint32_t space, + const uint64_t addr, const unsigned length, const uint8_t* const data) { #ifndef NDEBUG const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; switch(length) { @@ -848,7 +850,8 @@ iss::status riscv_hart_m_p::write(const address_type type, c } } -template iss::status riscv_hart_m_p::read_csr(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_csr(unsigned addr, reg_t& val) { if(addr >= csr.size()) return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; @@ -860,7 +863,8 @@ template iss::status riscv_har return (this->*(it->second))(addr, val); } -template iss::status riscv_hart_m_p::write_csr(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_csr(unsigned addr, reg_t val) { if(addr >= csr.size()) return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; @@ -874,22 +878,26 @@ template iss::status riscv_har return (this->*(it->second))(addr, val); } -template iss::status riscv_hart_m_p::read_csr_reg(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_csr_reg(unsigned addr, reg_t& val) { val = csr[addr]; return iss::Ok; } -template iss::status riscv_hart_m_p::read_null(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_null(unsigned addr, reg_t& val) { val = 0; return iss::Ok; } -template iss::status riscv_hart_m_p::write_csr_reg(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_csr_reg(unsigned addr, reg_t val) { csr[addr] = val; return iss::Ok; } -template iss::status riscv_hart_m_p::read_cycle(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_cycle(unsigned addr, reg_t& val) { auto cycle_val = this->reg.icount + cycle_offset; if(addr == mcycle) { val = static_cast(cycle_val); @@ -899,7 +907,8 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_m_p::write_cycle(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_cycle(unsigned addr, reg_t val) { if(sizeof(typename traits::reg_t) != 4) { mcycle_csr = static_cast(val); } else { @@ -913,7 +922,8 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_m_p::read_instret(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_instret(unsigned addr, reg_t& val) { if((addr & 0xff) == (minstret & 0xff)) { val = static_cast(this->reg.instret); } else if((addr & 0xff) == (minstreth & 0xff)) { @@ -922,7 +932,8 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_m_p::write_instret(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_instret(unsigned addr, reg_t val) { if(sizeof(typename traits::reg_t) != 4) { this->reg.instret = static_cast(val); } else { @@ -936,7 +947,8 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_m_p::read_time(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_time(unsigned addr, reg_t& val) { uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052; if(addr == time) { val = static_cast(time_val); @@ -948,23 +960,27 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_m_p::read_tvec(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_tvec(unsigned addr, reg_t& val) { val = FEAT & features_e::FEAT_CLIC ? csr[addr] : csr[addr] & ~2; return iss::Ok; } -template iss::status riscv_hart_m_p::read_status(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_status(unsigned addr, reg_t& val) { val = state.mstatus & hart_state_type::get_mask(); return iss::Ok; } -template iss::status riscv_hart_m_p::write_status(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_status(unsigned addr, reg_t val) { state.write_mstatus(val); check_interrupt(); return iss::Ok; } -template iss::status riscv_hart_m_p::read_cause(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_cause(unsigned addr, reg_t& val) { if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec] & 0x3) == 3) { val = csr[addr] & ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1) | (0xfUL << 16)); val |= clic_mprev_lvl << 16; @@ -975,7 +991,8 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_m_p::write_cause(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_cause(unsigned addr, reg_t val) { if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec] & 0x3) == 3) { auto mask = ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1) | (0xfUL << 16)); csr[addr] = (val & mask) | (csr[addr] & ~mask); @@ -989,36 +1006,42 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_m_p::read_hartid(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_hartid(unsigned addr, reg_t& val) { val = mhartid_reg; return iss::Ok; } -template iss::status riscv_hart_m_p::read_ie(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_ie(unsigned addr, reg_t& val) { auto mask = get_irq_mask(); val = csr[mie] & mask; return iss::Ok; } -template iss::status riscv_hart_m_p::write_ie(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_ie(unsigned addr, reg_t val) { auto mask = get_irq_mask(); csr[mie] = (csr[mie] & ~mask) | (val & mask); check_interrupt(); return iss::Ok; } -template iss::status riscv_hart_m_p::read_ip(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_ip(unsigned addr, reg_t& val) { auto mask = get_irq_mask(); val = csr[mip] & mask; return iss::Ok; } -template iss::status riscv_hart_m_p::write_epc(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_epc(unsigned addr, reg_t val) { csr[addr] = val & get_pc_mask(); return iss::Ok; } -template iss::status riscv_hart_m_p::write_dcsr_dcsr(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_dcsr_dcsr(unsigned addr, reg_t val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); // +-------------- ebreakm @@ -1029,45 +1052,52 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_m_p::read_dcsr_reg(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_dcsr_reg(unsigned addr, reg_t& val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); val = csr[addr]; return iss::Ok; } -template iss::status riscv_hart_m_p::write_dcsr_reg(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_dcsr_reg(unsigned addr, reg_t val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); csr[addr] = val; return iss::Ok; } -template iss::status riscv_hart_m_p::read_dpc_reg(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_dpc_reg(unsigned addr, reg_t& val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); val = this->reg.DPC; return iss::Ok; } -template iss::status riscv_hart_m_p::write_dpc_reg(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_dpc_reg(unsigned addr, reg_t val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); this->reg.DPC = val; return iss::Ok; } -template iss::status riscv_hart_m_p::read_intstatus(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_m_p::read_intstatus(unsigned addr, reg_t& val) { val = (clic_mact_lvl & 0xff) << 24; return iss::Ok; } -template iss::status riscv_hart_m_p::write_intthresh(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_intthresh(unsigned addr, reg_t val) { csr[addr] = (val & 0xff) | (1 << (cfg.clic_int_ctl_bits)) - 1; return iss::Ok; } -template iss::status riscv_hart_m_p::write_xtvt(unsigned addr, reg_t val) { +template +iss::status riscv_hart_m_p::write_xtvt(unsigned addr, reg_t val) { csr[addr] = val & ~0x3fULL; return iss::Ok; } @@ -1207,7 +1237,8 @@ template void riscv_hart_m_p uint64_t riscv_hart_m_p::enter_trap(uint64_t flags, uint64_t addr, uint64_t tval) { +template +uint64_t riscv_hart_m_p::enter_trap(uint64_t flags, uint64_t addr, uint64_t tval) { // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0] // calculate and write mcause val auto const trap_id = bit_sub<0, 16>(flags); @@ -1317,8 +1348,8 @@ template uint64_t riscv_hart_m #endif if((flags & 0xffffffff) != 0xffffffff) NSCLOG(INFO, LOGCAT) << (trap_id ? "Interrupt" : "Trap") << " with cause '" << (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" - << cause << ")" - << " at address " << buffer.data() << " occurred"; + << cause << ")" + << " at address " << buffer.data() << " occurred"; return this->reg.NEXT_PC; } diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index fc27466..09a213b 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -60,7 +60,8 @@ namespace iss { namespace arch { -template class riscv_hart_mu_p : public BASE, public riscv_hart_common { +template +class riscv_hart_mu_p : public BASE, public riscv_hart_common { protected: const std::array lvl = {{'U', 'S', 'H', 'M'}}; const std::array trap_str = {{"" @@ -641,7 +642,8 @@ riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg) hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status { return this->write_mem(a, l, d); }; } -template std::pair riscv_hart_mu_p::load_file(std::string name, int type) { +template +std::pair riscv_hart_mu_p::load_file(std::string name, int type) { FILE* fp = fopen(name.c_str(), "r"); if(fp) { std::array buf; @@ -711,7 +713,7 @@ template std::pair inline void riscv_hart_mu_p::insert_mem_range(uint64_t base, uint64_t size, std::function rd_f, - std::function wr_fn) { + std::function wr_fn) { std::tuple entry{base, size}; auto it = std::upper_bound( memfn_range.begin(), memfn_range.end(), entry, @@ -722,7 +724,8 @@ inline void riscv_hart_mu_p::insert_mem_range(uint64_t base, memfn_write.insert(std::begin(memfn_write) + idx, wr_fn); } -template inline iss::status riscv_hart_mu_p::write_pmpcfg_reg(unsigned addr, reg_t val) { +template +inline iss::status riscv_hart_mu_p::write_pmpcfg_reg(unsigned addr, reg_t val) { csr[addr] = val & 0x9f9f9f9f; return iss::Ok; } @@ -809,8 +812,8 @@ bool riscv_hart_mu_p::pmp_check(const access_type type, cons } template -iss::status riscv_hart_mu_p::read(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, - const unsigned length, uint8_t* const data) { +iss::status riscv_hart_mu_p::read(const address_type type, const access_type access, const uint32_t space, + const uint64_t addr, const unsigned length, uint8_t* const data) { #ifndef NDEBUG if(access && iss::access_type::DEBUG) { CPPLOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr; @@ -902,8 +905,8 @@ iss::status riscv_hart_mu_p::read(const address_type type, c } template -iss::status riscv_hart_mu_p::write(const address_type type, const access_type access, const uint32_t space, const uint64_t addr, - const unsigned length, const uint8_t* const data) { +iss::status riscv_hart_mu_p::write(const address_type type, const access_type access, const uint32_t space, + const uint64_t addr, const unsigned length, const uint8_t* const data) { #ifndef NDEBUG const char* prefix = (access && iss::access_type::DEBUG) ? "debug " : ""; switch(length) { @@ -1043,7 +1046,8 @@ iss::status riscv_hart_mu_p::write(const address_type type, } } -template iss::status riscv_hart_mu_p::read_csr(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_csr(unsigned addr, reg_t& val) { if(addr >= csr.size()) return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; @@ -1055,7 +1059,8 @@ template iss::status riscv_har return (this->*(it->second))(addr, val); } -template iss::status riscv_hart_mu_p::write_csr(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_csr(unsigned addr, reg_t val) { if(addr >= csr.size()) return iss::Err; auto req_priv_lvl = (addr >> 8) & 0x3; @@ -1069,22 +1074,26 @@ template iss::status riscv_har return (this->*(it->second))(addr, val); } -template iss::status riscv_hart_mu_p::read_csr_reg(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_csr_reg(unsigned addr, reg_t& val) { val = csr[addr]; return iss::Ok; } -template iss::status riscv_hart_mu_p::read_null(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_null(unsigned addr, reg_t& val) { val = 0; return iss::Ok; } -template iss::status riscv_hart_mu_p::write_csr_reg(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_csr_reg(unsigned addr, reg_t val) { csr[addr] = val; return iss::Ok; } -template iss::status riscv_hart_mu_p::read_cycle(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_cycle(unsigned addr, reg_t& val) { auto cycle_val = this->reg.icount + cycle_offset; if(addr == mcycle) { val = static_cast(cycle_val); @@ -1094,7 +1103,8 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_mu_p::write_cycle(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_cycle(unsigned addr, reg_t val) { if(sizeof(typename traits::reg_t) != 4) { mcycle_csr = static_cast(val); } else { @@ -1108,7 +1118,8 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_mu_p::read_instret(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_instret(unsigned addr, reg_t& val) { if((addr & 0xff) == (minstret & 0xff)) { val = static_cast(this->reg.instret); } else if((addr & 0xff) == (minstreth & 0xff)) { @@ -1117,7 +1128,8 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_mu_p::write_instret(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_instret(unsigned addr, reg_t val) { if(sizeof(typename traits::reg_t) != 4) { this->reg.instret = static_cast(val); } else { @@ -1131,7 +1143,8 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_mu_p::read_time(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_time(unsigned addr, reg_t& val) { uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052; if(addr == time) { val = static_cast(time_val); @@ -1143,22 +1156,26 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_mu_p::read_tvec(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_tvec(unsigned addr, reg_t& val) { val = FEAT & features_e::FEAT_CLIC ? csr[addr] : csr[addr] & ~2; return iss::Ok; } -template iss::status riscv_hart_mu_p::read_status(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_status(unsigned addr, reg_t& val) { val = state.mstatus & hart_state_type::get_mask((addr >> 8) & 0x3); return iss::Ok; } -template iss::status riscv_hart_mu_p::write_status(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_status(unsigned addr, reg_t val) { state.write_mstatus(val, (addr >> 8) & 0x3); check_interrupt(); return iss::Ok; } -template iss::status riscv_hart_mu_p::read_cause(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_cause(unsigned addr, reg_t& val) { if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec] & 0x3) == 3) { val = csr[addr] & ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1) | (0xfUL << 16)); auto mode = (addr >> 8) & 0x3; @@ -1178,7 +1195,8 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_mu_p::write_cause(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_cause(unsigned addr, reg_t val) { if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec] & 0x3) == 3) { auto mask = ((1UL << (traits::XLEN - 1)) | (mcause_max_irq - 1) | (0xfUL << 16)); csr[addr] = (val & mask) | (csr[addr] & ~mask); @@ -1201,12 +1219,14 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_mu_p::read_hartid(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_hartid(unsigned addr, reg_t& val) { val = mhartid_reg; return iss::Ok; } -template iss::status riscv_hart_mu_p::read_ie(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_ie(unsigned addr, reg_t& val) { auto mask = get_irq_mask((addr >> 8) & 0x3); val = csr[mie] & mask; if(this->reg.PRIV != 3) @@ -1214,14 +1234,16 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_mu_p::write_ie(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_ie(unsigned addr, reg_t val) { auto mask = get_irq_mask((addr >> 8) & 0x3); csr[mie] = (csr[mie] & ~mask) | (val & mask); check_interrupt(); return iss::Ok; } -template iss::status riscv_hart_mu_p::read_ip(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_ip(unsigned addr, reg_t& val) { auto mask = get_irq_mask((addr >> 8) & 0x3); val = csr[mip] & mask; if(this->reg.PRIV != 3) @@ -1229,24 +1251,28 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_mu_p::write_ideleg(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_ideleg(unsigned addr, reg_t val) { auto mask = 0b000100010001; // only U mode supported csr[mideleg] = (csr[mideleg] & ~mask) | (val & mask); return iss::Ok; } -template iss::status riscv_hart_mu_p::write_edeleg(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_edeleg(unsigned addr, reg_t val) { auto mask = 0b1011001111110111; // bit 14/10 (reserved), bit 11 (Env call), and 3 (break) are hardwired to 0 csr[medeleg] = (csr[medeleg] & ~mask) | (val & mask); return iss::Ok; } -template iss::status riscv_hart_mu_p::write_epc(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_epc(unsigned addr, reg_t val) { csr[addr] = val & get_pc_mask(); return iss::Ok; } -template iss::status riscv_hart_mu_p::write_dcsr_dcsr(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_dcsr_dcsr(unsigned addr, reg_t val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); // +-------------- ebreakm @@ -1257,35 +1283,40 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_mu_p::read_dcsr_reg(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_dcsr_reg(unsigned addr, reg_t& val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); val = csr[addr]; return iss::Ok; } -template iss::status riscv_hart_mu_p::write_dcsr_reg(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_dcsr_reg(unsigned addr, reg_t val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); csr[addr] = val; return iss::Ok; } -template iss::status riscv_hart_mu_p::read_dpc_reg(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_dpc_reg(unsigned addr, reg_t& val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); val = this->reg.DPC; return iss::Ok; } -template iss::status riscv_hart_mu_p::write_dpc_reg(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_dpc_reg(unsigned addr, reg_t val) { if(!debug_mode_active()) throw illegal_instruction_fault(this->fault_data); this->reg.DPC = val; return iss::Ok; } -template iss::status riscv_hart_mu_p::read_intstatus(unsigned addr, reg_t& val) { +template +iss::status riscv_hart_mu_p::read_intstatus(unsigned addr, reg_t& val) { auto mode = (addr >> 8) & 0x3; val = clic_uact_lvl & 0xff; if(mode == 0x3) @@ -1293,12 +1324,14 @@ template iss::status riscv_har return iss::Ok; } -template iss::status riscv_hart_mu_p::write_intthresh(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_intthresh(unsigned addr, reg_t val) { csr[addr] = (val & 0xff) | (1 << (cfg.clic_int_ctl_bits)) - 1; return iss::Ok; } -template iss::status riscv_hart_mu_p::write_xtvt(unsigned addr, reg_t val) { +template +iss::status riscv_hart_mu_p::write_xtvt(unsigned addr, reg_t val) { csr[addr] = val & ~0x3fULL; return iss::Ok; } @@ -1441,7 +1474,8 @@ template void riscv_hart_mu_p< } } -template uint64_t riscv_hart_mu_p::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) { +template +uint64_t riscv_hart_mu_p::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) { // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0] // calculate and write mcause val if(flags == std::numeric_limits::max())