From e6f11081eba931b8d2a783939fa13f60448e6404 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Fri, 27 Oct 2023 21:12:49 +0200
Subject: [PATCH] fixes quantum and quantum break handling

---
 src/sysc/core_complex.cpp  | 30 +++++++++++++++++++++---------
 src/sysc/core_complex.h    | 14 +++++++++-----
 src/sysc/sc_core_adapter.h | 10 ++++++++--
 3 files changed, 38 insertions(+), 16 deletions(-)

diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 0689b59..faa878a 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -391,7 +391,10 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
     if (lut_entry.get_granted_access() != tlm::tlm_dmi::DMI_ACCESS_NONE && addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
         std::copy(lut_entry.get_dmi_ptr() + offset, lut_entry.get_dmi_ptr() + offset + length, data);
-        quantum_keeper.inc(lut_entry.get_read_latency());
+        if(is_fetch)
+            ibus_inc+=lut_entry.get_read_latency()/curr_clk;
+        else
+            dbus_inc+=lut_entry.get_read_latency()/curr_clk;
         return true;
     } else {
         auto& sckt = is_fetch? ibus : dbus;
@@ -409,12 +412,17 @@ bool core_complex::read_mem(uint64_t addr, unsigned length, uint8_t *const data,
             auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
-        sckt->b_transport(gp, delay);
-        auto incr = delay-quantum_keeper.get_local_time();
-        if(is_fetch)
-            ibus_inc+=incr;
-        else
-            dbus_inc+=incr;
+        auto pre_delay = delay;
+        dbus->b_transport(gp, delay);
+        if(pre_delay>delay) {
+            quantum_keeper.reset();
+        } else {
+            auto incr = (delay-quantum_keeper.get_local_time())/curr_clk;
+            if(is_fetch)
+                ibus_inc+=incr;
+            else
+                dbus_inc+=incr;
+        }
         SCCTRACE(this->name()) << "[local time: "<<delay<<"]: finish read_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
@@ -439,7 +447,7 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
         addr + length <= lut_entry.get_end_address() + 1) {
         auto offset = addr - lut_entry.get_start_address();
         std::copy(data, data + length, lut_entry.get_dmi_ptr() + offset);
-        quantum_keeper.inc(lut_entry.get_read_latency());
+        dbus_inc+=lut_entry.get_write_latency()/curr_clk;
         return true;
     } else {
         write_buf.resize(length);
@@ -455,8 +463,12 @@ bool core_complex::write_mem(uint64_t addr, unsigned length, const uint8_t *cons
             auto preExt = new tlm::scc::scv::tlm_recording_extension(trc->tr_handle, this);
             gp.set_extension(preExt);
         }
+        auto pre_delay = delay;
         dbus->b_transport(gp, delay);
-        dbus_inc+=delay-quantum_keeper.get_local_time();
+        if(pre_delay>delay)
+            quantum_keeper.reset();
+        else
+            dbus_inc+=(delay-quantum_keeper.get_local_time())/curr_clk;
         SCCTRACE() << "[local time: "<<delay<<"]: finish write_mem(0x" << std::hex << addr << ") : 0x" << (length==4?*(uint32_t*)data:length==2?*(uint16_t*)data:(unsigned)*data);
         if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
             return false;
diff --git a/src/sysc/core_complex.h b/src/sysc/core_complex.h
index ec3a05a..e477639 100644
--- a/src/sysc/core_complex.h
+++ b/src/sysc/core_complex.h
@@ -156,17 +156,21 @@ public:
 
     ~core_complex();
 
+
+    inline unsigned get_last_bus_cycles() {
+        auto mem_incr = std::max(ibus_inc, dbus_inc);
+        ibus_inc = dbus_inc = 0;
+	    return mem_incr>1?mem_incr:1;
+    }
+
     inline void sync(uint64_t cycle) {
         auto core_inc = curr_clk * (cycle - last_sync_cycle);
-        auto incr = std::max(core_inc, std::max(ibus_inc, dbus_inc));
-        quantum_keeper.inc(incr);
+        quantum_keeper.inc(core_inc);
         if (quantum_keeper.need_sync()) {
             wait(quantum_keeper.get_local_time());
             quantum_keeper.reset();
         }
         last_sync_cycle = cycle;
-        ibus_inc = sc_core::SC_ZERO_TIME;
-        dbus_inc = sc_core::SC_ZERO_TIME;
     }
 
     bool read_mem(uint64_t addr, unsigned length, uint8_t *const data, bool is_fetch);
@@ -198,7 +202,7 @@ protected:
     std::vector<uint8_t> write_buf;
     core_wrapper* cpu{nullptr};
     sc_core::sc_signal<sc_core::sc_time> curr_clk;
-    sc_core::sc_time ibus_inc, dbus_inc;
+    uint64_t ibus_inc{0}, dbus_inc{0};
     core_trace* trc{nullptr};
     std::unique_ptr<scc::tick2time> t2t;
 private:
diff --git a/src/sysc/sc_core_adapter.h b/src/sysc/sc_core_adapter.h
index 4b937ac..b544791 100644
--- a/src/sysc/sc_core_adapter.h
+++ b/src/sysc/sc_core_adapter.h
@@ -39,8 +39,13 @@ public:
     uint64_t get_state() override { return this->state.mstatus.backing.val; }
 
     void notify_phase(iss::arch_if::exec_phase p) override {
-        if (p == iss::arch_if::ISTART)
+        if (p == iss::arch_if::ISTART && !first) {
+            auto cycle_incr = owner->get_last_bus_cycles();
+            if(cycle_incr>1)
+                this->instr_if.update_last_instr_cycles(cycle_incr);
             owner->sync(this->instr_if.get_total_cycles());
+        }
+        first=false;
     }
 
     iss::sync_type needed_sync() const override { return iss::PRE_SYNC; }
@@ -175,8 +180,9 @@ public:
 private:
     sysc::tgfs::core_complex *const owner;
     sc_core::sc_event wfi_evt;
-    uint64_t hostvar;
+    uint64_t hostvar{std::numeric_limits<uint64_t>::max()};
     unsigned to_host_wr_cnt = 0;
+    bool first{true};
 };
 }
 #endif /* _SYSC_SC_CORE_ADAPTER_H_ */