From d0f3a120fdc87c8d675dac9f3b0170243113c804 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Mon, 19 Jul 2021 16:26:23 +0200 Subject: [PATCH] fix naming in MU wrapper --- incl/iss/arch/riscv_hart_mu_p.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/incl/iss/arch/riscv_hart_mu_p.h b/incl/iss/arch/riscv_hart_mu_p.h index c7f5b2f..7a7267a 100644 --- a/incl/iss/arch/riscv_hart_mu_p.h +++ b/incl/iss/arch/riscv_hart_mu_p.h @@ -666,7 +666,7 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_m_p::read_null(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_null(unsigned addr, reg_t &val) { val = 0; return iss::Ok; } @@ -687,7 +687,7 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_m_p::write_cycle(unsigned addr, reg_t val) { +template iss::status riscv_hart_mu_p::write_cycle(unsigned addr, reg_t val) { if (sizeof(typename traits::reg_t) != 4) { if (addr == mcycleh) return iss::Err; @@ -703,7 +703,7 @@ template iss::status riscv_hart_m_p return iss::Ok; } -template iss::status riscv_hart_m_p::read_instret(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_instret(unsigned addr, reg_t &val) { if ((addr&0xff) == (minstret&0xff)) { val = static_cast(this->reg.instret); } else if ((addr&0xff) == (minstreth&0xff)) { @@ -713,7 +713,7 @@ template iss::status riscv_hart_m_p return iss::Ok; } -template iss::status riscv_hart_m_p::write_instret(unsigned addr, reg_t val) { +template iss::status riscv_hart_mu_p::write_instret(unsigned addr, reg_t val) { if (sizeof(typename traits::reg_t) != 4) { if ((addr&0xff) == (minstreth&0xff)) return iss::Err; @@ -740,7 +740,7 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_m_p::read_mtvec(unsigned addr, reg_t &val) { +template iss::status riscv_hart_mu_p::read_mtvec(unsigned addr, reg_t &val) { val = csr[mtvec] & ~2; return iss::Ok; } @@ -791,7 +791,7 @@ template iss::status riscv_hart_mu_p iss::status riscv_hart_m_p::write_mepc(unsigned addr, reg_t val) { +template iss::status riscv_hart_mu_p::write_mepc(unsigned addr, reg_t val) { auto mask = get_pc_mask(); csr[addr] = val;//(csr[addr] & ~mask) | (val & mask); return iss::Ok;