diff --git a/src/vm/tcc/vm_mnrv32.cpp b/src/vm/tcc/vm_mnrv32.cpp index 69719f4..67bd5ef 100644 --- a/src/vm/tcc/vm_mnrv32.cpp +++ b/src/vm/tcc/vm_mnrv32.cpp @@ -184,165 +184,165 @@ private: const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ - /* instruction LUI */ + /* instruction LUI, encoding '.........................0110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, - /* instruction AUIPC */ + /* instruction AUIPC, encoding '.........................0010111' */ {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, - /* instruction JAL */ + /* instruction JAL, encoding '.........................1101111' */ {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, - /* instruction JALR */ + /* instruction JALR, encoding '.................000.....1100111' */ {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, - /* instruction BEQ */ + /* instruction BEQ, encoding '.................000.....1100011' */ {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, - /* instruction BNE */ + /* instruction BNE, encoding '.................001.....1100011' */ {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne}, - /* instruction BLT */ + /* instruction BLT, encoding '.................100.....1100011' */ {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt}, - /* instruction BGE */ + /* instruction BGE, encoding '.................101.....1100011' */ {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge}, - /* instruction BLTU */ + /* instruction BLTU, encoding '.................110.....1100011' */ {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu}, - /* instruction BGEU */ + /* instruction BGEU, encoding '.................111.....1100011' */ {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu}, - /* instruction LB */ + /* instruction LB, encoding '.................000.....0000011' */ {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb}, - /* instruction LH */ + /* instruction LH, encoding '.................001.....0000011' */ {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh}, - /* instruction LW */ + /* instruction LW, encoding '.................010.....0000011' */ {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw}, - /* instruction LBU */ + /* instruction LBU, encoding '.................100.....0000011' */ {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu}, - /* instruction LHU */ + /* instruction LHU, encoding '.................101.....0000011' */ {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu}, - /* instruction SB */ + /* instruction SB, encoding '.................000.....0100011' */ {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb}, - /* instruction SH */ + /* instruction SH, encoding '.................001.....0100011' */ {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh}, - /* instruction SW */ + /* instruction SW, encoding '.................010.....0100011' */ {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw}, - /* instruction ADDI */ + /* instruction ADDI, encoding '.................000.....0010011' */ {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi}, - /* instruction SLTI */ + /* instruction SLTI, encoding '.................010.....0010011' */ {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti}, - /* instruction SLTIU */ + /* instruction SLTIU, encoding '.................011.....0010011' */ {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu}, - /* instruction XORI */ + /* instruction XORI, encoding '.................100.....0010011' */ {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori}, - /* instruction ORI */ + /* instruction ORI, encoding '.................110.....0010011' */ {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori}, - /* instruction ANDI */ + /* instruction ANDI, encoding '.................111.....0010011' */ {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi}, - /* instruction SLLI */ + /* instruction SLLI, encoding '0000000..........001.....0010011' */ {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli}, - /* instruction SRLI */ + /* instruction SRLI, encoding '0000000..........101.....0010011' */ {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli}, - /* instruction SRAI */ + /* instruction SRAI, encoding '0100000..........101.....0010011' */ {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai}, - /* instruction ADD */ + /* instruction ADD, encoding '0000000..........000.....0110011' */ {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add}, - /* instruction SUB */ + /* instruction SUB, encoding '0100000..........000.....0110011' */ {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub}, - /* instruction SLL */ + /* instruction SLL, encoding '0000000..........001.....0110011' */ {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll}, - /* instruction SLT */ + /* instruction SLT, encoding '0000000..........010.....0110011' */ {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt}, - /* instruction SLTU */ + /* instruction SLTU, encoding '0000000..........011.....0110011' */ {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu}, - /* instruction XOR */ + /* instruction XOR, encoding '0000000..........100.....0110011' */ {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor}, - /* instruction SRL */ + /* instruction SRL, encoding '0000000..........101.....0110011' */ {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl}, - /* instruction SRA */ + /* instruction SRA, encoding '0100000..........101.....0110011' */ {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra}, - /* instruction OR */ + /* instruction OR, encoding '0000000..........110.....0110011' */ {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or}, - /* instruction AND */ + /* instruction AND, encoding '0000000..........111.....0110011' */ {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and}, - /* instruction FENCE */ + /* instruction FENCE, encoding '0000.............000.....0001111' */ {32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence}, - /* instruction FENCE_I */ + /* instruction FENCE_I, encoding '.................001.....0001111' */ {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i}, - /* instruction ECALL */ + /* instruction ECALL, encoding '00000000000000000000000001110011' */ {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall}, - /* instruction EBREAK */ + /* instruction EBREAK, encoding '00000000000100000000000001110011' */ {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak}, - /* instruction URET */ + /* instruction URET, encoding '00000000001000000000000001110011' */ {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret}, - /* instruction SRET */ + /* instruction SRET, encoding '00010000001000000000000001110011' */ {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret}, - /* instruction MRET */ + /* instruction MRET, encoding '00110000001000000000000001110011' */ {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret}, - /* instruction WFI */ + /* instruction WFI, encoding '00010000010100000000000001110011' */ {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi}, - /* instruction SFENCE.VMA */ + /* instruction SFENCE.VMA, encoding '0001001..........000000001110011' */ {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma}, - /* instruction CSRRW */ + /* instruction CSRRW, encoding '.................001.....1110011' */ {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw}, - /* instruction CSRRS */ + /* instruction CSRRS, encoding '.................010.....1110011' */ {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs}, - /* instruction CSRRC */ + /* instruction CSRRC, encoding '.................011.....1110011' */ {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc}, - /* instruction CSRRWI */ + /* instruction CSRRWI, encoding '.................101.....1110011' */ {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi}, - /* instruction CSRRSI */ + /* instruction CSRRSI, encoding '.................110.....1110011' */ {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi}, - /* instruction CSRRCI */ + /* instruction CSRRCI, encoding '.................111.....1110011' */ {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci}, - /* instruction C.ADDI4SPN */ + /* instruction C.ADDI4SPN, encoding '000...........00' */ {16, 0b0000000000000000, 0b1110000000000011, &this_class::__c_addi4spn}, - /* instruction C.LW */ + /* instruction C.LW, encoding '010...........00' */ {16, 0b0100000000000000, 0b1110000000000011, &this_class::__c_lw}, - /* instruction C.SW */ + /* instruction C.SW, encoding '110...........00' */ {16, 0b1100000000000000, 0b1110000000000011, &this_class::__c_sw}, - /* instruction C.ADDI */ + /* instruction C.ADDI, encoding '000...........01' */ {16, 0b0000000000000001, 0b1110000000000011, &this_class::__c_addi}, - /* instruction C.NOP */ + /* instruction C.NOP, encoding '0000000000000001' */ {16, 0b0000000000000001, 0b1111111111111111, &this_class::__c_nop}, - /* instruction C.JAL */ + /* instruction C.JAL, encoding '001...........01' */ {16, 0b0010000000000001, 0b1110000000000011, &this_class::__c_jal}, - /* instruction C.LI */ + /* instruction C.LI, encoding '010...........01' */ {16, 0b0100000000000001, 0b1110000000000011, &this_class::__c_li}, - /* instruction C.LUI */ + /* instruction C.LUI, encoding '011...........01' */ {16, 0b0110000000000001, 0b1110000000000011, &this_class::__c_lui}, - /* instruction C.ADDI16SP */ + /* instruction C.ADDI16SP, encoding '011.00010.....01' */ {16, 0b0110000100000001, 0b1110111110000011, &this_class::__c_addi16sp}, - /* instruction C.SRLI */ + /* instruction C.SRLI, encoding '100000........01' */ {16, 0b1000000000000001, 0b1111110000000011, &this_class::__c_srli}, - /* instruction C.SRAI */ + /* instruction C.SRAI, encoding '100001........01' */ {16, 0b1000010000000001, 0b1111110000000011, &this_class::__c_srai}, - /* instruction C.ANDI */ + /* instruction C.ANDI, encoding '100.10........01' */ {16, 0b1000100000000001, 0b1110110000000011, &this_class::__c_andi}, - /* instruction C.SUB */ + /* instruction C.SUB, encoding '100011...00...01' */ {16, 0b1000110000000001, 0b1111110001100011, &this_class::__c_sub}, - /* instruction C.XOR */ + /* instruction C.XOR, encoding '100011...01...01' */ {16, 0b1000110000100001, 0b1111110001100011, &this_class::__c_xor}, - /* instruction C.OR */ + /* instruction C.OR, encoding '100011...10...01' */ {16, 0b1000110001000001, 0b1111110001100011, &this_class::__c_or}, - /* instruction C.AND */ + /* instruction C.AND, encoding '100011...11...01' */ {16, 0b1000110001100001, 0b1111110001100011, &this_class::__c_and}, - /* instruction C.J */ + /* instruction C.J, encoding '101...........01' */ {16, 0b1010000000000001, 0b1110000000000011, &this_class::__c_j}, - /* instruction C.BEQZ */ + /* instruction C.BEQZ, encoding '110...........01' */ {16, 0b1100000000000001, 0b1110000000000011, &this_class::__c_beqz}, - /* instruction C.BNEZ */ + /* instruction C.BNEZ, encoding '111...........01' */ {16, 0b1110000000000001, 0b1110000000000011, &this_class::__c_bnez}, - /* instruction C.SLLI */ + /* instruction C.SLLI, encoding '0000..........10' */ {16, 0b0000000000000010, 0b1111000000000011, &this_class::__c_slli}, - /* instruction C.LWSP */ + /* instruction C.LWSP, encoding '010...........10' */ {16, 0b0100000000000010, 0b1110000000000011, &this_class::__c_lwsp}, - /* instruction C.MV */ + /* instruction C.MV, encoding '1000..........10' */ {16, 0b1000000000000010, 0b1111000000000011, &this_class::__c_mv}, - /* instruction C.JR */ + /* instruction C.JR, encoding '1000.....0000010' */ {16, 0b1000000000000010, 0b1111000001111111, &this_class::__c_jr}, - /* instruction C.ADD */ + /* instruction C.ADD, encoding '1001..........10' */ {16, 0b1001000000000010, 0b1111000000000011, &this_class::__c_add}, - /* instruction C.JALR */ + /* instruction C.JALR, encoding '1001.....0000010' */ {16, 0b1001000000000010, 0b1111000001111111, &this_class::__c_jalr}, - /* instruction C.EBREAK */ + /* instruction C.EBREAK, encoding '1001000000000010' */ {16, 0b1001000000000010, 0b1111111111111111, &this_class::__c_ebreak}, - /* instruction C.SWSP */ + /* instruction C.SWSP, encoding '110...........10' */ {16, 0b1100000000000010, 0b1110000000000011, &this_class::__c_swsp}, - /* instruction DII */ + /* instruction DII, encoding '0000000000000000' */ {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, }}; diff --git a/src/vm/tcc/vm_rv32gc.cpp b/src/vm/tcc/vm_rv32gc.cpp index 6ec5597..7b7a858 100644 --- a/src/vm/tcc/vm_rv32gc.cpp +++ b/src/vm/tcc/vm_rv32gc.cpp @@ -184,323 +184,323 @@ private: const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ - /* instruction LUI */ + /* instruction LUI, encoding '.........................0110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, - /* instruction AUIPC */ + /* instruction AUIPC, encoding '.........................0010111' */ {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, - /* instruction JAL */ + /* instruction JAL, encoding '.........................1101111' */ {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, - /* instruction JALR */ + /* instruction JALR, encoding '.................000.....1100111' */ {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, - /* instruction BEQ */ + /* instruction BEQ, encoding '.................000.....1100011' */ {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, - /* instruction BNE */ + /* instruction BNE, encoding '.................001.....1100011' */ {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne}, - /* instruction BLT */ + /* instruction BLT, encoding '.................100.....1100011' */ {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt}, - /* instruction BGE */ + /* instruction BGE, encoding '.................101.....1100011' */ {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge}, - /* instruction BLTU */ + /* instruction BLTU, encoding '.................110.....1100011' */ {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu}, - /* instruction BGEU */ + /* instruction BGEU, encoding '.................111.....1100011' */ {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu}, - /* instruction LB */ + /* instruction LB, encoding '.................000.....0000011' */ {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb}, - /* instruction LH */ + /* instruction LH, encoding '.................001.....0000011' */ {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh}, - /* instruction LW */ + /* instruction LW, encoding '.................010.....0000011' */ {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw}, - /* instruction LBU */ + /* instruction LBU, encoding '.................100.....0000011' */ {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu}, - /* instruction LHU */ + /* instruction LHU, encoding '.................101.....0000011' */ {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu}, - /* instruction SB */ + /* instruction SB, encoding '.................000.....0100011' */ {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb}, - /* instruction SH */ + /* instruction SH, encoding '.................001.....0100011' */ {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh}, - /* instruction SW */ + /* instruction SW, encoding '.................010.....0100011' */ {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw}, - /* instruction ADDI */ + /* instruction ADDI, encoding '.................000.....0010011' */ {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi}, - /* instruction SLTI */ + /* instruction SLTI, encoding '.................010.....0010011' */ {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti}, - /* instruction SLTIU */ + /* instruction SLTIU, encoding '.................011.....0010011' */ {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu}, - /* instruction XORI */ + /* instruction XORI, encoding '.................100.....0010011' */ {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori}, - /* instruction ORI */ + /* instruction ORI, encoding '.................110.....0010011' */ {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori}, - /* instruction ANDI */ + /* instruction ANDI, encoding '.................111.....0010011' */ {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi}, - /* instruction SLLI */ + /* instruction SLLI, encoding '0000000..........001.....0010011' */ {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli}, - /* instruction SRLI */ + /* instruction SRLI, encoding '0000000..........101.....0010011' */ {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli}, - /* instruction SRAI */ + /* instruction SRAI, encoding '0100000..........101.....0010011' */ {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai}, - /* instruction ADD */ + /* instruction ADD, encoding '0000000..........000.....0110011' */ {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add}, - /* instruction SUB */ + /* instruction SUB, encoding '0100000..........000.....0110011' */ {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub}, - /* instruction SLL */ + /* instruction SLL, encoding '0000000..........001.....0110011' */ {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll}, - /* instruction SLT */ + /* instruction SLT, encoding '0000000..........010.....0110011' */ {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt}, - /* instruction SLTU */ + /* instruction SLTU, encoding '0000000..........011.....0110011' */ {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu}, - /* instruction XOR */ + /* instruction XOR, encoding '0000000..........100.....0110011' */ {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor}, - /* instruction SRL */ + /* instruction SRL, encoding '0000000..........101.....0110011' */ {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl}, - /* instruction SRA */ + /* instruction SRA, encoding '0100000..........101.....0110011' */ {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra}, - /* instruction OR */ + /* instruction OR, encoding '0000000..........110.....0110011' */ {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or}, - /* instruction AND */ + /* instruction AND, encoding '0000000..........111.....0110011' */ {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and}, - /* instruction FENCE */ + /* instruction FENCE, encoding '0000.............000.....0001111' */ {32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence}, - /* instruction FENCE_I */ + /* instruction FENCE_I, encoding '.................001.....0001111' */ {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i}, - /* instruction ECALL */ + /* instruction ECALL, encoding '00000000000000000000000001110011' */ {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall}, - /* instruction EBREAK */ + /* instruction EBREAK, encoding '00000000000100000000000001110011' */ {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak}, - /* instruction URET */ + /* instruction URET, encoding '00000000001000000000000001110011' */ {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret}, - /* instruction SRET */ + /* instruction SRET, encoding '00010000001000000000000001110011' */ {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret}, - /* instruction MRET */ + /* instruction MRET, encoding '00110000001000000000000001110011' */ {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret}, - /* instruction WFI */ + /* instruction WFI, encoding '00010000010100000000000001110011' */ {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi}, - /* instruction SFENCE.VMA */ + /* instruction SFENCE.VMA, encoding '0001001..........000000001110011' */ {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma}, - /* instruction CSRRW */ + /* instruction CSRRW, encoding '.................001.....1110011' */ {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw}, - /* instruction CSRRS */ + /* instruction CSRRS, encoding '.................010.....1110011' */ {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs}, - /* instruction CSRRC */ + /* instruction CSRRC, encoding '.................011.....1110011' */ {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc}, - /* instruction CSRRWI */ + /* instruction CSRRWI, encoding '.................101.....1110011' */ {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi}, - /* instruction CSRRSI */ + /* instruction CSRRSI, encoding '.................110.....1110011' */ {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi}, - /* instruction CSRRCI */ + /* instruction CSRRCI, encoding '.................111.....1110011' */ {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci}, - /* instruction MUL */ + /* instruction MUL, encoding '0000001..........000.....0110011' */ {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul}, - /* instruction MULH */ + /* instruction MULH, encoding '0000001..........001.....0110011' */ {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh}, - /* instruction MULHSU */ + /* instruction MULHSU, encoding '0000001..........010.....0110011' */ {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu}, - /* instruction MULHU */ + /* instruction MULHU, encoding '0000001..........011.....0110011' */ {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu}, - /* instruction DIV */ + /* instruction DIV, encoding '0000001..........100.....0110011' */ {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div}, - /* instruction DIVU */ + /* instruction DIVU, encoding '0000001..........101.....0110011' */ {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu}, - /* instruction REM */ + /* instruction REM, encoding '0000001..........110.....0110011' */ {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem}, - /* instruction REMU */ + /* instruction REMU, encoding '0000001..........111.....0110011' */ {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu}, - /* instruction LR.W */ + /* instruction LR.W, encoding '00010..00000.....010.....0101111' */ {32, 0b00010000000000000010000000101111, 0b11111001111100000111000001111111, &this_class::__lr_w}, - /* instruction SC.W */ + /* instruction SC.W, encoding '00011............010.....0101111' */ {32, 0b00011000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__sc_w}, - /* instruction AMOSWAP.W */ + /* instruction AMOSWAP.W, encoding '00001............010.....0101111' */ {32, 0b00001000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoswap_w}, - /* instruction AMOADD.W */ + /* instruction AMOADD.W, encoding '00000............010.....0101111' */ {32, 0b00000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoadd_w}, - /* instruction AMOXOR.W */ + /* instruction AMOXOR.W, encoding '00100............010.....0101111' */ {32, 0b00100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoxor_w}, - /* instruction AMOAND.W */ + /* instruction AMOAND.W, encoding '01100............010.....0101111' */ {32, 0b01100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoand_w}, - /* instruction AMOOR.W */ + /* instruction AMOOR.W, encoding '01000............010.....0101111' */ {32, 0b01000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoor_w}, - /* instruction AMOMIN.W */ + /* instruction AMOMIN.W, encoding '10000............010.....0101111' */ {32, 0b10000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomin_w}, - /* instruction AMOMAX.W */ + /* instruction AMOMAX.W, encoding '10100............010.....0101111' */ {32, 0b10100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomax_w}, - /* instruction AMOMINU.W */ + /* instruction AMOMINU.W, encoding '11000............010.....0101111' */ {32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominu_w}, - /* instruction AMOMAXU.W */ + /* instruction AMOMAXU.W, encoding '11100............010.....0101111' */ {32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_w}, - /* instruction FLW */ + /* instruction FLW, encoding '.................010.....0000111' */ {32, 0b00000000000000000010000000000111, 0b00000000000000000111000001111111, &this_class::__flw}, - /* instruction FSW */ + /* instruction FSW, encoding '.................010.....0100111' */ {32, 0b00000000000000000010000000100111, 0b00000000000000000111000001111111, &this_class::__fsw}, - /* instruction FMADD.S */ + /* instruction FMADD.S, encoding '.....00..................1000011' */ {32, 0b00000000000000000000000001000011, 0b00000110000000000000000001111111, &this_class::__fmadd_s}, - /* instruction FMSUB.S */ + /* instruction FMSUB.S, encoding '.....00..................1000111' */ {32, 0b00000000000000000000000001000111, 0b00000110000000000000000001111111, &this_class::__fmsub_s}, - /* instruction FNMADD.S */ + /* instruction FNMADD.S, encoding '.....00..................1001111' */ {32, 0b00000000000000000000000001001111, 0b00000110000000000000000001111111, &this_class::__fnmadd_s}, - /* instruction FNMSUB.S */ + /* instruction FNMSUB.S, encoding '.....00..................1001011' */ {32, 0b00000000000000000000000001001011, 0b00000110000000000000000001111111, &this_class::__fnmsub_s}, - /* instruction FADD.S */ + /* instruction FADD.S, encoding '0000000..................1010011' */ {32, 0b00000000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fadd_s}, - /* instruction FSUB.S */ + /* instruction FSUB.S, encoding '0000100..................1010011' */ {32, 0b00001000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fsub_s}, - /* instruction FMUL.S */ + /* instruction FMUL.S, encoding '0001000..................1010011' */ {32, 0b00010000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fmul_s}, - /* instruction FDIV.S */ + /* instruction FDIV.S, encoding '0001100..................1010011' */ {32, 0b00011000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fdiv_s}, - /* instruction FSQRT.S */ + /* instruction FSQRT.S, encoding '010110000000.............1010011' */ {32, 0b01011000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fsqrt_s}, - /* instruction FSGNJ.S */ + /* instruction FSGNJ.S, encoding '0010000..........000.....1010011' */ {32, 0b00100000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnj_s}, - /* instruction FSGNJN.S */ + /* instruction FSGNJN.S, encoding '0010000..........001.....1010011' */ {32, 0b00100000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjn_s}, - /* instruction FSGNJX.S */ + /* instruction FSGNJX.S, encoding '0010000..........010.....1010011' */ {32, 0b00100000000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjx_s}, - /* instruction FMIN.S */ + /* instruction FMIN.S, encoding '0010100..........000.....1010011' */ {32, 0b00101000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fmin_s}, - /* instruction FMAX.S */ + /* instruction FMAX.S, encoding '0010100..........001.....1010011' */ {32, 0b00101000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fmax_s}, - /* instruction FCVT.W.S */ + /* instruction FCVT.W.S, encoding '110000000000.............1010011' */ {32, 0b11000000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_w_s}, - /* instruction FCVT.WU.S */ + /* instruction FCVT.WU.S, encoding '110000000001.............1010011' */ {32, 0b11000000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_wu_s}, - /* instruction FEQ.S */ + /* instruction FEQ.S, encoding '1010000..........010.....1010011' */ {32, 0b10100000000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__feq_s}, - /* instruction FLT.S */ + /* instruction FLT.S, encoding '1010000..........001.....1010011' */ {32, 0b10100000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__flt_s}, - /* instruction FLE.S */ + /* instruction FLE.S, encoding '1010000..........000.....1010011' */ {32, 0b10100000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fle_s}, - /* instruction FCLASS.S */ + /* instruction FCLASS.S, encoding '111000000000.....001.....1010011' */ {32, 0b11100000000000000001000001010011, 0b11111111111100000111000001111111, &this_class::__fclass_s}, - /* instruction FCVT.S.W */ + /* instruction FCVT.S.W, encoding '110100000000.............1010011' */ {32, 0b11010000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_s_w}, - /* instruction FCVT.S.WU */ + /* instruction FCVT.S.WU, encoding '110100000001.............1010011' */ {32, 0b11010000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_s_wu}, - /* instruction FMV.X.W */ + /* instruction FMV.X.W, encoding '111000000000.....000.....1010011' */ {32, 0b11100000000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv_x_w}, - /* instruction FMV.W.X */ + /* instruction FMV.W.X, encoding '111100000000.....000.....1010011' */ {32, 0b11110000000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv_w_x}, - /* instruction FLD */ + /* instruction FLD, encoding '.................011.....0000111' */ {32, 0b00000000000000000011000000000111, 0b00000000000000000111000001111111, &this_class::__fld}, - /* instruction FSD */ + /* instruction FSD, encoding '.................011.....0100111' */ {32, 0b00000000000000000011000000100111, 0b00000000000000000111000001111111, &this_class::__fsd}, - /* instruction FMADD.D */ + /* instruction FMADD.D, encoding '.....01..................1000011' */ {32, 0b00000010000000000000000001000011, 0b00000110000000000000000001111111, &this_class::__fmadd_d}, - /* instruction FMSUB.D */ + /* instruction FMSUB.D, encoding '.....01..................1000111' */ {32, 0b00000010000000000000000001000111, 0b00000110000000000000000001111111, &this_class::__fmsub_d}, - /* instruction FNMADD.D */ + /* instruction FNMADD.D, encoding '.....01..................1001111' */ {32, 0b00000010000000000000000001001111, 0b00000110000000000000000001111111, &this_class::__fnmadd_d}, - /* instruction FNMSUB.D */ + /* instruction FNMSUB.D, encoding '.....01..................1001011' */ {32, 0b00000010000000000000000001001011, 0b00000110000000000000000001111111, &this_class::__fnmsub_d}, - /* instruction FADD.D */ + /* instruction FADD.D, encoding '0000001..................1010011' */ {32, 0b00000010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fadd_d}, - /* instruction FSUB.D */ + /* instruction FSUB.D, encoding '0000101..................1010011' */ {32, 0b00001010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fsub_d}, - /* instruction FMUL.D */ + /* instruction FMUL.D, encoding '0001001..................1010011' */ {32, 0b00010010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fmul_d}, - /* instruction FDIV.D */ + /* instruction FDIV.D, encoding '0001101..................1010011' */ {32, 0b00011010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fdiv_d}, - /* instruction FSQRT.D */ + /* instruction FSQRT.D, encoding '010110100000.............1010011' */ {32, 0b01011010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fsqrt_d}, - /* instruction FSGNJ.D */ + /* instruction FSGNJ.D, encoding '0010001..........000.....1010011' */ {32, 0b00100010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnj_d}, - /* instruction FSGNJN.D */ + /* instruction FSGNJN.D, encoding '0010001..........001.....1010011' */ {32, 0b00100010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjn_d}, - /* instruction FSGNJX.D */ + /* instruction FSGNJX.D, encoding '0010001..........010.....1010011' */ {32, 0b00100010000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjx_d}, - /* instruction FMIN.D */ + /* instruction FMIN.D, encoding '0010101..........000.....1010011' */ {32, 0b00101010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fmin_d}, - /* instruction FMAX.D */ + /* instruction FMAX.D, encoding '0010101..........001.....1010011' */ {32, 0b00101010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fmax_d}, - /* instruction FCVT.S.D */ + /* instruction FCVT.S.D, encoding '010000000001.............1010011' */ {32, 0b01000000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_s_d}, - /* instruction FCVT.D.S */ + /* instruction FCVT.D.S, encoding '010000100000.............1010011' */ {32, 0b01000010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_d_s}, - /* instruction FEQ.D */ + /* instruction FEQ.D, encoding '1010001..........010.....1010011' */ {32, 0b10100010000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__feq_d}, - /* instruction FLT.D */ + /* instruction FLT.D, encoding '1010001..........001.....1010011' */ {32, 0b10100010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__flt_d}, - /* instruction FLE.D */ + /* instruction FLE.D, encoding '1010001..........000.....1010011' */ {32, 0b10100010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fle_d}, - /* instruction FCLASS.D */ + /* instruction FCLASS.D, encoding '111000100000.....001.....1010011' */ {32, 0b11100010000000000001000001010011, 0b11111111111100000111000001111111, &this_class::__fclass_d}, - /* instruction FCVT.W.D */ + /* instruction FCVT.W.D, encoding '110000100000.............1010011' */ {32, 0b11000010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_w_d}, - /* instruction FCVT.WU.D */ + /* instruction FCVT.WU.D, encoding '110000100001.............1010011' */ {32, 0b11000010000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_wu_d}, - /* instruction FCVT.D.W */ + /* instruction FCVT.D.W, encoding '110100100000.............1010011' */ {32, 0b11010010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_d_w}, - /* instruction FCVT.D.WU */ + /* instruction FCVT.D.WU, encoding '110100100001.............1010011' */ {32, 0b11010010000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_d_wu}, - /* instruction C.ADDI4SPN */ + /* instruction C.ADDI4SPN, encoding '000...........00' */ {16, 0b0000000000000000, 0b1110000000000011, &this_class::__c_addi4spn}, - /* instruction C.LW */ + /* instruction C.LW, encoding '010...........00' */ {16, 0b0100000000000000, 0b1110000000000011, &this_class::__c_lw}, - /* instruction C.SW */ + /* instruction C.SW, encoding '110...........00' */ {16, 0b1100000000000000, 0b1110000000000011, &this_class::__c_sw}, - /* instruction C.ADDI */ + /* instruction C.ADDI, encoding '000...........01' */ {16, 0b0000000000000001, 0b1110000000000011, &this_class::__c_addi}, - /* instruction C.NOP */ + /* instruction C.NOP, encoding '0000000000000001' */ {16, 0b0000000000000001, 0b1111111111111111, &this_class::__c_nop}, - /* instruction C.JAL */ + /* instruction C.JAL, encoding '001...........01' */ {16, 0b0010000000000001, 0b1110000000000011, &this_class::__c_jal}, - /* instruction C.LI */ + /* instruction C.LI, encoding '010...........01' */ {16, 0b0100000000000001, 0b1110000000000011, &this_class::__c_li}, - /* instruction C.LUI */ + /* instruction C.LUI, encoding '011...........01' */ {16, 0b0110000000000001, 0b1110000000000011, &this_class::__c_lui}, - /* instruction C.ADDI16SP */ + /* instruction C.ADDI16SP, encoding '011.00010.....01' */ {16, 0b0110000100000001, 0b1110111110000011, &this_class::__c_addi16sp}, - /* instruction C.SRLI */ + /* instruction C.SRLI, encoding '100000........01' */ {16, 0b1000000000000001, 0b1111110000000011, &this_class::__c_srli}, - /* instruction C.SRAI */ + /* instruction C.SRAI, encoding '100001........01' */ {16, 0b1000010000000001, 0b1111110000000011, &this_class::__c_srai}, - /* instruction C.ANDI */ + /* instruction C.ANDI, encoding '100.10........01' */ {16, 0b1000100000000001, 0b1110110000000011, &this_class::__c_andi}, - /* instruction C.SUB */ + /* instruction C.SUB, encoding '100011...00...01' */ {16, 0b1000110000000001, 0b1111110001100011, &this_class::__c_sub}, - /* instruction C.XOR */ + /* instruction C.XOR, encoding '100011...01...01' */ {16, 0b1000110000100001, 0b1111110001100011, &this_class::__c_xor}, - /* instruction C.OR */ + /* instruction C.OR, encoding '100011...10...01' */ {16, 0b1000110001000001, 0b1111110001100011, &this_class::__c_or}, - /* instruction C.AND */ + /* instruction C.AND, encoding '100011...11...01' */ {16, 0b1000110001100001, 0b1111110001100011, &this_class::__c_and}, - /* instruction C.J */ + /* instruction C.J, encoding '101...........01' */ {16, 0b1010000000000001, 0b1110000000000011, &this_class::__c_j}, - /* instruction C.BEQZ */ + /* instruction C.BEQZ, encoding '110...........01' */ {16, 0b1100000000000001, 0b1110000000000011, &this_class::__c_beqz}, - /* instruction C.BNEZ */ + /* instruction C.BNEZ, encoding '111...........01' */ {16, 0b1110000000000001, 0b1110000000000011, &this_class::__c_bnez}, - /* instruction C.SLLI */ + /* instruction C.SLLI, encoding '0000..........10' */ {16, 0b0000000000000010, 0b1111000000000011, &this_class::__c_slli}, - /* instruction C.LWSP */ + /* instruction C.LWSP, encoding '010...........10' */ {16, 0b0100000000000010, 0b1110000000000011, &this_class::__c_lwsp}, - /* instruction C.MV */ + /* instruction C.MV, encoding '1000..........10' */ {16, 0b1000000000000010, 0b1111000000000011, &this_class::__c_mv}, - /* instruction C.JR */ + /* instruction C.JR, encoding '1000.....0000010' */ {16, 0b1000000000000010, 0b1111000001111111, &this_class::__c_jr}, - /* instruction C.ADD */ + /* instruction C.ADD, encoding '1001..........10' */ {16, 0b1001000000000010, 0b1111000000000011, &this_class::__c_add}, - /* instruction C.JALR */ + /* instruction C.JALR, encoding '1001.....0000010' */ {16, 0b1001000000000010, 0b1111000001111111, &this_class::__c_jalr}, - /* instruction C.EBREAK */ + /* instruction C.EBREAK, encoding '1001000000000010' */ {16, 0b1001000000000010, 0b1111111111111111, &this_class::__c_ebreak}, - /* instruction C.SWSP */ + /* instruction C.SWSP, encoding '110...........10' */ {16, 0b1100000000000010, 0b1110000000000011, &this_class::__c_swsp}, - /* instruction DII */ + /* instruction DII, encoding '0000000000000000' */ {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, - /* instruction C.FLW */ + /* instruction C.FLW, encoding '011...........00' */ {16, 0b0110000000000000, 0b1110000000000011, &this_class::__c_flw}, - /* instruction C.FSW */ + /* instruction C.FSW, encoding '111...........00' */ {16, 0b1110000000000000, 0b1110000000000011, &this_class::__c_fsw}, - /* instruction C.FLWSP */ + /* instruction C.FLWSP, encoding '011...........10' */ {16, 0b0110000000000010, 0b1110000000000011, &this_class::__c_flwsp}, - /* instruction C.FSWSP */ + /* instruction C.FSWSP, encoding '111...........10' */ {16, 0b1110000000000010, 0b1110000000000011, &this_class::__c_fswsp}, - /* instruction C.FLD */ + /* instruction C.FLD, encoding '001...........00' */ {16, 0b0010000000000000, 0b1110000000000011, &this_class::__c_fld}, - /* instruction C.FSD */ + /* instruction C.FSD, encoding '101...........00' */ {16, 0b1010000000000000, 0b1110000000000011, &this_class::__c_fsd}, - /* instruction C.FLDSP */ + /* instruction C.FLDSP, encoding '001...........10' */ {16, 0b0010000000000010, 0b1110000000000011, &this_class::__c_fldsp}, - /* instruction C.FSDSP */ + /* instruction C.FSDSP, encoding '101...........10' */ {16, 0b1010000000000010, 0b1110000000000011, &this_class::__c_fsdsp}, }}; @@ -7213,7 +7213,8 @@ template void vm_impl::gen_raise_trap(tu_builder& tu, uint } template void vm_impl::gen_leave_trap(tu_builder& tu, unsigned lvl) { - tu.store(value{fmt::format("leave_trap(core_ptr, {})", lvl), traits::XLEN}, traits::NEXT_PC); + tu("leave_trap(core_ptr, {});", lvl); + tu.store(tu.read_mem(traits::CSR, (lvl << 8) + 0x41, traits::XLEN),traits::NEXT_PC); tu.store(tu.constant(std::numeric_limits::max(), 32),traits::LAST_BRANCH); } diff --git a/src/vm/tcc/vm_rv32imac.cpp b/src/vm/tcc/vm_rv32imac.cpp index f9f0383..60f2494 100644 --- a/src/vm/tcc/vm_rv32imac.cpp +++ b/src/vm/tcc/vm_rv32imac.cpp @@ -184,203 +184,203 @@ private: const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ - /* instruction LUI */ + /* instruction LUI, encoding '.........................0110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, - /* instruction AUIPC */ + /* instruction AUIPC, encoding '.........................0010111' */ {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, - /* instruction JAL */ + /* instruction JAL, encoding '.........................1101111' */ {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, - /* instruction JALR */ + /* instruction JALR, encoding '.................000.....1100111' */ {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, - /* instruction BEQ */ + /* instruction BEQ, encoding '.................000.....1100011' */ {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, - /* instruction BNE */ + /* instruction BNE, encoding '.................001.....1100011' */ {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne}, - /* instruction BLT */ + /* instruction BLT, encoding '.................100.....1100011' */ {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt}, - /* instruction BGE */ + /* instruction BGE, encoding '.................101.....1100011' */ {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge}, - /* instruction BLTU */ + /* instruction BLTU, encoding '.................110.....1100011' */ {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu}, - /* instruction BGEU */ + /* instruction BGEU, encoding '.................111.....1100011' */ {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu}, - /* instruction LB */ + /* instruction LB, encoding '.................000.....0000011' */ {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb}, - /* instruction LH */ + /* instruction LH, encoding '.................001.....0000011' */ {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh}, - /* instruction LW */ + /* instruction LW, encoding '.................010.....0000011' */ {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw}, - /* instruction LBU */ + /* instruction LBU, encoding '.................100.....0000011' */ {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu}, - /* instruction LHU */ + /* instruction LHU, encoding '.................101.....0000011' */ {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu}, - /* instruction SB */ + /* instruction SB, encoding '.................000.....0100011' */ {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb}, - /* instruction SH */ + /* instruction SH, encoding '.................001.....0100011' */ {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh}, - /* instruction SW */ + /* instruction SW, encoding '.................010.....0100011' */ {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw}, - /* instruction ADDI */ + /* instruction ADDI, encoding '.................000.....0010011' */ {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi}, - /* instruction SLTI */ + /* instruction SLTI, encoding '.................010.....0010011' */ {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti}, - /* instruction SLTIU */ + /* instruction SLTIU, encoding '.................011.....0010011' */ {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu}, - /* instruction XORI */ + /* instruction XORI, encoding '.................100.....0010011' */ {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori}, - /* instruction ORI */ + /* instruction ORI, encoding '.................110.....0010011' */ {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori}, - /* instruction ANDI */ + /* instruction ANDI, encoding '.................111.....0010011' */ {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi}, - /* instruction SLLI */ + /* instruction SLLI, encoding '0000000..........001.....0010011' */ {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli}, - /* instruction SRLI */ + /* instruction SRLI, encoding '0000000..........101.....0010011' */ {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli}, - /* instruction SRAI */ + /* instruction SRAI, encoding '0100000..........101.....0010011' */ {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai}, - /* instruction ADD */ + /* instruction ADD, encoding '0000000..........000.....0110011' */ {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add}, - /* instruction SUB */ + /* instruction SUB, encoding '0100000..........000.....0110011' */ {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub}, - /* instruction SLL */ + /* instruction SLL, encoding '0000000..........001.....0110011' */ {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll}, - /* instruction SLT */ + /* instruction SLT, encoding '0000000..........010.....0110011' */ {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt}, - /* instruction SLTU */ + /* instruction SLTU, encoding '0000000..........011.....0110011' */ {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu}, - /* instruction XOR */ + /* instruction XOR, encoding '0000000..........100.....0110011' */ {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor}, - /* instruction SRL */ + /* instruction SRL, encoding '0000000..........101.....0110011' */ {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl}, - /* instruction SRA */ + /* instruction SRA, encoding '0100000..........101.....0110011' */ {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra}, - /* instruction OR */ + /* instruction OR, encoding '0000000..........110.....0110011' */ {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or}, - /* instruction AND */ + /* instruction AND, encoding '0000000..........111.....0110011' */ {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and}, - /* instruction FENCE */ + /* instruction FENCE, encoding '0000.............000.....0001111' */ {32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence}, - /* instruction FENCE_I */ + /* instruction FENCE_I, encoding '.................001.....0001111' */ {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i}, - /* instruction ECALL */ + /* instruction ECALL, encoding '00000000000000000000000001110011' */ {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall}, - /* instruction EBREAK */ + /* instruction EBREAK, encoding '00000000000100000000000001110011' */ {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak}, - /* instruction URET */ + /* instruction URET, encoding '00000000001000000000000001110011' */ {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret}, - /* instruction SRET */ + /* instruction SRET, encoding '00010000001000000000000001110011' */ {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret}, - /* instruction MRET */ + /* instruction MRET, encoding '00110000001000000000000001110011' */ {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret}, - /* instruction WFI */ + /* instruction WFI, encoding '00010000010100000000000001110011' */ {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi}, - /* instruction SFENCE.VMA */ + /* instruction SFENCE.VMA, encoding '0001001..........000000001110011' */ {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma}, - /* instruction CSRRW */ + /* instruction CSRRW, encoding '.................001.....1110011' */ {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw}, - /* instruction CSRRS */ + /* instruction CSRRS, encoding '.................010.....1110011' */ {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs}, - /* instruction CSRRC */ + /* instruction CSRRC, encoding '.................011.....1110011' */ {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc}, - /* instruction CSRRWI */ + /* instruction CSRRWI, encoding '.................101.....1110011' */ {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi}, - /* instruction CSRRSI */ + /* instruction CSRRSI, encoding '.................110.....1110011' */ {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi}, - /* instruction CSRRCI */ + /* instruction CSRRCI, encoding '.................111.....1110011' */ {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci}, - /* instruction MUL */ + /* instruction MUL, encoding '0000001..........000.....0110011' */ {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul}, - /* instruction MULH */ + /* instruction MULH, encoding '0000001..........001.....0110011' */ {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh}, - /* instruction MULHSU */ + /* instruction MULHSU, encoding '0000001..........010.....0110011' */ {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu}, - /* instruction MULHU */ + /* instruction MULHU, encoding '0000001..........011.....0110011' */ {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu}, - /* instruction DIV */ + /* instruction DIV, encoding '0000001..........100.....0110011' */ {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div}, - /* instruction DIVU */ + /* instruction DIVU, encoding '0000001..........101.....0110011' */ {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu}, - /* instruction REM */ + /* instruction REM, encoding '0000001..........110.....0110011' */ {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem}, - /* instruction REMU */ + /* instruction REMU, encoding '0000001..........111.....0110011' */ {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu}, - /* instruction LR.W */ + /* instruction LR.W, encoding '00010..00000.....010.....0101111' */ {32, 0b00010000000000000010000000101111, 0b11111001111100000111000001111111, &this_class::__lr_w}, - /* instruction SC.W */ + /* instruction SC.W, encoding '00011............010.....0101111' */ {32, 0b00011000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__sc_w}, - /* instruction AMOSWAP.W */ + /* instruction AMOSWAP.W, encoding '00001............010.....0101111' */ {32, 0b00001000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoswap_w}, - /* instruction AMOADD.W */ + /* instruction AMOADD.W, encoding '00000............010.....0101111' */ {32, 0b00000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoadd_w}, - /* instruction AMOXOR.W */ + /* instruction AMOXOR.W, encoding '00100............010.....0101111' */ {32, 0b00100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoxor_w}, - /* instruction AMOAND.W */ + /* instruction AMOAND.W, encoding '01100............010.....0101111' */ {32, 0b01100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoand_w}, - /* instruction AMOOR.W */ + /* instruction AMOOR.W, encoding '01000............010.....0101111' */ {32, 0b01000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoor_w}, - /* instruction AMOMIN.W */ + /* instruction AMOMIN.W, encoding '10000............010.....0101111' */ {32, 0b10000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomin_w}, - /* instruction AMOMAX.W */ + /* instruction AMOMAX.W, encoding '10100............010.....0101111' */ {32, 0b10100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomax_w}, - /* instruction AMOMINU.W */ + /* instruction AMOMINU.W, encoding '11000............010.....0101111' */ {32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominu_w}, - /* instruction AMOMAXU.W */ + /* instruction AMOMAXU.W, encoding '11100............010.....0101111' */ {32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_w}, - /* instruction C.ADDI4SPN */ + /* instruction C.ADDI4SPN, encoding '000...........00' */ {16, 0b0000000000000000, 0b1110000000000011, &this_class::__c_addi4spn}, - /* instruction C.LW */ + /* instruction C.LW, encoding '010...........00' */ {16, 0b0100000000000000, 0b1110000000000011, &this_class::__c_lw}, - /* instruction C.SW */ + /* instruction C.SW, encoding '110...........00' */ {16, 0b1100000000000000, 0b1110000000000011, &this_class::__c_sw}, - /* instruction C.ADDI */ + /* instruction C.ADDI, encoding '000...........01' */ {16, 0b0000000000000001, 0b1110000000000011, &this_class::__c_addi}, - /* instruction C.NOP */ + /* instruction C.NOP, encoding '0000000000000001' */ {16, 0b0000000000000001, 0b1111111111111111, &this_class::__c_nop}, - /* instruction C.JAL */ + /* instruction C.JAL, encoding '001...........01' */ {16, 0b0010000000000001, 0b1110000000000011, &this_class::__c_jal}, - /* instruction C.LI */ + /* instruction C.LI, encoding '010...........01' */ {16, 0b0100000000000001, 0b1110000000000011, &this_class::__c_li}, - /* instruction C.LUI */ + /* instruction C.LUI, encoding '011...........01' */ {16, 0b0110000000000001, 0b1110000000000011, &this_class::__c_lui}, - /* instruction C.ADDI16SP */ + /* instruction C.ADDI16SP, encoding '011.00010.....01' */ {16, 0b0110000100000001, 0b1110111110000011, &this_class::__c_addi16sp}, - /* instruction C.SRLI */ + /* instruction C.SRLI, encoding '100000........01' */ {16, 0b1000000000000001, 0b1111110000000011, &this_class::__c_srli}, - /* instruction C.SRAI */ + /* instruction C.SRAI, encoding '100001........01' */ {16, 0b1000010000000001, 0b1111110000000011, &this_class::__c_srai}, - /* instruction C.ANDI */ + /* instruction C.ANDI, encoding '100.10........01' */ {16, 0b1000100000000001, 0b1110110000000011, &this_class::__c_andi}, - /* instruction C.SUB */ + /* instruction C.SUB, encoding '100011...00...01' */ {16, 0b1000110000000001, 0b1111110001100011, &this_class::__c_sub}, - /* instruction C.XOR */ + /* instruction C.XOR, encoding '100011...01...01' */ {16, 0b1000110000100001, 0b1111110001100011, &this_class::__c_xor}, - /* instruction C.OR */ + /* instruction C.OR, encoding '100011...10...01' */ {16, 0b1000110001000001, 0b1111110001100011, &this_class::__c_or}, - /* instruction C.AND */ + /* instruction C.AND, encoding '100011...11...01' */ {16, 0b1000110001100001, 0b1111110001100011, &this_class::__c_and}, - /* instruction C.J */ + /* instruction C.J, encoding '101...........01' */ {16, 0b1010000000000001, 0b1110000000000011, &this_class::__c_j}, - /* instruction C.BEQZ */ + /* instruction C.BEQZ, encoding '110...........01' */ {16, 0b1100000000000001, 0b1110000000000011, &this_class::__c_beqz}, - /* instruction C.BNEZ */ + /* instruction C.BNEZ, encoding '111...........01' */ {16, 0b1110000000000001, 0b1110000000000011, &this_class::__c_bnez}, - /* instruction C.SLLI */ + /* instruction C.SLLI, encoding '0000..........10' */ {16, 0b0000000000000010, 0b1111000000000011, &this_class::__c_slli}, - /* instruction C.LWSP */ + /* instruction C.LWSP, encoding '010...........10' */ {16, 0b0100000000000010, 0b1110000000000011, &this_class::__c_lwsp}, - /* instruction C.MV */ + /* instruction C.MV, encoding '1000..........10' */ {16, 0b1000000000000010, 0b1111000000000011, &this_class::__c_mv}, - /* instruction C.JR */ + /* instruction C.JR, encoding '1000.....0000010' */ {16, 0b1000000000000010, 0b1111000001111111, &this_class::__c_jr}, - /* instruction C.ADD */ + /* instruction C.ADD, encoding '1001..........10' */ {16, 0b1001000000000010, 0b1111000000000011, &this_class::__c_add}, - /* instruction C.JALR */ + /* instruction C.JALR, encoding '1001.....0000010' */ {16, 0b1001000000000010, 0b1111000001111111, &this_class::__c_jalr}, - /* instruction C.EBREAK */ + /* instruction C.EBREAK, encoding '1001000000000010' */ {16, 0b1001000000000010, 0b1111111111111111, &this_class::__c_ebreak}, - /* instruction C.SWSP */ + /* instruction C.SWSP, encoding '110...........10' */ {16, 0b1100000000000010, 0b1110000000000011, &this_class::__c_swsp}, - /* instruction DII */ + /* instruction DII, encoding '0000000000000000' */ {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, }}; diff --git a/src/vm/tcc/vm_rv64gc.cpp b/src/vm/tcc/vm_rv64gc.cpp index 8c5343f..df3e057 100644 --- a/src/vm/tcc/vm_rv64gc.cpp +++ b/src/vm/tcc/vm_rv64gc.cpp @@ -182,416 +182,418 @@ private: compile_func op; }; - const std::array instr_descr = {{ + const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ - /* instruction LUI */ + /* instruction LUI, encoding '.........................0110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, - /* instruction AUIPC */ + /* instruction AUIPC, encoding '.........................0010111' */ {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, - /* instruction JAL */ + /* instruction JAL, encoding '.........................1101111' */ {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, - /* instruction JALR */ + /* instruction JALR, encoding '.................000.....1100111' */ {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, - /* instruction BEQ */ + /* instruction BEQ, encoding '.................000.....1100011' */ {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, - /* instruction BNE */ + /* instruction BNE, encoding '.................001.....1100011' */ {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne}, - /* instruction BLT */ + /* instruction BLT, encoding '.................100.....1100011' */ {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt}, - /* instruction BGE */ + /* instruction BGE, encoding '.................101.....1100011' */ {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge}, - /* instruction BLTU */ + /* instruction BLTU, encoding '.................110.....1100011' */ {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu}, - /* instruction BGEU */ + /* instruction BGEU, encoding '.................111.....1100011' */ {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu}, - /* instruction LB */ + /* instruction LB, encoding '.................000.....0000011' */ {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb}, - /* instruction LH */ + /* instruction LH, encoding '.................001.....0000011' */ {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh}, - /* instruction LW */ + /* instruction LW, encoding '.................010.....0000011' */ {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw}, - /* instruction LBU */ + /* instruction LBU, encoding '.................100.....0000011' */ {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu}, - /* instruction LHU */ + /* instruction LHU, encoding '.................101.....0000011' */ {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu}, - /* instruction SB */ + /* instruction SB, encoding '.................000.....0100011' */ {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb}, - /* instruction SH */ + /* instruction SH, encoding '.................001.....0100011' */ {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh}, - /* instruction SW */ + /* instruction SW, encoding '.................010.....0100011' */ {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw}, - /* instruction ADDI */ + /* instruction ADDI, encoding '.................000.....0010011' */ {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi}, - /* instruction SLTI */ + /* instruction SLTI, encoding '.................010.....0010011' */ {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti}, - /* instruction SLTIU */ + /* instruction SLTIU, encoding '.................011.....0010011' */ {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu}, - /* instruction XORI */ + /* instruction XORI, encoding '.................100.....0010011' */ {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori}, - /* instruction ORI */ + /* instruction ORI, encoding '.................110.....0010011' */ {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori}, - /* instruction ANDI */ + /* instruction ANDI, encoding '.................111.....0010011' */ {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi}, - /* instruction SLLI */ + /* instruction SLLI, encoding '0000000..........001.....0010011' */ {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli}, - /* instruction SRLI */ + /* instruction SRLI, encoding '0000000..........101.....0010011' */ {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli}, - /* instruction SRAI */ + /* instruction SRAI, encoding '0100000..........101.....0010011' */ {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai}, - /* instruction ADD */ + /* instruction ADD, encoding '0000000..........000.....0110011' */ {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add}, - /* instruction SUB */ + /* instruction SUB, encoding '0100000..........000.....0110011' */ {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub}, - /* instruction SLL */ + /* instruction SLL, encoding '0000000..........001.....0110011' */ {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll}, - /* instruction SLT */ + /* instruction SLT, encoding '0000000..........010.....0110011' */ {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt}, - /* instruction SLTU */ + /* instruction SLTU, encoding '0000000..........011.....0110011' */ {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu}, - /* instruction XOR */ + /* instruction XOR, encoding '0000000..........100.....0110011' */ {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor}, - /* instruction SRL */ + /* instruction SRL, encoding '0000000..........101.....0110011' */ {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl}, - /* instruction SRA */ + /* instruction SRA, encoding '0100000..........101.....0110011' */ {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra}, - /* instruction OR */ + /* instruction OR, encoding '0000000..........110.....0110011' */ {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or}, - /* instruction AND */ + /* instruction AND, encoding '0000000..........111.....0110011' */ {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and}, - /* instruction FENCE */ + /* instruction FENCE, encoding '0000.............000.....0001111' */ {32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence}, - /* instruction FENCE_I */ + /* instruction FENCE_I, encoding '.................001.....0001111' */ {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i}, - /* instruction ECALL */ + /* instruction ECALL, encoding '00000000000000000000000001110011' */ {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall}, - /* instruction EBREAK */ + /* instruction EBREAK, encoding '00000000000100000000000001110011' */ {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak}, - /* instruction URET */ + /* instruction URET, encoding '00000000001000000000000001110011' */ {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret}, - /* instruction SRET */ + /* instruction SRET, encoding '00010000001000000000000001110011' */ {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret}, - /* instruction MRET */ + /* instruction MRET, encoding '00110000001000000000000001110011' */ {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret}, - /* instruction WFI */ + /* instruction WFI, encoding '00010000010100000000000001110011' */ {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi}, - /* instruction SFENCE.VMA */ + /* instruction SFENCE.VMA, encoding '0001001..........000000001110011' */ {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma}, - /* instruction CSRRW */ + /* instruction CSRRW, encoding '.................001.....1110011' */ {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw}, - /* instruction CSRRS */ + /* instruction CSRRS, encoding '.................010.....1110011' */ {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs}, - /* instruction CSRRC */ + /* instruction CSRRC, encoding '.................011.....1110011' */ {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc}, - /* instruction CSRRWI */ + /* instruction CSRRWI, encoding '.................101.....1110011' */ {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi}, - /* instruction CSRRSI */ + /* instruction CSRRSI, encoding '.................110.....1110011' */ {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi}, - /* instruction CSRRCI */ + /* instruction CSRRCI, encoding '.................111.....1110011' */ {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci}, - /* instruction LWU */ + /* instruction LWU, encoding '.................110.....0000011' */ {32, 0b00000000000000000110000000000011, 0b00000000000000000111000001111111, &this_class::__lwu}, - /* instruction LD */ + /* instruction LD, encoding '.................011.....0000011' */ {32, 0b00000000000000000011000000000011, 0b00000000000000000111000001111111, &this_class::__ld}, - /* instruction SD */ + /* instruction SD, encoding '.................011.....0100011' */ {32, 0b00000000000000000011000000100011, 0b00000000000000000111000001111111, &this_class::__sd}, - /* instruction ADDIW */ + /* instruction SLLI, encoding '000000...........001.....0010011' */ + {32, 0b00000000000000000001000000010011, 0b11111100000000000111000001111111, &this_class::__slli}, + /* instruction SRLI, encoding '000000...........101.....0010011' */ + {32, 0b00000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srli}, + /* instruction SRAI, encoding '010000...........101.....0010011' */ + {32, 0b01000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srai}, + /* instruction ADDIW, encoding '.................000.....0011011' */ {32, 0b00000000000000000000000000011011, 0b00000000000000000111000001111111, &this_class::__addiw}, - /* instruction SLLIW */ + /* instruction SLLIW, encoding '0000000..........001.....0011011' */ {32, 0b00000000000000000001000000011011, 0b11111110000000000111000001111111, &this_class::__slliw}, - /* instruction SRLIW */ + /* instruction SRLIW, encoding '0000000..........101.....0011011' */ {32, 0b00000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__srliw}, - /* instruction SRAIW */ + /* instruction SRAIW, encoding '0100000..........101.....0011011' */ {32, 0b01000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__sraiw}, - /* instruction ADDW */ + /* instruction ADDW, encoding '0000000..........000.....0111011' */ {32, 0b00000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__addw}, - /* instruction SUBW */ + /* instruction SUBW, encoding '0100000..........000.....0111011' */ {32, 0b01000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__subw}, - /* instruction SLLW */ + /* instruction SLLW, encoding '0000000..........001.....0111011' */ {32, 0b00000000000000000001000000111011, 0b11111110000000000111000001111111, &this_class::__sllw}, - /* instruction SRLW */ + /* instruction SRLW, encoding '0000000..........101.....0111011' */ {32, 0b00000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__srlw}, - /* instruction SRAW */ + /* instruction SRAW, encoding '0100000..........101.....0111011' */ {32, 0b01000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__sraw}, - /* instruction MUL */ + /* instruction MUL, encoding '0000001..........000.....0110011' */ {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul}, - /* instruction MULH */ + /* instruction MULH, encoding '0000001..........001.....0110011' */ {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh}, - /* instruction MULHSU */ + /* instruction MULHSU, encoding '0000001..........010.....0110011' */ {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu}, - /* instruction MULHU */ + /* instruction MULHU, encoding '0000001..........011.....0110011' */ {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu}, - /* instruction DIV */ + /* instruction DIV, encoding '0000001..........100.....0110011' */ {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div}, - /* instruction DIVU */ + /* instruction DIVU, encoding '0000001..........101.....0110011' */ {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu}, - /* instruction REM */ + /* instruction REM, encoding '0000001..........110.....0110011' */ {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem}, - /* instruction REMU */ + /* instruction REMU, encoding '0000001..........111.....0110011' */ {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu}, - /* instruction MULW */ + /* instruction MULW, encoding '0000001..........000.....0111011' */ {32, 0b00000010000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__mulw}, - /* instruction DIVW */ + /* instruction DIVW, encoding '0000001..........100.....0111011' */ {32, 0b00000010000000000100000000111011, 0b11111110000000000111000001111111, &this_class::__divw}, - /* instruction DIVUW */ + /* instruction DIVUW, encoding '0000001..........101.....0111011' */ {32, 0b00000010000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__divuw}, - /* instruction REMW */ + /* instruction REMW, encoding '0000001..........110.....0111011' */ {32, 0b00000010000000000110000000111011, 0b11111110000000000111000001111111, &this_class::__remw}, - /* instruction REMUW */ + /* instruction REMUW, encoding '0000001..........111.....0111011' */ {32, 0b00000010000000000111000000111011, 0b11111110000000000111000001111111, &this_class::__remuw}, - /* instruction LR.W */ + /* instruction LR.W, encoding '00010..00000.....010.....0101111' */ {32, 0b00010000000000000010000000101111, 0b11111001111100000111000001111111, &this_class::__lr_w}, - /* instruction SC.W */ + /* instruction SC.W, encoding '00011............010.....0101111' */ {32, 0b00011000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__sc_w}, - /* instruction AMOSWAP.W */ + /* instruction AMOSWAP.W, encoding '00001............010.....0101111' */ {32, 0b00001000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoswap_w}, - /* instruction AMOADD.W */ + /* instruction AMOADD.W, encoding '00000............010.....0101111' */ {32, 0b00000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoadd_w}, - /* instruction AMOXOR.W */ + /* instruction AMOXOR.W, encoding '00100............010.....0101111' */ {32, 0b00100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoxor_w}, - /* instruction AMOAND.W */ + /* instruction AMOAND.W, encoding '01100............010.....0101111' */ {32, 0b01100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoand_w}, - /* instruction AMOOR.W */ + /* instruction AMOOR.W, encoding '01000............010.....0101111' */ {32, 0b01000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amoor_w}, - /* instruction AMOMIN.W */ + /* instruction AMOMIN.W, encoding '10000............010.....0101111' */ {32, 0b10000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomin_w}, - /* instruction AMOMAX.W */ + /* instruction AMOMAX.W, encoding '10100............010.....0101111' */ {32, 0b10100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomax_w}, - /* instruction AMOMINU.W */ + /* instruction AMOMINU.W, encoding '11000............010.....0101111' */ {32, 0b11000000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amominu_w}, - /* instruction AMOMAXU.W */ + /* instruction AMOMAXU.W, encoding '11100............010.....0101111' */ {32, 0b11100000000000000010000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_w}, - /* instruction LR.D */ + /* instruction LR.D, encoding '00010..00000.....011.....0101111' */ {32, 0b00010000000000000011000000101111, 0b11111001111100000111000001111111, &this_class::__lr_d}, - /* instruction SC.D */ + /* instruction SC.D, encoding '00011............011.....0101111' */ {32, 0b00011000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__sc_d}, - /* instruction AMOSWAP.D */ + /* instruction AMOSWAP.D, encoding '00001............011.....0101111' */ {32, 0b00001000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoswap_d}, - /* instruction AMOADD.D */ + /* instruction AMOADD.D, encoding '00000............011.....0101111' */ {32, 0b00000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoadd_d}, - /* instruction AMOXOR.D */ + /* instruction AMOXOR.D, encoding '00100............011.....0101111' */ {32, 0b00100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoxor_d}, - /* instruction AMOAND.D */ + /* instruction AMOAND.D, encoding '01100............011.....0101111' */ {32, 0b01100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoand_d}, - /* instruction AMOOR.D */ + /* instruction AMOOR.D, encoding '01000............011.....0101111' */ {32, 0b01000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amoor_d}, - /* instruction AMOMIN.D */ + /* instruction AMOMIN.D, encoding '10000............011.....0101111' */ {32, 0b10000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amomin_d}, - /* instruction AMOMAX.D */ + /* instruction AMOMAX.D, encoding '10100............011.....0101111' */ {32, 0b10100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amomax_d}, - /* instruction AMOMINU.D */ + /* instruction AMOMINU.D, encoding '11000............011.....0101111' */ {32, 0b11000000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amominu_d}, - /* instruction AMOMAXU.D */ + /* instruction AMOMAXU.D, encoding '11100............011.....0101111' */ {32, 0b11100000000000000011000000101111, 0b11111000000000000111000001111111, &this_class::__amomaxu_d}, - /* instruction FLW */ + /* instruction FLW, encoding '.................010.....0000111' */ {32, 0b00000000000000000010000000000111, 0b00000000000000000111000001111111, &this_class::__flw}, - /* instruction FSW */ + /* instruction FSW, encoding '.................010.....0100111' */ {32, 0b00000000000000000010000000100111, 0b00000000000000000111000001111111, &this_class::__fsw}, - /* instruction FMADD.S */ + /* instruction FMADD.S, encoding '.....00..................1000011' */ {32, 0b00000000000000000000000001000011, 0b00000110000000000000000001111111, &this_class::__fmadd_s}, - /* instruction FMSUB.S */ + /* instruction FMSUB.S, encoding '.....00..................1000111' */ {32, 0b00000000000000000000000001000111, 0b00000110000000000000000001111111, &this_class::__fmsub_s}, - /* instruction FNMADD.S */ + /* instruction FNMADD.S, encoding '.....00..................1001111' */ {32, 0b00000000000000000000000001001111, 0b00000110000000000000000001111111, &this_class::__fnmadd_s}, - /* instruction FNMSUB.S */ + /* instruction FNMSUB.S, encoding '.....00..................1001011' */ {32, 0b00000000000000000000000001001011, 0b00000110000000000000000001111111, &this_class::__fnmsub_s}, - /* instruction FADD.S */ + /* instruction FADD.S, encoding '0000000..................1010011' */ {32, 0b00000000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fadd_s}, - /* instruction FSUB.S */ + /* instruction FSUB.S, encoding '0000100..................1010011' */ {32, 0b00001000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fsub_s}, - /* instruction FMUL.S */ + /* instruction FMUL.S, encoding '0001000..................1010011' */ {32, 0b00010000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fmul_s}, - /* instruction FDIV.S */ + /* instruction FDIV.S, encoding '0001100..................1010011' */ {32, 0b00011000000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fdiv_s}, - /* instruction FSQRT.S */ + /* instruction FSQRT.S, encoding '010110000000.............1010011' */ {32, 0b01011000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fsqrt_s}, - /* instruction FSGNJ.S */ + /* instruction FSGNJ.S, encoding '0010000..........000.....1010011' */ {32, 0b00100000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnj_s}, - /* instruction FSGNJN.S */ + /* instruction FSGNJN.S, encoding '0010000..........001.....1010011' */ {32, 0b00100000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjn_s}, - /* instruction FSGNJX.S */ + /* instruction FSGNJX.S, encoding '0010000..........010.....1010011' */ {32, 0b00100000000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjx_s}, - /* instruction FMIN.S */ + /* instruction FMIN.S, encoding '0010100..........000.....1010011' */ {32, 0b00101000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fmin_s}, - /* instruction FMAX.S */ + /* instruction FMAX.S, encoding '0010100..........001.....1010011' */ {32, 0b00101000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fmax_s}, - /* instruction FCVT.W.S */ + /* instruction FCVT.W.S, encoding '110000000000.............1010011' */ {32, 0b11000000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_w_s}, - /* instruction FCVT.WU.S */ + /* instruction FCVT.WU.S, encoding '110000000001.............1010011' */ {32, 0b11000000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_wu_s}, - /* instruction FEQ.S */ + /* instruction FEQ.S, encoding '1010000..........010.....1010011' */ {32, 0b10100000000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__feq_s}, - /* instruction FLT.S */ + /* instruction FLT.S, encoding '1010000..........001.....1010011' */ {32, 0b10100000000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__flt_s}, - /* instruction FLE.S */ + /* instruction FLE.S, encoding '1010000..........000.....1010011' */ {32, 0b10100000000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fle_s}, - /* instruction FCLASS.S */ + /* instruction FCLASS.S, encoding '111000000000.....001.....1010011' */ {32, 0b11100000000000000001000001010011, 0b11111111111100000111000001111111, &this_class::__fclass_s}, - /* instruction FCVT.S.W */ + /* instruction FCVT.S.W, encoding '110100000000.............1010011' */ {32, 0b11010000000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_s_w}, - /* instruction FCVT.S.WU */ + /* instruction FCVT.S.WU, encoding '110100000001.............1010011' */ {32, 0b11010000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_s_wu}, - /* instruction FMV.X.W */ + /* instruction FMV.X.W, encoding '111000000000.....000.....1010011' */ {32, 0b11100000000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv_x_w}, - /* instruction FMV.W.X */ + /* instruction FMV.W.X, encoding '111100000000.....000.....1010011' */ {32, 0b11110000000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv_w_x}, - /* instruction FCVT.L.S */ + /* instruction FCVT.L.S, encoding '110000000010.............1010011' */ {32, 0b11000000001000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_l_s}, - /* instruction FCVT.LU.S */ + /* instruction FCVT.LU.S, encoding '110000000011.............1010011' */ {32, 0b11000000001100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_lu_s}, - /* instruction FCVT.S.L */ + /* instruction FCVT.S.L, encoding '110100000010.............1010011' */ {32, 0b11010000001000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_s_l}, - /* instruction FCVT.S.LU */ + /* instruction FCVT.S.LU, encoding '110100000011.............1010011' */ {32, 0b11010000001100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_s_lu}, - /* instruction FLD */ + /* instruction FLD, encoding '.................011.....0000111' */ {32, 0b00000000000000000011000000000111, 0b00000000000000000111000001111111, &this_class::__fld}, - /* instruction FSD */ + /* instruction FSD, encoding '.................011.....0100111' */ {32, 0b00000000000000000011000000100111, 0b00000000000000000111000001111111, &this_class::__fsd}, - /* instruction FMADD.D */ + /* instruction FMADD.D, encoding '.....01..................1000011' */ {32, 0b00000010000000000000000001000011, 0b00000110000000000000000001111111, &this_class::__fmadd_d}, - /* instruction FMSUB.D */ + /* instruction FMSUB.D, encoding '.....01..................1000111' */ {32, 0b00000010000000000000000001000111, 0b00000110000000000000000001111111, &this_class::__fmsub_d}, - /* instruction FNMADD.D */ + /* instruction FNMADD.D, encoding '.....01..................1001111' */ {32, 0b00000010000000000000000001001111, 0b00000110000000000000000001111111, &this_class::__fnmadd_d}, - /* instruction FNMSUB.D */ + /* instruction FNMSUB.D, encoding '.....01..................1001011' */ {32, 0b00000010000000000000000001001011, 0b00000110000000000000000001111111, &this_class::__fnmsub_d}, - /* instruction FADD.D */ + /* instruction FADD.D, encoding '0000001..................1010011' */ {32, 0b00000010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fadd_d}, - /* instruction FSUB.D */ + /* instruction FSUB.D, encoding '0000101..................1010011' */ {32, 0b00001010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fsub_d}, - /* instruction FMUL.D */ + /* instruction FMUL.D, encoding '0001001..................1010011' */ {32, 0b00010010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fmul_d}, - /* instruction FDIV.D */ + /* instruction FDIV.D, encoding '0001101..................1010011' */ {32, 0b00011010000000000000000001010011, 0b11111110000000000000000001111111, &this_class::__fdiv_d}, - /* instruction FSQRT.D */ + /* instruction FSQRT.D, encoding '010110100000.............1010011' */ {32, 0b01011010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fsqrt_d}, - /* instruction FSGNJ.D */ + /* instruction FSGNJ.D, encoding '0010001..........000.....1010011' */ {32, 0b00100010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnj_d}, - /* instruction FSGNJN.D */ + /* instruction FSGNJN.D, encoding '0010001..........001.....1010011' */ {32, 0b00100010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjn_d}, - /* instruction FSGNJX.D */ + /* instruction FSGNJX.D, encoding '0010001..........010.....1010011' */ {32, 0b00100010000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__fsgnjx_d}, - /* instruction FMIN.D */ + /* instruction FMIN.D, encoding '0010101..........000.....1010011' */ {32, 0b00101010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fmin_d}, - /* instruction FMAX.D */ + /* instruction FMAX.D, encoding '0010101..........001.....1010011' */ {32, 0b00101010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__fmax_d}, - /* instruction FCVT.S.D */ + /* instruction FCVT.S.D, encoding '010000000001.............1010011' */ {32, 0b01000000000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_s_d}, - /* instruction FCVT.D.S */ + /* instruction FCVT.D.S, encoding '010000100000.............1010011' */ {32, 0b01000010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_d_s}, - /* instruction FEQ.D */ + /* instruction FEQ.D, encoding '1010001..........010.....1010011' */ {32, 0b10100010000000000010000001010011, 0b11111110000000000111000001111111, &this_class::__feq_d}, - /* instruction FLT.D */ + /* instruction FLT.D, encoding '1010001..........001.....1010011' */ {32, 0b10100010000000000001000001010011, 0b11111110000000000111000001111111, &this_class::__flt_d}, - /* instruction FLE.D */ + /* instruction FLE.D, encoding '1010001..........000.....1010011' */ {32, 0b10100010000000000000000001010011, 0b11111110000000000111000001111111, &this_class::__fle_d}, - /* instruction FCLASS.D */ + /* instruction FCLASS.D, encoding '111000100000.....001.....1010011' */ {32, 0b11100010000000000001000001010011, 0b11111111111100000111000001111111, &this_class::__fclass_d}, - /* instruction FCVT.W.D */ + /* instruction FCVT.W.D, encoding '110000100000.............1010011' */ {32, 0b11000010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_w_d}, - /* instruction FCVT.WU.D */ + /* instruction FCVT.WU.D, encoding '110000100001.............1010011' */ {32, 0b11000010000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_wu_d}, - /* instruction FCVT.D.W */ + /* instruction FCVT.D.W, encoding '110100100000.............1010011' */ {32, 0b11010010000000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_d_w}, - /* instruction FCVT.D.WU */ + /* instruction FCVT.D.WU, encoding '110100100001.............1010011' */ {32, 0b11010010000100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_d_wu}, - /* instruction FCVT.L.D */ + /* instruction FCVT.L.D, encoding '110000100010.............1010011' */ {32, 0b11000010001000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_l_d}, - /* instruction FCVT.LU.D */ + /* instruction FCVT.LU.D, encoding '110000100011.............1010011' */ {32, 0b11000010001100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_lu_d}, - /* instruction FCVT.D.L */ + /* instruction FCVT.D.L, encoding '110100100010.............1010011' */ {32, 0b11010010001000000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_d_l}, - /* instruction FCVT.D.LU */ + /* instruction FCVT.D.LU, encoding '110100100011.............1010011' */ {32, 0b11010010001100000000000001010011, 0b11111111111100000000000001111111, &this_class::__fcvt_d_lu}, - /* instruction FMV.X.D */ + /* instruction FMV.X.D, encoding '111000100000.....000.....1010011' */ {32, 0b11100010000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv_x_d}, - /* instruction FMV.D.X */ + /* instruction FMV.D.X, encoding '111100100000.....000.....1010011' */ {32, 0b11110010000000000000000001010011, 0b11111111111100000111000001111111, &this_class::__fmv_d_x}, - /* instruction C.ADDI4SPN */ + /* instruction C.ADDI4SPN, encoding '000...........00' */ {16, 0b0000000000000000, 0b1110000000000011, &this_class::__c_addi4spn}, - /* instruction C.LW */ + /* instruction C.LW, encoding '010...........00' */ {16, 0b0100000000000000, 0b1110000000000011, &this_class::__c_lw}, - /* instruction C.SW */ + /* instruction C.SW, encoding '110...........00' */ {16, 0b1100000000000000, 0b1110000000000011, &this_class::__c_sw}, - /* instruction C.ADDI */ + /* instruction C.ADDI, encoding '000...........01' */ {16, 0b0000000000000001, 0b1110000000000011, &this_class::__c_addi}, - /* instruction C.NOP */ + /* instruction C.NOP, encoding '0000000000000001' */ {16, 0b0000000000000001, 0b1111111111111111, &this_class::__c_nop}, - /* instruction C.JAL */ - {16, 0b0010000000000001, 0b1110000000000011, &this_class::__c_jal}, - /* instruction C.LI */ - {16, 0b0100000000000001, 0b1110000000000011, &this_class::__c_li}, - /* instruction C.LUI */ - {16, 0b0110000000000001, 0b1110000000000011, &this_class::__c_lui}, - /* instruction C.ADDI16SP */ - {16, 0b0110000100000001, 0b1110111110000011, &this_class::__c_addi16sp}, - /* instruction C.SRLI */ - {16, 0b1000000000000001, 0b1111110000000011, &this_class::__c_srli}, - /* instruction C.SRAI */ - {16, 0b1000010000000001, 0b1111110000000011, &this_class::__c_srai}, - /* instruction C.ANDI */ - {16, 0b1000100000000001, 0b1110110000000011, &this_class::__c_andi}, - /* instruction C.SUB */ - {16, 0b1000110000000001, 0b1111110001100011, &this_class::__c_sub}, - /* instruction C.XOR */ - {16, 0b1000110000100001, 0b1111110001100011, &this_class::__c_xor}, - /* instruction C.OR */ - {16, 0b1000110001000001, 0b1111110001100011, &this_class::__c_or}, - /* instruction C.AND */ - {16, 0b1000110001100001, 0b1111110001100011, &this_class::__c_and}, - /* instruction C.J */ - {16, 0b1010000000000001, 0b1110000000000011, &this_class::__c_j}, - /* instruction C.BEQZ */ - {16, 0b1100000000000001, 0b1110000000000011, &this_class::__c_beqz}, - /* instruction C.BNEZ */ - {16, 0b1110000000000001, 0b1110000000000011, &this_class::__c_bnez}, - /* instruction C.SLLI */ - {16, 0b0000000000000010, 0b1111000000000011, &this_class::__c_slli}, - /* instruction C.LWSP */ - {16, 0b0100000000000010, 0b1110000000000011, &this_class::__c_lwsp}, - /* instruction C.MV */ - {16, 0b1000000000000010, 0b1111000000000011, &this_class::__c_mv}, - /* instruction C.JR */ - {16, 0b1000000000000010, 0b1111000001111111, &this_class::__c_jr}, - /* instruction C.ADD */ - {16, 0b1001000000000010, 0b1111000000000011, &this_class::__c_add}, - /* instruction C.JALR */ - {16, 0b1001000000000010, 0b1111000001111111, &this_class::__c_jalr}, - /* instruction C.EBREAK */ - {16, 0b1001000000000010, 0b1111111111111111, &this_class::__c_ebreak}, - /* instruction C.SWSP */ - {16, 0b1100000000000010, 0b1110000000000011, &this_class::__c_swsp}, - /* instruction DII */ - {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, - /* instruction C.LD */ - {16, 0b0110000000000000, 0b1110000000000011, &this_class::__c_ld}, - /* instruction C.SD */ - {16, 0b1110000000000000, 0b1110000000000011, &this_class::__c_sd}, - /* instruction C.SUBW */ - {16, 0b1001110000000001, 0b1111110001100011, &this_class::__c_subw}, - /* instruction C.ADDW */ - {16, 0b1001110000100001, 0b1111110001100011, &this_class::__c_addw}, - /* instruction C.ADDIW */ + /* instruction C.ADDIW, encoding '001...........01' */ {16, 0b0010000000000001, 0b1110000000000011, &this_class::__c_addiw}, - /* instruction C.LDSP */ + /* instruction C.LI, encoding '010...........01' */ + {16, 0b0100000000000001, 0b1110000000000011, &this_class::__c_li}, + /* instruction C.LUI, encoding '011...........01' */ + {16, 0b0110000000000001, 0b1110000000000011, &this_class::__c_lui}, + /* instruction C.ADDI16SP, encoding '011.00010.....01' */ + {16, 0b0110000100000001, 0b1110111110000011, &this_class::__c_addi16sp}, + /* instruction C.SRLI, encoding '100000........01' */ + {16, 0b1000000000000001, 0b1111110000000011, &this_class::__c_srli}, + /* instruction C.SRAI, encoding '100001........01' */ + {16, 0b1000010000000001, 0b1111110000000011, &this_class::__c_srai}, + /* instruction C.ANDI, encoding '100.10........01' */ + {16, 0b1000100000000001, 0b1110110000000011, &this_class::__c_andi}, + /* instruction C.SUB, encoding '100011...00...01' */ + {16, 0b1000110000000001, 0b1111110001100011, &this_class::__c_sub}, + /* instruction C.XOR, encoding '100011...01...01' */ + {16, 0b1000110000100001, 0b1111110001100011, &this_class::__c_xor}, + /* instruction C.OR, encoding '100011...10...01' */ + {16, 0b1000110001000001, 0b1111110001100011, &this_class::__c_or}, + /* instruction C.AND, encoding '100011...11...01' */ + {16, 0b1000110001100001, 0b1111110001100011, &this_class::__c_and}, + /* instruction C.J, encoding '101...........01' */ + {16, 0b1010000000000001, 0b1110000000000011, &this_class::__c_j}, + /* instruction C.BEQZ, encoding '110...........01' */ + {16, 0b1100000000000001, 0b1110000000000011, &this_class::__c_beqz}, + /* instruction C.BNEZ, encoding '111...........01' */ + {16, 0b1110000000000001, 0b1110000000000011, &this_class::__c_bnez}, + /* instruction C.SLLI, encoding '0000..........10' */ + {16, 0b0000000000000010, 0b1111000000000011, &this_class::__c_slli}, + /* instruction C.LWSP, encoding '010...........10' */ + {16, 0b0100000000000010, 0b1110000000000011, &this_class::__c_lwsp}, + /* instruction C.MV, encoding '1000..........10' */ + {16, 0b1000000000000010, 0b1111000000000011, &this_class::__c_mv}, + /* instruction C.JR, encoding '1000.....0000010' */ + {16, 0b1000000000000010, 0b1111000001111111, &this_class::__c_jr}, + /* instruction C.ADD, encoding '1001..........10' */ + {16, 0b1001000000000010, 0b1111000000000011, &this_class::__c_add}, + /* instruction C.JALR, encoding '1001.....0000010' */ + {16, 0b1001000000000010, 0b1111000001111111, &this_class::__c_jalr}, + /* instruction C.EBREAK, encoding '1001000000000010' */ + {16, 0b1001000000000010, 0b1111111111111111, &this_class::__c_ebreak}, + /* instruction C.SWSP, encoding '110...........10' */ + {16, 0b1100000000000010, 0b1110000000000011, &this_class::__c_swsp}, + /* instruction DII, encoding '0000000000000000' */ + {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, + /* instruction C.LD, encoding '011...........00' */ + {16, 0b0110000000000000, 0b1110000000000011, &this_class::__c_ld}, + /* instruction C.SD, encoding '111...........00' */ + {16, 0b1110000000000000, 0b1110000000000011, &this_class::__c_sd}, + /* instruction C.LDSP, encoding '011...........10' */ {16, 0b0110000000000010, 0b1110000000000011, &this_class::__c_ldsp}, - /* instruction C.SDSP */ + /* instruction C.SDSP, encoding '111...........10' */ {16, 0b1110000000000010, 0b1110000000000011, &this_class::__c_sdsp}, - /* instruction C.FLW */ - {16, 0b0110000000000000, 0b1110000000000011, &this_class::__c_flw}, - /* instruction C.FSW */ - {16, 0b1110000000000000, 0b1110000000000011, &this_class::__c_fsw}, - /* instruction C.FLWSP */ - {16, 0b0110000000000010, 0b1110000000000011, &this_class::__c_flwsp}, - /* instruction C.FSWSP */ - {16, 0b1110000000000010, 0b1110000000000011, &this_class::__c_fswsp}, - /* instruction C.FLD */ + /* instruction C.FLD, encoding '001...........00' */ {16, 0b0010000000000000, 0b1110000000000011, &this_class::__c_fld}, - /* instruction C.FSD */ + /* instruction C.FSD, encoding '101...........00' */ {16, 0b1010000000000000, 0b1110000000000011, &this_class::__c_fsd}, - /* instruction C.FLDSP */ + /* instruction C.FLDSP, encoding '001...........10' */ {16, 0b0010000000000010, 0b1110000000000011, &this_class::__c_fldsp}, - /* instruction C.FSDSP */ + /* instruction C.FSDSP, encoding '101...........10' */ {16, 0b1010000000000010, 0b1110000000000011, &this_class::__c_fsdsp}, + /* instruction C.SUBW, encoding '100111...00...01' */ + {16, 0b1001110000000001, 0b1111110001100011, &this_class::__c_subw}, + /* instruction C.ADDW, encoding '100111...01...01' */ + {16, 0b1001110000100001, 0b1111110001100011, &this_class::__c_addw}, + /* instruction C.SRLI, encoding '100.00........01' */ + {16, 0b1000000000000001, 0b1110110000000011, &this_class::__c_srli}, + /* instruction C.SRAI, encoding '100.01........01' */ + {16, 0b1000010000000001, 0b1110110000000011, &this_class::__c_srai}, + /* instruction C.SLLI, encoding '000...........10' */ + {16, 0b0000000000000010, 0b1110000000000011, &this_class::__c_slli}, }}; /* instruction definitions */ @@ -2386,10 +2388,97 @@ private: return std::make_tuple(CONT); } - /* instruction 55: ADDIW */ + /* instruction 55: SLLI */ + compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SLLI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 55); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.shl( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 55); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 56: SRLI */ + compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SRLI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 56); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.lshr( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 56); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 57: SRAI */ + compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SRAI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 57); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.ashr( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 57); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 58: ADDIW */ compile_ret_t __addiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 55); + vm_base::gen_sync(tu, PRE_SYNC, 58); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -2419,15 +2508,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 55); + vm_base::gen_sync(tu, POST_SYNC, 58); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 56: SLLIW */ + /* instruction 59: SLLIW */ compile_ret_t __slliw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 56); + vm_base::gen_sync(tu, PRE_SYNC, 59); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2455,15 +2544,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 56); + vm_base::gen_sync(tu, POST_SYNC, 59); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 57: SRLIW */ + /* instruction 60: SRLIW */ compile_ret_t __srliw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 57); + vm_base::gen_sync(tu, PRE_SYNC, 60); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2491,15 +2580,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 57); + vm_base::gen_sync(tu, POST_SYNC, 60); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 58: SRAIW */ + /* instruction 61: SRAIW */ compile_ret_t __sraiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 58); + vm_base::gen_sync(tu, PRE_SYNC, 61); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2527,15 +2616,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 58); + vm_base::gen_sync(tu, POST_SYNC, 61); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 59: ADDW */ + /* instruction 62: ADDW */ compile_ret_t __addw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 59); + vm_base::gen_sync(tu, PRE_SYNC, 62); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2563,15 +2652,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 59); + vm_base::gen_sync(tu, POST_SYNC, 62); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 60: SUBW */ + /* instruction 63: SUBW */ compile_ret_t __subw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SUBW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 60); + vm_base::gen_sync(tu, PRE_SYNC, 63); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2599,15 +2688,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 60); + vm_base::gen_sync(tu, POST_SYNC, 63); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 61: SLLW */ + /* instruction 64: SLLW */ compile_ret_t __sllw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 61); + vm_base::gen_sync(tu, PRE_SYNC, 64); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2642,15 +2731,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 61); + vm_base::gen_sync(tu, POST_SYNC, 64); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 62: SRLW */ + /* instruction 65: SRLW */ compile_ret_t __srlw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 62); + vm_base::gen_sync(tu, PRE_SYNC, 65); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2685,15 +2774,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 62); + vm_base::gen_sync(tu, POST_SYNC, 65); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 63: SRAW */ + /* instruction 66: SRAW */ compile_ret_t __sraw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 63); + vm_base::gen_sync(tu, PRE_SYNC, 66); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2728,15 +2817,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 63); + vm_base::gen_sync(tu, POST_SYNC, 66); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 64: MUL */ + /* instruction 67: MUL */ compile_ret_t __mul(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MUL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 64); + vm_base::gen_sync(tu, PRE_SYNC, 67); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2767,15 +2856,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 64); + vm_base::gen_sync(tu, POST_SYNC, 67); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 65: MULH */ + /* instruction 68: MULH */ compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULH_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 65); + vm_base::gen_sync(tu, PRE_SYNC, 68); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2808,15 +2897,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 65); + vm_base::gen_sync(tu, POST_SYNC, 68); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 66: MULHSU */ + /* instruction 69: MULHSU */ compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHSU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 66); + vm_base::gen_sync(tu, PRE_SYNC, 69); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2849,15 +2938,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 66); + vm_base::gen_sync(tu, POST_SYNC, 69); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 67: MULHU */ + /* instruction 70: MULHU */ compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULHU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 67); + vm_base::gen_sync(tu, PRE_SYNC, 70); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2890,15 +2979,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 67); + vm_base::gen_sync(tu, POST_SYNC, 70); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 68: DIV */ + /* instruction 71: DIV */ compile_ret_t __div(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIV_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 68); + vm_base::gen_sync(tu, PRE_SYNC, 71); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2946,15 +3035,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 68); + vm_base::gen_sync(tu, POST_SYNC, 71); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 69: DIVU */ + /* instruction 72: DIVU */ compile_ret_t __divu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIVU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 69); + vm_base::gen_sync(tu, PRE_SYNC, 72); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2982,15 +3071,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 69); + vm_base::gen_sync(tu, POST_SYNC, 72); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 70: REM */ + /* instruction 73: REM */ compile_ret_t __rem(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REM_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 70); + vm_base::gen_sync(tu, PRE_SYNC, 73); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3038,15 +3127,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 70); + vm_base::gen_sync(tu, POST_SYNC, 73); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 71: REMU */ + /* instruction 74: REMU */ compile_ret_t __remu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REMU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 71); + vm_base::gen_sync(tu, PRE_SYNC, 74); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3074,15 +3163,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 71); + vm_base::gen_sync(tu, POST_SYNC, 74); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 72: MULW */ + /* instruction 75: MULW */ compile_ret_t __mulw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("MULW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 72); + vm_base::gen_sync(tu, PRE_SYNC, 75); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3112,15 +3201,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 72); + vm_base::gen_sync(tu, POST_SYNC, 75); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 73: DIVW */ + /* instruction 76: DIVW */ compile_ret_t __divw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIVW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 73); + vm_base::gen_sync(tu, PRE_SYNC, 76); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3184,15 +3273,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 73); + vm_base::gen_sync(tu, POST_SYNC, 76); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 74: DIVUW */ + /* instruction 77: DIVUW */ compile_ret_t __divuw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DIVUW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 74); + vm_base::gen_sync(tu, PRE_SYNC, 77); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3232,15 +3321,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 74); + vm_base::gen_sync(tu, POST_SYNC, 77); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 75: REMW */ + /* instruction 78: REMW */ compile_ret_t __remw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REMW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 75); + vm_base::gen_sync(tu, PRE_SYNC, 78); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3305,15 +3394,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 75); + vm_base::gen_sync(tu, POST_SYNC, 78); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 76: REMUW */ + /* instruction 79: REMUW */ compile_ret_t __remuw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("REMUW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 76); + vm_base::gen_sync(tu, PRE_SYNC, 79); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3359,15 +3448,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 76); + vm_base::gen_sync(tu, POST_SYNC, 79); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 77: LR.W */ + /* instruction 80: LR.W */ compile_ret_t __lr_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 77); + vm_base::gen_sync(tu, PRE_SYNC, 80); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rl = ((bit_sub<25,1>(instr))); @@ -3398,15 +3487,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 77); + vm_base::gen_sync(tu, POST_SYNC, 80); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 78: SC.W */ + /* instruction 81: SC.W */ compile_ret_t __sc_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SC_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 78); + vm_base::gen_sync(tu, PRE_SYNC, 81); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3447,15 +3536,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 78); + vm_base::gen_sync(tu, POST_SYNC, 81); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 79: AMOSWAP.W */ + /* instruction 82: AMOSWAP.W */ compile_ret_t __amoswap_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOSWAP_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 79); + vm_base::gen_sync(tu, PRE_SYNC, 82); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3484,15 +3573,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 79); + vm_base::gen_sync(tu, POST_SYNC, 82); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 80: AMOADD.W */ + /* instruction 83: AMOADD.W */ compile_ret_t __amoadd_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOADD_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 80); + vm_base::gen_sync(tu, PRE_SYNC, 83); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3525,15 +3614,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 80); + vm_base::gen_sync(tu, POST_SYNC, 83); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 81: AMOXOR.W */ + /* instruction 84: AMOXOR.W */ compile_ret_t __amoxor_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOXOR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 81); + vm_base::gen_sync(tu, PRE_SYNC, 84); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3566,15 +3655,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 81); + vm_base::gen_sync(tu, POST_SYNC, 84); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 82: AMOAND.W */ + /* instruction 85: AMOAND.W */ compile_ret_t __amoand_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOAND_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 82); + vm_base::gen_sync(tu, PRE_SYNC, 85); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3607,15 +3696,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 82); + vm_base::gen_sync(tu, POST_SYNC, 85); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 83: AMOOR.W */ + /* instruction 86: AMOOR.W */ compile_ret_t __amoor_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOOR_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 83); + vm_base::gen_sync(tu, PRE_SYNC, 86); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3648,15 +3737,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 83); + vm_base::gen_sync(tu, POST_SYNC, 86); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 84: AMOMIN.W */ + /* instruction 87: AMOMIN.W */ compile_ret_t __amomin_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMIN_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 84); + vm_base::gen_sync(tu, PRE_SYNC, 87); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3697,15 +3786,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 84); + vm_base::gen_sync(tu, POST_SYNC, 87); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 85: AMOMAX.W */ + /* instruction 88: AMOMAX.W */ compile_ret_t __amomax_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAX_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 85); + vm_base::gen_sync(tu, PRE_SYNC, 88); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3746,15 +3835,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 85); + vm_base::gen_sync(tu, POST_SYNC, 88); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 86: AMOMINU.W */ + /* instruction 89: AMOMINU.W */ compile_ret_t __amominu_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMINU_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 86); + vm_base::gen_sync(tu, PRE_SYNC, 89); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3791,15 +3880,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 86); + vm_base::gen_sync(tu, POST_SYNC, 89); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 87: AMOMAXU.W */ + /* instruction 90: AMOMAXU.W */ compile_ret_t __amomaxu_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAXU_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 87); + vm_base::gen_sync(tu, PRE_SYNC, 90); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3836,15 +3925,15 @@ private: tu.trunc(res2_val, 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 87); + vm_base::gen_sync(tu, POST_SYNC, 90); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 88: LR.D */ + /* instruction 91: LR.D */ compile_ret_t __lr_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("LR_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 88); + vm_base::gen_sync(tu, PRE_SYNC, 91); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rl = ((bit_sub<25,1>(instr))); @@ -3875,15 +3964,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 88); + vm_base::gen_sync(tu, POST_SYNC, 91); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 89: SC.D */ + /* instruction 92: SC.D */ compile_ret_t __sc_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SC_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 89); + vm_base::gen_sync(tu, PRE_SYNC, 92); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3918,15 +4007,15 @@ private: tu.close_scope(); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 89); + vm_base::gen_sync(tu, POST_SYNC, 92); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 90: AMOSWAP.D */ + /* instruction 93: AMOSWAP.D */ compile_ret_t __amoswap_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOSWAP_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 90); + vm_base::gen_sync(tu, PRE_SYNC, 93); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3955,15 +4044,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 90); + vm_base::gen_sync(tu, POST_SYNC, 93); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 91: AMOADD.D */ + /* instruction 94: AMOADD.D */ compile_ret_t __amoadd_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOADD_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 91); + vm_base::gen_sync(tu, PRE_SYNC, 94); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -3996,15 +4085,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 91); + vm_base::gen_sync(tu, POST_SYNC, 94); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 92: AMOXOR.D */ + /* instruction 95: AMOXOR.D */ compile_ret_t __amoxor_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOXOR_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 92); + vm_base::gen_sync(tu, PRE_SYNC, 95); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4037,15 +4126,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 92); + vm_base::gen_sync(tu, POST_SYNC, 95); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 93: AMOAND.D */ + /* instruction 96: AMOAND.D */ compile_ret_t __amoand_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOAND_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 93); + vm_base::gen_sync(tu, PRE_SYNC, 96); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4078,15 +4167,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 93); + vm_base::gen_sync(tu, POST_SYNC, 96); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 94: AMOOR.D */ + /* instruction 97: AMOOR.D */ compile_ret_t __amoor_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOOR_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 94); + vm_base::gen_sync(tu, PRE_SYNC, 97); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4119,15 +4208,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 94); + vm_base::gen_sync(tu, POST_SYNC, 97); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 95: AMOMIN.D */ + /* instruction 98: AMOMIN.D */ compile_ret_t __amomin_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMIN_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 95); + vm_base::gen_sync(tu, PRE_SYNC, 98); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4168,15 +4257,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 95); + vm_base::gen_sync(tu, POST_SYNC, 98); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 96: AMOMAX.D */ + /* instruction 99: AMOMAX.D */ compile_ret_t __amomax_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAX_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 96); + vm_base::gen_sync(tu, PRE_SYNC, 99); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4217,15 +4306,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 96); + vm_base::gen_sync(tu, POST_SYNC, 99); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 97: AMOMINU.D */ + /* instruction 100: AMOMINU.D */ compile_ret_t __amominu_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMINU_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 97); + vm_base::gen_sync(tu, PRE_SYNC, 100); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4262,15 +4351,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 97); + vm_base::gen_sync(tu, POST_SYNC, 100); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 98: AMOMAXU.D */ + /* instruction 101: AMOMAXU.D */ compile_ret_t __amomaxu_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("AMOMAXU_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 98); + vm_base::gen_sync(tu, PRE_SYNC, 101); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4307,15 +4396,15 @@ private: tu.trunc(res2_val, 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 98); + vm_base::gen_sync(tu, POST_SYNC, 101); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 99: FLW */ + /* instruction 102: FLW */ compile_ret_t __flw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 99); + vm_base::gen_sync(tu, PRE_SYNC, 102); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -4350,15 +4439,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 99); + vm_base::gen_sync(tu, POST_SYNC, 102); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 100: FSW */ + /* instruction 103: FSW */ compile_ret_t __fsw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 100); + vm_base::gen_sync(tu, PRE_SYNC, 103); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -4386,15 +4475,15 @@ private: ), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 100); + vm_base::gen_sync(tu, POST_SYNC, 103); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 101: FMADD.S */ + /* instruction 104: FMADD.S */ compile_ret_t __fmadd_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMADD_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 101); + vm_base::gen_sync(tu, PRE_SYNC, 104); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4479,15 +4568,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 101); + vm_base::gen_sync(tu, POST_SYNC, 104); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 102: FMSUB.S */ + /* instruction 105: FMSUB.S */ compile_ret_t __fmsub_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMSUB_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 102); + vm_base::gen_sync(tu, PRE_SYNC, 105); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4572,15 +4661,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 102); + vm_base::gen_sync(tu, POST_SYNC, 105); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 103: FNMADD.S */ + /* instruction 106: FNMADD.S */ compile_ret_t __fnmadd_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMADD_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 103); + vm_base::gen_sync(tu, PRE_SYNC, 106); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4665,15 +4754,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 103); + vm_base::gen_sync(tu, POST_SYNC, 106); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 104: FNMSUB.S */ + /* instruction 107: FNMSUB.S */ compile_ret_t __fnmsub_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMSUB_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 104); + vm_base::gen_sync(tu, PRE_SYNC, 107); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4758,15 +4847,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 104); + vm_base::gen_sync(tu, POST_SYNC, 107); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 105: FADD.S */ + /* instruction 108: FADD.S */ compile_ret_t __fadd_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FADD_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 105); + vm_base::gen_sync(tu, PRE_SYNC, 108); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4837,15 +4926,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 105); + vm_base::gen_sync(tu, POST_SYNC, 108); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 106: FSUB.S */ + /* instruction 109: FSUB.S */ compile_ret_t __fsub_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSUB_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 106); + vm_base::gen_sync(tu, PRE_SYNC, 109); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4916,15 +5005,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 106); + vm_base::gen_sync(tu, POST_SYNC, 109); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 107: FMUL.S */ + /* instruction 110: FMUL.S */ compile_ret_t __fmul_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMUL_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 107); + vm_base::gen_sync(tu, PRE_SYNC, 110); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -4995,15 +5084,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 107); + vm_base::gen_sync(tu, POST_SYNC, 110); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 108: FDIV.S */ + /* instruction 111: FDIV.S */ compile_ret_t __fdiv_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FDIV_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 108); + vm_base::gen_sync(tu, PRE_SYNC, 111); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5074,15 +5163,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 108); + vm_base::gen_sync(tu, POST_SYNC, 111); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 109: FSQRT.S */ + /* instruction 112: FSQRT.S */ compile_ret_t __fsqrt_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSQRT_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 109); + vm_base::gen_sync(tu, PRE_SYNC, 112); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5147,15 +5236,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 109); + vm_base::gen_sync(tu, POST_SYNC, 112); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 110: FSGNJ.S */ + /* instruction 113: FSGNJ.S */ compile_ret_t __fsgnj_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJ_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 110); + vm_base::gen_sync(tu, PRE_SYNC, 113); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5203,15 +5292,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 110); + vm_base::gen_sync(tu, POST_SYNC, 113); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 111: FSGNJN.S */ + /* instruction 114: FSGNJN.S */ compile_ret_t __fsgnjn_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJN_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 111); + vm_base::gen_sync(tu, PRE_SYNC, 114); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5259,15 +5348,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 111); + vm_base::gen_sync(tu, POST_SYNC, 114); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 112: FSGNJX.S */ + /* instruction 115: FSGNJX.S */ compile_ret_t __fsgnjx_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJX_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 112); + vm_base::gen_sync(tu, PRE_SYNC, 115); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5311,15 +5400,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 112); + vm_base::gen_sync(tu, POST_SYNC, 115); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 113: FMIN.S */ + /* instruction 116: FMIN.S */ compile_ret_t __fmin_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMIN_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 113); + vm_base::gen_sync(tu, PRE_SYNC, 116); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5377,15 +5466,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 113); + vm_base::gen_sync(tu, POST_SYNC, 116); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 114: FMAX.S */ + /* instruction 117: FMAX.S */ compile_ret_t __fmax_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMAX_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 114); + vm_base::gen_sync(tu, PRE_SYNC, 117); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5443,15 +5532,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 114); + vm_base::gen_sync(tu, POST_SYNC, 117); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 115: FCVT.W.S */ + /* instruction 118: FCVT.W.S */ compile_ret_t __fcvt_w_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_W_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 115); + vm_base::gen_sync(tu, PRE_SYNC, 118); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5503,15 +5592,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 115); + vm_base::gen_sync(tu, POST_SYNC, 118); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 116: FCVT.WU.S */ + /* instruction 119: FCVT.WU.S */ compile_ret_t __fcvt_wu_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_WU_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 116); + vm_base::gen_sync(tu, PRE_SYNC, 119); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5563,15 +5652,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 116); + vm_base::gen_sync(tu, POST_SYNC, 119); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 117: FEQ.S */ + /* instruction 120: FEQ.S */ compile_ret_t __feq_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FEQ_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 117); + vm_base::gen_sync(tu, PRE_SYNC, 120); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5626,15 +5715,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 117); + vm_base::gen_sync(tu, POST_SYNC, 120); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 118: FLT.S */ + /* instruction 121: FLT.S */ compile_ret_t __flt_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLT_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 118); + vm_base::gen_sync(tu, PRE_SYNC, 121); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5703,15 +5792,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 118); + vm_base::gen_sync(tu, POST_SYNC, 121); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 119: FLE.S */ + /* instruction 122: FLE.S */ compile_ret_t __fle_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLE_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 119); + vm_base::gen_sync(tu, PRE_SYNC, 122); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -5766,15 +5855,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 119); + vm_base::gen_sync(tu, POST_SYNC, 122); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 120: FCLASS.S */ + /* instruction 123: FCLASS.S */ compile_ret_t __fclass_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCLASS_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 120); + vm_base::gen_sync(tu, PRE_SYNC, 123); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -5794,15 +5883,15 @@ private: ), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 120); + vm_base::gen_sync(tu, POST_SYNC, 123); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 121: FCVT.S.W */ + /* instruction 124: FCVT.S.W */ compile_ret_t __fcvt_s_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 121); + vm_base::gen_sync(tu, PRE_SYNC, 124); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5852,15 +5941,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 121); + vm_base::gen_sync(tu, POST_SYNC, 124); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 122: FCVT.S.WU */ + /* instruction 125: FCVT.S.WU */ compile_ret_t __fcvt_s_wu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_WU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 122); + vm_base::gen_sync(tu, PRE_SYNC, 125); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -5910,15 +5999,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 122); + vm_base::gen_sync(tu, POST_SYNC, 125); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 123: FMV.X.W */ + /* instruction 126: FMV.X.W */ compile_ret_t __fmv_x_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMV_X_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 123); + vm_base::gen_sync(tu, PRE_SYNC, 126); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -5940,15 +6029,15 @@ private: false), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 123); + vm_base::gen_sync(tu, POST_SYNC, 126); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 124: FMV.W.X */ + /* instruction 127: FMV.W.X */ compile_ret_t __fmv_w_x(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMV_W_X_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 124); + vm_base::gen_sync(tu, PRE_SYNC, 127); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -5982,15 +6071,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 124); + vm_base::gen_sync(tu, POST_SYNC, 127); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 125: FCVT.L.S */ + /* instruction 128: FCVT.L.S */ compile_ret_t __fcvt_l_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_L_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 125); + vm_base::gen_sync(tu, PRE_SYNC, 128); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6028,15 +6117,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 125); + vm_base::gen_sync(tu, POST_SYNC, 128); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 126: FCVT.LU.S */ + /* instruction 129: FCVT.LU.S */ compile_ret_t __fcvt_lu_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_LU_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 126); + vm_base::gen_sync(tu, PRE_SYNC, 129); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6074,15 +6163,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 126); + vm_base::gen_sync(tu, POST_SYNC, 129); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 127: FCVT.S.L */ + /* instruction 130: FCVT.S.L */ compile_ret_t __fcvt_s_l(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_L_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 127); + vm_base::gen_sync(tu, PRE_SYNC, 130); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6119,15 +6208,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 127); + vm_base::gen_sync(tu, POST_SYNC, 130); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 128: FCVT.S.LU */ + /* instruction 131: FCVT.S.LU */ compile_ret_t __fcvt_s_lu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_LU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 128); + vm_base::gen_sync(tu, PRE_SYNC, 131); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6164,15 +6253,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 128); + vm_base::gen_sync(tu, POST_SYNC, 131); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 129: FLD */ + /* instruction 132: FLD */ compile_ret_t __fld(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 129); + vm_base::gen_sync(tu, PRE_SYNC, 132); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -6204,15 +6293,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 129); + vm_base::gen_sync(tu, POST_SYNC, 132); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 130: FSD */ + /* instruction 133: FSD */ compile_ret_t __fsd(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 130); + vm_base::gen_sync(tu, PRE_SYNC, 133); int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -6240,15 +6329,15 @@ private: ), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 130); + vm_base::gen_sync(tu, POST_SYNC, 133); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 131: FMADD.D */ + /* instruction 134: FMADD.D */ compile_ret_t __fmadd_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMADD_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 131); + vm_base::gen_sync(tu, PRE_SYNC, 134); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6312,15 +6401,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 131); + vm_base::gen_sync(tu, POST_SYNC, 134); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 132: FMSUB.D */ + /* instruction 135: FMSUB.D */ compile_ret_t __fmsub_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMSUB_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 132); + vm_base::gen_sync(tu, PRE_SYNC, 135); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6384,15 +6473,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 132); + vm_base::gen_sync(tu, POST_SYNC, 135); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 133: FNMADD.D */ + /* instruction 136: FNMADD.D */ compile_ret_t __fnmadd_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMADD_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 133); + vm_base::gen_sync(tu, PRE_SYNC, 136); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6456,15 +6545,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 133); + vm_base::gen_sync(tu, POST_SYNC, 136); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 134: FNMSUB.D */ + /* instruction 137: FNMSUB.D */ compile_ret_t __fnmsub_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FNMSUB_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 134); + vm_base::gen_sync(tu, PRE_SYNC, 137); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6528,15 +6617,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 134); + vm_base::gen_sync(tu, POST_SYNC, 137); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 135: FADD.D */ + /* instruction 138: FADD.D */ compile_ret_t __fadd_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FADD_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 135); + vm_base::gen_sync(tu, PRE_SYNC, 138); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6591,15 +6680,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 135); + vm_base::gen_sync(tu, POST_SYNC, 138); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 136: FSUB.D */ + /* instruction 139: FSUB.D */ compile_ret_t __fsub_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSUB_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 136); + vm_base::gen_sync(tu, PRE_SYNC, 139); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6654,15 +6743,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 136); + vm_base::gen_sync(tu, POST_SYNC, 139); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 137: FMUL.D */ + /* instruction 140: FMUL.D */ compile_ret_t __fmul_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMUL_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 137); + vm_base::gen_sync(tu, PRE_SYNC, 140); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6717,15 +6806,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 137); + vm_base::gen_sync(tu, POST_SYNC, 140); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 138: FDIV.D */ + /* instruction 141: FDIV.D */ compile_ret_t __fdiv_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FDIV_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 138); + vm_base::gen_sync(tu, PRE_SYNC, 141); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6780,15 +6869,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 138); + vm_base::gen_sync(tu, POST_SYNC, 141); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 139: FSQRT.D */ + /* instruction 142: FSQRT.D */ compile_ret_t __fsqrt_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSQRT_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 139); + vm_base::gen_sync(tu, PRE_SYNC, 142); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -6838,15 +6927,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 139); + vm_base::gen_sync(tu, POST_SYNC, 142); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 140: FSGNJ.D */ + /* instruction 143: FSGNJ.D */ compile_ret_t __fsgnj_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJ_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 140); + vm_base::gen_sync(tu, PRE_SYNC, 143); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -6888,15 +6977,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 140); + vm_base::gen_sync(tu, POST_SYNC, 143); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 141: FSGNJN.D */ + /* instruction 144: FSGNJN.D */ compile_ret_t __fsgnjn_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJN_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 141); + vm_base::gen_sync(tu, PRE_SYNC, 144); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -6938,15 +7027,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 141); + vm_base::gen_sync(tu, POST_SYNC, 144); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 142: FSGNJX.D */ + /* instruction 145: FSGNJX.D */ compile_ret_t __fsgnjx_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FSGNJX_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 142); + vm_base::gen_sync(tu, PRE_SYNC, 145); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -6985,15 +7074,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 142); + vm_base::gen_sync(tu, POST_SYNC, 145); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 143: FMIN.D */ + /* instruction 146: FMIN.D */ compile_ret_t __fmin_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMIN_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 143); + vm_base::gen_sync(tu, PRE_SYNC, 146); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7041,15 +7130,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 143); + vm_base::gen_sync(tu, POST_SYNC, 146); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 144: FMAX.D */ + /* instruction 147: FMAX.D */ compile_ret_t __fmax_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMAX_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 144); + vm_base::gen_sync(tu, PRE_SYNC, 147); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7097,15 +7186,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 144); + vm_base::gen_sync(tu, POST_SYNC, 147); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 145: FCVT.S.D */ + /* instruction 148: FCVT.S.D */ compile_ret_t __fcvt_s_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_S_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 145); + vm_base::gen_sync(tu, PRE_SYNC, 148); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7134,15 +7223,15 @@ private: true)), rd + traits::F0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 145); + vm_base::gen_sync(tu, POST_SYNC, 148); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 146: FCVT.D.S */ + /* instruction 149: FCVT.D.S */ compile_ret_t __fcvt_d_s(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_S_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 146); + vm_base::gen_sync(tu, PRE_SYNC, 149); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7175,15 +7264,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 146); + vm_base::gen_sync(tu, POST_SYNC, 149); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 147: FEQ.D */ + /* instruction 150: FEQ.D */ compile_ret_t __feq_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FEQ_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 147); + vm_base::gen_sync(tu, PRE_SYNC, 150); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7224,15 +7313,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 147); + vm_base::gen_sync(tu, POST_SYNC, 150); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 148: FLT.D */ + /* instruction 151: FLT.D */ compile_ret_t __flt_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLT_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 148); + vm_base::gen_sync(tu, PRE_SYNC, 151); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7273,15 +7362,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 148); + vm_base::gen_sync(tu, POST_SYNC, 151); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 149: FLE.D */ + /* instruction 152: FLE.D */ compile_ret_t __fle_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FLE_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 149); + vm_base::gen_sync(tu, PRE_SYNC, 152); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -7322,15 +7411,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 149); + vm_base::gen_sync(tu, POST_SYNC, 152); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 150: FCLASS.D */ + /* instruction 153: FCLASS.D */ compile_ret_t __fclass_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCLASS_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 150); + vm_base::gen_sync(tu, PRE_SYNC, 153); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -7351,15 +7440,15 @@ private: ), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 150); + vm_base::gen_sync(tu, POST_SYNC, 153); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 151: FCVT.W.D */ + /* instruction 154: FCVT.W.D */ compile_ret_t __fcvt_w_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_W_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 151); + vm_base::gen_sync(tu, PRE_SYNC, 154); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7397,15 +7486,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 151); + vm_base::gen_sync(tu, POST_SYNC, 154); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 152: FCVT.WU.D */ + /* instruction 155: FCVT.WU.D */ compile_ret_t __fcvt_wu_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_WU_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 152); + vm_base::gen_sync(tu, PRE_SYNC, 155); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7443,15 +7532,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 152); + vm_base::gen_sync(tu, POST_SYNC, 155); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 153: FCVT.D.W */ + /* instruction 156: FCVT.D.W */ compile_ret_t __fcvt_d_w(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_W_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 153); + vm_base::gen_sync(tu, PRE_SYNC, 156); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7491,15 +7580,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 153); + vm_base::gen_sync(tu, POST_SYNC, 156); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 154: FCVT.D.WU */ + /* instruction 157: FCVT.D.WU */ compile_ret_t __fcvt_d_wu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_WU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 154); + vm_base::gen_sync(tu, PRE_SYNC, 157); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7539,15 +7628,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 154); + vm_base::gen_sync(tu, POST_SYNC, 157); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 155: FCVT.L.D */ + /* instruction 158: FCVT.L.D */ compile_ret_t __fcvt_l_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_L_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 155); + vm_base::gen_sync(tu, PRE_SYNC, 158); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7585,15 +7674,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 155); + vm_base::gen_sync(tu, POST_SYNC, 158); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 156: FCVT.LU.D */ + /* instruction 159: FCVT.LU.D */ compile_ret_t __fcvt_lu_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_LU_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 156); + vm_base::gen_sync(tu, PRE_SYNC, 159); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7631,15 +7720,15 @@ private: tu.store(FCSR_val_v, traits::FCSR); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 156); + vm_base::gen_sync(tu, POST_SYNC, 159); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 157: FCVT.D.L */ + /* instruction 160: FCVT.D.L */ compile_ret_t __fcvt_d_l(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_L_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 157); + vm_base::gen_sync(tu, PRE_SYNC, 160); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7676,15 +7765,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 157); + vm_base::gen_sync(tu, POST_SYNC, 160); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 158: FCVT.D.LU */ + /* instruction 161: FCVT.D.LU */ compile_ret_t __fcvt_d_lu(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FCVT_D_LU_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 158); + vm_base::gen_sync(tu, PRE_SYNC, 161); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rm = ((bit_sub<12,3>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); @@ -7721,15 +7810,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 158); + vm_base::gen_sync(tu, POST_SYNC, 161); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 159: FMV.X.D */ + /* instruction 162: FMV.X.D */ compile_ret_t __fmv_x_d(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMV_X_D_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 159); + vm_base::gen_sync(tu, PRE_SYNC, 162); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -7748,15 +7837,15 @@ private: false), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 159); + vm_base::gen_sync(tu, POST_SYNC, 162); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 160: FMV.D.X */ + /* instruction 163: FMV.D.X */ compile_ret_t __fmv_d_x(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("FMV_D_X_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 160); + vm_base::gen_sync(tu, PRE_SYNC, 163); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); if(this->disass_enabled){ @@ -7775,15 +7864,15 @@ private: true), rd + traits::F0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 160); + vm_base::gen_sync(tu, POST_SYNC, 163); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 161: C.ADDI4SPN */ + /* instruction 164: C.ADDI4SPN */ compile_ret_t __c_addi4spn(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_ADDI4SPN_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 161); + vm_base::gen_sync(tu, PRE_SYNC, 164); uint8_t rd = ((bit_sub<2,3>(instr))); uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4)); if(this->disass_enabled){ @@ -7804,15 +7893,15 @@ private: tu.constant(imm, 64U)), rd + 8 + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 161); + vm_base::gen_sync(tu, POST_SYNC, 164); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 162: C.LW */ + /* instruction 165: C.LW */ compile_ret_t __c_lw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_LW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 162); + vm_base::gen_sync(tu, PRE_SYNC, 165); uint8_t rd = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -7835,15 +7924,15 @@ private: false), rd + 8 + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 162); + vm_base::gen_sync(tu, POST_SYNC, 165); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 163: C.SW */ + /* instruction 166: C.SW */ compile_ret_t __c_sw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_SW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 163); + vm_base::gen_sync(tu, PRE_SYNC, 166); uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -7866,15 +7955,15 @@ private: tu.trunc(tu.load(rs2 + 8 + traits::X0, 0), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 163); + vm_base::gen_sync(tu, POST_SYNC, 166); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 164: C.ADDI */ + /* instruction 167: C.ADDI */ compile_ret_t __c_addi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_ADDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 164); + vm_base::gen_sync(tu, PRE_SYNC, 167); int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -7894,15 +7983,15 @@ private: tu.constant(imm, 64U)), rs1 + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 164); + vm_base::gen_sync(tu, POST_SYNC, 167); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 165: C.NOP */ + /* instruction 168: C.NOP */ compile_ret_t __c_nop(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_NOP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 165); + vm_base::gen_sync(tu, PRE_SYNC, 168); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c.nop"); @@ -7913,49 +8002,52 @@ private: tu.close_scope(); /* TODO: describe operations for C.NOP ! */ gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 165); + vm_base::gen_sync(tu, POST_SYNC, 168); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 166: C.JAL */ - compile_ret_t __c_jal(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_JAL_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 166); - int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + /* instruction 169: C.ADDIW */ + compile_ret_t __c_addiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_ADDIW_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 169); + int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( - "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "c.jal"), - fmt::arg("imm", imm)); + "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addiw"), + fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); } auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); pc=pc+2; tu.open_scope(); - tu.store(tu.add( - cur_pc_val, - tu.constant(2, 64U)), 1 + traits::X0); - auto PC_val_v = tu.assignment("PC_val", tu.add( - tu.ext( - cur_pc_val, - 64, false), - tu.constant(imm, 64U)), 64); - tu.store(PC_val_v, traits::NEXT_PC); - auto is_cont_v = tu.choose( - tu.icmp(ICmpInst::ICMP_NE, tu.ext(PC_val_v, 64U, true), tu.constant(pc.val, 64U)), - tu.constant(0U, 32), tu.constant(1U, 32)); - tu.store(is_cont_v, traits::LAST_BRANCH); + if(rs1 != 0){ + auto res_val = tu.assignment(tu.add( + tu.ext( + tu.trunc( + tu.load(rs1 + traits::X0, 0), + 32 + ), + 32, false), + tu.constant(imm, 32U)), 32); + tu.store(tu.ext( + res_val, + 64, + false), rs1 + traits::X0); + } tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 166); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 169); gen_trap_check(tu); - return std::make_tuple(BRANCH); + return std::make_tuple(CONT); } - /* instruction 167: C.LI */ + /* instruction 170: C.LI */ compile_ret_t __c_li(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_LI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 167); + vm_base::gen_sync(tu, PRE_SYNC, 170); int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -7974,15 +8066,15 @@ private: tu.store(tu.constant(imm, 64U), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 167); + vm_base::gen_sync(tu, POST_SYNC, 170); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 168: C.LUI */ + /* instruction 171: C.LUI */ compile_ret_t __c_lui(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_LUI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 168); + vm_base::gen_sync(tu, PRE_SYNC, 171); int32_t imm = signextend((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -8004,15 +8096,15 @@ private: tu.store(tu.constant(imm, 64U), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 168); + vm_base::gen_sync(tu, POST_SYNC, 171); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 169: C.ADDI16SP */ + /* instruction 172: C.ADDI16SP */ compile_ret_t __c_addi16sp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_ADDI16SP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 169); + vm_base::gen_sync(tu, PRE_SYNC, 172); int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -8031,15 +8123,15 @@ private: tu.constant(imm, 64U)), 2 + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 169); + vm_base::gen_sync(tu, POST_SYNC, 172); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 170: C.SRLI */ + /* instruction 173: C.SRLI */ compile_ret_t __c_srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_SRLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 170); + vm_base::gen_sync(tu, PRE_SYNC, 173); uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -8058,15 +8150,15 @@ private: tu.constant(shamt, 64U)), rs1_idx_val + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 170); + vm_base::gen_sync(tu, POST_SYNC, 173); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 171: C.SRAI */ + /* instruction 174: C.SRAI */ compile_ret_t __c_srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_SRAI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 171); + vm_base::gen_sync(tu, PRE_SYNC, 174); uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -8085,15 +8177,15 @@ private: tu.constant(shamt, 64U)), rs1_idx_val + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 171); + vm_base::gen_sync(tu, POST_SYNC, 174); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 172: C.ANDI */ + /* instruction 175: C.ANDI */ compile_ret_t __c_andi(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_ANDI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 172); + vm_base::gen_sync(tu, PRE_SYNC, 175); int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -8114,15 +8206,15 @@ private: tu.constant(imm, 64U)), rs1_idx_val + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 172); + vm_base::gen_sync(tu, POST_SYNC, 175); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 173: C.SUB */ + /* instruction 176: C.SUB */ compile_ret_t __c_sub(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_SUB_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 173); + vm_base::gen_sync(tu, PRE_SYNC, 176); uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -8141,15 +8233,15 @@ private: tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 173); + vm_base::gen_sync(tu, POST_SYNC, 176); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 174: C.XOR */ + /* instruction 177: C.XOR */ compile_ret_t __c_xor(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_XOR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 174); + vm_base::gen_sync(tu, PRE_SYNC, 177); uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -8168,15 +8260,15 @@ private: tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 174); + vm_base::gen_sync(tu, POST_SYNC, 177); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 175: C.OR */ + /* instruction 178: C.OR */ compile_ret_t __c_or(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_OR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 175); + vm_base::gen_sync(tu, PRE_SYNC, 178); uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -8195,15 +8287,15 @@ private: tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 175); + vm_base::gen_sync(tu, POST_SYNC, 178); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 176: C.AND */ + /* instruction 179: C.AND */ compile_ret_t __c_and(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_AND_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 176); + vm_base::gen_sync(tu, PRE_SYNC, 179); uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t rd = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -8222,15 +8314,15 @@ private: tu.load(rs2 + 8 + traits::X0, 0)), rd_idx_val + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 176); + vm_base::gen_sync(tu, POST_SYNC, 179); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 177: C.J */ + /* instruction 180: C.J */ compile_ret_t __c_j(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_J_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 177); + vm_base::gen_sync(tu, PRE_SYNC, 180); int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -8253,15 +8345,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 177); + vm_base::gen_sync(tu, POST_SYNC, 180); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 178: C.BEQZ */ + /* instruction 181: C.BEQZ */ compile_ret_t __c_beqz(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_BEQZ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 178); + vm_base::gen_sync(tu, PRE_SYNC, 181); int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -8293,15 +8385,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 178); + vm_base::gen_sync(tu, POST_SYNC, 181); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 179: C.BNEZ */ + /* instruction 182: C.BNEZ */ compile_ret_t __c_bnez(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_BNEZ_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 179); + vm_base::gen_sync(tu, PRE_SYNC, 182); int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ @@ -8333,15 +8425,15 @@ private: tu.constant(0U, 32), tu.constant(1U, 32)); tu.store(is_cont_v, traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 179); + vm_base::gen_sync(tu, POST_SYNC, 182); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 180: C.SLLI */ + /* instruction 183: C.SLLI */ compile_ret_t __c_slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_SLLI_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 180); + vm_base::gen_sync(tu, PRE_SYNC, 183); uint8_t shamt = ((bit_sub<2,5>(instr))); uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -8362,15 +8454,15 @@ private: tu.constant(shamt, 64U)), rs1 + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 180); + vm_base::gen_sync(tu, POST_SYNC, 183); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 181: C.LWSP */ + /* instruction 184: C.LWSP */ compile_ret_t __c_lwsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_LWSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 181); + vm_base::gen_sync(tu, PRE_SYNC, 184); uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -8392,15 +8484,15 @@ private: false), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 181); + vm_base::gen_sync(tu, POST_SYNC, 184); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 182: C.MV */ + /* instruction 185: C.MV */ compile_ret_t __c_mv(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_MV_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 182); + vm_base::gen_sync(tu, PRE_SYNC, 185); uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -8416,15 +8508,15 @@ private: tu.store(tu.load(rs2 + traits::X0, 0), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 182); + vm_base::gen_sync(tu, POST_SYNC, 185); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 183: C.JR */ + /* instruction 186: C.JR */ compile_ret_t __c_jr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_JR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 183); + vm_base::gen_sync(tu, PRE_SYNC, 186); uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -8440,15 +8532,15 @@ private: tu.store(PC_val_v, traits::NEXT_PC); tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 183); + vm_base::gen_sync(tu, POST_SYNC, 186); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 184: C.ADD */ + /* instruction 187: C.ADD */ compile_ret_t __c_add(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_ADD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 184); + vm_base::gen_sync(tu, PRE_SYNC, 187); uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -8466,15 +8558,15 @@ private: tu.load(rs2 + traits::X0, 0)), rd + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 184); + vm_base::gen_sync(tu, POST_SYNC, 187); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 185: C.JALR */ + /* instruction 188: C.JALR */ compile_ret_t __c_jalr(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_JALR_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 185); + vm_base::gen_sync(tu, PRE_SYNC, 188); uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -8493,15 +8585,15 @@ private: tu.store(PC_val_v, traits::NEXT_PC); tu.store(tu.constant(std::numeric_limits::max(), 32U), traits::LAST_BRANCH); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 185); + vm_base::gen_sync(tu, POST_SYNC, 188); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 186: C.EBREAK */ + /* instruction 189: C.EBREAK */ compile_ret_t __c_ebreak(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_EBREAK_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 186); + vm_base::gen_sync(tu, PRE_SYNC, 189); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "c.ebreak"); @@ -8511,15 +8603,15 @@ private: tu.open_scope(); this->gen_raise_trap(tu, 0, 3); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 186); + vm_base::gen_sync(tu, POST_SYNC, 189); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 187: C.SWSP */ + /* instruction 190: C.SWSP */ compile_ret_t __c_swsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_SWSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 187); + vm_base::gen_sync(tu, PRE_SYNC, 190); uint8_t rs2 = ((bit_sub<2,5>(instr))); uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); if(this->disass_enabled){ @@ -8541,15 +8633,15 @@ private: tu.trunc(tu.load(rs2 + traits::X0, 0), 32)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 187); + vm_base::gen_sync(tu, POST_SYNC, 190); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 188: DII */ + /* instruction 191: DII */ compile_ret_t __dii(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("DII_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 188); + vm_base::gen_sync(tu, PRE_SYNC, 191); if(this->disass_enabled){ /* generate console output when executing the command */ tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, "dii"); @@ -8559,15 +8651,15 @@ private: tu.open_scope(); this->gen_raise_trap(tu, 0, 2); tu.close_scope(); - vm_base::gen_sync(tu, POST_SYNC, 188); + vm_base::gen_sync(tu, POST_SYNC, 191); gen_trap_check(tu); return std::make_tuple(BRANCH); } - /* instruction 189: C.LD */ + /* instruction 192: C.LD */ compile_ret_t __c_ld(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_LD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 189); + vm_base::gen_sync(tu, PRE_SYNC, 192); uint8_t rd = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -8590,15 +8682,15 @@ private: false), rd + 8 + traits::X0); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 189); + vm_base::gen_sync(tu, POST_SYNC, 192); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 190: C.SD */ + /* instruction 193: C.SD */ compile_ret_t __c_sd(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_SD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 190); + vm_base::gen_sync(tu, PRE_SYNC, 193); uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -8621,115 +8713,6 @@ private: tu.trunc(tu.load(rs2 + 8 + traits::X0, 0), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 190); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 191: C.SUBW */ - compile_ret_t __c_subw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_SUBW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 191); - uint8_t rs2 = ((bit_sub<2,3>(instr))); - uint8_t rd = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rd}, {rs2}", fmt::arg("mnemonic", "c.subw"), - fmt::arg("rd", name(8+rd)), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto res_val = tu.assignment(tu.sub( - tu.trunc( - tu.load(rd + 8 + traits::X0, 0), - 32 - ), - tu.trunc( - tu.load(rs2 + 8 + traits::X0, 0), - 32 - )), 32); - tu.store(tu.ext( - res_val, - 64, - false), rd + 8 + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 191); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 192: C.ADDW */ - compile_ret_t __c_addw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_ADDW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 192); - uint8_t rs2 = ((bit_sub<2,3>(instr))); - uint8_t rd = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rd}, {rd}, {rs2}", fmt::arg("mnemonic", "c.addw"), - fmt::arg("rd", name(8+rd)), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto res_val = tu.assignment(tu.add( - tu.trunc( - tu.load(rd + 8 + traits::X0, 0), - 32 - ), - tu.trunc( - tu.load(rs2 + 8 + traits::X0, 0), - 32 - )), 32); - tu.store(tu.ext( - res_val, - 64, - false), rd + 8 + traits::X0); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 192); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 193: C.ADDIW */ - compile_ret_t __c_addiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_ADDIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 193); - int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); - uint8_t rs1 = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "c.addiw"), - fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - if(rs1 != 0){ - auto res_val = tu.assignment(tu.add( - tu.ext( - tu.trunc( - tu.load(rs1 + traits::X0, 0), - 32 - ), - 32, false), - tu.constant(imm, 32U)), 32); - tu.store(tu.ext( - res_val, - 64, - false), rs1 + traits::X0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); vm_base::gen_sync(tu, POST_SYNC, 193); gen_trap_check(tu); return std::make_tuple(CONT); @@ -8797,158 +8780,10 @@ private: return std::make_tuple(CONT); } - /* instruction 196: C.FLW */ - compile_ret_t __c_flw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_FLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 196); - uint8_t rd = ((bit_sub<2,3>(instr))); - uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} f(8+{rd}), {uimm}({rs1})", fmt::arg("mnemonic", "c.flw"), - fmt::arg("rd", rd), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.load(rs1 + 8 + traits::X0, 0), - tu.constant(uimm, 64U)), 64); - auto res_val = tu.assignment(tu.read_mem(traits::MEM, offs_val, 32), 32); - if(64 == 32){ - tu.store(res_val, rd + 8 + traits::F0); - } else { - uint64_t upper_val = - 1; - tu.store(tu.l_or( - tu.shl( - tu.constant(upper_val, 64U), - tu.constant(32, 64U)), - tu.ext( - res_val, - 64, - true)), rd + 8 + traits::F0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 196); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 197: C.FSW */ - compile_ret_t __c_fsw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_FSW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 197); - uint8_t rs2 = ((bit_sub<2,3>(instr))); - uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3)); - uint8_t rs1 = ((bit_sub<7,3>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} f(8+{rs2}), {uimm}({rs1})", fmt::arg("mnemonic", "c.fsw"), - fmt::arg("rs2", rs2), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1))); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.load(rs1 + 8 + traits::X0, 0), - tu.constant(uimm, 64U)), 64); - tu.write_mem( - traits::MEM, - offs_val, - tu.trunc(tu.trunc( - tu.load(rs2 + 8 + traits::F0, 0), - 32 - ), 32)); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 197); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 198: C.FLWSP */ - compile_ret_t __c_flwsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_FLWSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 198); - uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5)); - uint8_t rd = ((bit_sub<7,5>(instr))); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} f{rd}, {uimm}(x2)", fmt::arg("mnemonic", "c.flwsp"), - fmt::arg("rd", rd), fmt::arg("uimm", uimm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.load(2 + traits::X0, 0), - tu.constant(uimm, 64U)), 64); - auto res_val = tu.assignment(tu.read_mem(traits::MEM, offs_val, 32), 32); - if(64 == 32){ - tu.store(res_val, rd + traits::F0); - } else { - uint64_t upper_val = - 1; - tu.store(tu.l_or( - tu.shl( - tu.constant(upper_val, 64U), - tu.constant(32, 64U)), - tu.ext( - res_val, - 64, - true)), rd + traits::F0); - } - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 198); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 199: C.FSWSP */ - compile_ret_t __c_fswsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ - tu("C_FSWSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 199); - uint8_t rs2 = ((bit_sub<2,5>(instr))); - uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2)); - if(this->disass_enabled){ - /* generate console output when executing the command */ - auto mnemonic = fmt::format( - "{mnemonic:10} f{rs2}, {uimm}(x2), ", fmt::arg("mnemonic", "c.fswsp"), - fmt::arg("rs2", rs2), fmt::arg("uimm", uimm)); - tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); - } - auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); - pc=pc+2; - tu.open_scope(); - auto offs_val = tu.assignment(tu.add( - tu.load(2 + traits::X0, 0), - tu.constant(uimm, 64U)), 64); - tu.write_mem( - traits::MEM, - offs_val, - tu.trunc(tu.trunc( - tu.load(rs2 + traits::F0, 0), - 32 - ), 32)); - tu.close_scope(); - gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 199); - gen_trap_check(tu); - return std::make_tuple(CONT); - } - - /* instruction 200: C.FLD */ + /* instruction 196: C.FLD */ compile_ret_t __c_fld(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_FLD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 200); + vm_base::gen_sync(tu, PRE_SYNC, 196); uint8_t rd = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -8978,15 +8813,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 200); + vm_base::gen_sync(tu, POST_SYNC, 196); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 201: C.FSD */ + /* instruction 197: C.FSD */ compile_ret_t __c_fsd(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_FSD_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 201); + vm_base::gen_sync(tu, PRE_SYNC, 197); uint8_t rs2 = ((bit_sub<2,3>(instr))); uint8_t uimm = ((bit_sub<5,2>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); uint8_t rs1 = ((bit_sub<7,3>(instr))); @@ -9012,15 +8847,15 @@ private: ), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 201); + vm_base::gen_sync(tu, POST_SYNC, 197); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 202: C.FLDSP */ + /* instruction 198: C.FLDSP */ compile_ret_t __c_fldsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_FLDSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 202); + vm_base::gen_sync(tu, PRE_SYNC, 198); uint16_t uimm = ((bit_sub<2,3>(instr) << 6) | (bit_sub<5,2>(instr) << 3) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ @@ -9052,15 +8887,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 202); + vm_base::gen_sync(tu, POST_SYNC, 198); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 203: C.FSDSP */ + /* instruction 199: C.FSDSP */ compile_ret_t __c_fsdsp(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("C_FSDSP_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 203); + vm_base::gen_sync(tu, PRE_SYNC, 199); uint8_t rs2 = ((bit_sub<2,5>(instr))); uint16_t uimm = ((bit_sub<7,3>(instr) << 6) | (bit_sub<10,3>(instr) << 3)); if(this->disass_enabled){ @@ -9085,11 +8920,166 @@ private: ), 64)); tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 199); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 200: C.SUBW */ + compile_ret_t __c_subw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_SUBW_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 200); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rd}, {rs2}", fmt::arg("mnemonic", "c.subw"), + fmt::arg("rd", name(8+rd)), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + auto res_val = tu.assignment(tu.sub( + tu.trunc( + tu.load(rd + 8 + traits::X0, 0), + 32 + ), + tu.trunc( + tu.load(rs2 + 8 + traits::X0, 0), + 32 + )), 32); + tu.store(tu.ext( + res_val, + 64, + false), rd + 8 + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 200); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 201: C.ADDW */ + compile_ret_t __c_addw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_ADDW_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 201); + uint8_t rs2 = ((bit_sub<2,3>(instr))); + uint8_t rd = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rd}, {rs2}", fmt::arg("mnemonic", "c.addw"), + fmt::arg("rd", name(8+rd)), fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2))); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + auto res_val = tu.assignment(tu.add( + tu.trunc( + tu.load(rd + 8 + traits::X0, 0), + 32 + ), + tu.trunc( + tu.load(rs2 + 8 + traits::X0, 0), + 32 + )), 32); + tu.store(tu.ext( + res_val, + 64, + false), rd + 8 + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 201); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 202: C.SRLI */ + compile_ret_t __c_srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_SRLI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 202); + uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srli"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + uint8_t rs1_idx_val = rs1 + 8; + tu.store(tu.lshr( + tu.load(rs1_idx_val + traits::X0, 0), + tu.constant(shamt, 64U)), rs1_idx_val + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 202); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 203: C.SRAI */ + compile_ret_t __c_srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_SRAI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 203); + uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,3>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.srai"), + fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + uint8_t rs1_idx_val = rs1 + 8; + tu.store(tu.ashr( + tu.load(rs1_idx_val + traits::X0, 0), + tu.constant(shamt, 64U)), rs1_idx_val + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); vm_base::gen_sync(tu, POST_SYNC, 203); gen_trap_check(tu); return std::make_tuple(CONT); } + /* instruction 204: C.SLLI */ + compile_ret_t __c_slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("C_SLLI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 204); + uint8_t shamt = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t rs1 = ((bit_sub<7,5>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "c.slli"), + fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+2; + tu.open_scope(); + if(rs1 == 0){ + this->gen_raise_trap(tu, 0, 2); + } + tu.store(tu.shl( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rs1 + traits::X0); + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 204); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + /**************************************************************************** * end opcode definitions ****************************************************************************/ diff --git a/src/vm/tcc/vm_rv64i.cpp b/src/vm/tcc/vm_rv64i.cpp index 9c92f33..e57c22a 100644 --- a/src/vm/tcc/vm_rv64i.cpp +++ b/src/vm/tcc/vm_rv64i.cpp @@ -182,135 +182,141 @@ private: compile_func op; }; - const std::array instr_descr = {{ + const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ - /* instruction LUI */ + /* instruction LUI, encoding '.........................0110111' */ {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, - /* instruction AUIPC */ + /* instruction AUIPC, encoding '.........................0010111' */ {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, - /* instruction JAL */ + /* instruction JAL, encoding '.........................1101111' */ {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, - /* instruction JALR */ + /* instruction JALR, encoding '.................000.....1100111' */ {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, - /* instruction BEQ */ + /* instruction BEQ, encoding '.................000.....1100011' */ {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, - /* instruction BNE */ + /* instruction BNE, encoding '.................001.....1100011' */ {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne}, - /* instruction BLT */ + /* instruction BLT, encoding '.................100.....1100011' */ {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt}, - /* instruction BGE */ + /* instruction BGE, encoding '.................101.....1100011' */ {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge}, - /* instruction BLTU */ + /* instruction BLTU, encoding '.................110.....1100011' */ {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu}, - /* instruction BGEU */ + /* instruction BGEU, encoding '.................111.....1100011' */ {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu}, - /* instruction LB */ + /* instruction LB, encoding '.................000.....0000011' */ {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb}, - /* instruction LH */ + /* instruction LH, encoding '.................001.....0000011' */ {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh}, - /* instruction LW */ + /* instruction LW, encoding '.................010.....0000011' */ {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw}, - /* instruction LBU */ + /* instruction LBU, encoding '.................100.....0000011' */ {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu}, - /* instruction LHU */ + /* instruction LHU, encoding '.................101.....0000011' */ {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu}, - /* instruction SB */ + /* instruction SB, encoding '.................000.....0100011' */ {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb}, - /* instruction SH */ + /* instruction SH, encoding '.................001.....0100011' */ {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh}, - /* instruction SW */ + /* instruction SW, encoding '.................010.....0100011' */ {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw}, - /* instruction ADDI */ + /* instruction ADDI, encoding '.................000.....0010011' */ {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi}, - /* instruction SLTI */ + /* instruction SLTI, encoding '.................010.....0010011' */ {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti}, - /* instruction SLTIU */ + /* instruction SLTIU, encoding '.................011.....0010011' */ {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu}, - /* instruction XORI */ + /* instruction XORI, encoding '.................100.....0010011' */ {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori}, - /* instruction ORI */ + /* instruction ORI, encoding '.................110.....0010011' */ {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori}, - /* instruction ANDI */ + /* instruction ANDI, encoding '.................111.....0010011' */ {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi}, - /* instruction SLLI */ - {32, 0b00000000000000000001000000010011, 0b11111100000000000111000001111111, &this_class::__slli}, - /* instruction SRLI */ - {32, 0b00000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srli}, - /* instruction SRAI */ - {32, 0b01000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srai}, - /* instruction ADD */ + /* instruction SLLI, encoding '0000000..........001.....0010011' */ + {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli}, + /* instruction SRLI, encoding '0000000..........101.....0010011' */ + {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli}, + /* instruction SRAI, encoding '0100000..........101.....0010011' */ + {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai}, + /* instruction ADD, encoding '0000000..........000.....0110011' */ {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add}, - /* instruction SUB */ + /* instruction SUB, encoding '0100000..........000.....0110011' */ {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub}, - /* instruction SLL */ + /* instruction SLL, encoding '0000000..........001.....0110011' */ {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll}, - /* instruction SLT */ + /* instruction SLT, encoding '0000000..........010.....0110011' */ {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt}, - /* instruction SLTU */ + /* instruction SLTU, encoding '0000000..........011.....0110011' */ {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu}, - /* instruction XOR */ + /* instruction XOR, encoding '0000000..........100.....0110011' */ {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor}, - /* instruction SRL */ + /* instruction SRL, encoding '0000000..........101.....0110011' */ {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl}, - /* instruction SRA */ + /* instruction SRA, encoding '0100000..........101.....0110011' */ {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra}, - /* instruction OR */ + /* instruction OR, encoding '0000000..........110.....0110011' */ {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or}, - /* instruction AND */ + /* instruction AND, encoding '0000000..........111.....0110011' */ {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and}, - /* instruction FENCE */ + /* instruction FENCE, encoding '0000.............000.....0001111' */ {32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence}, - /* instruction FENCE_I */ + /* instruction FENCE_I, encoding '.................001.....0001111' */ {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i}, - /* instruction ECALL */ + /* instruction ECALL, encoding '00000000000000000000000001110011' */ {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall}, - /* instruction EBREAK */ + /* instruction EBREAK, encoding '00000000000100000000000001110011' */ {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak}, - /* instruction URET */ + /* instruction URET, encoding '00000000001000000000000001110011' */ {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret}, - /* instruction SRET */ + /* instruction SRET, encoding '00010000001000000000000001110011' */ {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret}, - /* instruction MRET */ + /* instruction MRET, encoding '00110000001000000000000001110011' */ {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret}, - /* instruction WFI */ + /* instruction WFI, encoding '00010000010100000000000001110011' */ {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi}, - /* instruction SFENCE.VMA */ + /* instruction SFENCE.VMA, encoding '0001001..........000000001110011' */ {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma}, - /* instruction CSRRW */ + /* instruction CSRRW, encoding '.................001.....1110011' */ {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw}, - /* instruction CSRRS */ + /* instruction CSRRS, encoding '.................010.....1110011' */ {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs}, - /* instruction CSRRC */ + /* instruction CSRRC, encoding '.................011.....1110011' */ {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc}, - /* instruction CSRRWI */ + /* instruction CSRRWI, encoding '.................101.....1110011' */ {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi}, - /* instruction CSRRSI */ + /* instruction CSRRSI, encoding '.................110.....1110011' */ {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi}, - /* instruction CSRRCI */ + /* instruction CSRRCI, encoding '.................111.....1110011' */ {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci}, - /* instruction LWU */ + /* instruction LWU, encoding '.................110.....0000011' */ {32, 0b00000000000000000110000000000011, 0b00000000000000000111000001111111, &this_class::__lwu}, - /* instruction LD */ + /* instruction LD, encoding '.................011.....0000011' */ {32, 0b00000000000000000011000000000011, 0b00000000000000000111000001111111, &this_class::__ld}, - /* instruction SD */ + /* instruction SD, encoding '.................011.....0100011' */ {32, 0b00000000000000000011000000100011, 0b00000000000000000111000001111111, &this_class::__sd}, - /* instruction ADDIW */ + /* instruction SLLI, encoding '000000...........001.....0010011' */ + {32, 0b00000000000000000001000000010011, 0b11111100000000000111000001111111, &this_class::__slli}, + /* instruction SRLI, encoding '000000...........101.....0010011' */ + {32, 0b00000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srli}, + /* instruction SRAI, encoding '010000...........101.....0010011' */ + {32, 0b01000000000000000101000000010011, 0b11111100000000000111000001111111, &this_class::__srai}, + /* instruction ADDIW, encoding '.................000.....0011011' */ {32, 0b00000000000000000000000000011011, 0b00000000000000000111000001111111, &this_class::__addiw}, - /* instruction SLLIW */ + /* instruction SLLIW, encoding '0000000..........001.....0011011' */ {32, 0b00000000000000000001000000011011, 0b11111110000000000111000001111111, &this_class::__slliw}, - /* instruction SRLIW */ + /* instruction SRLIW, encoding '0000000..........101.....0011011' */ {32, 0b00000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__srliw}, - /* instruction SRAIW */ + /* instruction SRAIW, encoding '0100000..........101.....0011011' */ {32, 0b01000000000000000101000000011011, 0b11111110000000000111000001111111, &this_class::__sraiw}, - /* instruction ADDW */ + /* instruction ADDW, encoding '0000000..........000.....0111011' */ {32, 0b00000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__addw}, - /* instruction SUBW */ + /* instruction SUBW, encoding '0100000..........000.....0111011' */ {32, 0b01000000000000000000000000111011, 0b11111110000000000111000001111111, &this_class::__subw}, - /* instruction SLLW */ + /* instruction SLLW, encoding '0000000..........001.....0111011' */ {32, 0b00000000000000000001000000111011, 0b11111110000000000111000001111111, &this_class::__sllw}, - /* instruction SRLW */ + /* instruction SRLW, encoding '0000000..........101.....0111011' */ {32, 0b00000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__srlw}, - /* instruction SRAW */ + /* instruction SRAW, encoding '0100000..........101.....0111011' */ {32, 0b01000000000000000101000000111011, 0b11111110000000000111000001111111, &this_class::__sraw}, }}; @@ -1183,7 +1189,7 @@ private: vm_base::gen_sync(tu, PRE_SYNC, 24); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,6>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1194,10 +1200,14 @@ private: auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); pc=pc+4; tu.open_scope(); - if(rd != 0){ - tu.store(tu.shl( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); + if(shamt > 31){ + this->gen_raise_trap(tu, 0, 0); + } else { + if(rd != 0){ + tu.store(tu.shl( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); + } } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); @@ -1212,7 +1222,7 @@ private: vm_base::gen_sync(tu, PRE_SYNC, 25); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,6>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1223,10 +1233,14 @@ private: auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); pc=pc+4; tu.open_scope(); - if(rd != 0){ - tu.store(tu.lshr( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); + if(shamt > 31){ + this->gen_raise_trap(tu, 0, 0); + } else { + if(rd != 0){ + tu.store(tu.lshr( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); + } } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); @@ -1241,7 +1255,7 @@ private: vm_base::gen_sync(tu, PRE_SYNC, 26); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - uint8_t shamt = ((bit_sub<20,6>(instr))); + uint8_t shamt = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1252,10 +1266,14 @@ private: auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); pc=pc+4; tu.open_scope(); - if(rd != 0){ - tu.store(tu.ashr( - tu.load(rs1 + traits::X0, 0), - tu.constant(shamt, 64U)), rd + traits::X0); + if(shamt > 31){ + this->gen_raise_trap(tu, 0, 0); + } else { + if(rd != 0){ + tu.store(tu.ashr( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); + } } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); @@ -2104,10 +2122,97 @@ private: return std::make_tuple(CONT); } - /* instruction 55: ADDIW */ + /* instruction 55: SLLI */ + compile_ret_t __slli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SLLI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 55); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.shl( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 55); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 56: SRLI */ + compile_ret_t __srli(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SRLI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 56); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.lshr( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 56); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 57: SRAI */ + compile_ret_t __srai(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ + tu("SRAI_{:#010x}:", pc.val); + vm_base::gen_sync(tu, PRE_SYNC, 57); + uint8_t rd = ((bit_sub<7,5>(instr))); + uint8_t rs1 = ((bit_sub<15,5>(instr))); + uint8_t shamt = ((bit_sub<20,6>(instr))); + if(this->disass_enabled){ + /* generate console output when executing the command */ + auto mnemonic = fmt::format( + "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"), + fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt)); + tu("print_disass(core_ptr, {:#x}, \"{}\");", pc.val, mnemonic); + } + auto cur_pc_val = tu.constant(pc.val, arch::traits::reg_bit_widths[traits::PC]); + pc=pc+4; + tu.open_scope(); + if(rd != 0){ + tu.store(tu.ashr( + tu.load(rs1 + traits::X0, 0), + tu.constant(shamt, 64U)), rd + traits::X0); + } + tu.close_scope(); + gen_set_pc(tu, pc, traits::NEXT_PC); + vm_base::gen_sync(tu, POST_SYNC, 57); + gen_trap_check(tu); + return std::make_tuple(CONT); + } + + /* instruction 58: ADDIW */ compile_ret_t __addiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 55); + vm_base::gen_sync(tu, PRE_SYNC, 58); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); int16_t imm = signextend((bit_sub<20,12>(instr))); @@ -2137,15 +2242,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 55); + vm_base::gen_sync(tu, POST_SYNC, 58); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 56: SLLIW */ + /* instruction 59: SLLIW */ compile_ret_t __slliw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 56); + vm_base::gen_sync(tu, PRE_SYNC, 59); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2173,15 +2278,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 56); + vm_base::gen_sync(tu, POST_SYNC, 59); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 57: SRLIW */ + /* instruction 60: SRLIW */ compile_ret_t __srliw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 57); + vm_base::gen_sync(tu, PRE_SYNC, 60); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2209,15 +2314,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 57); + vm_base::gen_sync(tu, POST_SYNC, 60); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 58: SRAIW */ + /* instruction 61: SRAIW */ compile_ret_t __sraiw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAIW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 58); + vm_base::gen_sync(tu, PRE_SYNC, 61); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t shamt = ((bit_sub<20,5>(instr))); @@ -2245,15 +2350,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 58); + vm_base::gen_sync(tu, POST_SYNC, 61); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 59: ADDW */ + /* instruction 62: ADDW */ compile_ret_t __addw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("ADDW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 59); + vm_base::gen_sync(tu, PRE_SYNC, 62); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2281,15 +2386,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 59); + vm_base::gen_sync(tu, POST_SYNC, 62); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 60: SUBW */ + /* instruction 63: SUBW */ compile_ret_t __subw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SUBW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 60); + vm_base::gen_sync(tu, PRE_SYNC, 63); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2317,15 +2422,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 60); + vm_base::gen_sync(tu, POST_SYNC, 63); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 61: SLLW */ + /* instruction 64: SLLW */ compile_ret_t __sllw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SLLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 61); + vm_base::gen_sync(tu, PRE_SYNC, 64); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2360,15 +2465,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 61); + vm_base::gen_sync(tu, POST_SYNC, 64); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 62: SRLW */ + /* instruction 65: SRLW */ compile_ret_t __srlw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRLW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 62); + vm_base::gen_sync(tu, PRE_SYNC, 65); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2403,15 +2508,15 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 62); + vm_base::gen_sync(tu, POST_SYNC, 65); gen_trap_check(tu); return std::make_tuple(CONT); } - /* instruction 63: SRAW */ + /* instruction 66: SRAW */ compile_ret_t __sraw(virt_addr_t& pc, code_word_t instr, tu_builder& tu){ tu("SRAW_{:#010x}:", pc.val); - vm_base::gen_sync(tu, PRE_SYNC, 63); + vm_base::gen_sync(tu, PRE_SYNC, 66); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); @@ -2446,7 +2551,7 @@ private: } tu.close_scope(); gen_set_pc(tu, pc, traits::NEXT_PC); - vm_base::gen_sync(tu, POST_SYNC, 63); + vm_base::gen_sync(tu, POST_SYNC, 66); gen_trap_check(tu); return std::make_tuple(CONT); }