diff --git a/gen_input/CoreDSL-Instruction-Set-Description b/gen_input/CoreDSL-Instruction-Set-Description index 89763fc..37b66a3 160000 --- a/gen_input/CoreDSL-Instruction-Set-Description +++ b/gen_input/CoreDSL-Instruction-Set-Description @@ -1 +1 @@ -Subproject commit 89763fcb973838a634e48ee05dca28782807b344 +Subproject commit 37b66a36d40c499bfb3348b9a5e077b70445260e diff --git a/gen_input/TGFS.core_desc b/gen_input/TGFS.core_desc index 7e04c19..56b3674 100644 --- a/gen_input/TGFS.core_desc +++ b/gen_input/TGFS.core_desc @@ -7,8 +7,8 @@ Core TGF_B provides RV32I { unsigned XLEN=32; unsigned PCLEN=32; // definitions for the architecture wrapper - // XL ZYXWVUTSRQPONMLKJIHGFEDCBA - unsigned MISA_VAL=0b01000000000000000000000100000000; + // XL ZYXWVUTSRQPONMLKJIHGFEDCBA + unsigned MISA_VAL = 0b01000000000000000000000100000000; unsigned PGSIZE = 0x1000; //1 << 12; unsigned PGMASK = 0xfff; //PGSIZE-1 } @@ -19,8 +19,8 @@ Core TGF_C provides RV32I, RV32M, RV32IC { unsigned XLEN=32; unsigned PCLEN=32; // definitions for the architecture wrapper - // XL ZYXWVUTSRQPONMLKJIHGFEDCBA - unsigned MISA_VAL=0b01000000000000000001000100000100; + // XL ZYXWVUTSRQPONMLKJIHGFEDCBA + unsigned MISA_VAL = 0b01000000000000000001000100000100; unsigned PGSIZE = 0x1000; //1 << 12; unsigned PGMASK = 0xfff; //PGSIZE-1 } diff --git a/gen_input/templates/interp/CORENAME.h.gtl b/gen_input/templates/interp/CORENAME.h.gtl index 610fd14..6c982d3 100644 --- a/gen_input/templates/interp/CORENAME.h.gtl +++ b/gen_input/templates/interp/CORENAME.h.gtl @@ -30,6 +30,8 @@ * *******************************************************************************/ <% +import com.minres.coredsl.util.BigIntegerWithRadix + def nativeTypeSize(int size){ if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64; } @@ -54,6 +56,12 @@ def byteSize(int size){ if(size<=64) return 64; return 128; } +def getCString(def val){ + if(val instanceof BigIntegerWithRadix) + return ((BigIntegerWithRadix)val).toCString() + else + return val.toString() +} %> #ifndef _${coreDef.name.toUpperCase()}_H_ #define _${coreDef.name.toUpperCase()}_H_ @@ -78,7 +86,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> { static constexpr std::array reg_aliases{ {"${registers.collect{it.alias}.join('", "')}"}}; - enum constants {${constants.collect{c -> c.name+"="+c.value}.join(', ')}}; + enum constants {${constants.collect{c -> c.name+"="+getCString(c.value)}.join(', ')}}; constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0}; diff --git a/incl/iss/arch/tgf_b.h b/incl/iss/arch/tgf_b.h index 84a43bf..f297cd7 100644 --- a/incl/iss/arch/tgf_b.h +++ b/incl/iss/arch/tgf_b.h @@ -53,7 +53,7 @@ template <> struct traits { static constexpr std::array reg_aliases{ {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}}; - enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3}; + enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000000000100000000, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3}; constexpr static unsigned FP_REGS_SIZE = 0; diff --git a/incl/iss/arch/tgf_c.h b/incl/iss/arch/tgf_c.h index 5aacf2f..4e20d11 100644 --- a/incl/iss/arch/tgf_c.h +++ b/incl/iss/arch/tgf_c.h @@ -53,7 +53,7 @@ template <> struct traits { static constexpr std::array reg_aliases{ {"X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", "X16", "X17", "X18", "X19", "X20", "X21", "X22", "X23", "X24", "X25", "X26", "X27", "X28", "X29", "X30", "X31", "PC", "NEXT_PC", "PRIV"}}; - enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0xfff, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64}; + enum constants {XLEN=32, PCLEN=32, MISA_VAL=0b1000000000000000001000100000100, PGSIZE=0x1000, PGMASK=0b111111111111, CSR_SIZE=4096, fence=0, fencei=1, fencevmal=2, fencevmau=3, MUL_LEN=64}; constexpr static unsigned FP_REGS_SIZE = 0; diff --git a/src/vm/interp/vm_tgf_b.cpp b/src/vm/interp/vm_tgf_b.cpp index 0672a77..e3e2571 100644 --- a/src/vm/interp/vm_tgf_b.cpp +++ b/src/vm/interp/vm_tgf_b.cpp @@ -180,17 +180,17 @@ private: const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ /* instruction LUI */ - {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, + {32, 0b0000000000000000000000000110111, 0b0000000000000000000000000111111, &this_class::__lui}, /* instruction AUIPC */ - {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, + {32, 0b000000000000000000000000010111, 0b000000000000000000000000011111, &this_class::__auipc}, /* instruction JAL */ {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, /* instruction JALR */ - {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, + {32, 0b000000000000000000000001100111, 0b000000000000000001000001111111, &this_class::__jalr}, /* instruction BEQ */ - {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, + {32, 0b000000000000000000000001100011, 0b000000000000000001000001111111, &this_class::__beq}, /* instruction BNE */ - {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne}, + {32, 0b000000000000000001000001100011, 0b000000000000000001000001111111, &this_class::__bne}, /* instruction BLT */ {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt}, /* instruction BGE */ @@ -200,83 +200,83 @@ private: /* instruction BGEU */ {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu}, /* instruction LB */ - {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb}, + {32, 0b0000000000000000000000011, 0b0000000000000000010000011, &this_class::__lb}, /* instruction LH */ - {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh}, + {32, 0b0000000000000000010000011, 0b0000000000000000010000011, &this_class::__lh}, /* instruction LW */ - {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw}, + {32, 0b00000000000000000100000011, 0b00000000000000000110000011, &this_class::__lw}, /* instruction LBU */ - {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu}, + {32, 0b000000000000000001000000011, 0b000000000000000001110000011, &this_class::__lbu}, /* instruction LHU */ - {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu}, + {32, 0b000000000000000001010000011, 0b000000000000000001110000011, &this_class::__lhu}, /* instruction SB */ - {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb}, + {32, 0b00000000000000000000000100011, 0b00000000000000000100000111111, &this_class::__sb}, /* instruction SH */ - {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh}, + {32, 0b00000000000000000100000100011, 0b00000000000000000100000111111, &this_class::__sh}, /* instruction SW */ - {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw}, + {32, 0b000000000000000001000000100011, 0b000000000000000001100000111111, &this_class::__sw}, /* instruction ADDI */ - {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi}, + {32, 0b0000000000000000000000010011, 0b0000000000000000010000011111, &this_class::__addi}, /* instruction SLTI */ - {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti}, + {32, 0b00000000000000000100000010011, 0b00000000000000000110000011111, &this_class::__slti}, /* instruction SLTIU */ - {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu}, + {32, 0b00000000000000000110000010011, 0b00000000000000000110000011111, &this_class::__sltiu}, /* instruction XORI */ - {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori}, + {32, 0b000000000000000001000000010011, 0b000000000000000001110000011111, &this_class::__xori}, /* instruction ORI */ - {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori}, + {32, 0b000000000000000001100000010011, 0b000000000000000001110000011111, &this_class::__ori}, /* instruction ANDI */ - {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi}, + {32, 0b000000000000000001110000010011, 0b000000000000000001110000011111, &this_class::__andi}, /* instruction SLLI */ - {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli}, + {32, 0b0000000000010000010011, 0b1000000000010000011111, &this_class::__slli}, /* instruction SRLI */ - {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli}, + {32, 0b000000000001010000010011, 0b100000000001110000011111, &this_class::__srli}, /* instruction SRAI */ - {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai}, + {32, 0b10000000000000001010000010011, 0b11111100000000001110000011111, &this_class::__srai}, /* instruction ADD */ - {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add}, + {32, 0b00000000000000000110011, 0b10000000000100000111111, &this_class::__add}, /* instruction SUB */ - {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub}, + {32, 0b1000000000000000000000110011, 0b1111110000000000100000111111, &this_class::__sub}, /* instruction SLL */ - {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll}, + {32, 0b00000000000100000110011, 0b10000000000100000111111, &this_class::__sll}, /* instruction SLT */ - {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt}, + {32, 0b000000000001000000110011, 0b100000000001100000111111, &this_class::__slt}, /* instruction SLTU */ - {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu}, + {32, 0b000000000001100000110011, 0b100000000001100000111111, &this_class::__sltu}, /* instruction XOR */ - {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor}, + {32, 0b0000000000010000000110011, 0b1000000000011100000111111, &this_class::__xor}, /* instruction SRL */ - {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl}, + {32, 0b0000000000010100000110011, 0b1000000000011100000111111, &this_class::__srl}, /* instruction SRA */ - {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra}, + {32, 0b100000000000000010100000110011, 0b111111000000000011100000111111, &this_class::__sra}, /* instruction OR */ - {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or}, + {32, 0b0000000000011000000110011, 0b1000000000011100000111111, &this_class::__or}, /* instruction AND */ - {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and}, + {32, 0b0000000000011100000110011, 0b1000000000011100000111111, &this_class::__and}, /* instruction FENCE */ - {32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence}, + {32, 0b000000000000000000001111, 0b100000000000001000001111, &this_class::__fence}, /* instruction FENCE_I */ - {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i}, + {32, 0b000000000000000001000001111, 0b000000000000000001000001111, &this_class::__fence_i}, /* instruction ECALL */ - {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall}, + {32, 0b00001110011, 0b11111111111, &this_class::__ecall}, /* instruction EBREAK */ - {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak}, + {32, 0b10001110011, 0b11111111111, &this_class::__ebreak}, /* instruction URET */ - {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret}, + {32, 0b0100001110011, 0b1111111111111, &this_class::__uret}, /* instruction SRET */ - {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret}, + {32, 0b1000100001110011, 0b1111111111111111, &this_class::__sret}, /* instruction MRET */ - {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret}, + {32, 0b11000100001110011, 0b11111111111111111, &this_class::__mret}, /* instruction WFI */ - {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi}, + {32, 0b10001010001110011, 0b11111111111111111, &this_class::__wfi}, /* instruction SFENCE_VMA */ - {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma}, + {32, 0b10010000000000001110011, 0b11110000000000111111111, &this_class::__sfence_vma}, /* instruction CSRRW */ - {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw}, + {32, 0b000000000000000001000001110011, 0b000000000000000001000001111111, &this_class::__csrrw}, /* instruction CSRRS */ - {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs}, + {32, 0b0000000000000000010000001110011, 0b0000000000000000011000001111111, &this_class::__csrrs}, /* instruction CSRRC */ - {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc}, + {32, 0b0000000000000000011000001110011, 0b0000000000000000011000001111111, &this_class::__csrrc}, /* instruction CSRRWI */ {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi}, /* instruction CSRRSI */ @@ -291,7 +291,7 @@ private: // pre execution stuff this->do_sync(PRE_SYNC, 0); uint8_t rd = ((bit_sub<7,5>(instr))); - int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -306,7 +306,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = imm; + if(rd != 0) *(X+rd) = (int32_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 0); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -323,7 +323,7 @@ private: // pre execution stuff this->do_sync(PRE_SYNC, 1); uint8_t rd = ((bit_sub<7,5>(instr))); - int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -338,7 +338,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *PC + imm; + if(rd != 0) *(X+rd) = *PC + (int32_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 1); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -355,7 +355,7 @@ private: // pre execution stuff this->do_sync(PRE_SYNC, 2); uint8_t rd = ((bit_sub<7,5>(instr))); - int32_t imm = signextend((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -372,7 +372,7 @@ private: // execute instruction { if(rd != 0) *(X+rd) = *PC + 4; - pc_assign(*NEXT_PC) = *PC + imm; + pc_assign(*NEXT_PC) = *PC + (int32_t)imm; } // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 2); @@ -391,7 +391,7 @@ private: this->do_sync(PRE_SYNC, 3); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -407,10 +407,10 @@ private: *NEXT_PC = *PC + 4; // execute instruction { - int32_t new_pc = *(X+rs1) + imm; + int32_t new_pc = *(X+rs1) + (int16_t)imm; int32_t align = new_pc & 0x2; if(align != 0) { - raise(0, 0); + (0, 0); } else { if(rd != 0) *(X+rd) = *PC + 4; @@ -432,7 +432,7 @@ private: compile_ret_t __beq(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 4); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -449,7 +449,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) == *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) == *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 4); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -465,7 +465,7 @@ private: compile_ret_t __bne(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 5); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -482,7 +482,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) != *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) != *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 5); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -498,7 +498,7 @@ private: compile_ret_t __blt(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 6); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -515,7 +515,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -531,7 +531,7 @@ private: compile_ret_t __bge(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 7); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -548,7 +548,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -564,7 +564,7 @@ private: compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 8); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -581,7 +581,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 8); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -597,7 +597,7 @@ private: compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 9); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -614,7 +614,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 9); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -632,7 +632,7 @@ private: this->do_sync(PRE_SYNC, 10); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -647,7 +647,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = readSpace1(traits::MEM, *(X+rs1) + imm); + if(rd != 0) *(X+rd) = readSpace1(traits::MEM, *(X+rs1) + (int16_t)imm); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 10); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -665,7 +665,7 @@ private: this->do_sync(PRE_SYNC, 11); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -680,7 +680,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = (int16_t)readSpace2(traits::MEM, *(X+rs1) + imm); + if(rd != 0) *(X+rd) = (int16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)imm); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 11); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -698,7 +698,7 @@ private: this->do_sync(PRE_SYNC, 12); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -713,7 +713,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = (uint32_t)readSpace4(traits::MEM, *(X+rs1) + imm); + if(rd != 0) *(X+rd) = (uint32_t)readSpace4(traits::MEM, *(X+rs1) + (int16_t)imm); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 12); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -731,7 +731,7 @@ private: this->do_sync(PRE_SYNC, 13); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -746,7 +746,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + imm); + if(rd != 0) *(X+rd) = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)imm); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 13); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -764,7 +764,7 @@ private: this->do_sync(PRE_SYNC, 14); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -779,7 +779,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = (uint16_t)readSpace2(traits::MEM, *(X+rs1) + imm); + if(rd != 0) *(X+rd) = (uint16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)imm); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 14); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -795,7 +795,7 @@ private: compile_ret_t __sb(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 15); - int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -812,7 +812,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - writeSpace1(traits::MEM, *(X+rs1) + imm, (int8_t)*(X+rs2)); + writeSpace1(traits::MEM, *(X+rs1) + (int16_t)imm, (int8_t)*(X+rs2)); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 15); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -828,7 +828,7 @@ private: compile_ret_t __sh(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 16); - int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -845,7 +845,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - writeSpace2(traits::MEM, *(X+rs1) + imm, (int16_t)*(X+rs2)); + writeSpace2(traits::MEM, *(X+rs1) + (int16_t)imm, (int16_t)*(X+rs2)); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 16); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -861,7 +861,7 @@ private: compile_ret_t __sw(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 17); - int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -878,7 +878,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - writeSpace4(traits::MEM, *(X+rs1) + imm, *(X+rs2)); + writeSpace4(traits::MEM, *(X+rs1) + (int16_t)imm, *(X+rs2)); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 17); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -896,7 +896,7 @@ private: this->do_sync(PRE_SYNC, 18); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -911,7 +911,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *(X+rs1) + imm; + if(rd != 0) *(X+rd) = *(X+rs1) + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 18); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -929,7 +929,7 @@ private: this->do_sync(PRE_SYNC, 19); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -944,7 +944,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *(X+rs1) < imm? 1 : 0; + if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int16_t)imm? 1 : 0; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 19); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -962,7 +962,7 @@ private: this->do_sync(PRE_SYNC, 20); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -977,7 +977,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = (uint8_t)*(X+rs1) < (uint8_t)(int32_t)imm? 1 : 0; + if(rd != 0) *(X+rd) = *(X+rs1) < imm? 1 : 0; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 20); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -995,7 +995,7 @@ private: this->do_sync(PRE_SYNC, 21); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1010,7 +1010,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *(X+rs1) ^ imm; + if(rd != 0) *(X+rd) = *(X+rs1) ^ (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 21); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1028,7 +1028,7 @@ private: this->do_sync(PRE_SYNC, 22); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1043,7 +1043,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *(X+rs1) | imm; + if(rd != 0) *(X+rd) = *(X+rs1) | (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 22); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1061,7 +1061,7 @@ private: this->do_sync(PRE_SYNC, 23); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1076,7 +1076,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *(X+rs1) & imm; + if(rd != 0) *(X+rd) = *(X+rs1) & (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 23); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1110,7 +1110,7 @@ private: *NEXT_PC = *PC + 4; // execute instruction if(shamt > 31) { - raise(0, 0); + (0, 0); } else { if(rd != 0) *(X+rd) = *(X+rs1) << shamt; @@ -1148,7 +1148,7 @@ private: *NEXT_PC = *PC + 4; // execute instruction if(shamt > 31) { - raise(0, 0); + (0, 0); } else { if(rd != 0) *(X+rd) = ((uint8_t)*(X+rs1)) >> shamt; @@ -1186,7 +1186,7 @@ private: *NEXT_PC = *PC + 4; // execute instruction if(shamt > 31) { - raise(0, 0); + (0, 0); } else { if(rd != 0) *(X+rd) = *(X+rs1) >> shamt; @@ -1614,7 +1614,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - raise(0, 11); + (0, 11); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 39); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1641,7 +1641,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - raise(0, 3); + (0, 3); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 40); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1668,7 +1668,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - leave(0); + (0); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 41); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1695,7 +1695,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - leave(1); + (1); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 42); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1722,7 +1722,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - leave(3); + (3); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 43); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1749,7 +1749,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - wait(1); + (1); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 44); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); diff --git a/src/vm/interp/vm_tgf_c.cpp b/src/vm/interp/vm_tgf_c.cpp index 7ce27e4..455e5aa 100644 --- a/src/vm/interp/vm_tgf_c.cpp +++ b/src/vm/interp/vm_tgf_c.cpp @@ -180,17 +180,17 @@ private: const std::array instr_descr = {{ /* entries are: size, valid value, valid mask, function ptr */ /* instruction LUI */ - {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui}, + {32, 0b0000000000000000000000000110111, 0b0000000000000000000000000111111, &this_class::__lui}, /* instruction AUIPC */ - {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc}, + {32, 0b000000000000000000000000010111, 0b000000000000000000000000011111, &this_class::__auipc}, /* instruction JAL */ {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal}, /* instruction JALR */ - {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr}, + {32, 0b000000000000000000000001100111, 0b000000000000000001000001111111, &this_class::__jalr}, /* instruction BEQ */ - {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq}, + {32, 0b000000000000000000000001100011, 0b000000000000000001000001111111, &this_class::__beq}, /* instruction BNE */ - {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne}, + {32, 0b000000000000000001000001100011, 0b000000000000000001000001111111, &this_class::__bne}, /* instruction BLT */ {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt}, /* instruction BGE */ @@ -200,83 +200,83 @@ private: /* instruction BGEU */ {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu}, /* instruction LB */ - {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb}, + {32, 0b0000000000000000000000011, 0b0000000000000000010000011, &this_class::__lb}, /* instruction LH */ - {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh}, + {32, 0b0000000000000000010000011, 0b0000000000000000010000011, &this_class::__lh}, /* instruction LW */ - {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw}, + {32, 0b00000000000000000100000011, 0b00000000000000000110000011, &this_class::__lw}, /* instruction LBU */ - {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu}, + {32, 0b000000000000000001000000011, 0b000000000000000001110000011, &this_class::__lbu}, /* instruction LHU */ - {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu}, + {32, 0b000000000000000001010000011, 0b000000000000000001110000011, &this_class::__lhu}, /* instruction SB */ - {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb}, + {32, 0b00000000000000000000000100011, 0b00000000000000000100000111111, &this_class::__sb}, /* instruction SH */ - {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh}, + {32, 0b00000000000000000100000100011, 0b00000000000000000100000111111, &this_class::__sh}, /* instruction SW */ - {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw}, + {32, 0b000000000000000001000000100011, 0b000000000000000001100000111111, &this_class::__sw}, /* instruction ADDI */ - {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi}, + {32, 0b0000000000000000000000010011, 0b0000000000000000010000011111, &this_class::__addi}, /* instruction SLTI */ - {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti}, + {32, 0b00000000000000000100000010011, 0b00000000000000000110000011111, &this_class::__slti}, /* instruction SLTIU */ - {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu}, + {32, 0b00000000000000000110000010011, 0b00000000000000000110000011111, &this_class::__sltiu}, /* instruction XORI */ - {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori}, + {32, 0b000000000000000001000000010011, 0b000000000000000001110000011111, &this_class::__xori}, /* instruction ORI */ - {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori}, + {32, 0b000000000000000001100000010011, 0b000000000000000001110000011111, &this_class::__ori}, /* instruction ANDI */ - {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi}, + {32, 0b000000000000000001110000010011, 0b000000000000000001110000011111, &this_class::__andi}, /* instruction SLLI */ - {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli}, + {32, 0b0000000000010000010011, 0b1000000000010000011111, &this_class::__slli}, /* instruction SRLI */ - {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli}, + {32, 0b000000000001010000010011, 0b100000000001110000011111, &this_class::__srli}, /* instruction SRAI */ - {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai}, + {32, 0b10000000000000001010000010011, 0b11111100000000001110000011111, &this_class::__srai}, /* instruction ADD */ - {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add}, + {32, 0b00000000000000000110011, 0b10000000000100000111111, &this_class::__add}, /* instruction SUB */ - {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub}, + {32, 0b1000000000000000000000110011, 0b1111110000000000100000111111, &this_class::__sub}, /* instruction SLL */ - {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll}, + {32, 0b00000000000100000110011, 0b10000000000100000111111, &this_class::__sll}, /* instruction SLT */ - {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt}, + {32, 0b000000000001000000110011, 0b100000000001100000111111, &this_class::__slt}, /* instruction SLTU */ - {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu}, + {32, 0b000000000001100000110011, 0b100000000001100000111111, &this_class::__sltu}, /* instruction XOR */ - {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor}, + {32, 0b0000000000010000000110011, 0b1000000000011100000111111, &this_class::__xor}, /* instruction SRL */ - {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl}, + {32, 0b0000000000010100000110011, 0b1000000000011100000111111, &this_class::__srl}, /* instruction SRA */ - {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra}, + {32, 0b100000000000000010100000110011, 0b111111000000000011100000111111, &this_class::__sra}, /* instruction OR */ - {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or}, + {32, 0b0000000000011000000110011, 0b1000000000011100000111111, &this_class::__or}, /* instruction AND */ - {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and}, + {32, 0b0000000000011100000110011, 0b1000000000011100000111111, &this_class::__and}, /* instruction FENCE */ - {32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence}, + {32, 0b000000000000000000001111, 0b100000000000001000001111, &this_class::__fence}, /* instruction FENCE_I */ - {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i}, + {32, 0b000000000000000001000001111, 0b000000000000000001000001111, &this_class::__fence_i}, /* instruction ECALL */ - {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall}, + {32, 0b00001110011, 0b11111111111, &this_class::__ecall}, /* instruction EBREAK */ - {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak}, + {32, 0b10001110011, 0b11111111111, &this_class::__ebreak}, /* instruction URET */ - {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret}, + {32, 0b0100001110011, 0b1111111111111, &this_class::__uret}, /* instruction SRET */ - {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret}, + {32, 0b1000100001110011, 0b1111111111111111, &this_class::__sret}, /* instruction MRET */ - {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret}, + {32, 0b11000100001110011, 0b11111111111111111, &this_class::__mret}, /* instruction WFI */ - {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi}, + {32, 0b10001010001110011, 0b11111111111111111, &this_class::__wfi}, /* instruction SFENCE_VMA */ - {32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma}, + {32, 0b10010000000000001110011, 0b11110000000000111111111, &this_class::__sfence_vma}, /* instruction CSRRW */ - {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw}, + {32, 0b000000000000000001000001110011, 0b000000000000000001000001111111, &this_class::__csrrw}, /* instruction CSRRS */ - {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs}, + {32, 0b0000000000000000010000001110011, 0b0000000000000000011000001111111, &this_class::__csrrs}, /* instruction CSRRC */ - {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc}, + {32, 0b0000000000000000011000001110011, 0b0000000000000000011000001111111, &this_class::__csrrc}, /* instruction CSRRWI */ {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi}, /* instruction CSRRSI */ @@ -284,77 +284,77 @@ private: /* instruction CSRRCI */ {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci}, /* instruction MUL */ - {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul}, + {32, 0b10000000000000000110011, 0b10000000000100000111111, &this_class::__mul}, /* instruction MULH */ - {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh}, + {32, 0b10000000000100000110011, 0b10000000000100000111111, &this_class::__mulh}, /* instruction MULHSU */ - {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu}, + {32, 0b100000000001000000110011, 0b100000000001100000111111, &this_class::__mulhsu}, /* instruction MULHU */ - {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu}, + {32, 0b100000000001100000110011, 0b100000000001100000111111, &this_class::__mulhu}, /* instruction DIV */ - {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div}, + {32, 0b1000000000010000000110011, 0b1000000000011100000111111, &this_class::__div}, /* instruction DIVU */ - {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu}, + {32, 0b1000000000010100000110011, 0b1000000000011100000111111, &this_class::__divu}, /* instruction REM */ - {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem}, + {32, 0b1000000000011000000110011, 0b1000000000011100000111111, &this_class::__rem}, /* instruction REMU */ - {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu}, + {32, 0b1000000000011100000110011, 0b1000000000011100000111111, &this_class::__remu}, /* instruction CADDI4SPN */ - {16, 0b0000000000000000, 0b1110000000000011, &this_class::__caddi4spn}, + {16, 0b0000000000000, 0b1000000000001, &this_class::__caddi4spn}, /* instruction CLW */ - {16, 0b0100000000000000, 0b1110000000000011, &this_class::__clw}, + {16, 0b10000000000000, 0b11000000000001, &this_class::__clw}, /* instruction CSW */ - {16, 0b1100000000000000, 0b1110000000000011, &this_class::__csw}, + {16, 0b110000000000000, 0b111000000000001, &this_class::__csw}, /* instruction CADDI */ - {16, 0b0000000000000001, 0b1110000000000011, &this_class::__caddi}, + {16, 0b0000000000001, 0b1000000000001, &this_class::__caddi}, /* instruction CNOP */ - {16, 0b0000000000000001, 0b1111111111111111, &this_class::__cnop}, + {16, 0b00001, 0b11111, &this_class::__cnop}, /* instruction CJAL */ - {16, 0b0010000000000001, 0b1110000000000011, &this_class::__cjal}, + {16, 0b1000000000001, 0b1000000000001, &this_class::__cjal}, /* instruction CLI */ - {16, 0b0100000000000001, 0b1110000000000011, &this_class::__cli}, + {16, 0b10000000000001, 0b11000000000001, &this_class::__cli}, /* instruction CLUI */ - {16, 0b0110000000000001, 0b1110000000000011, &this_class::__clui}, + {16, 0b11000000000001, 0b11000000000001, &this_class::__clui}, /* instruction CADDI16SP */ - {16, 0b0110000100000001, 0b1110111110000011, &this_class::__caddi16sp}, + {16, 0b11010000001, 0b11011000001, &this_class::__caddi16sp}, /* instruction CSRLI */ - {16, 0b1000000000000001, 0b1111110000000011, &this_class::__csrli}, + {16, 0b10000000000001, 0b11111000000001, &this_class::__csrli}, /* instruction CSRAI */ - {16, 0b1000010000000001, 0b1111110000000011, &this_class::__csrai}, + {16, 0b10001000000001, 0b11111000000001, &this_class::__csrai}, /* instruction CANDI */ - {16, 0b1000100000000001, 0b1110110000000011, &this_class::__candi}, + {16, 0b100010000000001, 0b111011000000001, &this_class::__candi}, /* instruction CSUB */ - {16, 0b1000110000000001, 0b1111110001100011, &this_class::__csub}, + {16, 0b10001100000001, 0b11111100010001, &this_class::__csub}, /* instruction CXOR */ - {16, 0b1000110000100001, 0b1111110001100011, &this_class::__cxor}, + {16, 0b10001100010001, 0b11111100010001, &this_class::__cxor}, /* instruction COR */ - {16, 0b1000110001000001, 0b1111110001100011, &this_class::__cor}, + {16, 0b100011000100001, 0b111111000110001, &this_class::__cor}, /* instruction CAND */ - {16, 0b1000110001100001, 0b1111110001100011, &this_class::__cand}, + {16, 0b100011000110001, 0b111111000110001, &this_class::__cand}, /* instruction CJ */ - {16, 0b1010000000000001, 0b1110000000000011, &this_class::__cj}, + {16, 0b101000000000001, 0b111000000000001, &this_class::__cj}, /* instruction CBEQZ */ - {16, 0b1100000000000001, 0b1110000000000011, &this_class::__cbeqz}, + {16, 0b110000000000001, 0b111000000000001, &this_class::__cbeqz}, /* instruction CBNEZ */ - {16, 0b1110000000000001, 0b1110000000000011, &this_class::__cbnez}, + {16, 0b111000000000001, 0b111000000000001, &this_class::__cbnez}, /* instruction CSLLI */ - {16, 0b0000000000000010, 0b1111000000000011, &this_class::__cslli}, + {16, 0b00000000000010, 0b11000000000011, &this_class::__cslli}, /* instruction CLWSP */ - {16, 0b0100000000000010, 0b1110000000000011, &this_class::__clwsp}, + {16, 0b100000000000010, 0b110000000000011, &this_class::__clwsp}, /* instruction CMV */ {16, 0b1000000000000010, 0b1111000000000011, &this_class::__cmv}, /* instruction CJR */ - {16, 0b1000000000000010, 0b1111000001111111, &this_class::__cjr}, + {16, 0b100000000010, 0b111100000111, &this_class::__cjr}, /* instruction CADD */ {16, 0b1001000000000010, 0b1111000000000011, &this_class::__cadd}, /* instruction CJALR */ - {16, 0b1001000000000010, 0b1111000001111111, &this_class::__cjalr}, + {16, 0b100100000010, 0b111100000111, &this_class::__cjalr}, /* instruction CEBREAK */ - {16, 0b1001000000000010, 0b1111111111111111, &this_class::__cebreak}, + {16, 0b10010010, 0b11111111, &this_class::__cebreak}, /* instruction CSWSP */ {16, 0b1100000000000010, 0b1110000000000011, &this_class::__cswsp}, /* instruction DII */ - {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii}, + {16, 0b00000, 0b11111, &this_class::__dii}, }}; /* instruction definitions */ @@ -363,7 +363,7 @@ private: // pre execution stuff this->do_sync(PRE_SYNC, 0); uint8_t rd = ((bit_sub<7,5>(instr))); - int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -378,7 +378,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = imm; + if(rd != 0) *(X+rd) = (int32_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 0); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -395,7 +395,7 @@ private: // pre execution stuff this->do_sync(PRE_SYNC, 1); uint8_t rd = ((bit_sub<7,5>(instr))); - int32_t imm = signextend((bit_sub<12,20>(instr) << 12)); + uint32_t imm = ((bit_sub<12,20>(instr) << 12)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -410,7 +410,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *PC + imm; + if(rd != 0) *(X+rd) = *PC + (int32_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 1); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -427,7 +427,7 @@ private: // pre execution stuff this->do_sync(PRE_SYNC, 2); uint8_t rd = ((bit_sub<7,5>(instr))); - int32_t imm = signextend((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); + uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -444,7 +444,7 @@ private: // execute instruction { if(rd != 0) *(X+rd) = *PC + 4; - pc_assign(*NEXT_PC) = *PC + imm; + pc_assign(*NEXT_PC) = *PC + (int32_t)imm; } // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 2); @@ -463,7 +463,7 @@ private: this->do_sync(PRE_SYNC, 3); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -479,7 +479,7 @@ private: *NEXT_PC = *PC + 4; // execute instruction { - int32_t new_pc = *(X+rs1) + imm; + int32_t new_pc = *(X+rs1) + (int16_t)imm; if(rd != 0) *(X+rd) = *PC + 4; pc_assign(*NEXT_PC) = new_pc & ~ 0x1; } @@ -498,7 +498,7 @@ private: compile_ret_t __beq(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 4); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -515,7 +515,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) == *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) == *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 4); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -531,7 +531,7 @@ private: compile_ret_t __bne(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 5); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -548,7 +548,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) != *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) != *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 5); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -564,7 +564,7 @@ private: compile_ret_t __blt(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 6); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -581,7 +581,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -597,7 +597,7 @@ private: compile_ret_t __bge(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 7); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -614,7 +614,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -630,7 +630,7 @@ private: compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 8); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -647,7 +647,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) < *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 8); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -663,7 +663,7 @@ private: compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 9); - int16_t imm = signextend((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); + uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -680,7 +680,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+rs1) >= *(X+rs2)) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 9); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -698,7 +698,7 @@ private: this->do_sync(PRE_SYNC, 10); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -713,7 +713,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = readSpace1(traits::MEM, *(X+rs1) + imm); + if(rd != 0) *(X+rd) = readSpace1(traits::MEM, *(X+rs1) + (int16_t)imm); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 10); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -731,7 +731,7 @@ private: this->do_sync(PRE_SYNC, 11); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -746,7 +746,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = (int16_t)readSpace2(traits::MEM, *(X+rs1) + imm); + if(rd != 0) *(X+rd) = (int16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)imm); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 11); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -764,7 +764,7 @@ private: this->do_sync(PRE_SYNC, 12); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -779,7 +779,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = (uint32_t)readSpace4(traits::MEM, *(X+rs1) + imm); + if(rd != 0) *(X+rd) = (uint32_t)readSpace4(traits::MEM, *(X+rs1) + (int16_t)imm); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 12); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -797,7 +797,7 @@ private: this->do_sync(PRE_SYNC, 13); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -812,7 +812,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + imm); + if(rd != 0) *(X+rd) = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)imm); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 13); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -830,7 +830,7 @@ private: this->do_sync(PRE_SYNC, 14); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -845,7 +845,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = (uint16_t)readSpace2(traits::MEM, *(X+rs1) + imm); + if(rd != 0) *(X+rd) = (uint16_t)readSpace2(traits::MEM, *(X+rs1) + (int16_t)imm); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 14); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -861,7 +861,7 @@ private: compile_ret_t __sb(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 15); - int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -878,7 +878,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - writeSpace1(traits::MEM, *(X+rs1) + imm, (int8_t)*(X+rs2)); + writeSpace1(traits::MEM, *(X+rs1) + (int16_t)imm, (int8_t)*(X+rs2)); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 15); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -894,7 +894,7 @@ private: compile_ret_t __sh(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 16); - int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -911,7 +911,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - writeSpace2(traits::MEM, *(X+rs1) + imm, (int16_t)*(X+rs2)); + writeSpace2(traits::MEM, *(X+rs1) + (int16_t)imm, (int16_t)*(X+rs2)); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 16); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -927,7 +927,7 @@ private: compile_ret_t __sw(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 17); - int16_t imm = signextend((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); + uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5)); uint8_t rs1 = ((bit_sub<15,5>(instr))); uint8_t rs2 = ((bit_sub<20,5>(instr))); if(this->disass_enabled){ @@ -944,7 +944,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - writeSpace4(traits::MEM, *(X+rs1) + imm, *(X+rs2)); + writeSpace4(traits::MEM, *(X+rs1) + (int16_t)imm, *(X+rs2)); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 17); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -962,7 +962,7 @@ private: this->do_sync(PRE_SYNC, 18); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -977,7 +977,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *(X+rs1) + imm; + if(rd != 0) *(X+rd) = *(X+rs1) + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 18); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -995,7 +995,7 @@ private: this->do_sync(PRE_SYNC, 19); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1010,7 +1010,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *(X+rs1) < imm? 1 : 0; + if(rd != 0) *(X+rd) = (int32_t)*(X+rs1) < (int16_t)imm? 1 : 0; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 19); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1028,7 +1028,7 @@ private: this->do_sync(PRE_SYNC, 20); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1043,7 +1043,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = (uint8_t)*(X+rs1) < (uint8_t)(int32_t)imm? 1 : 0; + if(rd != 0) *(X+rd) = *(X+rs1) < imm? 1 : 0; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 20); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1061,7 +1061,7 @@ private: this->do_sync(PRE_SYNC, 21); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1076,7 +1076,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *(X+rs1) ^ imm; + if(rd != 0) *(X+rd) = *(X+rs1) ^ (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 21); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1094,7 +1094,7 @@ private: this->do_sync(PRE_SYNC, 22); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1109,7 +1109,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *(X+rs1) | imm; + if(rd != 0) *(X+rd) = *(X+rs1) | (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 22); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1127,7 +1127,7 @@ private: this->do_sync(PRE_SYNC, 23); uint8_t rd = ((bit_sub<7,5>(instr))); uint8_t rs1 = ((bit_sub<15,5>(instr))); - int16_t imm = signextend((bit_sub<20,12>(instr))); + uint16_t imm = ((bit_sub<20,12>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -1142,7 +1142,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - if(rd != 0) *(X+rd) = *(X+rs1) & imm; + if(rd != 0) *(X+rd) = *(X+rs1) & (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 23); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1176,7 +1176,7 @@ private: *NEXT_PC = *PC + 4; // execute instruction if(shamt > 31) { - raise(0, 0); + (0, 0); } else { if(rd != 0) *(X+rd) = *(X+rs1) << shamt; @@ -1214,7 +1214,7 @@ private: *NEXT_PC = *PC + 4; // execute instruction if(shamt > 31) { - raise(0, 0); + (0, 0); } else { if(rd != 0) *(X+rd) = ((uint8_t)*(X+rs1)) >> shamt; @@ -1252,7 +1252,7 @@ private: *NEXT_PC = *PC + 4; // execute instruction if(shamt > 31) { - raise(0, 0); + (0, 0); } else { if(rd != 0) *(X+rd) = *(X+rs1) >> shamt; @@ -1680,7 +1680,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - raise(0, 11); + (0, 11); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 39); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1707,7 +1707,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - raise(0, 3); + (0, 3); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 40); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1734,7 +1734,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - leave(0); + (0); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 41); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1761,7 +1761,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - leave(1); + (1); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 42); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1788,7 +1788,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - leave(3); + (3); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 43); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -1815,7 +1815,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 4; // execute instruction - wait(1); + (1); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 44); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -2424,7 +2424,7 @@ private: *NEXT_PC = *PC + 2; // execute instruction { - if(imm == 0) raise(0, 2); + if(imm == 0) (0, 2); *(X+(rd + 8)) = *(X+2) + imm; } // post execution stuff @@ -2514,7 +2514,7 @@ private: compile_ret_t __caddi(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 63); - int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -2530,7 +2530,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 2; // execute instruction - *(X+rs1) = (int8_t)*(X+rs1) + imm; + *(X+rs1) = *(X+rs1) + (int8_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 63); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -2574,7 +2574,7 @@ private: compile_ret_t __cjal(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 65); - int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -2591,7 +2591,7 @@ private: // execute instruction { *(X+1) = *PC + 2; - pc_assign(*NEXT_PC) = (int8_t)*PC + imm; + pc_assign(*NEXT_PC) = (int8_t)*PC + (int16_t)imm; } // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65); @@ -2608,7 +2608,7 @@ private: compile_ret_t __cli(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 66); - int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -2625,8 +2625,8 @@ private: *NEXT_PC = *PC + 2; // execute instruction { - if(rd == 0) raise(0, 2); - *(X+rd) = imm; + if(rd == 0) (0, 2); + *(X+rd) = (int8_t)imm; } // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 66); @@ -2643,7 +2643,7 @@ private: compile_ret_t __clui(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 67); - int32_t imm = signextend((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); + uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17)); uint8_t rd = ((bit_sub<7,5>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -2660,9 +2660,9 @@ private: *NEXT_PC = *PC + 2; // execute instruction { - if(rd == 0) raise(0, 2); - if(imm == 0) raise(0, 2); - *(X+rd) = imm; + if(rd == 0) (0, 2); + if(imm == 0) (0, 2); + *(X+rd) = (int32_t)imm; } // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 67); @@ -2679,7 +2679,7 @@ private: compile_ret_t __caddi16sp(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 68); - int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -2694,7 +2694,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 2; // execute instruction - *(X+2) = (int8_t)*(X+2) + imm; + *(X+2) = *(X+2) + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 68); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -2780,7 +2780,7 @@ private: compile_ret_t __candi(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 71); - int8_t imm = signextend((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); + uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -2798,7 +2798,7 @@ private: // execute instruction { uint8_t rs1_idx = rs1 + 8; - *(X+rs1_idx) = *(X+rs1_idx) & imm; + *(X+rs1_idx) = *(X+rs1_idx) & (int8_t)imm; } // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 71); @@ -2955,7 +2955,7 @@ private: compile_ret_t __cj(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 76); - int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11)); if(this->disass_enabled){ /* generate console output when executing the command */ auto mnemonic = fmt::format( @@ -2970,7 +2970,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 2; // execute instruction - pc_assign(*NEXT_PC) = (int8_t)*PC + imm; + pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 76); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -2986,7 +2986,7 @@ private: compile_ret_t __cbeqz(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 77); - int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -3002,7 +3002,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 2; // execute instruction - if(*(X+(rs1 + 8)) == 0) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+(rs1 + 8)) == 0) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 77); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -3018,7 +3018,7 @@ private: compile_ret_t __cbnez(virt_addr_t& pc, code_word_t instr){ // pre execution stuff this->do_sync(PRE_SYNC, 78); - int16_t imm = signextend((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); + uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8)); uint8_t rs1 = ((bit_sub<7,3>(instr))); if(this->disass_enabled){ /* generate console output when executing the command */ @@ -3034,7 +3034,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 2; // execute instruction - if(*(X+(rs1 + 8)) != 0) pc_assign(*NEXT_PC) = *PC + imm; + if(*(X+(rs1 + 8)) != 0) pc_assign(*NEXT_PC) = *PC + (int16_t)imm; // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 78); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -3067,7 +3067,7 @@ private: *NEXT_PC = *PC + 2; // execute instruction { - if(rs1 == 0) raise(0, 2); + if(rs1 == 0) (0, 2); *(X+rs1) = *(X+rs1) << shamt; } // post execution stuff @@ -3260,7 +3260,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 2; // execute instruction - raise(0, 3); + (0, 3); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 85); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE); @@ -3322,7 +3322,7 @@ private: uint32_t* NEXT_PC = reinterpret_cast(this->regs_base_ptr+arch::traits::reg_byte_offsets[arch::traits::NEXT_PC]); *NEXT_PC = *PC + 2; // execute instruction - raise(0, 2); + (0, 2); // post execution stuff if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 87); auto& trap_state = super::template get_reg(arch::traits::TRAP_STATE);