From ad7bb28b4c2c3e7041771f57e6d1995c34965e5e Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sat, 17 Sep 2022 12:14:03 +0200 Subject: [PATCH] fixes write mask of clic memory mapped registers --- src/iss/arch/riscv_hart_mu_p.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 87ff8b9..55c8f0c 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -487,7 +487,7 @@ riscv_hart_mu_p::riscv_hart_mu_p(feature_config cfg) csr_rd_cb[mclicbase] = &this_class::read_csr_reg; csr_wr_cb[mclicbase] = &this_class::write_null; - clic_int_reg.resize(cfg.clic_num_irq); + clic_int_reg.resize(cfg.clic_num_irq, clic_int_reg_t{.raw=0}); clic_cfg_reg=0x20; clic_info_reg = (/*CLICINTCTLBITS*/ 4U<<21) + cfg.clic_num_irq; mcause_max_irq=cfg.clic_num_irq+16; @@ -1261,6 +1261,7 @@ iss::status riscv_hart_mu_p::write_clic(uint64_t addr, unsigned leng } else if(addr>=(cfg.clic_base+0x1000) && (addr+length)<=(cfg.clic_base+0x1000+cfg.clic_num_irq*4)){ // clicintip/clicintie/clicintattr/clicintctl auto offset = ((addr&0x7fff)-0x1000)/4; write_reg_uint32(addr, clic_int_reg[offset].raw, data, length); + clic_int_reg[offset].raw &= 0xf0c70101; // clicIntCtlBits->0xf0, clicintattr->0xc7, clicintie->0x1, clicintip->0x1 } return iss::Ok; }